1 /* armemu.h -- ARMulator emulation macros: ARM6 Instruction Emulator.
2 Copyright (C) 1994 Advanced RISC Machines Ltd.
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
20 /***************************************************************************\
21 * Condition code values *
22 \***************************************************************************/
41 /***************************************************************************\
43 \***************************************************************************/
50 /***************************************************************************\
51 * Macros to twiddle the status flags and mode *
52 \***************************************************************************/
54 #define NBIT ((unsigned)1L << 31)
55 #define ZBIT (1L << 30)
56 #define CBIT (1L << 29)
57 #define VBIT (1L << 28)
58 #define IBIT (1L << 7)
59 #define FBIT (1L << 6)
60 #define IFBITS (3L << 6)
61 #define R15IBIT (1L << 27)
62 #define R15FBIT (1L << 26)
63 #define R15IFBITS (3L << 26)
65 #define POS(i) ( (~(i)) >> 31 )
66 #define NEG(i) ( (i) >> 31 )
68 #ifdef MODET /* Thumb support */
69 /* ??? This bit is actually in the low order bit of the PC in the hardware.
70 It isn't clear if the simulator needs to model that or not. */
71 #define TBIT (1L << 5)
72 #define TFLAG state->TFlag
73 #define SETT state->TFlag = 1
74 #define CLEART state->TFlag = 0
75 #define ASSIGNT(res) state->TFlag = res
78 #define NFLAG state->NFlag
79 #define SETN state->NFlag = 1
80 #define CLEARN state->NFlag = 0
81 #define ASSIGNN(res) state->NFlag = res
83 #define ZFLAG state->ZFlag
84 #define SETZ state->ZFlag = 1
85 #define CLEARZ state->ZFlag = 0
86 #define ASSIGNZ(res) state->ZFlag = res
88 #define CFLAG state->CFlag
89 #define SETC state->CFlag = 1
90 #define CLEARC state->CFlag = 0
91 #define ASSIGNC(res) state->CFlag = res
93 #define VFLAG state->VFlag
94 #define SETV state->VFlag = 1
95 #define CLEARV state->VFlag = 0
96 #define ASSIGNV(res) state->VFlag = res
99 #define IFLAG (state->IFFlags >> 1)
100 #define FFLAG (state->IFFlags & 1)
101 #define IFFLAGS state->IFFlags
102 #define ASSIGNINT(res) state->IFFlags = (((res) >> 6) & 3)
103 #define ASSIGNR15INT(res) state->IFFlags = (((res) >> 26) & 3) ;
105 #define CCBITS (0xf0000000L)
106 #define INTBITS (0xc0L)
108 #if defined MODET && defined MODE32
109 #define PCBITS (0xffffffffL)
111 #define PCBITS (0xfffffffcL)
114 #define MODEBITS (0x1fL)
115 #define R15INTBITS (3L << 26)
117 #if defined MODET && defined MODE32
118 #define R15PCBITS (0x03ffffffL)
120 #define R15PCBITS (0x03fffffcL)
123 #define R15PCMODEBITS (0x03ffffffL)
124 #define R15MODEBITS (0x3L)
127 #define PCMASK PCBITS
128 #define PCWRAP(pc) (pc)
130 #define PCMASK R15PCBITS
131 #define PCWRAP(pc) ((pc) & R15PCBITS)
134 #define PC (state->Reg[15] & PCMASK)
135 #define R15CCINTMODE (state->Reg[15] & (CCBITS | R15INTBITS | R15MODEBITS))
136 #define R15INT (state->Reg[15] & R15INTBITS)
137 #define R15INTPC (state->Reg[15] & (R15INTBITS | R15PCBITS))
138 #define R15INTPCMODE (state->Reg[15] & (R15INTBITS | R15PCBITS | R15MODEBITS))
139 #define R15INTMODE (state->Reg[15] & (R15INTBITS | R15MODEBITS))
140 #define R15PC (state->Reg[15] & R15PCBITS)
141 #define R15PCMODE (state->Reg[15] & (R15PCBITS | R15MODEBITS))
142 #define R15MODE (state->Reg[15] & R15MODEBITS)
144 #define ECC ((NFLAG << 31) | (ZFLAG << 30) | (CFLAG << 29) | (VFLAG << 28))
145 #define EINT (IFFLAGS << 6)
146 #define ER15INT (IFFLAGS << 26)
147 #define EMODE (state->Mode)
150 #define CPSR (ECC | EINT | EMODE | (TFLAG << 5))
152 #define CPSR (ECC | EINT | EMODE)
158 #define PATCHR15 state->Reg[15] = ECC | ER15INT | EMODE | R15PC
161 #define GETSPSR(bank) bank>0?state->Spsr[bank]:ECC | EINT | EMODE ;
162 #define SETPSR(d,s) d = (s) & (ARMword)(CCBITS | INTBITS | MODEBITS)
163 #define SETINTMODE(d,s) d = ((d) & CCBITS) | ((s) & (INTBITS | MODEBITS))
164 #define SETCC(d,s) d = ((d) & (INTBITS | MODEBITS)) | ((s) & CCBITS)
165 #define SETR15PSR(s) if (state->Mode == USER26MODE) { \
166 state->Reg[15] = ((s) & CCBITS) | R15PC | ER15INT | EMODE ; \
167 ASSIGNN((state->Reg[15] & NBIT) != 0) ; \
168 ASSIGNZ((state->Reg[15] & ZBIT) != 0) ; \
169 ASSIGNC((state->Reg[15] & CBIT) != 0) ; \
170 ASSIGNV((state->Reg[15] & VBIT) != 0) ; \
173 state->Reg[15] = R15PC | ((s) & (CCBITS | R15INTBITS | R15MODEBITS)) ; \
174 ARMul_R15Altered (state) ; \
176 #define SETABORT(i,m) state->Cpsr = ECC | EINT | (i) | (m)
180 #define LEGALADDR 0x03ffffff
181 #define VECTORACCESS(address) (address < VECTORS && ARMul_MODE26BIT && state->prog32Sig)
182 #define ADDREXCEPT(address) (address > LEGALADDR && !state->data32Sig)
185 #define INTERNALABORT(address) if (address < VECTORS) \
186 state->Aborted = ARMul_DataAbortV ; \
188 state->Aborted = ARMul_AddrExceptnV ;
191 #define TAKEABORT ARMul_Abort(state,ARMul_DataAbortV)
193 #define TAKEABORT if (state->Aborted == ARMul_AddrExceptnV) \
194 ARMul_Abort(state,ARMul_AddrExceptnV) ; \
196 ARMul_Abort(state,ARMul_DataAbortV)
198 #define CPTAKEABORT if (!state->Aborted) \
199 ARMul_Abort(state,ARMul_UndefinedInstrV) ; \
200 else if (state->Aborted == ARMul_AddrExceptnV) \
201 ARMul_Abort(state,ARMul_AddrExceptnV) ; \
203 ARMul_Abort(state,ARMul_DataAbortV)
206 /***************************************************************************\
207 * Different ways to start the next instruction *
208 \***************************************************************************/
213 #define PCINCEDNONSEQ 3
217 #define NORMALCYCLE state->NextInstr = 0
218 #define BUSUSEDN state->NextInstr |= 1 /* the next fetch will be an N cycle */
219 #define BUSUSEDINCPCS state->Reg[15] += isize ; /* a standard PC inc and an S cycle */ \
220 state->NextInstr = (state->NextInstr & 0xff) | 2
221 #define BUSUSEDINCPCN state->Reg[15] += isize ; /* a standard PC inc and an N cycle */ \
222 state->NextInstr |= 3
223 #define INCPC state->Reg[15] += isize ; /* a standard PC inc */ \
224 state->NextInstr |= 2
225 #define FLUSHPIPE state->NextInstr |= PRIMEPIPE
227 /***************************************************************************\
228 * Cycle based emulation *
229 \***************************************************************************/
231 #define OUTPUTCP(i,a,b)
238 /***************************************************************************\
239 * States of the cycle based state machine *
240 \***************************************************************************/
243 /***************************************************************************\
244 * Macros to extract parts of instructions *
245 \***************************************************************************/
247 #define DESTReg (BITS(12,15))
248 #define LHSReg (BITS(16,19))
249 #define RHSReg (BITS(0,3))
251 #define DEST (state->Reg[DESTReg])
255 #define LHS ((LHSReg == 15) ? (state->Reg[15] & 0xFFFFFFFC): (state->Reg[LHSReg]))
257 #define LHS (state->Reg[LHSReg])
260 #define LHS ((LHSReg == 15) ? R15PC : (state->Reg[LHSReg]) )
263 #define MULDESTReg (BITS(16,19))
264 #define MULLHSReg (BITS(0,3))
265 #define MULRHSReg (BITS(8,11))
266 #define MULACCReg (BITS(12,15))
268 #define DPImmRHS (ARMul_ImmedTable[BITS(0,11)])
269 #define DPSImmRHS temp = BITS(0,11) ; \
270 rhs = ARMul_ImmedTable[temp] ; \
271 if (temp > 255) /* there was a shift */ \
275 #define DPRegRHS ((BITS(4,11)==0) ? state->Reg[RHSReg] \
276 : GetDPRegRHS(state, instr))
277 #define DPSRegRHS ((BITS(4,11)==0) ? state->Reg[RHSReg] \
278 : GetDPSRegRHS(state, instr))
280 #define DPRegRHS ((BITS(0,11)<15) ? state->Reg[RHSReg] \
281 : GetDPRegRHS(state, instr))
282 #define DPSRegRHS ((BITS(0,11)<15) ? state->Reg[RHSReg] \
283 : GetDPSRegRHS(state, instr))
286 #define LSBase state->Reg[LHSReg]
287 #define LSImmRHS (BITS(0,11))
290 #define LSRegRHS ((BITS(4,11)==0) ? state->Reg[RHSReg] \
291 : GetLSRegRHS(state, instr))
293 #define LSRegRHS ((BITS(0,11)<15) ? state->Reg[RHSReg] \
294 : GetLSRegRHS(state, instr))
297 #define LSMNumRegs ((ARMword)ARMul_BitList[BITS(0,7)] + \
298 (ARMword)ARMul_BitList[BITS(8,15)] )
299 #define LSMBaseFirst ((LHSReg == 0 && BIT(0)) || \
300 (BIT(LHSReg) && BITS(0,LHSReg-1) == 0))
302 #define SWAPSRC (state->Reg[RHSReg])
304 #define LSCOff (BITS(0,7) << 2)
305 #define CPNum BITS(8,11)
307 /***************************************************************************\
308 * Macro to rotate n right by b bits *
309 \***************************************************************************/
311 #define ROTATER(n,b) (((n)>>(b))|((n)<<(32-(b))))
313 /***************************************************************************\
314 * Macros to store results of instructions *
315 \***************************************************************************/
317 #define WRITEDEST(d) if (DESTReg==15) \
318 WriteR15(state, d) ; \
322 #define WRITESDEST(d) if (DESTReg == 15) \
323 WriteSR15(state, d) ; \
326 ARMul_NegZero(state, d) ; \
329 #define BYTETOBUS(data) ((data & 0xff) | \
330 ((data & 0xff) << 8) | \
331 ((data & 0xff) << 16) | \
332 ((data & 0xff) << 24))
333 #define BUSTOBYTE(address,data) \
334 if (state->bigendSig) \
335 temp = (data >> (((address ^ 3) & 3) << 3)) & 0xff ; \
337 temp = (data >> ((address & 3) << 3)) & 0xff
339 #define LOADMULT(instr,address,wb) LoadMult(state,instr,address,wb)
340 #define LOADSMULT(instr,address,wb) LoadSMult(state,instr,address,wb)
341 #define STOREMULT(instr,address,wb) StoreMult(state,instr,address,wb)
342 #define STORESMULT(instr,address,wb) StoreSMult(state,instr,address,wb)
344 #define POSBRANCH ((instr & 0x7fffff) << 2)
345 #define NEGBRANCH (0xff000000 | ((instr & 0xffffff) << 2))
347 /***************************************************************************\
348 * Values for Emulate *
349 \***************************************************************************/
351 #define STOP 0 /* stop */
352 #define CHANGEMODE 1 /* change mode */
353 #define ONCE 2 /* execute just one interation */
354 #define RUN 3 /* continuous execution */
356 /***************************************************************************\
357 * Stuff that is shared across modes *
358 \***************************************************************************/
360 extern ARMword ARMul_Emulate26 (ARMul_State * state);
361 extern ARMword ARMul_Emulate32 (ARMul_State * state);
362 extern unsigned ARMul_MultTable[]; /* Number of I cycles for a mult */
363 extern ARMword ARMul_ImmedTable[]; /* immediate DP LHS values */
364 extern char ARMul_BitList[]; /* number of bits in a byte table */
365 extern void ARMul_Abort26 (ARMul_State * state, ARMword);
366 extern void ARMul_Abort32 (ARMul_State * state, ARMword);
367 extern unsigned ARMul_NthReg (ARMword instr, unsigned number);
368 extern void ARMul_MSRCpsr (ARMul_State * state, ARMword instr, ARMword rhs);
369 extern void ARMul_NegZero (ARMul_State * state, ARMword result);
370 extern void ARMul_AddCarry (ARMul_State * state, ARMword a, ARMword b,
372 extern int AddOverflow (ARMword a, ARMword b, ARMword result);
373 extern int SubOverflow (ARMword a, ARMword b, ARMword result);
374 extern void ARMul_AddOverflow (ARMul_State * state, ARMword a, ARMword b,
376 extern void ARMul_SubCarry (ARMul_State * state, ARMword a, ARMword b,
378 extern void ARMul_SubOverflow (ARMul_State * state, ARMword a, ARMword b,
380 extern void ARMul_CPSRAltered (ARMul_State * state);
381 extern void ARMul_R15Altered (ARMul_State * state);
382 extern ARMword ARMul_SwitchMode (ARMul_State * state, ARMword oldmode,
384 extern unsigned ARMul_NthReg (ARMword instr, unsigned number);
385 extern void ARMul_LDC (ARMul_State * state, ARMword instr, ARMword address);
386 extern void ARMul_STC (ARMul_State * state, ARMword instr, ARMword address);
387 extern void ARMul_MCR (ARMul_State * state, ARMword instr, ARMword source);
388 extern ARMword ARMul_MRC (ARMul_State * state, ARMword instr);
389 extern void ARMul_CDP (ARMul_State * state, ARMword instr);
390 extern unsigned IntPending (ARMul_State * state);
391 extern ARMword ARMul_Align (ARMul_State * state, ARMword address,
393 #define EVENTLISTSIZE 1024L
399 t_undefined, /* undefined Thumb instruction */
400 t_decoded, /* instruction decoded to ARM equivalent */
401 t_branch /* Thumb branch (already processed) */
405 extern tdstate ARMul_ThumbDecode (ARMul_State * state, ARMword pc,
406 ARMword tinstr, ARMword * ainstr);
408 /***************************************************************************\
409 * Macros to scrutinize instructions *
410 \***************************************************************************/
417 #define UNDEF_MULPCDest
418 #define UNDEF_MULDestEQOp1
420 #define UNDEF_LSRBaseEQOffWb
421 #define UNDEF_LSRBaseEQDestWb
422 #define UNDEF_LSRPCBaseWb
423 #define UNDEF_LSRPCOffWb
424 #define UNDEF_LSMNoRegs
425 #define UNDEF_LSMPCBase
426 #define UNDEF_LSMUserBankWb
427 #define UNDEF_LSMBaseInListWb
429 #define UNDEF_CoProHS
431 #define UNDEF_LSCPCBaseWb
432 #define UNDEF_UndefNotBounced
433 #define UNDEF_ShortInt
434 #define UNDEF_IllegalMode
435 #define UNDEF_Prog32SigChange
436 #define UNDEF_Data32SigChange