1 /* armcopro.c -- co-processor interface: ARM6 Instruction Emulator.
2 Copyright (C) 1994, 2000 Advanced RISC Machines Ltd.
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
23 /* Dummy Co-processors. */
26 NoCoPro3R (ARMul_State * state ATTRIBUTE_UNUSED,
27 unsigned a ATTRIBUTE_UNUSED,
28 ARMword b ATTRIBUTE_UNUSED)
34 NoCoPro4R (ARMul_State * state ATTRIBUTE_UNUSED,
35 unsigned a ATTRIBUTE_UNUSED,
36 ARMword b ATTRIBUTE_UNUSED,
37 ARMword c ATTRIBUTE_UNUSED)
43 NoCoPro4W (ARMul_State * state ATTRIBUTE_UNUSED,
44 unsigned a ATTRIBUTE_UNUSED,
45 ARMword b ATTRIBUTE_UNUSED,
46 ARMword * c ATTRIBUTE_UNUSED)
51 /* The XScale Co-processors. */
53 /* Coprocessor 15: System Control. */
54 static void write_cp14_reg (unsigned, ARMword);
55 static ARMword read_cp14_reg (unsigned);
57 /* There are two sets of registers for copro 15.
58 One set is available when opcode_2 is 0 and
59 the other set when opcode_2 >= 1. */
60 static ARMword XScale_cp15_opcode_2_is_0_Regs[16];
61 static ARMword XScale_cp15_opcode_2_is_not_0_Regs[16];
62 /* There are also a set of breakpoint registers
63 which are accessed via CRm instead of opcode_2. */
64 static ARMword XScale_cp15_DBR1;
65 static ARMword XScale_cp15_DBCON;
66 static ARMword XScale_cp15_IBCR0;
67 static ARMword XScale_cp15_IBCR1;
70 XScale_cp15_init (ARMul_State * state ATTRIBUTE_UNUSED)
76 XScale_cp15_opcode_2_is_0_Regs[i] = 0;
77 XScale_cp15_opcode_2_is_not_0_Regs[i] = 0;
80 /* Initialise the processor ID. */
81 XScale_cp15_opcode_2_is_0_Regs[0] = 0x69052000;
83 /* Initialise the cache type. */
84 XScale_cp15_opcode_2_is_not_0_Regs[0] = 0x0B1AA1AA;
86 /* Initialise the ARM Control Register. */
87 XScale_cp15_opcode_2_is_0_Regs[1] = 0x00000078;
90 /* Check an access to a register. */
93 check_cp15_access (ARMul_State * state,
99 /* Do not allow access to these register in USER mode. */
100 if (state->Mode == USER26MODE || state->Mode == USER32MODE)
103 /* Opcode_1should be zero. */
107 /* Different register have different access requirements. */
112 /* CRm must be 0. Opcode_2 can be anything. */
118 /* CRm must be 0. Opcode_2 must be zero. */
119 if ((CRm != 0) || (opcode_2 != 0))
123 /* Access not allowed. */
127 /* Opcode_2 must be zero. CRm must be 0. */
128 if ((CRm != 0) || (opcode_2 != 0))
132 /* Permissable combinations:
145 default: return ARMul_CANT;
146 case 6: if (CRm != 5) return ARMul_CANT; break;
147 case 5: if (CRm != 2) return ARMul_CANT; break;
148 case 4: if (CRm != 10) return ARMul_CANT; break;
149 case 1: if ((CRm != 5) && (CRm != 6) && (CRm != 10)) return ARMul_CANT; break;
150 case 0: if ((CRm < 5) || (CRm > 7)) return ARMul_CANT; break;
155 /* Permissable combinations:
164 if ((CRm < 5) || (CRm > 7))
166 if (opcode_2 == 1 && CRm == 7)
170 /* Opcode_2 must be zero or one. CRm must be 1 or 2. */
171 if ( ((CRm != 0) && (CRm != 1))
172 || ((opcode_2 != 1) && (opcode_2 != 2)))
176 /* Opcode_2 must be zero or one. CRm must be 4 or 8. */
177 if ( ((CRm != 0) && (CRm != 1))
178 || ((opcode_2 != 4) && (opcode_2 != 8)))
182 /* Access not allowed. */
185 /* Access not allowed. */
188 /* Opcode_2 must be zero. CRm must be 0. */
189 if ((CRm != 0) || (opcode_2 != 0))
193 /* Opcode_2 must be 0. CRm must be 0, 3, 4, 8 or 9. */
197 if ((CRm != 0) && (CRm != 3) && (CRm != 4) && (CRm != 8) && (CRm != 9))
201 /* Opcode_2 must be zero. CRm must be 1. */
202 if ((CRm != 1) || (opcode_2 != 0))
206 /* Should never happen. */
213 /* Store a value into one of coprocessor 15's registers. */
216 write_cp15_reg (ARMul_State * state,
226 case 0: /* Cache Type. */
227 /* Writes are not allowed. */
230 case 1: /* Auxillary Control. */
231 /* Only BITS (5, 4) and BITS (1, 0) can be written. */
239 XScale_cp15_opcode_2_is_not_0_Regs [reg] = value;
246 /* Writes are not allowed. */
249 case 1: /* ARM Control. */
250 /* Only BITS (13, 11), BITS (9, 7) and BITS (2, 0) can be written.
251 BITS (31, 14) and BIT (10) write as zero, BITS (6, 3) write as one. */
255 /* Change the endianness if necessary. */
256 if ((value & ARMul_CP15_R1_ENDIAN) !=
257 (XScale_cp15_opcode_2_is_0_Regs [reg] & ARMul_CP15_R1_ENDIAN))
259 state->bigendSig = value & ARMul_CP15_R1_ENDIAN;
260 /* Force ARMulator to notice these now. */
261 state->Emulate = CHANGEMODE;
265 case 2: /* Translation Table Base. */
266 /* Only BITS (31, 14) can be written. */
270 case 3: /* Domain Access Control. */
271 /* All bits writable. */
274 case 5: /* Fault Status Register. */
275 /* BITS (10, 9) and BITS (7, 0) can be written. */
279 case 6: /* Fault Address Register. */
280 /* All bits writable. */
283 case 7: /* Cache Functions. */
284 case 8: /* TLB Operations. */
285 case 10: /* TLB Lock Down. */
289 case 9: /* Data Cache Lock. */
290 /* Only BIT (0) can be written. */
294 case 13: /* Process ID. */
295 /* Only BITS (31, 25) are writable. */
299 case 14: /* DBR0, DBR1, DBCON, IBCR0, IBCR1 */
300 /* All bits can be written. Which register is accessed is
301 dependent upon CRm. */
307 XScale_cp15_DBR1 = value;
310 XScale_cp15_DBCON = value;
313 XScale_cp15_IBCR0 = value;
316 XScale_cp15_IBCR1 = value;
323 case 15: /* Coprpcessor Access Register. */
324 /* Access is only valid if CRm == 1. */
328 /* Only BITS (13, 0) may be written. */
336 XScale_cp15_opcode_2_is_0_Regs [reg] = value;
342 /* Return the value in a cp15 register. */
345 read_cp15_reg (unsigned reg, unsigned opcode_2, unsigned CRm)
349 if (reg == 15 && CRm != 1)
356 case 3: return XScale_cp15_DBR1;
357 case 4: return XScale_cp15_DBCON;
358 case 8: return XScale_cp15_IBCR0;
359 case 9: return XScale_cp15_IBCR1;
365 return XScale_cp15_opcode_2_is_0_Regs [reg];
368 return XScale_cp15_opcode_2_is_not_0_Regs [reg];
374 XScale_cp15_LDC (ARMul_State * state, unsigned type, ARMword instr, ARMword data)
376 unsigned reg = BITS (12, 15);
379 result = check_cp15_access (state, reg, 0, 0, 0);
381 if (result == ARMul_DONE && type == ARMul_DATA)
382 write_cp15_reg (state, reg, 0, 0, data);
388 XScale_cp15_STC (ARMul_State * state, unsigned type, ARMword instr, ARMword * data)
390 unsigned reg = BITS (12, 15);
393 result = check_cp15_access (state, reg, 0, 0, 0);
395 if (result == ARMul_DONE && type == ARMul_DATA)
396 * data = read_cp15_reg (reg, 0, 0);
402 XScale_cp15_MRC (ARMul_State * state,
403 unsigned type ATTRIBUTE_UNUSED,
407 unsigned opcode_2 = BITS (5, 7);
408 unsigned CRm = BITS (0, 3);
409 unsigned reg = BITS (16, 19);
412 result = check_cp15_access (state, reg, CRm, BITS (21, 23), opcode_2);
414 if (result == ARMul_DONE)
415 * value = read_cp15_reg (reg, opcode_2, CRm);
421 XScale_cp15_MCR (ARMul_State * state,
422 unsigned type ATTRIBUTE_UNUSED,
426 unsigned opcode_2 = BITS (5, 7);
427 unsigned CRm = BITS (0, 3);
428 unsigned reg = BITS (16, 19);
431 result = check_cp15_access (state, reg, CRm, BITS (21, 23), opcode_2);
433 if (result == ARMul_DONE)
434 write_cp15_reg (state, reg, opcode_2, CRm, value);
440 XScale_cp15_read_reg (ARMul_State * state ATTRIBUTE_UNUSED,
444 /* FIXME: Not sure what to do about the alternative register set
445 here. For now default to just accessing CRm == 0 registers. */
446 * value = read_cp15_reg (reg, 0, 0);
452 XScale_cp15_write_reg (ARMul_State * state ATTRIBUTE_UNUSED,
456 /* FIXME: Not sure what to do about the alternative register set
457 here. For now default to just accessing CRm == 0 registers. */
458 write_cp15_reg (state, reg, 0, 0, value);
463 /* Check for special XScale memory access features. */
466 XScale_check_memacc (ARMul_State * state, ARMword * address, int store)
468 ARMword dbcon, r0, r1;
471 if (!state->is_XScale)
474 /* Check for PID-ification.
475 XXX BTB access support will require this test failing. */
476 r0 = (read_cp15_reg (13, 0, 0) & 0xfe000000);
477 if (r0 && (* address & 0xfe000000) == 0)
480 /* Check alignment fault enable/disable. */
481 if ((read_cp15_reg (1, 0, 0) & ARMul_CP15_R1_ALIGN) && (* address & 3))
483 /* Set the FSR and FAR.
484 Do not use XScale_set_fsr_far as this checks the DCSR register. */
485 write_cp15_reg (state, 5, 0, 0, ARMul_CP15_R5_MMU_EXCPT);
486 write_cp15_reg (state, 6, 0, 0, * address);
488 ARMul_Abort (state, ARMul_DataAbortV);
491 if (XScale_debug_moe (state, -1))
494 /* Check the data breakpoint registers. */
495 dbcon = read_cp15_reg (14, 0, 4);
496 r0 = read_cp15_reg (14, 0, 0);
497 r1 = read_cp15_reg (14, 0, 3);
498 e0 = dbcon & ARMul_CP15_DBCON_E0;
500 if (dbcon & ARMul_CP15_DBCON_M)
502 /* r1 is a inverse mask. */
503 if (e0 != 0 && ((store && e0 != 3) || (!store && e0 != 1))
504 && ((* address & ~r1) == (r0 & ~r1)))
506 XScale_debug_moe (state, ARMul_CP14_R10_MOE_DB);
507 ARMul_OSHandleSWI (state, SWI_Breakpoint);
512 if (e0 != 0 && ((store && e0 != 3) || (!store && e0 != 1))
513 && ((* address & ~3) == (r0 & ~3)))
515 XScale_debug_moe (state, ARMul_CP14_R10_MOE_DB);
516 ARMul_OSHandleSWI (state, SWI_Breakpoint);
519 e1 = (dbcon & ARMul_CP15_DBCON_E1) >> 2;
520 if (e1 != 0 && ((store && e1 != 3) || (!store && e1 != 1))
521 && ((* address & ~3) == (r1 & ~3)))
523 XScale_debug_moe (state, ARMul_CP14_R10_MOE_DB);
524 ARMul_OSHandleSWI (state, SWI_Breakpoint);
529 /* Set the XScale FSR and FAR registers. */
532 XScale_set_fsr_far (ARMul_State * state, ARMword fsr, ARMword far)
534 if (!state->is_XScale || (read_cp14_reg (10) & (1UL << 31)) == 0)
537 write_cp15_reg (state, 5, 0, 0, fsr);
538 write_cp15_reg (state, 6, 0, 0, far);
541 /* Set the XScale debug `method of entry' if it is enabled. */
544 XScale_debug_moe (ARMul_State * state, int moe)
548 if (!state->is_XScale)
551 value = read_cp14_reg (10);
552 if (value & (1UL << 31))
559 write_cp14_reg (10, value);
566 /* Coprocessor 13: Interrupt Controller and Bus Controller. */
568 /* There are two sets of registers for copro 13.
569 One set (of three registers) is available when CRm is 0
570 and the other set (of six registers) when CRm is 1. */
572 static ARMword XScale_cp13_CR0_Regs[16];
573 static ARMword XScale_cp13_CR1_Regs[16];
576 XScale_cp13_init (ARMul_State * state ATTRIBUTE_UNUSED)
582 XScale_cp13_CR0_Regs[i] = 0;
583 XScale_cp13_CR1_Regs[i] = 0;
587 /* Check an access to a register. */
590 check_cp13_access (ARMul_State * state,
596 /* Do not allow access to these registers in USER mode. */
597 if (state->Mode == USER26MODE || state->Mode == USER32MODE)
600 /* The opcodes should be zero. */
601 if ((opcode_1 != 0) || (opcode_2 != 0))
604 /* Do not allow access to these register if bit
605 13 of coprocessor 15's register 15 is zero. */
606 if (! CP_ACCESS_ALLOWED (state, 13))
609 /* Registers 0, 4 and 8 are defined when CRm == 0.
610 Registers 0, 1, 4, 5, 6, 7, 8 are defined when CRm == 1.
611 For all other CRm values undefined behaviour results. */
614 if (reg == 0 || reg == 4 || reg == 8)
619 if (reg == 0 || reg == 1 || (reg >= 4 && reg <= 8))
626 /* Store a value into one of coprocessor 13's registers. */
629 write_cp13_reg (unsigned reg, unsigned CRm, ARMword value)
637 /* Only BITS (3:0) can be written. */
642 /* No bits may be written. */
646 /* Only BITS (1:0) can be written. */
651 /* Should not happen. Ignore any writes to unimplemented registers. */
655 XScale_cp13_CR0_Regs [reg] = value;
662 /* Only BITS (30:28) and BITS (3:0) can be written.
663 BIT(31) is write ignored. */
665 value |= XScale_cp13_CR1_Regs[0] & (1UL << 31);
669 /* Only bit 0 is accecssible. */
671 value |= XScale_cp13_CR1_Regs[1] & ~ 1;
678 /* No bits can be written. */
682 /* Only BITS (7:0) can be written. */
687 /* Should not happen. Ignore any writes to unimplemented registers. */
691 XScale_cp13_CR1_Regs [reg] = value;
695 /* Should not happen. */
702 /* Return the value in a cp13 register. */
705 read_cp13_reg (unsigned reg, unsigned CRm)
708 return XScale_cp13_CR0_Regs [reg];
710 return XScale_cp13_CR1_Regs [reg];
716 XScale_cp13_LDC (ARMul_State * state, unsigned type, ARMword instr, ARMword data)
718 unsigned reg = BITS (12, 15);
721 result = check_cp13_access (state, reg, 0, 0, 0);
723 if (result == ARMul_DONE && type == ARMul_DATA)
724 write_cp13_reg (reg, 0, data);
730 XScale_cp13_STC (ARMul_State * state, unsigned type, ARMword instr, ARMword * data)
732 unsigned reg = BITS (12, 15);
735 result = check_cp13_access (state, reg, 0, 0, 0);
737 if (result == ARMul_DONE && type == ARMul_DATA)
738 * data = read_cp13_reg (reg, 0);
744 XScale_cp13_MRC (ARMul_State * state,
745 unsigned type ATTRIBUTE_UNUSED,
749 unsigned CRm = BITS (0, 3);
750 unsigned reg = BITS (16, 19);
753 result = check_cp13_access (state, reg, CRm, BITS (21, 23), BITS (5, 7));
755 if (result == ARMul_DONE)
756 * value = read_cp13_reg (reg, CRm);
762 XScale_cp13_MCR (ARMul_State * state,
763 unsigned type ATTRIBUTE_UNUSED,
767 unsigned CRm = BITS (0, 3);
768 unsigned reg = BITS (16, 19);
771 result = check_cp13_access (state, reg, CRm, BITS (21, 23), BITS (5, 7));
773 if (result == ARMul_DONE)
774 write_cp13_reg (reg, CRm, value);
780 XScale_cp13_read_reg (ARMul_State * state ATTRIBUTE_UNUSED,
784 /* FIXME: Not sure what to do about the alternative register set
785 here. For now default to just accessing CRm == 0 registers. */
786 * value = read_cp13_reg (reg, 0);
792 XScale_cp13_write_reg (ARMul_State * state ATTRIBUTE_UNUSED,
796 /* FIXME: Not sure what to do about the alternative register set
797 here. For now default to just accessing CRm == 0 registers. */
798 write_cp13_reg (reg, 0, value);
803 /* Coprocessor 14: Performance Monitoring, Clock and Power management,
806 static ARMword XScale_cp14_Regs[16];
809 XScale_cp14_init (ARMul_State * state ATTRIBUTE_UNUSED)
814 XScale_cp14_Regs[i] = 0;
817 /* Check an access to a register. */
820 check_cp14_access (ARMul_State * state,
826 /* Not allowed to access these register in USER mode. */
827 if (state->Mode == USER26MODE || state->Mode == USER32MODE)
830 /* CRm should be zero. */
834 /* OPcodes should be zero. */
835 if (opcode1 != 0 || opcode2 != 0)
838 /* Accessing registers 4 or 5 has unpredicatable results. */
839 if (reg >= 4 && reg <= 5)
845 /* Store a value into one of coprocessor 14's registers. */
848 write_cp14_reg (unsigned reg, ARMword value)
853 /* Only BITS (27:12), BITS (10:8) and BITS (6:0) can be written. */
856 /* Reset the clock counter if necessary. */
857 if (value & ARMul_CP14_R0_CLKRST)
858 XScale_cp14_Regs [1] = 0;
863 /* We should not normally reach this code. The debugger interface
864 can bypass the normal checks though, so it could happen. */
868 case 6: /* CCLKCFG */
869 /* Only BITS (3:0) can be written. */
873 case 7: /* PWRMODE */
874 /* Although BITS (1:0) can be written with non-zero values, this would
875 have the side effect of putting the processor to sleep. Thus in
876 order for the register to be read again, it would have to go into
877 ACTIVE mode, which means that any read will see these bits as zero.
879 Rather than trying to implement complex reset-to-zero-upon-read logic
880 we just override the write value with zero. */
885 /* Only BITS (31:30), BITS (23:22), BITS (20:16) and BITS (5:0) can
891 /* No writes are permitted. */
895 case 14: /* TXRXCTRL */
896 /* Only BITS (31:30) can be written. */
901 /* All bits can be written. */
905 XScale_cp14_Regs [reg] = value;
908 /* Return the value in a cp14 register. Not a static function since
909 it is used by the code to emulate the BKPT instruction in armemu.c. */
912 read_cp14_reg (unsigned reg)
914 return XScale_cp14_Regs [reg];
918 XScale_cp14_LDC (ARMul_State * state, unsigned type, ARMword instr, ARMword data)
920 unsigned reg = BITS (12, 15);
923 result = check_cp14_access (state, reg, 0, 0, 0);
925 if (result == ARMul_DONE && type == ARMul_DATA)
926 write_cp14_reg (reg, data);
932 XScale_cp14_STC (ARMul_State * state, unsigned type, ARMword instr, ARMword * data)
934 unsigned reg = BITS (12, 15);
937 result = check_cp14_access (state, reg, 0, 0, 0);
939 if (result == ARMul_DONE && type == ARMul_DATA)
940 * data = read_cp14_reg (reg);
949 unsigned type ATTRIBUTE_UNUSED,
954 unsigned reg = BITS (16, 19);
957 result = check_cp14_access (state, reg, BITS (0, 3), BITS (21, 23), BITS (5, 7));
959 if (result == ARMul_DONE)
960 * value = read_cp14_reg (reg);
969 unsigned type ATTRIBUTE_UNUSED,
974 unsigned reg = BITS (16, 19);
977 result = check_cp14_access (state, reg, BITS (0, 3), BITS (21, 23), BITS (5, 7));
979 if (result == ARMul_DONE)
980 write_cp14_reg (reg, value);
988 ARMul_State * state ATTRIBUTE_UNUSED,
993 * value = read_cp14_reg (reg);
999 XScale_cp14_write_reg
1001 ARMul_State * state ATTRIBUTE_UNUSED,
1006 write_cp14_reg (reg, value);
1011 /* Here's ARMulator's MMU definition. A few things to note:
1012 1) It has eight registers, but only two are defined.
1013 2) You can only access its registers with MCR and MRC.
1014 3) MMU Register 0 (ID) returns 0x41440110
1015 4) Register 1 only has 4 bits defined. Bits 0 to 3 are unused, bit 4
1016 controls 32/26 bit program space, bit 5 controls 32/26 bit data space,
1017 bit 6 controls late abort timimg and bit 7 controls big/little endian. */
1019 static ARMword MMUReg[8];
1022 MMUInit (ARMul_State * state)
1024 MMUReg[1] = state->prog32Sig << 4 |
1025 state->data32Sig << 5 | state->lateabtSig << 6 | state->bigendSig << 7;
1027 ARMul_ConsolePrint (state, ", MMU present");
1033 MMUMRC (ARMul_State * state ATTRIBUTE_UNUSED,
1034 unsigned type ATTRIBUTE_UNUSED,
1038 int reg = BITS (16, 19) & 7;
1041 *value = 0x41440110;
1043 *value = MMUReg[reg];
1049 MMUMCR (ARMul_State * state,
1050 unsigned type ATTRIBUTE_UNUSED,
1054 int reg = BITS (16, 19) & 7;
1056 MMUReg[reg] = value;
1062 p = state->prog32Sig;
1063 d = state->data32Sig;
1064 l = state->lateabtSig;
1065 b = state->bigendSig;
1067 state->prog32Sig = value >> 4 & 1;
1068 state->data32Sig = value >> 5 & 1;
1069 state->lateabtSig = value >> 6 & 1;
1070 state->bigendSig = value >> 7 & 1;
1072 if ( p != state->prog32Sig
1073 || d != state->data32Sig
1074 || l != state->lateabtSig
1075 || b != state->bigendSig)
1076 /* Force ARMulator to notice these now. */
1077 state->Emulate = CHANGEMODE;
1084 MMURead (ARMul_State * state ATTRIBUTE_UNUSED, unsigned reg, ARMword * value)
1087 *value = 0x41440110;
1089 *value = MMUReg[reg];
1095 MMUWrite (ARMul_State * state, unsigned reg, ARMword value)
1098 MMUReg[reg] = value;
1104 p = state->prog32Sig;
1105 d = state->data32Sig;
1106 l = state->lateabtSig;
1107 b = state->bigendSig;
1109 state->prog32Sig = value >> 4 & 1;
1110 state->data32Sig = value >> 5 & 1;
1111 state->lateabtSig = value >> 6 & 1;
1112 state->bigendSig = value >> 7 & 1;
1114 if ( p != state->prog32Sig
1115 || d != state->data32Sig
1116 || l != state->lateabtSig
1117 || b != state->bigendSig)
1118 /* Force ARMulator to notice these now. */
1119 state->Emulate = CHANGEMODE;
1126 /* What follows is the Validation Suite Coprocessor. It uses two
1127 co-processor numbers (4 and 5) and has the follwing functionality.
1128 Sixteen registers. Both co-processor nuimbers can be used in an MCR
1129 and MRC to access these registers. CP 4 can LDC and STC to and from
1130 the registers. CP 4 and CP 5 CDP 0 will busy wait for the number of
1131 cycles specified by a CP register. CP 5 CDP 1 issues a FIQ after a
1132 number of cycles (specified in a CP register), CDP 2 issues an IRQW
1133 in the same way, CDP 3 and 4 turn of the FIQ and IRQ source, and CDP 5
1134 stores a 32 bit time value in a CP register (actually it's the total
1135 number of N, S, I, C and F cyles). */
1137 static ARMword ValReg[16];
1140 ValLDC (ARMul_State * state ATTRIBUTE_UNUSED,
1145 static unsigned words;
1147 if (type != ARMul_DATA)
1151 ValReg[BITS (12, 15)] = data;
1154 /* It's a long access, get two words. */
1163 ValSTC (ARMul_State * state ATTRIBUTE_UNUSED,
1168 static unsigned words;
1170 if (type != ARMul_DATA)
1174 * data = ValReg[BITS (12, 15)];
1177 /* It's a long access, get two words. */
1186 ValMRC (ARMul_State * state ATTRIBUTE_UNUSED,
1187 unsigned type ATTRIBUTE_UNUSED,
1191 *value = ValReg[BITS (16, 19)];
1197 ValMCR (ARMul_State * state ATTRIBUTE_UNUSED,
1198 unsigned type ATTRIBUTE_UNUSED,
1202 ValReg[BITS (16, 19)] = value;
1208 ValCDP (ARMul_State * state, unsigned type, ARMword instr)
1210 static unsigned long finish = 0;
1212 if (BITS (20, 23) != 0)
1215 if (type == ARMul_FIRST)
1219 howlong = ValReg[BITS (0, 3)];
1221 /* First cycle of a busy wait. */
1222 finish = ARMul_Time (state) + howlong;
1224 return howlong == 0 ? ARMul_DONE : ARMul_BUSY;
1226 else if (type == ARMul_BUSY)
1228 if (ARMul_Time (state) >= finish)
1238 DoAFIQ (ARMul_State * state)
1240 state->NfiqSig = LOW;
1246 DoAIRQ (ARMul_State * state)
1248 state->NirqSig = LOW;
1254 IntCDP (ARMul_State * state, unsigned type, ARMword instr)
1256 static unsigned long finish;
1259 howlong = ValReg[BITS (0, 3)];
1261 switch ((int) BITS (20, 23))
1264 if (type == ARMul_FIRST)
1266 /* First cycle of a busy wait. */
1267 finish = ARMul_Time (state) + howlong;
1269 return howlong == 0 ? ARMul_DONE : ARMul_BUSY;
1271 else if (type == ARMul_BUSY)
1273 if (ARMul_Time (state) >= finish)
1282 ARMul_Abort (state, ARMul_FIQV);
1284 ARMul_ScheduleEvent (state, howlong, DoAFIQ);
1289 ARMul_Abort (state, ARMul_IRQV);
1291 ARMul_ScheduleEvent (state, howlong, DoAIRQ);
1295 state->NfiqSig = HIGH;
1300 state->NirqSig = HIGH;
1305 ValReg[BITS (0, 3)] = ARMul_Time (state);
1312 /* Install co-processor instruction handlers in this routine. */
1315 ARMul_CoProInit (ARMul_State * state)
1319 /* Initialise tham all first. */
1320 for (i = 0; i < 16; i++)
1321 ARMul_CoProDetach (state, i);
1323 /* Install CoPro Instruction handlers here.
1325 ARMul_CoProAttach (state, CP Number, Init routine, Exit routine
1326 LDC routine, STC routine, MRC routine, MCR routine,
1327 CDP routine, Read Reg routine, Write Reg routine). */
1328 if (state->is_ep9312)
1330 ARMul_CoProAttach (state, 4, NULL, NULL, DSPLDC4, DSPSTC4,
1331 DSPMRC4, DSPMCR4, DSPCDP4, NULL, NULL);
1332 ARMul_CoProAttach (state, 5, NULL, NULL, DSPLDC5, DSPSTC5,
1333 DSPMRC5, DSPMCR5, DSPCDP5, NULL, NULL);
1334 ARMul_CoProAttach (state, 6, NULL, NULL, NULL, NULL,
1335 DSPMRC6, DSPMCR6, DSPCDP6, NULL, NULL);
1339 ARMul_CoProAttach (state, 4, NULL, NULL, ValLDC, ValSTC,
1340 ValMRC, ValMCR, ValCDP, NULL, NULL);
1342 ARMul_CoProAttach (state, 5, NULL, NULL, NULL, NULL,
1343 ValMRC, ValMCR, IntCDP, NULL, NULL);
1346 if (state->is_XScale)
1348 ARMul_CoProAttach (state, 13, XScale_cp13_init, NULL,
1349 XScale_cp13_LDC, XScale_cp13_STC, XScale_cp13_MRC,
1350 XScale_cp13_MCR, NULL, XScale_cp13_read_reg,
1351 XScale_cp13_write_reg);
1353 ARMul_CoProAttach (state, 14, XScale_cp14_init, NULL,
1354 XScale_cp14_LDC, XScale_cp14_STC, XScale_cp14_MRC,
1355 XScale_cp14_MCR, NULL, XScale_cp14_read_reg,
1356 XScale_cp14_write_reg);
1358 ARMul_CoProAttach (state, 15, XScale_cp15_init, NULL,
1359 NULL, NULL, XScale_cp15_MRC, XScale_cp15_MCR,
1360 NULL, XScale_cp15_read_reg, XScale_cp15_write_reg);
1364 ARMul_CoProAttach (state, 15, MMUInit, NULL, NULL, NULL,
1365 MMUMRC, MMUMCR, NULL, MMURead, MMUWrite);
1368 /* No handlers below here. */
1370 /* Call all the initialisation routines. */
1371 for (i = 0; i < 16; i++)
1372 if (state->CPInit[i])
1373 (state->CPInit[i]) (state);
1378 /* Install co-processor finalisation routines in this routine. */
1381 ARMul_CoProExit (ARMul_State * state)
1383 register unsigned i;
1385 for (i = 0; i < 16; i++)
1386 if (state->CPExit[i])
1387 (state->CPExit[i]) (state);
1389 for (i = 0; i < 16; i++) /* Detach all handlers. */
1390 ARMul_CoProDetach (state, i);
1393 /* Routines to hook Co-processors into ARMulator. */
1396 ARMul_CoProAttach (ARMul_State * state,
1398 ARMul_CPInits * init,
1399 ARMul_CPExits * exit,
1405 ARMul_CPReads * read,
1406 ARMul_CPWrites * write)
1409 state->CPInit[number] = init;
1411 state->CPExit[number] = exit;
1413 state->LDC[number] = ldc;
1415 state->STC[number] = stc;
1417 state->MRC[number] = mrc;
1419 state->MCR[number] = mcr;
1421 state->CDP[number] = cdp;
1423 state->CPRead[number] = read;
1425 state->CPWrite[number] = write;
1429 ARMul_CoProDetach (ARMul_State * state, unsigned number)
1431 ARMul_CoProAttach (state, number, NULL, NULL,
1432 NoCoPro4R, NoCoPro4W, NoCoPro4W, NoCoPro4R,
1433 NoCoPro3R, NULL, NULL);
1435 state->CPInit[number] = NULL;
1436 state->CPExit[number] = NULL;
1437 state->CPRead[number] = NULL;
1438 state->CPWrite[number] = NULL;