1 /* armcopro.c -- co-processor interface: ARM6 Instruction Emulator.
2 Copyright (C) 1994, 2000 Advanced RISC Machines Ltd.
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
22 extern unsigned ARMul_CoProInit (ARMul_State * state);
23 extern void ARMul_CoProExit (ARMul_State * state);
24 extern void ARMul_CoProAttach (ARMul_State * state, unsigned number,
25 ARMul_CPInits * init, ARMul_CPExits * exit,
26 ARMul_LDCs * ldc, ARMul_STCs * stc,
27 ARMul_MRCs * mrc, ARMul_MCRs * mcr,
29 ARMul_CPReads * read, ARMul_CPWrites * write);
30 extern void ARMul_CoProDetach (ARMul_State * state, unsigned number);
33 /***************************************************************************\
34 * Dummy Co-processors *
35 \***************************************************************************/
37 static unsigned NoCoPro3R (ARMul_State * state, unsigned, ARMword);
38 static unsigned NoCoPro4R (ARMul_State * state, unsigned, ARMword, ARMword);
39 static unsigned NoCoPro4W (ARMul_State * state, unsigned, ARMword, ARMword *);
41 /***************************************************************************\
42 * Define Co-Processor instruction handlers here *
43 \***************************************************************************/
45 /* Here's ARMulator's MMU definition. A few things to note:
46 1) it has eight registers, but only two are defined.
47 2) you can only access its registers with MCR and MRC.
48 3) MMU Register 0 (ID) returns 0x41440110
49 4) Register 1 only has 4 bits defined. Bits 0 to 3 are unused, bit 4
50 controls 32/26 bit program space, bit 5 controls 32/26 bit data space,
51 bit 6 controls late abort timimg and bit 7 controls big/little endian.
54 static ARMword MMUReg[8];
57 MMUInit (ARMul_State * state)
59 MMUReg[1] = state->prog32Sig << 4 |
60 state->data32Sig << 5 | state->lateabtSig << 6 | state->bigendSig << 7;
61 ARMul_ConsolePrint (state, ", MMU present");
66 MMUMRC (ARMul_State * state ATTRIBUTE_UNUSED, unsigned type ATTRIBUTE_UNUSED, ARMword instr, ARMword * value)
68 int reg = BITS (16, 19) & 7;
78 MMUMCR (ARMul_State * state, unsigned type ATTRIBUTE_UNUSED, ARMword instr, ARMword value)
80 int reg = BITS (16, 19) & 7;
90 l = state->lateabtSig;
93 state->prog32Sig = value >> 4 & 1;
94 state->data32Sig = value >> 5 & 1;
95 state->lateabtSig = value >> 6 & 1;
96 state->bigendSig = value >> 7 & 1;
98 if (p != state->prog32Sig
99 || d != state->data32Sig
100 || l != state->lateabtSig
101 || b != state->bigendSig)
102 state->Emulate = CHANGEMODE; /* Force ARMulator to notice these now. */
110 MMURead (ARMul_State * state ATTRIBUTE_UNUSED, unsigned reg, ARMword * value)
115 *value = MMUReg[reg];
120 MMUWrite (ARMul_State * state, unsigned reg, ARMword value)
129 p = state->prog32Sig;
130 d = state->data32Sig;
131 l = state->lateabtSig;
132 b = state->bigendSig;
134 state->prog32Sig = value >> 4 & 1;
135 state->data32Sig = value >> 5 & 1;
136 state->lateabtSig = value >> 6 & 1;
137 state->bigendSig = value >> 7 & 1;
140 if (p != state->prog32Sig
141 || d != state->data32Sig
142 || l != state->lateabtSig
143 || b != state->bigendSig)
144 state->Emulate = CHANGEMODE; /* Force ARMulator to notice these now. */
151 /* What follows is the Validation Suite Coprocessor. It uses two
152 co-processor numbers (4 and 5) and has the follwing functionality.
153 Sixteen registers. Both co-processor nuimbers can be used in an MCR and
154 MRC to access these registers. CP 4 can LDC and STC to and from the
155 registers. CP 4 and CP 5 CDP 0 will busy wait for the number of cycles
156 specified by a CP register. CP 5 CDP 1 issues a FIQ after a number of
157 cycles (specified in a CP register), CDP 2 issues an IRQW in the same
158 way, CDP 3 and 4 turn of the FIQ and IRQ source, and CDP 5 stores a 32
159 bit time value in a CP register (actually it's the total number of N, S,
162 static ARMword ValReg[16];
165 ValLDC (ARMul_State * state ATTRIBUTE_UNUSED, unsigned type, ARMword instr, ARMword data)
167 static unsigned words;
169 if (type != ARMul_DATA)
175 { /* it's a long access, get two words */
176 ValReg[BITS (12, 15)] = data;
183 { /* get just one word */
184 ValReg[BITS (12, 15)] = data;
190 ValSTC (ARMul_State * state ATTRIBUTE_UNUSED, unsigned type, ARMword instr, ARMword * data)
192 static unsigned words;
194 if (type != ARMul_DATA)
200 { /* it's a long access, get two words */
201 *data = ValReg[BITS (12, 15)];
208 { /* get just one word */
209 *data = ValReg[BITS (12, 15)];
215 ValMRC (ARMul_State * state ATTRIBUTE_UNUSED, unsigned type ATTRIBUTE_UNUSED, ARMword instr, ARMword * value)
217 *value = ValReg[BITS (16, 19)];
222 ValMCR (ARMul_State * state ATTRIBUTE_UNUSED, unsigned type ATTRIBUTE_UNUSED, ARMword instr, ARMword value)
224 ValReg[BITS (16, 19)] = value;
229 ValCDP (ARMul_State * state, unsigned type, ARMword instr)
231 static unsigned long finish = 0;
234 howlong = ValReg[BITS (0, 3)];
235 if (BITS (20, 23) == 0)
237 if (type == ARMul_FIRST)
238 { /* First cycle of a busy wait */
239 finish = ARMul_Time (state) + howlong;
245 else if (type == ARMul_BUSY)
247 if (ARMul_Time (state) >= finish)
257 DoAFIQ (ARMul_State * state)
259 state->NfiqSig = LOW;
265 DoAIRQ (ARMul_State * state)
267 state->NirqSig = LOW;
273 IntCDP (ARMul_State * state, unsigned type, ARMword instr)
275 static unsigned long finish;
278 howlong = ValReg[BITS (0, 3)];
279 switch ((int) BITS (20, 23))
282 if (type == ARMul_FIRST)
283 { /* First cycle of a busy wait */
284 finish = ARMul_Time (state) + howlong;
290 else if (type == ARMul_BUSY)
292 if (ARMul_Time (state) >= finish)
300 ARMul_Abort (state, ARMul_FIQV);
302 ARMul_ScheduleEvent (state, howlong, DoAFIQ);
306 ARMul_Abort (state, ARMul_IRQV);
308 ARMul_ScheduleEvent (state, howlong, DoAIRQ);
311 state->NfiqSig = HIGH;
315 state->NirqSig = HIGH;
319 ValReg[BITS (0, 3)] = ARMul_Time (state);
325 /***************************************************************************\
326 * Install co-processor instruction handlers in this routine *
327 \***************************************************************************/
330 ARMul_CoProInit (ARMul_State * state)
334 for (i = 0; i < 16; i++) /* initialise tham all first */
335 ARMul_CoProDetach (state, i);
337 /* Install CoPro Instruction handlers here
339 ARMul_CoProAttach(state, CP Number, Init routine, Exit routine
340 LDC routine, STC routine, MRC routine, MCR routine,
341 CDP routine, Read Reg routine, Write Reg routine) ;
344 ARMul_CoProAttach (state, 4, NULL, NULL,
345 ValLDC, ValSTC, ValMRC, ValMCR, ValCDP, NULL, NULL);
347 ARMul_CoProAttach (state, 5, NULL, NULL,
348 NULL, NULL, ValMRC, ValMCR, IntCDP, NULL, NULL);
350 ARMul_CoProAttach (state, 15, MMUInit, NULL,
351 NULL, NULL, MMUMRC, MMUMCR, NULL, MMURead, MMUWrite);
354 /* No handlers below here */
356 for (i = 0; i < 16; i++) /* Call all the initialisation routines */
357 if (state->CPInit[i])
358 (state->CPInit[i]) (state);
362 /***************************************************************************\
363 * Install co-processor finalisation routines in this routine *
364 \***************************************************************************/
367 ARMul_CoProExit (ARMul_State * state)
371 for (i = 0; i < 16; i++)
372 if (state->CPExit[i])
373 (state->CPExit[i]) (state);
374 for (i = 0; i < 16; i++) /* Detach all handlers */
375 ARMul_CoProDetach (state, i);
378 /***************************************************************************\
379 * Routines to hook Co-processors into ARMulator *
380 \***************************************************************************/
383 ARMul_CoProAttach (ARMul_State * state, unsigned number,
384 ARMul_CPInits * init, ARMul_CPExits * exit,
385 ARMul_LDCs * ldc, ARMul_STCs * stc,
386 ARMul_MRCs * mrc, ARMul_MCRs * mcr, ARMul_CDPs * cdp,
387 ARMul_CPReads * read, ARMul_CPWrites * write)
390 state->CPInit[number] = init;
392 state->CPExit[number] = exit;
394 state->LDC[number] = ldc;
396 state->STC[number] = stc;
398 state->MRC[number] = mrc;
400 state->MCR[number] = mcr;
402 state->CDP[number] = cdp;
404 state->CPRead[number] = read;
406 state->CPWrite[number] = write;
410 ARMul_CoProDetach (ARMul_State * state, unsigned number)
412 ARMul_CoProAttach (state, number, NULL, NULL,
413 NoCoPro4R, NoCoPro4W, NoCoPro4W, NoCoPro4R,
414 NoCoPro3R, NULL, NULL);
415 state->CPInit[number] = NULL;
416 state->CPExit[number] = NULL;
417 state->CPRead[number] = NULL;
418 state->CPWrite[number] = NULL;
421 /***************************************************************************\
422 * There is no CoPro around, so Undefined Instruction trap *
423 \***************************************************************************/
426 NoCoPro3R (ARMul_State * state ATTRIBUTE_UNUSED,
427 unsigned a ATTRIBUTE_UNUSED,
428 ARMword b ATTRIBUTE_UNUSED)
435 ARMul_State * state ATTRIBUTE_UNUSED,
436 unsigned a ATTRIBUTE_UNUSED,
437 ARMword b ATTRIBUTE_UNUSED,
438 ARMword c ATTRIBUTE_UNUSED)
445 ARMul_State * state ATTRIBUTE_UNUSED,
446 unsigned a ATTRIBUTE_UNUSED,
447 ARMword b ATTRIBUTE_UNUSED,
448 ARMword * c ATTRIBUTE_UNUSED)