1 /* armcopro.c -- co-processor interface: ARM6 Instruction Emulator.
2 Copyright (C) 1994, 2000 Advanced RISC Machines Ltd.
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 /* Dummy Co-processors. */
27 NoCoPro3R (ARMul_State * state ATTRIBUTE_UNUSED,
28 unsigned a ATTRIBUTE_UNUSED,
29 ARMword b ATTRIBUTE_UNUSED)
35 NoCoPro4R (ARMul_State * state ATTRIBUTE_UNUSED,
36 unsigned a ATTRIBUTE_UNUSED,
37 ARMword b ATTRIBUTE_UNUSED,
38 ARMword c ATTRIBUTE_UNUSED)
44 NoCoPro4W (ARMul_State * state ATTRIBUTE_UNUSED,
45 unsigned a ATTRIBUTE_UNUSED,
46 ARMword b ATTRIBUTE_UNUSED,
47 ARMword * c ATTRIBUTE_UNUSED)
52 /* The XScale Co-processors. */
54 /* Coprocessor 15: System Control. */
55 static void write_cp14_reg (unsigned, ARMword);
56 static ARMword read_cp14_reg (unsigned);
58 /* There are two sets of registers for copro 15.
59 One set is available when opcode_2 is 0 and
60 the other set when opcode_2 >= 1. */
61 static ARMword XScale_cp15_opcode_2_is_0_Regs[16];
62 static ARMword XScale_cp15_opcode_2_is_not_0_Regs[16];
63 /* There are also a set of breakpoint registers
64 which are accessed via CRm instead of opcode_2. */
65 static ARMword XScale_cp15_DBR1;
66 static ARMword XScale_cp15_DBCON;
67 static ARMword XScale_cp15_IBCR0;
68 static ARMword XScale_cp15_IBCR1;
71 XScale_cp15_init (ARMul_State * state ATTRIBUTE_UNUSED)
77 XScale_cp15_opcode_2_is_0_Regs[i] = 0;
78 XScale_cp15_opcode_2_is_not_0_Regs[i] = 0;
81 /* Initialise the processor ID. */
82 XScale_cp15_opcode_2_is_0_Regs[0] = 0x69052000;
84 /* Initialise the cache type. */
85 XScale_cp15_opcode_2_is_not_0_Regs[0] = 0x0B1AA1AA;
87 /* Initialise the ARM Control Register. */
88 XScale_cp15_opcode_2_is_0_Regs[1] = 0x00000078;
91 /* Check an access to a register. */
94 check_cp15_access (ARMul_State * state,
100 /* Do not allow access to these register in USER mode. */
101 if (state->Mode == USER26MODE || state->Mode == USER32MODE)
104 /* Opcode_1should be zero. */
108 /* Different register have different access requirements. */
113 /* CRm must be 0. Opcode_2 can be anything. */
119 /* CRm must be 0. Opcode_2 must be zero. */
120 if ((CRm != 0) || (opcode_2 != 0))
124 /* Access not allowed. */
128 /* Opcode_2 must be zero. CRm must be 0. */
129 if ((CRm != 0) || (opcode_2 != 0))
133 /* Permissable combinations:
146 default: return ARMul_CANT;
147 case 6: if (CRm != 5) return ARMul_CANT; break;
148 case 5: if (CRm != 2) return ARMul_CANT; break;
149 case 4: if (CRm != 10) return ARMul_CANT; break;
150 case 1: if ((CRm != 5) && (CRm != 6) && (CRm != 10)) return ARMul_CANT; break;
151 case 0: if ((CRm < 5) || (CRm > 7)) return ARMul_CANT; break;
156 /* Permissable combinations:
165 if ((CRm < 5) || (CRm > 7))
167 if (opcode_2 == 1 && CRm == 7)
171 /* Opcode_2 must be zero or one. CRm must be 1 or 2. */
172 if ( ((CRm != 0) && (CRm != 1))
173 || ((opcode_2 != 1) && (opcode_2 != 2)))
177 /* Opcode_2 must be zero or one. CRm must be 4 or 8. */
178 if ( ((CRm != 0) && (CRm != 1))
179 || ((opcode_2 != 4) && (opcode_2 != 8)))
183 /* Access not allowed. */
186 /* Access not allowed. */
189 /* Opcode_2 must be zero. CRm must be 0. */
190 if ((CRm != 0) || (opcode_2 != 0))
194 /* Opcode_2 must be 0. CRm must be 0, 3, 4, 8 or 9. */
198 if ((CRm != 0) && (CRm != 3) && (CRm != 4) && (CRm != 8) && (CRm != 9))
202 /* Opcode_2 must be zero. CRm must be 1. */
203 if ((CRm != 1) || (opcode_2 != 0))
207 /* Should never happen. */
214 /* Store a value into one of coprocessor 15's registers. */
217 write_cp15_reg (ARMul_State * state,
227 case 0: /* Cache Type. */
228 /* Writes are not allowed. */
231 case 1: /* Auxillary Control. */
232 /* Only BITS (5, 4) and BITS (1, 0) can be written. */
240 XScale_cp15_opcode_2_is_not_0_Regs [reg] = value;
247 /* Writes are not allowed. */
250 case 1: /* ARM Control. */
251 /* Only BITS (13, 11), BITS (9, 7) and BITS (2, 0) can be written.
252 BITS (31, 14) and BIT (10) write as zero, BITS (6, 3) write as one. */
256 /* Change the endianness if necessary. */
257 if ((value & ARMul_CP15_R1_ENDIAN) !=
258 (XScale_cp15_opcode_2_is_0_Regs [reg] & ARMul_CP15_R1_ENDIAN))
260 state->bigendSig = value & ARMul_CP15_R1_ENDIAN;
261 /* Force ARMulator to notice these now. */
262 state->Emulate = CHANGEMODE;
266 case 2: /* Translation Table Base. */
267 /* Only BITS (31, 14) can be written. */
271 case 3: /* Domain Access Control. */
272 /* All bits writable. */
275 case 5: /* Fault Status Register. */
276 /* BITS (10, 9) and BITS (7, 0) can be written. */
280 case 6: /* Fault Address Register. */
281 /* All bits writable. */
284 case 7: /* Cache Functions. */
285 case 8: /* TLB Operations. */
286 case 10: /* TLB Lock Down. */
290 case 9: /* Data Cache Lock. */
291 /* Only BIT (0) can be written. */
295 case 13: /* Process ID. */
296 /* Only BITS (31, 25) are writable. */
300 case 14: /* DBR0, DBR1, DBCON, IBCR0, IBCR1 */
301 /* All bits can be written. Which register is accessed is
302 dependent upon CRm. */
308 XScale_cp15_DBR1 = value;
311 XScale_cp15_DBCON = value;
314 XScale_cp15_IBCR0 = value;
317 XScale_cp15_IBCR1 = value;
324 case 15: /* Coprpcessor Access Register. */
325 /* Access is only valid if CRm == 1. */
329 /* Only BITS (13, 0) may be written. */
337 XScale_cp15_opcode_2_is_0_Regs [reg] = value;
343 /* Return the value in a cp15 register. */
346 read_cp15_reg (unsigned reg, unsigned opcode_2, unsigned CRm)
350 if (reg == 15 && CRm != 1)
357 case 3: return XScale_cp15_DBR1;
358 case 4: return XScale_cp15_DBCON;
359 case 8: return XScale_cp15_IBCR0;
360 case 9: return XScale_cp15_IBCR1;
366 return XScale_cp15_opcode_2_is_0_Regs [reg];
369 return XScale_cp15_opcode_2_is_not_0_Regs [reg];
375 XScale_cp15_LDC (ARMul_State * state, unsigned type, ARMword instr, ARMword data)
377 unsigned reg = BITS (12, 15);
380 result = check_cp15_access (state, reg, 0, 0, 0);
382 if (result == ARMul_DONE && type == ARMul_DATA)
383 write_cp15_reg (state, reg, 0, 0, data);
389 XScale_cp15_STC (ARMul_State * state, unsigned type, ARMword instr, ARMword * data)
391 unsigned reg = BITS (12, 15);
394 result = check_cp15_access (state, reg, 0, 0, 0);
396 if (result == ARMul_DONE && type == ARMul_DATA)
397 * data = read_cp15_reg (reg, 0, 0);
403 XScale_cp15_MRC (ARMul_State * state,
404 unsigned type ATTRIBUTE_UNUSED,
408 unsigned opcode_2 = BITS (5, 7);
409 unsigned CRm = BITS (0, 3);
410 unsigned reg = BITS (16, 19);
413 result = check_cp15_access (state, reg, CRm, BITS (21, 23), opcode_2);
415 if (result == ARMul_DONE)
416 * value = read_cp15_reg (reg, opcode_2, CRm);
422 XScale_cp15_MCR (ARMul_State * state,
423 unsigned type ATTRIBUTE_UNUSED,
427 unsigned opcode_2 = BITS (5, 7);
428 unsigned CRm = BITS (0, 3);
429 unsigned reg = BITS (16, 19);
432 result = check_cp15_access (state, reg, CRm, BITS (21, 23), opcode_2);
434 if (result == ARMul_DONE)
435 write_cp15_reg (state, reg, opcode_2, CRm, value);
441 XScale_cp15_read_reg (ARMul_State * state ATTRIBUTE_UNUSED,
445 /* FIXME: Not sure what to do about the alternative register set
446 here. For now default to just accessing CRm == 0 registers. */
447 * value = read_cp15_reg (reg, 0, 0);
453 XScale_cp15_write_reg (ARMul_State * state ATTRIBUTE_UNUSED,
457 /* FIXME: Not sure what to do about the alternative register set
458 here. For now default to just accessing CRm == 0 registers. */
459 write_cp15_reg (state, reg, 0, 0, value);
464 /* Check for special XScale memory access features. */
467 XScale_check_memacc (ARMul_State * state, ARMword * address, int store)
469 ARMword dbcon, r0, r1;
472 if (!state->is_XScale)
475 /* Check for PID-ification.
476 XXX BTB access support will require this test failing. */
477 r0 = (read_cp15_reg (13, 0, 0) & 0xfe000000);
478 if (r0 && (* address & 0xfe000000) == 0)
481 /* Check alignment fault enable/disable. */
482 if ((read_cp15_reg (1, 0, 0) & ARMul_CP15_R1_ALIGN) && (* address & 3))
484 /* Set the FSR and FAR.
485 Do not use XScale_set_fsr_far as this checks the DCSR register. */
486 write_cp15_reg (state, 5, 0, 0, ARMul_CP15_R5_MMU_EXCPT);
487 write_cp15_reg (state, 6, 0, 0, * address);
489 ARMul_Abort (state, ARMul_DataAbortV);
492 if (XScale_debug_moe (state, -1))
495 /* Check the data breakpoint registers. */
496 dbcon = read_cp15_reg (14, 0, 4);
497 r0 = read_cp15_reg (14, 0, 0);
498 r1 = read_cp15_reg (14, 0, 3);
499 e0 = dbcon & ARMul_CP15_DBCON_E0;
501 if (dbcon & ARMul_CP15_DBCON_M)
503 /* r1 is a inverse mask. */
504 if (e0 != 0 && ((store && e0 != 3) || (!store && e0 != 1))
505 && ((* address & ~r1) == (r0 & ~r1)))
507 XScale_debug_moe (state, ARMul_CP14_R10_MOE_DB);
508 ARMul_OSHandleSWI (state, SWI_Breakpoint);
513 if (e0 != 0 && ((store && e0 != 3) || (!store && e0 != 1))
514 && ((* address & ~3) == (r0 & ~3)))
516 XScale_debug_moe (state, ARMul_CP14_R10_MOE_DB);
517 ARMul_OSHandleSWI (state, SWI_Breakpoint);
520 e1 = (dbcon & ARMul_CP15_DBCON_E1) >> 2;
521 if (e1 != 0 && ((store && e1 != 3) || (!store && e1 != 1))
522 && ((* address & ~3) == (r1 & ~3)))
524 XScale_debug_moe (state, ARMul_CP14_R10_MOE_DB);
525 ARMul_OSHandleSWI (state, SWI_Breakpoint);
530 /* Set the XScale FSR and FAR registers. */
533 XScale_set_fsr_far (ARMul_State * state, ARMword fsr, ARMword far)
535 if (!state->is_XScale || (read_cp14_reg (10) & (1UL << 31)) == 0)
538 write_cp15_reg (state, 5, 0, 0, fsr);
539 write_cp15_reg (state, 6, 0, 0, far);
542 /* Set the XScale debug `method of entry' if it is enabled. */
545 XScale_debug_moe (ARMul_State * state, int moe)
549 if (!state->is_XScale)
552 value = read_cp14_reg (10);
553 if (value & (1UL << 31))
560 write_cp14_reg (10, value);
567 /* Coprocessor 13: Interrupt Controller and Bus Controller. */
569 /* There are two sets of registers for copro 13.
570 One set (of three registers) is available when CRm is 0
571 and the other set (of six registers) when CRm is 1. */
573 static ARMword XScale_cp13_CR0_Regs[16];
574 static ARMword XScale_cp13_CR1_Regs[16];
577 XScale_cp13_init (ARMul_State * state ATTRIBUTE_UNUSED)
583 XScale_cp13_CR0_Regs[i] = 0;
584 XScale_cp13_CR1_Regs[i] = 0;
588 /* Check an access to a register. */
591 check_cp13_access (ARMul_State * state,
597 /* Do not allow access to these registers in USER mode. */
598 if (state->Mode == USER26MODE || state->Mode == USER32MODE)
601 /* The opcodes should be zero. */
602 if ((opcode_1 != 0) || (opcode_2 != 0))
605 /* Do not allow access to these register if bit
606 13 of coprocessor 15's register 15 is zero. */
607 if (! CP_ACCESS_ALLOWED (state, 13))
610 /* Registers 0, 4 and 8 are defined when CRm == 0.
611 Registers 0, 1, 4, 5, 6, 7, 8 are defined when CRm == 1.
612 For all other CRm values undefined behaviour results. */
615 if (reg == 0 || reg == 4 || reg == 8)
620 if (reg == 0 || reg == 1 || (reg >= 4 && reg <= 8))
627 /* Store a value into one of coprocessor 13's registers. */
630 write_cp13_reg (unsigned reg, unsigned CRm, ARMword value)
638 /* Only BITS (3:0) can be written. */
643 /* No bits may be written. */
647 /* Only BITS (1:0) can be written. */
652 /* Should not happen. Ignore any writes to unimplemented registers. */
656 XScale_cp13_CR0_Regs [reg] = value;
663 /* Only BITS (30:28) and BITS (3:0) can be written.
664 BIT(31) is write ignored. */
666 value |= XScale_cp13_CR1_Regs[0] & (1UL << 31);
670 /* Only bit 0 is accecssible. */
672 value |= XScale_cp13_CR1_Regs[1] & ~ 1;
679 /* No bits can be written. */
683 /* Only BITS (7:0) can be written. */
688 /* Should not happen. Ignore any writes to unimplemented registers. */
692 XScale_cp13_CR1_Regs [reg] = value;
696 /* Should not happen. */
703 /* Return the value in a cp13 register. */
706 read_cp13_reg (unsigned reg, unsigned CRm)
709 return XScale_cp13_CR0_Regs [reg];
711 return XScale_cp13_CR1_Regs [reg];
717 XScale_cp13_LDC (ARMul_State * state, unsigned type, ARMword instr, ARMword data)
719 unsigned reg = BITS (12, 15);
722 result = check_cp13_access (state, reg, 0, 0, 0);
724 if (result == ARMul_DONE && type == ARMul_DATA)
725 write_cp13_reg (reg, 0, data);
731 XScale_cp13_STC (ARMul_State * state, unsigned type, ARMword instr, ARMword * data)
733 unsigned reg = BITS (12, 15);
736 result = check_cp13_access (state, reg, 0, 0, 0);
738 if (result == ARMul_DONE && type == ARMul_DATA)
739 * data = read_cp13_reg (reg, 0);
745 XScale_cp13_MRC (ARMul_State * state,
746 unsigned type ATTRIBUTE_UNUSED,
750 unsigned CRm = BITS (0, 3);
751 unsigned reg = BITS (16, 19);
754 result = check_cp13_access (state, reg, CRm, BITS (21, 23), BITS (5, 7));
756 if (result == ARMul_DONE)
757 * value = read_cp13_reg (reg, CRm);
763 XScale_cp13_MCR (ARMul_State * state,
764 unsigned type ATTRIBUTE_UNUSED,
768 unsigned CRm = BITS (0, 3);
769 unsigned reg = BITS (16, 19);
772 result = check_cp13_access (state, reg, CRm, BITS (21, 23), BITS (5, 7));
774 if (result == ARMul_DONE)
775 write_cp13_reg (reg, CRm, value);
781 XScale_cp13_read_reg (ARMul_State * state ATTRIBUTE_UNUSED,
785 /* FIXME: Not sure what to do about the alternative register set
786 here. For now default to just accessing CRm == 0 registers. */
787 * value = read_cp13_reg (reg, 0);
793 XScale_cp13_write_reg (ARMul_State * state ATTRIBUTE_UNUSED,
797 /* FIXME: Not sure what to do about the alternative register set
798 here. For now default to just accessing CRm == 0 registers. */
799 write_cp13_reg (reg, 0, value);
804 /* Coprocessor 14: Performance Monitoring, Clock and Power management,
807 static ARMword XScale_cp14_Regs[16];
810 XScale_cp14_init (ARMul_State * state ATTRIBUTE_UNUSED)
815 XScale_cp14_Regs[i] = 0;
818 /* Check an access to a register. */
821 check_cp14_access (ARMul_State * state,
827 /* Not allowed to access these register in USER mode. */
828 if (state->Mode == USER26MODE || state->Mode == USER32MODE)
831 /* CRm should be zero. */
835 /* OPcodes should be zero. */
836 if (opcode1 != 0 || opcode2 != 0)
839 /* Accessing registers 4 or 5 has unpredicatable results. */
840 if (reg >= 4 && reg <= 5)
846 /* Store a value into one of coprocessor 14's registers. */
849 write_cp14_reg (unsigned reg, ARMword value)
854 /* Only BITS (27:12), BITS (10:8) and BITS (6:0) can be written. */
857 /* Reset the clock counter if necessary. */
858 if (value & ARMul_CP14_R0_CLKRST)
859 XScale_cp14_Regs [1] = 0;
864 /* We should not normally reach this code. The debugger interface
865 can bypass the normal checks though, so it could happen. */
869 case 6: /* CCLKCFG */
870 /* Only BITS (3:0) can be written. */
874 case 7: /* PWRMODE */
875 /* Although BITS (1:0) can be written with non-zero values, this would
876 have the side effect of putting the processor to sleep. Thus in
877 order for the register to be read again, it would have to go into
878 ACTIVE mode, which means that any read will see these bits as zero.
880 Rather than trying to implement complex reset-to-zero-upon-read logic
881 we just override the write value with zero. */
886 /* Only BITS (31:30), BITS (23:22), BITS (20:16) and BITS (5:0) can
892 /* No writes are permitted. */
896 case 14: /* TXRXCTRL */
897 /* Only BITS (31:30) can be written. */
902 /* All bits can be written. */
906 XScale_cp14_Regs [reg] = value;
909 /* Return the value in a cp14 register. Not a static function since
910 it is used by the code to emulate the BKPT instruction in armemu.c. */
913 read_cp14_reg (unsigned reg)
915 return XScale_cp14_Regs [reg];
919 XScale_cp14_LDC (ARMul_State * state, unsigned type, ARMword instr, ARMword data)
921 unsigned reg = BITS (12, 15);
924 result = check_cp14_access (state, reg, 0, 0, 0);
926 if (result == ARMul_DONE && type == ARMul_DATA)
927 write_cp14_reg (reg, data);
933 XScale_cp14_STC (ARMul_State * state, unsigned type, ARMword instr, ARMword * data)
935 unsigned reg = BITS (12, 15);
938 result = check_cp14_access (state, reg, 0, 0, 0);
940 if (result == ARMul_DONE && type == ARMul_DATA)
941 * data = read_cp14_reg (reg);
950 unsigned type ATTRIBUTE_UNUSED,
955 unsigned reg = BITS (16, 19);
958 result = check_cp14_access (state, reg, BITS (0, 3), BITS (21, 23), BITS (5, 7));
960 if (result == ARMul_DONE)
961 * value = read_cp14_reg (reg);
970 unsigned type ATTRIBUTE_UNUSED,
975 unsigned reg = BITS (16, 19);
978 result = check_cp14_access (state, reg, BITS (0, 3), BITS (21, 23), BITS (5, 7));
980 if (result == ARMul_DONE)
981 write_cp14_reg (reg, value);
989 ARMul_State * state ATTRIBUTE_UNUSED,
994 * value = read_cp14_reg (reg);
1000 XScale_cp14_write_reg
1002 ARMul_State * state ATTRIBUTE_UNUSED,
1007 write_cp14_reg (reg, value);
1012 /* Here's ARMulator's MMU definition. A few things to note:
1013 1) It has eight registers, but only two are defined.
1014 2) You can only access its registers with MCR and MRC.
1015 3) MMU Register 0 (ID) returns 0x41440110
1016 4) Register 1 only has 4 bits defined. Bits 0 to 3 are unused, bit 4
1017 controls 32/26 bit program space, bit 5 controls 32/26 bit data space,
1018 bit 6 controls late abort timimg and bit 7 controls big/little endian. */
1020 static ARMword MMUReg[8];
1023 MMUInit (ARMul_State * state)
1025 MMUReg[1] = state->prog32Sig << 4 |
1026 state->data32Sig << 5 | state->lateabtSig << 6 | state->bigendSig << 7;
1028 ARMul_ConsolePrint (state, ", MMU present");
1034 MMUMRC (ARMul_State * state ATTRIBUTE_UNUSED,
1035 unsigned type ATTRIBUTE_UNUSED,
1039 int reg = BITS (16, 19) & 7;
1042 *value = 0x41440110;
1044 *value = MMUReg[reg];
1050 MMUMCR (ARMul_State * state,
1051 unsigned type ATTRIBUTE_UNUSED,
1055 int reg = BITS (16, 19) & 7;
1057 MMUReg[reg] = value;
1063 p = state->prog32Sig;
1064 d = state->data32Sig;
1065 l = state->lateabtSig;
1066 b = state->bigendSig;
1068 state->prog32Sig = value >> 4 & 1;
1069 state->data32Sig = value >> 5 & 1;
1070 state->lateabtSig = value >> 6 & 1;
1071 state->bigendSig = value >> 7 & 1;
1073 if ( p != state->prog32Sig
1074 || d != state->data32Sig
1075 || l != state->lateabtSig
1076 || b != state->bigendSig)
1077 /* Force ARMulator to notice these now. */
1078 state->Emulate = CHANGEMODE;
1085 MMURead (ARMul_State * state ATTRIBUTE_UNUSED, unsigned reg, ARMword * value)
1088 *value = 0x41440110;
1090 *value = MMUReg[reg];
1096 MMUWrite (ARMul_State * state, unsigned reg, ARMword value)
1099 MMUReg[reg] = value;
1105 p = state->prog32Sig;
1106 d = state->data32Sig;
1107 l = state->lateabtSig;
1108 b = state->bigendSig;
1110 state->prog32Sig = value >> 4 & 1;
1111 state->data32Sig = value >> 5 & 1;
1112 state->lateabtSig = value >> 6 & 1;
1113 state->bigendSig = value >> 7 & 1;
1115 if ( p != state->prog32Sig
1116 || d != state->data32Sig
1117 || l != state->lateabtSig
1118 || b != state->bigendSig)
1119 /* Force ARMulator to notice these now. */
1120 state->Emulate = CHANGEMODE;
1127 /* What follows is the Validation Suite Coprocessor. It uses two
1128 co-processor numbers (4 and 5) and has the follwing functionality.
1129 Sixteen registers. Both co-processor nuimbers can be used in an MCR
1130 and MRC to access these registers. CP 4 can LDC and STC to and from
1131 the registers. CP 4 and CP 5 CDP 0 will busy wait for the number of
1132 cycles specified by a CP register. CP 5 CDP 1 issues a FIQ after a
1133 number of cycles (specified in a CP register), CDP 2 issues an IRQW
1134 in the same way, CDP 3 and 4 turn of the FIQ and IRQ source, and CDP 5
1135 stores a 32 bit time value in a CP register (actually it's the total
1136 number of N, S, I, C and F cyles). */
1138 static ARMword ValReg[16];
1141 ValLDC (ARMul_State * state ATTRIBUTE_UNUSED,
1146 static unsigned words;
1148 if (type != ARMul_DATA)
1152 ValReg[BITS (12, 15)] = data;
1155 /* It's a long access, get two words. */
1164 ValSTC (ARMul_State * state ATTRIBUTE_UNUSED,
1169 static unsigned words;
1171 if (type != ARMul_DATA)
1175 * data = ValReg[BITS (12, 15)];
1178 /* It's a long access, get two words. */
1187 ValMRC (ARMul_State * state ATTRIBUTE_UNUSED,
1188 unsigned type ATTRIBUTE_UNUSED,
1192 *value = ValReg[BITS (16, 19)];
1198 ValMCR (ARMul_State * state ATTRIBUTE_UNUSED,
1199 unsigned type ATTRIBUTE_UNUSED,
1203 ValReg[BITS (16, 19)] = value;
1209 ValCDP (ARMul_State * state, unsigned type, ARMword instr)
1211 static unsigned long finish = 0;
1213 if (BITS (20, 23) != 0)
1216 if (type == ARMul_FIRST)
1220 howlong = ValReg[BITS (0, 3)];
1222 /* First cycle of a busy wait. */
1223 finish = ARMul_Time (state) + howlong;
1225 return howlong == 0 ? ARMul_DONE : ARMul_BUSY;
1227 else if (type == ARMul_BUSY)
1229 if (ARMul_Time (state) >= finish)
1239 DoAFIQ (ARMul_State * state)
1241 state->NfiqSig = LOW;
1247 DoAIRQ (ARMul_State * state)
1249 state->NirqSig = LOW;
1255 IntCDP (ARMul_State * state, unsigned type, ARMword instr)
1257 static unsigned long finish;
1260 howlong = ValReg[BITS (0, 3)];
1262 switch ((int) BITS (20, 23))
1265 if (type == ARMul_FIRST)
1267 /* First cycle of a busy wait. */
1268 finish = ARMul_Time (state) + howlong;
1270 return howlong == 0 ? ARMul_DONE : ARMul_BUSY;
1272 else if (type == ARMul_BUSY)
1274 if (ARMul_Time (state) >= finish)
1283 ARMul_Abort (state, ARMul_FIQV);
1285 ARMul_ScheduleEvent (state, howlong, DoAFIQ);
1290 ARMul_Abort (state, ARMul_IRQV);
1292 ARMul_ScheduleEvent (state, howlong, DoAIRQ);
1296 state->NfiqSig = HIGH;
1301 state->NirqSig = HIGH;
1306 ValReg[BITS (0, 3)] = ARMul_Time (state);
1313 /* Install co-processor instruction handlers in this routine. */
1316 ARMul_CoProInit (ARMul_State * state)
1320 /* Initialise tham all first. */
1321 for (i = 0; i < 16; i++)
1322 ARMul_CoProDetach (state, i);
1324 /* Install CoPro Instruction handlers here.
1326 ARMul_CoProAttach (state, CP Number, Init routine, Exit routine
1327 LDC routine, STC routine, MRC routine, MCR routine,
1328 CDP routine, Read Reg routine, Write Reg routine). */
1329 if (state->is_ep9312)
1331 ARMul_CoProAttach (state, 4, NULL, NULL, DSPLDC4, DSPSTC4,
1332 DSPMRC4, DSPMCR4, DSPCDP4, NULL, NULL);
1333 ARMul_CoProAttach (state, 5, NULL, NULL, DSPLDC5, DSPSTC5,
1334 DSPMRC5, DSPMCR5, DSPCDP5, NULL, NULL);
1335 ARMul_CoProAttach (state, 6, NULL, NULL, NULL, NULL,
1336 DSPMRC6, DSPMCR6, DSPCDP6, NULL, NULL);
1340 ARMul_CoProAttach (state, 4, NULL, NULL, ValLDC, ValSTC,
1341 ValMRC, ValMCR, ValCDP, NULL, NULL);
1343 ARMul_CoProAttach (state, 5, NULL, NULL, NULL, NULL,
1344 ValMRC, ValMCR, IntCDP, NULL, NULL);
1347 if (state->is_XScale)
1349 ARMul_CoProAttach (state, 13, XScale_cp13_init, NULL,
1350 XScale_cp13_LDC, XScale_cp13_STC, XScale_cp13_MRC,
1351 XScale_cp13_MCR, NULL, XScale_cp13_read_reg,
1352 XScale_cp13_write_reg);
1354 ARMul_CoProAttach (state, 14, XScale_cp14_init, NULL,
1355 XScale_cp14_LDC, XScale_cp14_STC, XScale_cp14_MRC,
1356 XScale_cp14_MCR, NULL, XScale_cp14_read_reg,
1357 XScale_cp14_write_reg);
1359 ARMul_CoProAttach (state, 15, XScale_cp15_init, NULL,
1360 NULL, NULL, XScale_cp15_MRC, XScale_cp15_MCR,
1361 NULL, XScale_cp15_read_reg, XScale_cp15_write_reg);
1365 ARMul_CoProAttach (state, 15, MMUInit, NULL, NULL, NULL,
1366 MMUMRC, MMUMCR, NULL, MMURead, MMUWrite);
1369 if (state->is_iWMMXt)
1371 ARMul_CoProAttach (state, 0, NULL, NULL, IwmmxtLDC, IwmmxtSTC,
1372 NULL, NULL, IwmmxtCDP, NULL, NULL);
1374 ARMul_CoProAttach (state, 1, NULL, NULL, NULL, NULL,
1375 IwmmxtMRC, IwmmxtMCR, IwmmxtCDP, NULL, NULL);
1378 /* No handlers below here. */
1380 /* Call all the initialisation routines. */
1381 for (i = 0; i < 16; i++)
1382 if (state->CPInit[i])
1383 (state->CPInit[i]) (state);
1388 /* Install co-processor finalisation routines in this routine. */
1391 ARMul_CoProExit (ARMul_State * state)
1393 register unsigned i;
1395 for (i = 0; i < 16; i++)
1396 if (state->CPExit[i])
1397 (state->CPExit[i]) (state);
1399 for (i = 0; i < 16; i++) /* Detach all handlers. */
1400 ARMul_CoProDetach (state, i);
1403 /* Routines to hook Co-processors into ARMulator. */
1406 ARMul_CoProAttach (ARMul_State * state,
1408 ARMul_CPInits * init,
1409 ARMul_CPExits * exit,
1415 ARMul_CPReads * read,
1416 ARMul_CPWrites * write)
1419 state->CPInit[number] = init;
1421 state->CPExit[number] = exit;
1423 state->LDC[number] = ldc;
1425 state->STC[number] = stc;
1427 state->MRC[number] = mrc;
1429 state->MCR[number] = mcr;
1431 state->CDP[number] = cdp;
1433 state->CPRead[number] = read;
1435 state->CPWrite[number] = write;
1439 ARMul_CoProDetach (ARMul_State * state, unsigned number)
1441 ARMul_CoProAttach (state, number, NULL, NULL,
1442 NoCoPro4R, NoCoPro4W, NoCoPro4W, NoCoPro4R,
1443 NoCoPro3R, NULL, NULL);
1445 state->CPInit[number] = NULL;
1446 state->CPExit[number] = NULL;
1447 state->CPRead[number] = NULL;
1448 state->CPWrite[number] = NULL;