1 /* armcopro.c -- co-processor interface: ARM6 Instruction Emulator.
2 Copyright (C) 1994, 2000 Advanced RISC Machines Ltd.
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
23 /* Dummy Co-processors. */
26 NoCoPro3R (ARMul_State * state ATTRIBUTE_UNUSED,
27 unsigned a ATTRIBUTE_UNUSED,
28 ARMword b ATTRIBUTE_UNUSED)
34 NoCoPro4R (ARMul_State * state ATTRIBUTE_UNUSED,
35 unsigned a ATTRIBUTE_UNUSED,
36 ARMword b ATTRIBUTE_UNUSED,
37 ARMword c ATTRIBUTE_UNUSED)
43 NoCoPro4W (ARMul_State * state ATTRIBUTE_UNUSED,
44 unsigned a ATTRIBUTE_UNUSED,
45 ARMword b ATTRIBUTE_UNUSED,
46 ARMword * c ATTRIBUTE_UNUSED)
51 /* The XScale Co-processors. */
53 /* Coprocessor 15: System Control. */
54 static void write_cp14_reg (unsigned, ARMword);
55 static ARMword read_cp14_reg (unsigned);
57 /* There are two sets of registers for copro 15.
58 One set is available when opcode_2 is 0 and
59 the other set when opcode_2 >= 1. */
60 static ARMword XScale_cp15_opcode_2_is_0_Regs[16];
61 static ARMword XScale_cp15_opcode_2_is_not_0_Regs[16];
62 /* There are also a set of breakpoint registers
63 which are accessed via CRm instead of opcode_2. */
64 static ARMword XScale_cp15_DBR1;
65 static ARMword XScale_cp15_DBCON;
66 static ARMword XScale_cp15_IBCR0;
67 static ARMword XScale_cp15_IBCR1;
70 XScale_cp15_init (ARMul_State * state ATTRIBUTE_UNUSED)
76 XScale_cp15_opcode_2_is_0_Regs[i] = 0;
77 XScale_cp15_opcode_2_is_not_0_Regs[i] = 0;
80 /* Initialise the processor ID. */
81 XScale_cp15_opcode_2_is_0_Regs[0] = 0x69052000;
83 /* Initialise the cache type. */
84 XScale_cp15_opcode_2_is_not_0_Regs[0] = 0x0B1AA1AA;
86 /* Initialise the ARM Control Register. */
87 XScale_cp15_opcode_2_is_0_Regs[1] = 0x00000078;
90 /* Check an access to a register. */
93 check_cp15_access (ARMul_State * state,
99 /* Do not allow access to these register in USER mode. */
100 if (state->Mode == USER26MODE || state->Mode == USER32MODE)
103 /* Opcode_1should be zero. */
107 /* Different register have different access requirements. */
112 /* CRm must be 0. Opcode_2 can be anything. */
118 /* CRm must be 0. Opcode_2 must be zero. */
119 if ((CRm != 0) || (opcode_2 != 0))
123 /* Access not allowed. */
127 /* Opcode_2 must be zero. CRm must be 0. */
128 if ((CRm != 0) || (opcode_2 != 0))
132 /* Permissable combinations:
145 default: return ARMul_CANT;
146 case 6: if (CRm != 5) return ARMul_CANT; break;
147 case 5: if (CRm != 2) return ARMul_CANT; break;
148 case 4: if (CRm != 10) return ARMul_CANT; break;
149 case 1: if ((CRm != 5) && (CRm != 6) && (CRm != 10)) return ARMul_CANT; break;
150 case 0: if ((CRm < 5) || (CRm > 7)) return ARMul_CANT; break;
155 /* Permissable combinations:
164 if ((CRm < 5) || (CRm > 7))
166 if (opcode_2 == 1 && CRm == 7)
170 /* Opcode_2 must be zero or one. CRm must be 1 or 2. */
171 if ( ((CRm != 0) && (CRm != 1))
172 || ((opcode_2 != 1) && (opcode_2 != 2)))
176 /* Opcode_2 must be zero or one. CRm must be 4 or 8. */
177 if ( ((CRm != 0) && (CRm != 1))
178 || ((opcode_2 != 4) && (opcode_2 != 8)))
182 /* Access not allowed. */
185 /* Access not allowed. */
188 /* Opcode_2 must be zero. CRm must be 0. */
189 if ((CRm != 0) || (opcode_2 != 0))
193 /* Opcode_2 must be 0. CRm must be 0, 3, 4, 8 or 9. */
197 if ((CRm != 0) && (CRm != 3) && (CRm != 4) && (CRm != 8) && (CRm != 9))
201 /* Opcode_2 must be zero. CRm must be 1. */
202 if ((CRm != 1) || (opcode_2 != 0))
206 /* Should never happen. */
213 /* Store a value into one of coprocessor 15's registers. */
216 write_cp15_reg (ARMul_State * state,
226 case 0: /* Cache Type. */
227 /* Writes are not allowed. */
230 case 1: /* Auxillary Control. */
231 /* Only BITS (5, 4) and BITS (1, 0) can be written. */
239 XScale_cp15_opcode_2_is_not_0_Regs [reg] = value;
246 /* Writes are not allowed. */
249 case 1: /* ARM Control. */
250 /* Only BITS (13, 11), BITS (9, 7) and BITS (2, 0) can be written.
251 BITS (31, 14) and BIT (10) write as zero, BITS (6, 3) write as one. */
255 /* Change the endianness if necessary. */
256 if ((value & ARMul_CP15_R1_ENDIAN) !=
257 (XScale_cp15_opcode_2_is_0_Regs [reg] & ARMul_CP15_R1_ENDIAN))
259 state->bigendSig = value & ARMul_CP15_R1_ENDIAN;
260 /* Force ARMulator to notice these now. */
261 state->Emulate = CHANGEMODE;
265 case 2: /* Translation Table Base. */
266 /* Only BITS (31, 14) can be written. */
270 case 3: /* Domain Access Control. */
271 /* All bits writable. */
274 case 5: /* Fault Status Register. */
275 /* BITS (10, 9) and BITS (7, 0) can be written. */
279 case 6: /* Fault Address Register. */
280 /* All bits writable. */
283 case 7: /* Cache Functions. */
284 case 8: /* TLB Operations. */
285 case 10: /* TLB Lock Down. */
289 case 9: /* Data Cache Lock. */
290 /* Only BIT (0) can be written. */
294 case 13: /* Process ID. */
295 /* Only BITS (31, 25) are writable. */
299 case 14: /* DBR0, DBR1, DBCON, IBCR0, IBCR1 */
300 /* All bits can be written. Which register is accessed is
301 dependent upon CRm. */
307 XScale_cp15_DBR1 = value;
310 XScale_cp15_DBCON = value;
313 XScale_cp15_IBCR0 = value;
316 XScale_cp15_IBCR1 = value;
323 case 15: /* Coprpcessor Access Register. */
324 /* Access is only valid if CRm == 1. */
328 /* Only BITS (13, 0) may be written. */
336 XScale_cp15_opcode_2_is_0_Regs [reg] = value;
342 /* Return the value in a cp15 register. */
345 read_cp15_reg (unsigned reg, unsigned opcode_2, unsigned CRm)
349 if (reg == 15 && CRm != 1)
356 case 3: return XScale_cp15_DBR1;
357 case 4: return XScale_cp15_DBCON;
358 case 8: return XScale_cp15_IBCR0;
359 case 9: return XScale_cp15_IBCR1;
365 return XScale_cp15_opcode_2_is_0_Regs [reg];
368 return XScale_cp15_opcode_2_is_not_0_Regs [reg];
374 XScale_cp15_LDC (ARMul_State * state, unsigned type, ARMword instr, ARMword data)
376 unsigned reg = BITS (12, 15);
379 result = check_cp15_access (state, reg, 0, 0, 0);
381 if (result == ARMul_DONE && type == ARMul_DATA)
382 write_cp15_reg (state, reg, 0, 0, data);
388 XScale_cp15_STC (ARMul_State * state, unsigned type, ARMword instr, ARMword * data)
390 unsigned reg = BITS (12, 15);
393 result = check_cp15_access (state, reg, 0, 0, 0);
395 if (result == ARMul_DONE && type == ARMul_DATA)
396 * data = read_cp15_reg (reg, 0, 0);
402 XScale_cp15_MRC (ARMul_State * state,
403 unsigned type ATTRIBUTE_UNUSED,
407 unsigned opcode_2 = BITS (5, 7);
408 unsigned CRm = BITS (0, 3);
409 unsigned reg = BITS (16, 19);
412 result = check_cp15_access (state, reg, CRm, BITS (21, 23), opcode_2);
414 if (result == ARMul_DONE)
415 * value = read_cp15_reg (reg, opcode_2, CRm);
421 XScale_cp15_MCR (ARMul_State * state,
422 unsigned type ATTRIBUTE_UNUSED,
426 unsigned opcode_2 = BITS (5, 7);
427 unsigned CRm = BITS (0, 3);
428 unsigned reg = BITS (16, 19);
431 result = check_cp15_access (state, reg, CRm, BITS (21, 23), opcode_2);
433 if (result == ARMul_DONE)
434 write_cp15_reg (state, reg, opcode_2, CRm, value);
440 XScale_cp15_read_reg (ARMul_State * state ATTRIBUTE_UNUSED,
444 /* FIXME: Not sure what to do about the alternative register set
445 here. For now default to just accessing CRm == 0 registers. */
446 * value = read_cp15_reg (reg, 0, 0);
452 XScale_cp15_write_reg (ARMul_State * state ATTRIBUTE_UNUSED,
456 /* FIXME: Not sure what to do about the alternative register set
457 here. For now default to just accessing CRm == 0 registers. */
458 write_cp15_reg (state, reg, 0, 0, value);
463 /* Check for special XScale memory access features. */
466 XScale_check_memacc (ARMul_State * state, ARMword * address, int store)
468 ARMword dbcon, r0, r1;
471 if (!state->is_XScale)
474 /* Check for PID-ification.
475 XXX BTB access support will require this test failing. */
476 r0 = (read_cp15_reg (13, 0, 0) & 0xfe000000);
477 if (r0 && (* address & 0xfe000000) == 0)
480 /* Check alignment fault enable/disable. */
481 if ((read_cp15_reg (1, 0, 0) & ARMul_CP15_R1_ALIGN) && (* address & 3))
482 ARMul_Abort (state, ARMul_DataAbortV);
484 if (XScale_debug_moe (state, -1))
487 /* Check the data breakpoint registers. */
488 dbcon = read_cp15_reg (14, 0, 4);
489 r0 = read_cp15_reg (14, 0, 0);
490 r1 = read_cp15_reg (14, 0, 3);
491 e0 = dbcon & ARMul_CP15_DBCON_E0;
493 if (dbcon & ARMul_CP15_DBCON_M)
495 /* r1 is a inverse mask. */
496 if (e0 != 0 && ((store && e0 != 3) || (!store && e0 != 1))
497 && ((* address & ~r1) == (r0 & ~r1)))
499 XScale_debug_moe (state, ARMul_CP14_R10_MOE_DB);
500 ARMul_OSHandleSWI (state, SWI_Breakpoint);
505 if (e0 != 0 && ((store && e0 != 3) || (!store && e0 != 1))
506 && ((* address & ~3) == (r0 & ~3)))
508 XScale_debug_moe (state, ARMul_CP14_R10_MOE_DB);
509 ARMul_OSHandleSWI (state, SWI_Breakpoint);
512 e1 = (dbcon & ARMul_CP15_DBCON_E1) >> 2;
513 if (e1 != 0 && ((store && e1 != 3) || (!store && e1 != 1))
514 && ((* address & ~3) == (r1 & ~3)))
516 XScale_debug_moe (state, ARMul_CP14_R10_MOE_DB);
517 ARMul_OSHandleSWI (state, SWI_Breakpoint);
522 /* Set the XScale FSR and FAR registers. */
525 XScale_set_fsr_far (ARMul_State * state, ARMword fsr, ARMword far)
527 if (!state->is_XScale || (read_cp14_reg (10) & (1UL << 31)) == 0)
530 write_cp15_reg (state, 5, 0, 0, fsr);
531 write_cp15_reg (state, 6, 0, 0, far);
534 /* Set the XScale debug `method of entry' if it is enabled. */
537 XScale_debug_moe (ARMul_State * state, int moe)
541 if (!state->is_XScale)
544 value = read_cp14_reg (10);
545 if (value & (1UL << 31))
552 write_cp14_reg (10, value);
559 /* Coprocessor 13: Interrupt Controller and Bus Controller. */
561 /* There are two sets of registers for copro 13.
562 One set (of three registers) is available when CRm is 0
563 and the other set (of six registers) when CRm is 1. */
565 static ARMword XScale_cp13_CR0_Regs[16];
566 static ARMword XScale_cp13_CR1_Regs[16];
569 XScale_cp13_init (ARMul_State * state ATTRIBUTE_UNUSED)
575 XScale_cp13_CR0_Regs[i] = 0;
576 XScale_cp13_CR1_Regs[i] = 0;
580 /* Check an access to a register. */
583 check_cp13_access (ARMul_State * state,
589 /* Do not allow access to these registers in USER mode. */
590 if (state->Mode == USER26MODE || state->Mode == USER32MODE)
593 /* The opcodes should be zero. */
594 if ((opcode_1 != 0) || (opcode_2 != 0))
597 /* Do not allow access to these register if bit
598 13 of coprocessor 15's register 15 is zero. */
599 if (! CP_ACCESS_ALLOWED (state, 13))
602 /* Registers 0, 4 and 8 are defined when CRm == 0.
603 Registers 0, 1, 4, 5, 6, 7, 8 are defined when CRm == 1.
604 For all other CRm values undefined behaviour results. */
607 if (reg == 0 || reg == 4 || reg == 8)
612 if (reg == 0 || reg == 1 || (reg >= 4 && reg <= 8))
619 /* Store a value into one of coprocessor 13's registers. */
622 write_cp13_reg (unsigned reg, unsigned CRm, ARMword value)
630 /* Only BITS (3:0) can be written. */
635 /* No bits may be written. */
639 /* Only BITS (1:0) can be written. */
644 /* Should not happen. Ignore any writes to unimplemented registers. */
648 XScale_cp13_CR0_Regs [reg] = value;
655 /* Only BITS (30:28) and BITS (3:0) can be written.
656 BIT(31) is write ignored. */
658 value |= XScale_cp13_CR1_Regs[0] & (1UL << 31);
662 /* Only bit 0 is accecssible. */
664 value |= XScale_cp13_CR1_Regs[1] & ~ 1;
671 /* No bits can be written. */
675 /* Only BITS (7:0) can be written. */
680 /* Should not happen. Ignore any writes to unimplemented registers. */
684 XScale_cp13_CR1_Regs [reg] = value;
688 /* Should not happen. */
695 /* Return the value in a cp13 register. */
698 read_cp13_reg (unsigned reg, unsigned CRm)
701 return XScale_cp13_CR0_Regs [reg];
703 return XScale_cp13_CR1_Regs [reg];
709 XScale_cp13_LDC (ARMul_State * state, unsigned type, ARMword instr, ARMword data)
711 unsigned reg = BITS (12, 15);
714 result = check_cp13_access (state, reg, 0, 0, 0);
716 if (result == ARMul_DONE && type == ARMul_DATA)
717 write_cp13_reg (reg, 0, data);
723 XScale_cp13_STC (ARMul_State * state, unsigned type, ARMword instr, ARMword * data)
725 unsigned reg = BITS (12, 15);
728 result = check_cp13_access (state, reg, 0, 0, 0);
730 if (result == ARMul_DONE && type == ARMul_DATA)
731 * data = read_cp13_reg (reg, 0);
737 XScale_cp13_MRC (ARMul_State * state,
738 unsigned type ATTRIBUTE_UNUSED,
742 unsigned CRm = BITS (0, 3);
743 unsigned reg = BITS (16, 19);
746 result = check_cp13_access (state, reg, CRm, BITS (21, 23), BITS (5, 7));
748 if (result == ARMul_DONE)
749 * value = read_cp13_reg (reg, CRm);
755 XScale_cp13_MCR (ARMul_State * state,
756 unsigned type ATTRIBUTE_UNUSED,
760 unsigned CRm = BITS (0, 3);
761 unsigned reg = BITS (16, 19);
764 result = check_cp13_access (state, reg, CRm, BITS (21, 23), BITS (5, 7));
766 if (result == ARMul_DONE)
767 write_cp13_reg (reg, CRm, value);
773 XScale_cp13_read_reg (ARMul_State * state ATTRIBUTE_UNUSED,
777 /* FIXME: Not sure what to do about the alternative register set
778 here. For now default to just accessing CRm == 0 registers. */
779 * value = read_cp13_reg (reg, 0);
785 XScale_cp13_write_reg (ARMul_State * state ATTRIBUTE_UNUSED,
789 /* FIXME: Not sure what to do about the alternative register set
790 here. For now default to just accessing CRm == 0 registers. */
791 write_cp13_reg (reg, 0, value);
796 /* Coprocessor 14: Performance Monitoring, Clock and Power management,
799 static ARMword XScale_cp14_Regs[16];
802 XScale_cp14_init (ARMul_State * state ATTRIBUTE_UNUSED)
807 XScale_cp14_Regs[i] = 0;
810 /* Check an access to a register. */
813 check_cp14_access (ARMul_State * state,
819 /* Not allowed to access these register in USER mode. */
820 if (state->Mode == USER26MODE || state->Mode == USER32MODE)
823 /* CRm should be zero. */
827 /* OPcodes should be zero. */
828 if (opcode1 != 0 || opcode2 != 0)
831 /* Accessing registers 4 or 5 has unpredicatable results. */
832 if (reg >= 4 && reg <= 5)
838 /* Store a value into one of coprocessor 14's registers. */
841 write_cp14_reg (unsigned reg, ARMword value)
846 /* Only BITS (27:12), BITS (10:8) and BITS (6:0) can be written. */
849 /* Reset the clock counter if necessary. */
850 if (value & ARMul_CP14_R0_CLKRST)
851 XScale_cp14_Regs [1] = 0;
856 /* We should not normally reach this code. The debugger interface
857 can bypass the normal checks though, so it could happen. */
861 case 6: /* CCLKCFG */
862 /* Only BITS (3:0) can be written. */
866 case 7: /* PWRMODE */
867 /* Although BITS (1:0) can be written with non-zero values, this would
868 have the side effect of putting the processor to sleep. Thus in
869 order for the register to be read again, it would have to go into
870 ACTIVE mode, which means that any read will see these bits as zero.
872 Rather than trying to implement complex reset-to-zero-upon-read logic
873 we just override the write value with zero. */
878 /* Only BITS (31:30), BITS (23:22), BITS (20:16) and BITS (5:0) can
884 /* No writes are permitted. */
888 case 14: /* TXRXCTRL */
889 /* Only BITS (31:30) can be written. */
894 /* All bits can be written. */
898 XScale_cp14_Regs [reg] = value;
901 /* Return the value in a cp14 register. Not a static function since
902 it is used by the code to emulate the BKPT instruction in armemu.c. */
905 read_cp14_reg (unsigned reg)
907 return XScale_cp14_Regs [reg];
911 XScale_cp14_LDC (ARMul_State * state, unsigned type, ARMword instr, ARMword data)
913 unsigned reg = BITS (12, 15);
916 result = check_cp14_access (state, reg, 0, 0, 0);
918 if (result == ARMul_DONE && type == ARMul_DATA)
919 write_cp14_reg (reg, data);
925 XScale_cp14_STC (ARMul_State * state, unsigned type, ARMword instr, ARMword * data)
927 unsigned reg = BITS (12, 15);
930 result = check_cp14_access (state, reg, 0, 0, 0);
932 if (result == ARMul_DONE && type == ARMul_DATA)
933 * data = read_cp14_reg (reg);
942 unsigned type ATTRIBUTE_UNUSED,
947 unsigned reg = BITS (16, 19);
950 result = check_cp14_access (state, reg, BITS (0, 3), BITS (21, 23), BITS (5, 7));
952 if (result == ARMul_DONE)
953 * value = read_cp14_reg (reg);
962 unsigned type ATTRIBUTE_UNUSED,
967 unsigned reg = BITS (16, 19);
970 result = check_cp14_access (state, reg, BITS (0, 3), BITS (21, 23), BITS (5, 7));
972 if (result == ARMul_DONE)
973 write_cp14_reg (reg, value);
981 ARMul_State * state ATTRIBUTE_UNUSED,
986 * value = read_cp14_reg (reg);
992 XScale_cp14_write_reg
994 ARMul_State * state ATTRIBUTE_UNUSED,
999 write_cp14_reg (reg, value);
1004 /* Here's ARMulator's MMU definition. A few things to note:
1005 1) It has eight registers, but only two are defined.
1006 2) You can only access its registers with MCR and MRC.
1007 3) MMU Register 0 (ID) returns 0x41440110
1008 4) Register 1 only has 4 bits defined. Bits 0 to 3 are unused, bit 4
1009 controls 32/26 bit program space, bit 5 controls 32/26 bit data space,
1010 bit 6 controls late abort timimg and bit 7 controls big/little endian. */
1012 static ARMword MMUReg[8];
1015 MMUInit (ARMul_State * state)
1017 MMUReg[1] = state->prog32Sig << 4 |
1018 state->data32Sig << 5 | state->lateabtSig << 6 | state->bigendSig << 7;
1020 ARMul_ConsolePrint (state, ", MMU present");
1026 MMUMRC (ARMul_State * state ATTRIBUTE_UNUSED,
1027 unsigned type ATTRIBUTE_UNUSED,
1031 int reg = BITS (16, 19) & 7;
1034 *value = 0x41440110;
1036 *value = MMUReg[reg];
1042 MMUMCR (ARMul_State * state,
1043 unsigned type ATTRIBUTE_UNUSED,
1047 int reg = BITS (16, 19) & 7;
1049 MMUReg[reg] = value;
1055 p = state->prog32Sig;
1056 d = state->data32Sig;
1057 l = state->lateabtSig;
1058 b = state->bigendSig;
1060 state->prog32Sig = value >> 4 & 1;
1061 state->data32Sig = value >> 5 & 1;
1062 state->lateabtSig = value >> 6 & 1;
1063 state->bigendSig = value >> 7 & 1;
1065 if ( p != state->prog32Sig
1066 || d != state->data32Sig
1067 || l != state->lateabtSig
1068 || b != state->bigendSig)
1069 /* Force ARMulator to notice these now. */
1070 state->Emulate = CHANGEMODE;
1077 MMURead (ARMul_State * state ATTRIBUTE_UNUSED, unsigned reg, ARMword * value)
1080 *value = 0x41440110;
1082 *value = MMUReg[reg];
1088 MMUWrite (ARMul_State * state, unsigned reg, ARMword value)
1091 MMUReg[reg] = value;
1097 p = state->prog32Sig;
1098 d = state->data32Sig;
1099 l = state->lateabtSig;
1100 b = state->bigendSig;
1102 state->prog32Sig = value >> 4 & 1;
1103 state->data32Sig = value >> 5 & 1;
1104 state->lateabtSig = value >> 6 & 1;
1105 state->bigendSig = value >> 7 & 1;
1107 if ( p != state->prog32Sig
1108 || d != state->data32Sig
1109 || l != state->lateabtSig
1110 || b != state->bigendSig)
1111 /* Force ARMulator to notice these now. */
1112 state->Emulate = CHANGEMODE;
1119 /* What follows is the Validation Suite Coprocessor. It uses two
1120 co-processor numbers (4 and 5) and has the follwing functionality.
1121 Sixteen registers. Both co-processor nuimbers can be used in an MCR
1122 and MRC to access these registers. CP 4 can LDC and STC to and from
1123 the registers. CP 4 and CP 5 CDP 0 will busy wait for the number of
1124 cycles specified by a CP register. CP 5 CDP 1 issues a FIQ after a
1125 number of cycles (specified in a CP register), CDP 2 issues an IRQW
1126 in the same way, CDP 3 and 4 turn of the FIQ and IRQ source, and CDP 5
1127 stores a 32 bit time value in a CP register (actually it's the total
1128 number of N, S, I, C and F cyles). */
1130 static ARMword ValReg[16];
1133 ValLDC (ARMul_State * state ATTRIBUTE_UNUSED,
1138 static unsigned words;
1140 if (type != ARMul_DATA)
1144 ValReg[BITS (12, 15)] = data;
1147 /* It's a long access, get two words. */
1156 ValSTC (ARMul_State * state ATTRIBUTE_UNUSED,
1161 static unsigned words;
1163 if (type != ARMul_DATA)
1167 * data = ValReg[BITS (12, 15)];
1170 /* It's a long access, get two words. */
1179 ValMRC (ARMul_State * state ATTRIBUTE_UNUSED,
1180 unsigned type ATTRIBUTE_UNUSED,
1184 *value = ValReg[BITS (16, 19)];
1190 ValMCR (ARMul_State * state ATTRIBUTE_UNUSED,
1191 unsigned type ATTRIBUTE_UNUSED,
1195 ValReg[BITS (16, 19)] = value;
1201 ValCDP (ARMul_State * state, unsigned type, ARMword instr)
1203 static unsigned long finish = 0;
1205 if (BITS (20, 23) != 0)
1208 if (type == ARMul_FIRST)
1212 howlong = ValReg[BITS (0, 3)];
1214 /* First cycle of a busy wait. */
1215 finish = ARMul_Time (state) + howlong;
1217 return howlong == 0 ? ARMul_DONE : ARMul_BUSY;
1219 else if (type == ARMul_BUSY)
1221 if (ARMul_Time (state) >= finish)
1231 DoAFIQ (ARMul_State * state)
1233 state->NfiqSig = LOW;
1239 DoAIRQ (ARMul_State * state)
1241 state->NirqSig = LOW;
1247 IntCDP (ARMul_State * state, unsigned type, ARMword instr)
1249 static unsigned long finish;
1252 howlong = ValReg[BITS (0, 3)];
1254 switch ((int) BITS (20, 23))
1257 if (type == ARMul_FIRST)
1259 /* First cycle of a busy wait. */
1260 finish = ARMul_Time (state) + howlong;
1262 return howlong == 0 ? ARMul_DONE : ARMul_BUSY;
1264 else if (type == ARMul_BUSY)
1266 if (ARMul_Time (state) >= finish)
1275 ARMul_Abort (state, ARMul_FIQV);
1277 ARMul_ScheduleEvent (state, howlong, DoAFIQ);
1282 ARMul_Abort (state, ARMul_IRQV);
1284 ARMul_ScheduleEvent (state, howlong, DoAIRQ);
1288 state->NfiqSig = HIGH;
1293 state->NirqSig = HIGH;
1298 ValReg[BITS (0, 3)] = ARMul_Time (state);
1305 /* Install co-processor instruction handlers in this routine. */
1308 ARMul_CoProInit (ARMul_State * state)
1312 /* Initialise tham all first. */
1313 for (i = 0; i < 16; i++)
1314 ARMul_CoProDetach (state, i);
1316 /* Install CoPro Instruction handlers here.
1318 ARMul_CoProAttach (state, CP Number,
1319 Init routine, Exit routine
1320 LDC routine, STC routine,
1321 MRC routine, MCR routine,
1323 Read Reg routine, Write Reg routine). */
1324 ARMul_CoProAttach (state, 4, NULL, NULL,
1325 ValLDC, ValSTC, ValMRC, ValMCR, ValCDP, NULL, NULL);
1327 ARMul_CoProAttach (state, 5, NULL, NULL,
1328 NULL, NULL, ValMRC, ValMCR, IntCDP, NULL, NULL);
1330 ARMul_CoProAttach (state, 15, MMUInit, NULL,
1331 NULL, NULL, MMUMRC, MMUMCR, NULL, MMURead, MMUWrite);
1333 ARMul_CoProAttach (state, 13, XScale_cp13_init, NULL,
1334 XScale_cp13_LDC, XScale_cp13_STC, XScale_cp13_MRC,
1335 XScale_cp13_MCR, NULL, XScale_cp13_read_reg,
1336 XScale_cp13_write_reg);
1338 ARMul_CoProAttach (state, 14, XScale_cp14_init, NULL,
1339 XScale_cp14_LDC, XScale_cp14_STC, XScale_cp14_MRC,
1340 XScale_cp14_MCR, NULL, XScale_cp14_read_reg,
1341 XScale_cp14_write_reg);
1343 ARMul_CoProAttach (state, 15, XScale_cp15_init, NULL,
1344 NULL, NULL, XScale_cp15_MRC, XScale_cp15_MCR,
1345 NULL, XScale_cp15_read_reg, XScale_cp15_write_reg);
1347 /* No handlers below here. */
1349 /* Call all the initialisation routines. */
1350 for (i = 0; i < 16; i++)
1351 if (state->CPInit[i])
1352 (state->CPInit[i]) (state);
1357 /* Install co-processor finalisation routines in this routine. */
1360 ARMul_CoProExit (ARMul_State * state)
1362 register unsigned i;
1364 for (i = 0; i < 16; i++)
1365 if (state->CPExit[i])
1366 (state->CPExit[i]) (state);
1368 for (i = 0; i < 16; i++) /* Detach all handlers. */
1369 ARMul_CoProDetach (state, i);
1372 /* Routines to hook Co-processors into ARMulator. */
1375 ARMul_CoProAttach (ARMul_State * state,
1377 ARMul_CPInits * init,
1378 ARMul_CPExits * exit,
1384 ARMul_CPReads * read,
1385 ARMul_CPWrites * write)
1388 state->CPInit[number] = init;
1390 state->CPExit[number] = exit;
1392 state->LDC[number] = ldc;
1394 state->STC[number] = stc;
1396 state->MRC[number] = mrc;
1398 state->MCR[number] = mcr;
1400 state->CDP[number] = cdp;
1402 state->CPRead[number] = read;
1404 state->CPWrite[number] = write;
1408 ARMul_CoProDetach (ARMul_State * state, unsigned number)
1410 ARMul_CoProAttach (state, number, NULL, NULL,
1411 NoCoPro4R, NoCoPro4W, NoCoPro4W, NoCoPro4R,
1412 NoCoPro3R, NULL, NULL);
1414 state->CPInit[number] = NULL;
1415 state->CPExit[number] = NULL;
1416 state->CPRead[number] = NULL;
1417 state->CPWrite[number] = NULL;