1 /* armcopro.c -- co-processor interface: ARM6 Instruction Emulator.
2 Copyright (C) 1994 Advanced RISC Machines Ltd.
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
20 extern unsigned ARMul_CoProInit (ARMul_State * state);
21 extern void ARMul_CoProExit (ARMul_State * state);
22 extern void ARMul_CoProAttach (ARMul_State * state, unsigned number,
23 ARMul_CPInits * init, ARMul_CPExits * exit,
24 ARMul_LDCs * ldc, ARMul_STCs * stc,
25 ARMul_MRCs * mrc, ARMul_MCRs * mcr,
27 ARMul_CPReads * read, ARMul_CPWrites * write);
28 extern void ARMul_CoProDetach (ARMul_State * state, unsigned number);
31 /***************************************************************************\
32 * Dummy Co-processors *
33 \***************************************************************************/
35 static unsigned NoCoPro3R (ARMul_State * state, unsigned, ARMword);
36 static unsigned NoCoPro4R (ARMul_State * state, unsigned, ARMword, ARMword);
37 static unsigned NoCoPro4W (ARMul_State * state, unsigned, ARMword, ARMword *);
39 /***************************************************************************\
40 * Define Co-Processor instruction handlers here *
41 \***************************************************************************/
43 /* Here's ARMulator's MMU definition. A few things to note:
44 1) it has eight registers, but only two are defined.
45 2) you can only access its registers with MCR and MRC.
46 3) MMU Register 0 (ID) returns 0x41440110
47 4) Register 1 only has 4 bits defined. Bits 0 to 3 are unused, bit 4
48 controls 32/26 bit program space, bit 5 controls 32/26 bit data space,
49 bit 6 controls late abort timimg and bit 7 controls big/little endian.
52 static ARMword MMUReg[8];
55 MMUInit (ARMul_State * state)
57 MMUReg[1] = state->prog32Sig << 4 |
58 state->data32Sig << 5 | state->lateabtSig << 6 | state->bigendSig << 7;
59 ARMul_ConsolePrint (state, ", MMU present");
64 MMUMRC (ARMul_State * state, unsigned type, ARMword instr, ARMword * value)
66 int reg = BITS (16, 19) & 7;
76 MMUMCR (ARMul_State * state, unsigned type, ARMword instr, ARMword value)
78 int reg = BITS (16, 19) & 7;
83 state->prog32Sig = value >> 4 & 1;
84 state->data32Sig = value >> 5 & 1;
85 state->lateabtSig = value >> 6 & 1;
86 state->bigendSig = value >> 7 & 1;
87 state->Emulate = TRUE; /* force ARMulator to notice these now ! */
94 MMURead (ARMul_State * state, unsigned reg, ARMword * value)
104 MMUWrite (ARMul_State * state, unsigned reg, ARMword value)
110 state->prog32Sig = value >> 4 & 1;
111 state->data32Sig = value >> 5 & 1;
112 state->lateabtSig = value >> 6 & 1;
113 state->bigendSig = value >> 7 & 1;
114 state->Emulate = TRUE; /* force ARMulator to notice these now ! */
120 /* What follows is the Validation Suite Coprocessor. It uses two
121 co-processor numbers (4 and 5) and has the follwing functionality.
122 Sixteen registers. Both co-processor nuimbers can be used in an MCR and
123 MRC to access these registers. CP 4 can LDC and STC to and from the
124 registers. CP 4 and CP 5 CDP 0 will busy wait for the number of cycles
125 specified by a CP register. CP 5 CDP 1 issues a FIQ after a number of
126 cycles (specified in a CP register), CDP 2 issues an IRQW in the same
127 way, CDP 3 and 4 turn of the FIQ and IRQ source, and CDP 5 stores a 32
128 bit time value in a CP register (actually it's the total number of N, S,
131 static ARMword ValReg[16];
134 ValLDC (ARMul_State * state, unsigned type, ARMword instr, ARMword data)
136 static unsigned words;
138 if (type != ARMul_DATA)
144 { /* it's a long access, get two words */
145 ValReg[BITS (12, 15)] = data;
152 { /* get just one word */
153 ValReg[BITS (12, 15)] = data;
159 ValSTC (ARMul_State * state, unsigned type, ARMword instr, ARMword * data)
161 static unsigned words;
163 if (type != ARMul_DATA)
169 { /* it's a long access, get two words */
170 *data = ValReg[BITS (12, 15)];
177 { /* get just one word */
178 *data = ValReg[BITS (12, 15)];
184 ValMRC (ARMul_State * state, unsigned type, ARMword instr, ARMword * value)
186 *value = ValReg[BITS (16, 19)];
191 ValMCR (ARMul_State * state, unsigned type, ARMword instr, ARMword value)
193 ValReg[BITS (16, 19)] = value;
198 ValCDP (ARMul_State * state, unsigned type, ARMword instr)
200 static unsigned long finish = 0;
203 howlong = ValReg[BITS (0, 3)];
204 if (BITS (20, 23) == 0)
206 if (type == ARMul_FIRST)
207 { /* First cycle of a busy wait */
208 finish = ARMul_Time (state) + howlong;
214 else if (type == ARMul_BUSY)
216 if (ARMul_Time (state) >= finish)
226 DoAFIQ (ARMul_State * state)
228 state->NfiqSig = LOW;
234 DoAIRQ (ARMul_State * state)
236 state->NirqSig = LOW;
242 IntCDP (ARMul_State * state, unsigned type, ARMword instr)
244 static unsigned long finish;
247 howlong = ValReg[BITS (0, 3)];
248 switch ((int) BITS (20, 23))
251 if (type == ARMul_FIRST)
252 { /* First cycle of a busy wait */
253 finish = ARMul_Time (state) + howlong;
259 else if (type == ARMul_BUSY)
261 if (ARMul_Time (state) >= finish)
269 ARMul_Abort (state, ARMul_FIQV);
271 ARMul_ScheduleEvent (state, howlong, DoAFIQ);
275 ARMul_Abort (state, ARMul_IRQV);
277 ARMul_ScheduleEvent (state, howlong, DoAIRQ);
280 state->NfiqSig = HIGH;
284 state->NirqSig = HIGH;
288 ValReg[BITS (0, 3)] = ARMul_Time (state);
294 /***************************************************************************\
295 * Install co-processor instruction handlers in this routine *
296 \***************************************************************************/
299 ARMul_CoProInit (ARMul_State * state)
303 for (i = 0; i < 16; i++) /* initialise tham all first */
304 ARMul_CoProDetach (state, i);
306 /* Install CoPro Instruction handlers here
308 ARMul_CoProAttach(state, CP Number, Init routine, Exit routine
309 LDC routine, STC routine, MRC routine, MCR routine,
310 CDP routine, Read Reg routine, Write Reg routine) ;
313 ARMul_CoProAttach (state, 4, NULL, NULL,
314 ValLDC, ValSTC, ValMRC, ValMCR, ValCDP, NULL, NULL);
316 ARMul_CoProAttach (state, 5, NULL, NULL,
317 NULL, NULL, ValMRC, ValMCR, IntCDP, NULL, NULL);
319 ARMul_CoProAttach (state, 15, MMUInit, NULL,
320 NULL, NULL, MMUMRC, MMUMCR, NULL, MMURead, MMUWrite);
323 /* No handlers below here */
325 for (i = 0; i < 16; i++) /* Call all the initialisation routines */
326 if (state->CPInit[i])
327 (state->CPInit[i]) (state);
331 /***************************************************************************\
332 * Install co-processor finalisation routines in this routine *
333 \***************************************************************************/
336 ARMul_CoProExit (ARMul_State * state)
340 for (i = 0; i < 16; i++)
341 if (state->CPExit[i])
342 (state->CPExit[i]) (state);
343 for (i = 0; i < 16; i++) /* Detach all handlers */
344 ARMul_CoProDetach (state, i);
347 /***************************************************************************\
348 * Routines to hook Co-processors into ARMulator *
349 \***************************************************************************/
352 ARMul_CoProAttach (ARMul_State * state, unsigned number,
353 ARMul_CPInits * init, ARMul_CPExits * exit,
354 ARMul_LDCs * ldc, ARMul_STCs * stc,
355 ARMul_MRCs * mrc, ARMul_MCRs * mcr, ARMul_CDPs * cdp,
356 ARMul_CPReads * read, ARMul_CPWrites * write)
359 state->CPInit[number] = init;
361 state->CPExit[number] = exit;
363 state->LDC[number] = ldc;
365 state->STC[number] = stc;
367 state->MRC[number] = mrc;
369 state->MCR[number] = mcr;
371 state->CDP[number] = cdp;
373 state->CPRead[number] = read;
375 state->CPWrite[number] = write;
379 ARMul_CoProDetach (ARMul_State * state, unsigned number)
381 ARMul_CoProAttach (state, number, NULL, NULL,
382 NoCoPro4R, NoCoPro4W, NoCoPro4W, NoCoPro4R,
383 NoCoPro3R, NULL, NULL);
384 state->CPInit[number] = NULL;
385 state->CPExit[number] = NULL;
386 state->CPRead[number] = NULL;
387 state->CPWrite[number] = NULL;
390 /***************************************************************************\
391 * There is no CoPro around, so Undefined Instruction trap *
392 \***************************************************************************/
395 NoCoPro3R (ARMul_State * state, unsigned a, ARMword b)
401 NoCoPro4R (ARMul_State * state, unsigned a, ARMword b, ARMword c)
407 NoCoPro4W (ARMul_State * state, unsigned a, ARMword b, ARMword * c)