1 /* decode.h -- Prototypes for AArch64 simulator decoder functions.
3 Copyright (C) 2015-2016 Free Software Foundation, Inc.
5 Contributed by Red Hat.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
25 #include <sys/types.h>
28 /* Codes used in conditional instructions
30 These are passed to conditional operations to identify which
31 condition to test for. */
35 EQ = 0x0, /* meaning Z == 1 */
36 NE = 0x1, /* meaning Z == 0 */
37 HS = 0x2, /* meaning C == 1 */
39 LO = 0x3, /* meaning C == 0 */
41 MI = 0x4, /* meaning N == 1 */
42 PL = 0x5, /* meaning N == 0 */
43 VS = 0x6, /* meaning V == 1 */
44 VC = 0x7, /* meaning V == 0 */
45 HI = 0x8, /* meaning C == 1 && Z == 0 */
46 LS = 0x9, /* meaning !(C == 1 && Z == 0) */
47 GE = 0xa, /* meaning N == V */
48 LT = 0xb, /* meaning N != V */
49 GT = 0xc, /* meaning Z == 0 && N == V */
50 LE = 0xd, /* meaning !(Z == 0 && N == V) */
51 AL = 0xe, /* meaning ANY */
55 /* Certain addressing modes for load require pre or post writeback of
56 the computed address to a base register. */
58 typedef enum WriteBack
65 /* Certain addressing modes for load require an offset to
66 be optionally scaled so the decode needs to pass that
67 through to the execute routine. */
76 /* When we do have to scale we do so by shifting using
77 log(bytes in data element - 1) as the shift count.
78 so we don't have to scale offsets when loading
81 typedef enum ScaleShift
89 /* One of the addressing modes for load requires a 32-bit register
90 value to be either zero- or sign-extended for these instructions
91 UXTW or SXTW should be passed.
93 Arithmetic register data processing operations can optionally
94 extend a portion of the second register value for these
95 instructions the value supplied must identify the portion of the
96 register which is to be zero- or sign-exended. */
98 typedef enum Extension
111 /* Arithmetic and logical register data processing operations
112 optionally perform a shift on the second register value. */
122 /* Bit twiddling helpers for instruction decode. */
124 /* 32 bit mask with bits [hi,...,lo] set. */
125 static inline uint32_t
126 mask32 (int hi, int lo)
128 int nbits = (hi + 1) - lo;
129 return ((1 << nbits) - 1) << lo;
132 /* 64 bit mask with bits [hi,...,lo] set. */
133 static inline uint64_t
134 mask64 (int hi, int lo)
136 int nbits = (hi + 1) - lo;
137 return ((1L << nbits) - 1) << lo;
140 /* Pick bits [hi,...,lo] from val. */
141 static inline uint32_t
142 pick32 (uint32_t val, int hi, int lo)
144 return val & mask32 (hi, lo);
147 /* Pick bits [hi,...,lo] from val. */
148 static inline uint64_t
149 pick64 (uint64_t val, int hi, int lo)
151 return val & mask64 (hi, lo);
154 /* Pick bits [hi,...,lo] from val and shift to [(hi-(newlo - lo)),newlo]. */
155 static inline uint32_t
156 pickshift32 (uint32_t val, int hi, int lo, int newlo)
158 uint32_t bits = pick32 (val, hi, lo);
161 return bits << (newlo - lo);
163 return bits >> (lo - newlo);
166 /* Mask [hi,lo] and shift down to start at bit 0. */
167 static inline uint32_t
168 pickbits32 (uint32_t val, int hi, int lo)
170 return pick32 (val, hi, lo) >> lo;
173 /* Mask [hi,lo] and shift down to start at bit 0. */
174 static inline uint64_t
175 pickbits64 (uint64_t val, int hi, int lo)
177 return pick64 (val, hi, lo) >> lo;
180 /* Decode registers, immediates and constants of various types. */
183 greg (uint32_t val, int lo)
185 return (GReg) pickbits32 (val, lo + 4, lo);
189 vreg (uint32_t val, int lo)
191 return (VReg) pickbits32 (val, lo + 4, lo);
194 static inline uint32_t
195 uimm (uint32_t val, int hi, int lo)
197 return pickbits32 (val, hi, lo);
200 static inline int32_t
201 simm32 (uint32_t val, int hi, int lo)
209 x.u = val << (31 - hi);
210 return x.n >> (31 - hi + lo);
213 static inline int64_t
214 simm64 (uint64_t val, int hi, int lo)
222 x.u = val << (63 - hi);
223 return x.n >> (63 - hi + lo);
227 shift (uint32_t val, int lo)
229 return (Shift) pickbits32 (val, lo + 1, lo);
232 static inline Extension
233 extension (uint32_t val, int lo)
235 return (Extension) pickbits32 (val, lo + 2, lo);
238 static inline Scaling
239 scaling (uint32_t val, int lo)
241 return (Scaling) pickbits32 (val, lo, lo);
244 static inline WriteBack
245 writeback (uint32_t val, int lo)
247 return (WriteBack) pickbits32 (val, lo, lo);
250 static inline CondCode
251 condcode (uint32_t val, int lo)
253 return (CondCode) pickbits32 (val, lo + 3, lo);
257 Bits [28,24] are the primary dispatch vector. */
259 static inline uint32_t
260 dispatchGroup (uint32_t val)
262 return pickshift32 (val, 28, 25, 0);
265 /* The 16 possible values for bits [28,25] identified by tags which
266 map them to the 5 main instruction groups LDST, DPREG, ADVSIMD,
269 An extra group PSEUDO is included in one of the unallocated ranges
270 for simulator-specific pseudo-instructions. */
292 /* Bits [31, 29] of a Pseudo are the secondary dispatch vector. */
294 static inline uint32_t
295 dispatchPseudo (uint32_t val)
297 return pickshift32 (val, 31, 29, 0);
300 /* The 8 possible values for bits [31,29] in a Pseudo Instruction.
301 Bits [28,25] are always 0000. */
305 PSEUDO_UNALLOC_000, /* Unallocated. */
306 PSEUDO_UNALLOC_001, /* Ditto. */
307 PSEUDO_UNALLOC_010, /* Ditto. */
308 PSEUDO_UNALLOC_011, /* Ditto. */
309 PSEUDO_UNALLOC_100, /* Ditto. */
310 PSEUDO_UNALLOC_101, /* Ditto. */
311 PSEUDO_CALLOUT_110, /* CALLOUT -- bits [24,0] identify call/ret sig. */
312 PSEUDO_HALT_111 /* HALT -- bits [24, 0] identify halt code. */
315 /* Bits [25, 23] of a DPImm are the secondary dispatch vector. */
317 static inline uint32_t
318 dispatchDPImm (uint32_t instr)
320 return pickshift32 (instr, 25, 23, 0);
323 /* The 8 possible values for bits [25,23] in a Data Processing Immediate
324 Instruction. Bits [28,25] are always 100_. */
328 DPIMM_PCADR_000, /* PC-rel-addressing. */
329 DPIMM_PCADR_001, /* Ditto. */
330 DPIMM_ADDSUB_010, /* Add/Subtract (immediate). */
331 DPIMM_ADDSUB_011, /* Ditto. */
332 DPIMM_LOG_100, /* Logical (immediate). */
333 DPIMM_MOV_101, /* Move Wide (immediate). */
334 DPIMM_BITF_110, /* Bitfield. */
335 DPIMM_EXTR_111 /* Extract. */
338 /* Bits [29,28:26] of a LS are the secondary dispatch vector. */
340 static inline uint32_t
341 dispatchLS (uint32_t instr)
343 return ( pickshift32 (instr, 29, 28, 1)
344 | pickshift32 (instr, 26, 26, 0));
347 /* The 8 possible values for bits [29,28:26] in a Load/Store
348 Instruction. Bits [28,25] are always _1_0. */
352 LS_EXCL_000, /* Load/store exclusive (includes some unallocated). */
353 LS_ADVSIMD_001, /* AdvSIMD load/store (various -- includes some unallocated). */
354 LS_LIT_010, /* Load register literal (includes some unallocated). */
355 LS_LIT_011, /* Ditto. */
356 LS_PAIR_100, /* Load/store register pair (various). */
357 LS_PAIR_101, /* Ditto. */
358 LS_OTHER_110, /* Other load/store formats. */
359 LS_OTHER_111 /* Ditto. */
362 /* Bits [28:24:21] of a DPReg are the secondary dispatch vector. */
364 static inline uint32_t
365 dispatchDPReg (uint32_t instr)
367 return ( pickshift32 (instr, 28, 28, 2)
368 | pickshift32 (instr, 24, 24, 1)
369 | pickshift32 (instr, 21, 21, 0));
372 /* The 8 possible values for bits [28:24:21] in a Data Processing
373 Register Instruction. Bits [28,25] are always _101. */
377 DPREG_LOG_000, /* Logical (shifted register). */
378 DPREG_LOG_001, /* Ditto. */
379 DPREG_ADDSHF_010, /* Add/subtract (shifted register). */
380 DPREG_ADDEXT_011, /* Add/subtract (extended register). */
381 DPREG_ADDCOND_100, /* Add/subtract (with carry) AND
382 Cond compare/select AND
383 Data Processing (1/2 source). */
384 DPREG_UNALLOC_101, /* Unallocated. */
385 DPREG_3SRC_110, /* Data Processing (3 source). */
386 DPREG_3SRC_111 /* Data Processing (3 source). */
389 /* bits [31,29] of a BrExSys are the secondary dispatch vector. */
391 static inline uint32_t
392 dispatchBrExSys (uint32_t instr)
394 return pickbits32 (instr, 31, 29);
397 /* The 8 possible values for bits [31,29] in a Branch/Exception/System
398 Instruction. Bits [28,25] are always 101_. */
402 BR_IMM_000, /* Unconditional branch (immediate). */
403 BR_IMMCMP_001, /* Compare & branch (immediate) AND
404 Test & branch (immediate). */
405 BR_IMMCOND_010, /* Conditional branch (immediate) AND Unallocated. */
406 BR_UNALLOC_011, /* Unallocated. */
407 BR_IMM_100, /* Unconditional branch (immediate). */
408 BR_IMMCMP_101, /* Compare & branch (immediate) AND
409 Test & branch (immediate). */
410 BR_REG_110, /* Unconditional branch (register) AND System AND
411 Excn gen AND Unallocated. */
412 BR_UNALLOC_111 /* Unallocated. */
415 /* TODO still need to provide secondary decode and dispatch for
416 AdvSIMD Insructions with instr[28,25] = 0111 or 1111. */
418 #endif /* _DECODE_H */