1 /* cpustate.h -- Prototypes for AArch64 simulator functions.
3 Copyright (C) 2015-2019 Free Software Foundation, Inc.
5 Contributed by Red Hat.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
27 #include "simulator.h"
29 /* Some operands are allowed to access the stack pointer (reg 31).
30 For others a read from r31 always returns 0, and a write to r31 is ignored. */
31 #define reg_num(reg) (((reg) == R31 && !r31_is_sp) ? 32 : (reg))
34 aarch64_set_reg_u64 (sim_cpu *cpu, GReg reg, int r31_is_sp, uint64_t val)
36 if (reg == R31 && ! r31_is_sp)
38 TRACE_REGISTER (cpu, "GR[31] NOT CHANGED!");
42 if (val != cpu->gr[reg].u64)
44 "GR[%2d] changes from %16" PRIx64 " to %16" PRIx64,
45 reg, cpu->gr[reg].u64, val);
47 cpu->gr[reg].u64 = val;
51 aarch64_set_reg_s64 (sim_cpu *cpu, GReg reg, int r31_is_sp, int64_t val)
53 if (reg == R31 && ! r31_is_sp)
55 TRACE_REGISTER (cpu, "GR[31] NOT CHANGED!");
59 if (val != cpu->gr[reg].s64)
61 "GR[%2d] changes from %16" PRIx64 " to %16" PRIx64,
62 reg, cpu->gr[reg].s64, val);
64 cpu->gr[reg].s64 = val;
68 aarch64_get_reg_u64 (sim_cpu *cpu, GReg reg, int r31_is_sp)
70 return cpu->gr[reg_num(reg)].u64;
74 aarch64_get_reg_s64 (sim_cpu *cpu, GReg reg, int r31_is_sp)
76 return cpu->gr[reg_num(reg)].s64;
80 aarch64_get_reg_u32 (sim_cpu *cpu, GReg reg, int r31_is_sp)
82 return cpu->gr[reg_num(reg)].u32;
86 aarch64_get_reg_s32 (sim_cpu *cpu, GReg reg, int r31_is_sp)
88 return cpu->gr[reg_num(reg)].s32;
92 aarch64_set_reg_s32 (sim_cpu *cpu, GReg reg, int r31_is_sp, int32_t val)
94 if (reg == R31 && ! r31_is_sp)
96 TRACE_REGISTER (cpu, "GR[31] NOT CHANGED!");
100 if (val != cpu->gr[reg].s32)
101 TRACE_REGISTER (cpu, "GR[%2d] changes from %8x to %8x",
102 reg, cpu->gr[reg].s32, val);
104 /* The ARM ARM states that (C1.2.4):
105 When the data size is 32 bits, the lower 32 bits of the
106 register are used and the upper 32 bits are ignored on
107 a read and cleared to zero on a write.
108 We simulate this by first clearing the whole 64-bits and
109 then writing to the 32-bit value in the GRegister union. */
110 cpu->gr[reg].s64 = 0;
111 cpu->gr[reg].s32 = val;
115 aarch64_set_reg_u32 (sim_cpu *cpu, GReg reg, int r31_is_sp, uint32_t val)
117 if (reg == R31 && ! r31_is_sp)
119 TRACE_REGISTER (cpu, "GR[31] NOT CHANGED!");
123 if (val != cpu->gr[reg].u32)
124 TRACE_REGISTER (cpu, "GR[%2d] changes from %8x to %8x",
125 reg, cpu->gr[reg].u32, val);
127 cpu->gr[reg].u64 = 0;
128 cpu->gr[reg].u32 = val;
132 aarch64_get_reg_u16 (sim_cpu *cpu, GReg reg, int r31_is_sp)
134 return cpu->gr[reg_num(reg)].u16;
138 aarch64_get_reg_s16 (sim_cpu *cpu, GReg reg, int r31_is_sp)
140 return cpu->gr[reg_num(reg)].s16;
144 aarch64_get_reg_u8 (sim_cpu *cpu, GReg reg, int r31_is_sp)
146 return cpu->gr[reg_num(reg)].u8;
150 aarch64_get_reg_s8 (sim_cpu *cpu, GReg reg, int r31_is_sp)
152 return cpu->gr[reg_num(reg)].s8;
156 aarch64_get_PC (sim_cpu *cpu)
162 aarch64_get_next_PC (sim_cpu *cpu)
168 aarch64_set_next_PC (sim_cpu *cpu, uint64_t next)
170 if (next != cpu->nextpc + 4)
172 "NextPC changes from %16" PRIx64 " to %16" PRIx64,
179 aarch64_set_next_PC_by_offset (sim_cpu *cpu, int64_t offset)
181 if (cpu->pc + offset != cpu->nextpc + 4)
183 "NextPC changes from %16" PRIx64 " to %16" PRIx64,
184 cpu->nextpc, cpu->pc + offset);
186 cpu->nextpc = cpu->pc + offset;
189 /* Install nextpc as current pc. */
191 aarch64_update_PC (sim_cpu *cpu)
193 cpu->pc = cpu->nextpc;
194 /* Rezero the register we hand out when asked for ZR just in case it
195 was used as the destination for a write by the previous
197 cpu->gr[32].u64 = 0UL;
200 /* This instruction can be used to save the next PC to LR
201 just before installing a branch PC. */
203 aarch64_save_LR (sim_cpu *cpu)
205 if (cpu->gr[LR].u64 != cpu->nextpc)
207 "LR changes from %16" PRIx64 " to %16" PRIx64,
208 cpu->gr[LR].u64, cpu->nextpc);
210 cpu->gr[LR].u64 = cpu->nextpc;
214 decode_cpsr (FlagMask flags)
216 switch (flags & CPSR_ALL_FLAGS)
219 case 0: return "----";
220 case 1: return "---V";
221 case 2: return "--C-";
222 case 3: return "--CV";
223 case 4: return "-Z--";
224 case 5: return "-Z-V";
225 case 6: return "-ZC-";
226 case 7: return "-ZCV";
227 case 8: return "N---";
228 case 9: return "N--V";
229 case 10: return "N-C-";
230 case 11: return "N-CV";
231 case 12: return "NZ--";
232 case 13: return "NZ-V";
233 case 14: return "NZC-";
234 case 15: return "NZCV";
238 /* Retrieve the CPSR register as an int. */
240 aarch64_get_CPSR (sim_cpu *cpu)
245 /* Set the CPSR register as an int. */
247 aarch64_set_CPSR (sim_cpu *cpu, uint32_t new_flags)
249 if (TRACE_REGISTER_P (cpu))
251 if (cpu->CPSR != new_flags)
253 "CPSR changes from %s to %s",
254 decode_cpsr (cpu->CPSR), decode_cpsr (new_flags));
257 "CPSR stays at %s", decode_cpsr (cpu->CPSR));
260 cpu->CPSR = new_flags & CPSR_ALL_FLAGS;
263 /* Read a specific subset of the CPSR as a bit pattern. */
265 aarch64_get_CPSR_bits (sim_cpu *cpu, FlagMask mask)
267 return cpu->CPSR & mask;
270 /* Assign a specific subset of the CPSR as a bit pattern. */
272 aarch64_set_CPSR_bits (sim_cpu *cpu, uint32_t mask, uint32_t value)
274 uint32_t old_flags = cpu->CPSR;
276 mask &= CPSR_ALL_FLAGS;
278 cpu->CPSR |= (value & mask);
280 if (old_flags != cpu->CPSR)
282 "CPSR changes from %s to %s",
283 decode_cpsr (old_flags), decode_cpsr (cpu->CPSR));
286 /* Test the value of a single CPSR returned as non-zero or zero. */
288 aarch64_test_CPSR_bit (sim_cpu *cpu, FlagMask bit)
290 return cpu->CPSR & bit;
293 /* Set a single flag in the CPSR. */
295 aarch64_set_CPSR_bit (sim_cpu *cpu, FlagMask bit)
297 uint32_t old_flags = cpu->CPSR;
299 cpu->CPSR |= (bit & CPSR_ALL_FLAGS);
301 if (old_flags != cpu->CPSR)
303 "CPSR changes from %s to %s",
304 decode_cpsr (old_flags), decode_cpsr (cpu->CPSR));
307 /* Clear a single flag in the CPSR. */
309 aarch64_clear_CPSR_bit (sim_cpu *cpu, FlagMask bit)
311 uint32_t old_flags = cpu->CPSR;
313 cpu->CPSR &= ~(bit & CPSR_ALL_FLAGS);
315 if (old_flags != cpu->CPSR)
317 "CPSR changes from %s to %s",
318 decode_cpsr (old_flags), decode_cpsr (cpu->CPSR));
322 aarch64_get_FP_half (sim_cpu *cpu, VReg reg)
331 u.h[1] = cpu->fr[reg].h[0];
337 aarch64_get_FP_float (sim_cpu *cpu, VReg reg)
339 return cpu->fr[reg].s;
343 aarch64_get_FP_double (sim_cpu *cpu, VReg reg)
345 return cpu->fr[reg].d;
349 aarch64_get_FP_long_double (sim_cpu *cpu, VReg reg, FRegister *a)
351 a->v[0] = cpu->fr[reg].v[0];
352 a->v[1] = cpu->fr[reg].v[1];
356 aarch64_set_FP_half (sim_cpu *cpu, VReg reg, float val)
365 cpu->fr[reg].h[0] = u.h[1];
366 cpu->fr[reg].h[1] = 0;
371 aarch64_set_FP_float (sim_cpu *cpu, VReg reg, float val)
373 if (val != cpu->fr[reg].s
374 /* Handle +/- zero. */
375 || signbit (val) != signbit (cpu->fr[reg].s))
381 "FR[%d].s changes from %f to %f [hex: %0lx]",
382 reg, cpu->fr[reg].s, val, v.v[0]);
385 cpu->fr[reg].s = val;
389 aarch64_set_FP_double (sim_cpu *cpu, VReg reg, double val)
391 if (val != cpu->fr[reg].d
392 /* Handle +/- zero. */
393 || signbit (val) != signbit (cpu->fr[reg].d))
399 "FR[%d].d changes from %f to %f [hex: %0lx]",
400 reg, cpu->fr[reg].d, val, v.v[0]);
402 cpu->fr[reg].d = val;
406 aarch64_set_FP_long_double (sim_cpu *cpu, VReg reg, FRegister a)
408 if (cpu->fr[reg].v[0] != a.v[0]
409 || cpu->fr[reg].v[1] != a.v[1])
411 "FR[%d].q changes from [%0lx %0lx] to [%0lx %0lx] ",
413 cpu->fr[reg].v[0], cpu->fr[reg].v[1],
416 cpu->fr[reg].v[0] = a.v[0];
417 cpu->fr[reg].v[1] = a.v[1];
420 #define GET_VEC_ELEMENT(REG, ELEMENT, FIELD) \
423 if (ELEMENT >= ARRAY_SIZE (cpu->fr[0].FIELD)) \
425 TRACE_REGISTER (cpu, \
426 "Internal SIM error: invalid element number: %d ",\
428 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, aarch64_get_PC (cpu), \
429 sim_stopped, SIM_SIGBUS); \
431 return cpu->fr[REG].FIELD [ELEMENT]; \
436 aarch64_get_vec_u64 (sim_cpu *cpu, VReg reg, unsigned element)
438 GET_VEC_ELEMENT (reg, element, v);
442 aarch64_get_vec_u32 (sim_cpu *cpu, VReg reg, unsigned element)
444 GET_VEC_ELEMENT (reg, element, w);
448 aarch64_get_vec_u16 (sim_cpu *cpu, VReg reg, unsigned element)
450 GET_VEC_ELEMENT (reg, element, h);
454 aarch64_get_vec_u8 (sim_cpu *cpu, VReg reg, unsigned element)
456 GET_VEC_ELEMENT (reg, element, b);
460 aarch64_get_vec_s64 (sim_cpu *cpu, VReg reg, unsigned element)
462 GET_VEC_ELEMENT (reg, element, V);
466 aarch64_get_vec_s32 (sim_cpu *cpu, VReg reg, unsigned element)
468 GET_VEC_ELEMENT (reg, element, W);
472 aarch64_get_vec_s16 (sim_cpu *cpu, VReg reg, unsigned element)
474 GET_VEC_ELEMENT (reg, element, H);
478 aarch64_get_vec_s8 (sim_cpu *cpu, VReg reg, unsigned element)
480 GET_VEC_ELEMENT (reg, element, B);
484 aarch64_get_vec_float (sim_cpu *cpu, VReg reg, unsigned element)
486 GET_VEC_ELEMENT (reg, element, S);
490 aarch64_get_vec_double (sim_cpu *cpu, VReg reg, unsigned element)
492 GET_VEC_ELEMENT (reg, element, D);
496 #define SET_VEC_ELEMENT(REG, ELEMENT, VAL, FIELD, PRINTER) \
499 if (ELEMENT >= ARRAY_SIZE (cpu->fr[0].FIELD)) \
501 TRACE_REGISTER (cpu, \
502 "Internal SIM error: invalid element number: %d ",\
504 sim_engine_halt (CPU_STATE (cpu), cpu, NULL, aarch64_get_PC (cpu), \
505 sim_stopped, SIM_SIGBUS); \
507 if (VAL != cpu->fr[REG].FIELD [ELEMENT]) \
508 TRACE_REGISTER (cpu, \
509 "VR[%2d]." #FIELD " [%d] changes from " PRINTER \
510 " to " PRINTER , REG, \
511 ELEMENT, cpu->fr[REG].FIELD [ELEMENT], VAL); \
513 cpu->fr[REG].FIELD [ELEMENT] = VAL; \
518 aarch64_set_vec_u64 (sim_cpu *cpu, VReg reg, unsigned element, uint64_t val)
520 SET_VEC_ELEMENT (reg, element, val, v, "%16lx");
524 aarch64_set_vec_u32 (sim_cpu *cpu, VReg reg, unsigned element, uint32_t val)
526 SET_VEC_ELEMENT (reg, element, val, w, "%8x");
530 aarch64_set_vec_u16 (sim_cpu *cpu, VReg reg, unsigned element, uint16_t val)
532 SET_VEC_ELEMENT (reg, element, val, h, "%4x");
536 aarch64_set_vec_u8 (sim_cpu *cpu, VReg reg, unsigned element, uint8_t val)
538 SET_VEC_ELEMENT (reg, element, val, b, "%x");
542 aarch64_set_vec_s64 (sim_cpu *cpu, VReg reg, unsigned element, int64_t val)
544 SET_VEC_ELEMENT (reg, element, val, V, "%16lx");
548 aarch64_set_vec_s32 (sim_cpu *cpu, VReg reg, unsigned element, int32_t val)
550 SET_VEC_ELEMENT (reg, element, val, W, "%8x");
554 aarch64_set_vec_s16 (sim_cpu *cpu, VReg reg, unsigned element, int16_t val)
556 SET_VEC_ELEMENT (reg, element, val, H, "%4x");
560 aarch64_set_vec_s8 (sim_cpu *cpu, VReg reg, unsigned element, int8_t val)
562 SET_VEC_ELEMENT (reg, element, val, B, "%x");
566 aarch64_set_vec_float (sim_cpu *cpu, VReg reg, unsigned element, float val)
568 SET_VEC_ELEMENT (reg, element, val, S, "%f");
572 aarch64_set_vec_double (sim_cpu *cpu, VReg reg, unsigned element, double val)
574 SET_VEC_ELEMENT (reg, element, val, D, "%f");
578 aarch64_set_FPSR (sim_cpu *cpu, uint32_t value)
580 if (cpu->FPSR != value)
582 "FPSR changes from %x to %x", cpu->FPSR, value);
584 cpu->FPSR = value & FPSR_ALL_FPSRS;
588 aarch64_get_FPSR (sim_cpu *cpu)
594 aarch64_set_FPSR_bits (sim_cpu *cpu, uint32_t mask, uint32_t value)
596 uint32_t old_FPSR = cpu->FPSR;
598 mask &= FPSR_ALL_FPSRS;
600 cpu->FPSR |= (value & mask);
602 if (cpu->FPSR != old_FPSR)
604 "FPSR changes from %x to %x", old_FPSR, cpu->FPSR);
608 aarch64_get_FPSR_bits (sim_cpu *cpu, uint32_t mask)
610 mask &= FPSR_ALL_FPSRS;
611 return cpu->FPSR & mask;
615 aarch64_test_FPSR_bit (sim_cpu *cpu, FPSRMask flag)
617 return cpu->FPSR & flag;
621 aarch64_get_thread_id (sim_cpu *cpu)
627 aarch64_get_FPCR (sim_cpu *cpu)
633 aarch64_set_FPCR (sim_cpu *cpu, uint32_t val)
635 if (cpu->FPCR != val)
637 "FPCR changes from %x to %x", cpu->FPCR, val);