shared-core/via_dma.c

   1 /* via_dma.c -- DMA support for the VIA Unichrome/Pro
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Copyright 2004 Digeo, Inc., Palo Alto, CA, U.S.A.
   7  * All Rights Reserved.
   8  *
   9  * Copyright 2004 The Unichrome project.
  10  * All Rights Reserved.
  11  *
  12  * Permission is hereby granted, free of charge, to any person obtaining a
  13  * copy of this software and associated documentation files (the "Software"),
  14  * to deal in the Software without restriction, including without limitation
  15  * the rights to use, copy, modify, merge, publish, distribute, sub license,
  16  * and/or sell copies of the Software, and to permit persons to whom the
  17  * Software is furnished to do so, subject to the following conditions:
  18  *
  19  * The above copyright notice and this permission notice (including the
  20  * next paragraph) shall be included in all copies or substantial portions
  21  * of the Software.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  24  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  25  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  26  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  27  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  28  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  29  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  30  *
  31  * Authors:
  32  *    Tungsten Graphics,
  33  *    Erdi Chen,
  34  *    Thomas Hellstrom.
  35  */
  36
  37 #include "drmP.h"
  38 #include "drm.h"
  39 #include "via_drm.h"
  40 #include "via_drv.h"
  41 #include "via_3d_reg.h"
  42
  43 #define CMDBUF_ALIGNMENT_SIZE   (0x100)
  44 #define CMDBUF_ALIGNMENT_MASK   (0x0ff)
  45
  46 /* defines for VIA 3D registers */
  47 #define VIA_REG_STATUS    0x400
  48 #define VIA_REG_TRANSET  0x43C
  49 #define VIA_REG_TRANSPACE       0x440
  50
  51 /* VIA_REG_STATUS(0x400): Engine Status */
  52 #define VIA_CMD_RGTR_BUSY       0x00000080      /* Command Regulator is busy */
  53 #define VIA_2D_ENG_BUSY  0x00000001     /* 2D Engine is busy */
  54 #define VIA_3D_ENG_BUSY  0x00000002     /* 3D Engine is busy */
  55 #define VIA_VR_QUEUE_BUSY       0x00020000      /* Virtual Queue is busy */
  56
  57 #define SetReg2DAGP(nReg, nData) {                              \
  58         *((uint32_t *)(vb)) = ((nReg) >> 2) | HALCYON_HEADER1;  \
  59         *((uint32_t *)(vb) + 1) = (nData);                      \
  60         vb = ((uint32_t *)vb) + 2;                              \
  61         dev_priv->dma_low +=8;                                  \
  62 }
  63
  64 #define via_flush_write_combine() DRM_MEMORYBARRIER()
  65
  66 #define VIA_OUT_RING_QW(w1,w2)                  \
  67         *vb++ = (w1);                           \
  68         *vb++ = (w2);                           \
  69         dev_priv->dma_low += 8;
  70
  71 static void via_cmdbuf_start(drm_via_private_t * dev_priv);
  72 static void via_cmdbuf_pause(drm_via_private_t * dev_priv);
  73 static void via_cmdbuf_reset(drm_via_private_t * dev_priv);
  74 static void via_cmdbuf_rewind(drm_via_private_t * dev_priv);
  75 static int via_wait_idle(drm_via_private_t * dev_priv);
  76 static void via_pad_cache(drm_via_private_t *dev_priv, int qwords);
  77
  78
  79 /*
  80  * Free space in command buffer.
  81  */
  82
  83 static uint32_t via_cmdbuf_space(drm_via_private_t *dev_priv)
  84 {
  85         uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
  86         uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base;
  87
  88         return ((hw_addr <= dev_priv->dma_low) ?
  89                 (dev_priv->dma_high + hw_addr - dev_priv->dma_low) :
  90                 (hw_addr - dev_priv->dma_low));
  91 }
  92
  93 /*
  94  * How much does the command regulator lag behind?
  95  */
  96
  97 static uint32_t via_cmdbuf_lag(drm_via_private_t *dev_priv)
  98 {
  99         uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
 100         uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base;
 101
 102         return ((hw_addr <= dev_priv->dma_low) ?
 103                 (dev_priv->dma_low - hw_addr) :
 104                 (dev_priv->dma_wrap + dev_priv->dma_low - hw_addr));
 105 }
 106
 107 /*
 108  * Check that the given size fits in the buffer, otherwise wait.
 109  */
 110
 111 static inline int
 112 via_cmdbuf_wait(drm_via_private_t * dev_priv, unsigned int size)
 113 {
 114         uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
 115         uint32_t cur_addr, hw_addr, next_addr;
 116         volatile uint32_t *hw_addr_ptr;
 117         uint32_t count;
 118         hw_addr_ptr = dev_priv->hw_addr_ptr;
 119         cur_addr = dev_priv->dma_low;
 120         next_addr = cur_addr + size + 512*1024;
 121         count = 1000000;
 122         do {
 123                 hw_addr = *hw_addr_ptr - agp_base;
 124                 if (count-- == 0) {
 125                         DRM_ERROR
 126                             ("via_cmdbuf_wait timed out hw %x cur_addr %x next_addr %x\n",
 127                             hw_addr, cur_addr, next_addr);
 128                         return -1;
 129                 }
 130         } while ((cur_addr < hw_addr) && (next_addr >= hw_addr));
 131         return 0;
 132 }
 133
 134
 135 /*
 136  * Checks whether buffer head has reach the end. Rewind the ring buffer
 137  * when necessary.
 138  *
 139  * Returns virtual pointer to ring buffer.
 140  */
 141
 142 static inline uint32_t *via_check_dma(drm_via_private_t * dev_priv,
 143                                       unsigned int size)
 144 {
 145         if ((dev_priv->dma_low + size + 4 * CMDBUF_ALIGNMENT_SIZE) >
 146             dev_priv->dma_high) {
 147                 via_cmdbuf_rewind(dev_priv);
 148         }
 149         if (via_cmdbuf_wait(dev_priv, size) != 0) {
 150                 return NULL;
 151         }
 152
 153         return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low);
 154 }
 155
 156 int via_dma_cleanup(drm_device_t * dev)
 157 {
 158         if (dev->dev_private) {
 159                 drm_via_private_t *dev_priv =
 160                         (drm_via_private_t *) dev->dev_private;
 161
 162                 if (dev_priv->ring.virtual_start) {
 163                         via_cmdbuf_reset(dev_priv);
 164
 165                         drm_core_ioremapfree(&dev_priv->ring.map, dev);
 166                         dev_priv->ring.virtual_start = NULL;
 167                 }
 168
 169         }
 170
 171         return 0;
 172 }
 173
 174 static int via_initialize(drm_device_t * dev,
 175                           drm_via_private_t * dev_priv,
 176                           drm_via_dma_init_t * init)
 177 {
 178         if (!dev_priv || !dev_priv->mmio) {
 179                 DRM_ERROR("via_dma_init called before via_map_init\n");
 180                 return DRM_ERR(EFAULT);
 181         }
 182
 183         if (dev_priv->ring.virtual_start != NULL) {
 184                 DRM_ERROR("%s called again without calling cleanup\n",
 185                           __FUNCTION__);
 186                 return DRM_ERR(EFAULT);
 187         }
 188
 189         if (!dev->agp || !dev->agp->base) {
 190                 DRM_ERROR("%s called with no agp memory available\n",
 191                           __FUNCTION__);
 192                 return DRM_ERR(EFAULT);
 193         }
 194
 195         dev_priv->ring.map.offset = dev->agp->base + init->offset;
 196         dev_priv->ring.map.size = init->size;
 197         dev_priv->ring.map.type = 0;
 198         dev_priv->ring.map.flags = 0;
 199         dev_priv->ring.map.mtrr = 0;
 200
 201         drm_core_ioremap(&dev_priv->ring.map, dev);
 202
 203         if (dev_priv->ring.map.handle == NULL) {
 204                 via_dma_cleanup(dev);
 205                 DRM_ERROR("can not ioremap virtual address for"
 206                           " ring buffer\n");
 207                 return DRM_ERR(ENOMEM);
 208         }
 209
 210         dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
 211
 212         dev_priv->dma_ptr = dev_priv->ring.virtual_start;
 213         dev_priv->dma_low = 0;
 214         dev_priv->dma_high = init->size;
 215         dev_priv->dma_wrap = init->size;
 216         dev_priv->dma_offset = init->offset;
 217         dev_priv->last_pause_ptr = NULL;
 218         dev_priv->hw_addr_ptr =
 219             (volatile uint32_t *)((char *)dev_priv->mmio->handle +
 220             init->reg_pause_addr);
 221
 222         via_cmdbuf_start(dev_priv);
 223
 224         return 0;
 225 }
 226
 227 static int via_dma_init(DRM_IOCTL_ARGS)
 228 {
 229         DRM_DEVICE;
 230         drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
 231         drm_via_dma_init_t init;
 232         int retcode = 0;
 233
 234         DRM_COPY_FROM_USER_IOCTL(init, (drm_via_dma_init_t __user *) data,
 235                                  sizeof(init));
 236
 237         switch (init.func) {
 238         case VIA_INIT_DMA:
 239                 if (!DRM_SUSER(DRM_CURPROC))
 240                         retcode = DRM_ERR(EPERM);
 241                 else
 242                         retcode = via_initialize(dev, dev_priv, &init);
 243                 break;
 244         case VIA_CLEANUP_DMA:
 245                 if (!DRM_SUSER(DRM_CURPROC))
 246                         retcode = DRM_ERR(EPERM);
 247                 else
 248                         retcode = via_dma_cleanup(dev);
 249                 break;
 250         case VIA_DMA_INITIALIZED:
 251                 retcode = (dev_priv->ring.virtual_start != NULL) ?
 252                         0: DRM_ERR( EFAULT );
 253                 break;
 254         default:
 255                 retcode = DRM_ERR(EINVAL);
 256                 break;
 257         }
 258
 259         return retcode;
 260 }
 261
 262
 263
 264 static int via_dispatch_cmdbuffer(drm_device_t * dev, drm_via_cmdbuffer_t * cmd)
 265 {
 266         drm_via_private_t *dev_priv;
 267         uint32_t *vb;
 268         int ret;
 269
 270         dev_priv = (drm_via_private_t *) dev->dev_private;
 271
 272         if (dev_priv->ring.virtual_start == NULL) {
 273                 DRM_ERROR("%s called without initializing AGP ring buffer.\n",
 274                           __FUNCTION__);
 275                 return DRM_ERR(EFAULT);
 276         }
 277
 278         if (cmd->size > VIA_PCI_BUF_SIZE) {
 279                 return DRM_ERR(ENOMEM);
 280         }
 281
 282
 283         if (DRM_COPY_FROM_USER(dev_priv->pci_buf, cmd->buf, cmd->size))
 284                 return DRM_ERR(EFAULT);
 285
 286         /*
 287          * Running this function on AGP memory is dead slow. Therefore
 288          * we run it on a temporary cacheable system memory buffer and
 289          * copy it to AGP memory when ready.
 290          */
 291
 292         if ((ret =
 293              via_verify_command_stream((uint32_t *)dev_priv->pci_buf,
 294                                        cmd->size, dev, 1))) {
 295                 return ret;
 296         }
 297
 298         vb = via_check_dma(dev_priv, (cmd->size < 0x100) ? 0x102 : cmd->size);
 299         if (vb == NULL) {
 300                 return DRM_ERR(EAGAIN);
 301         }
 302
 303         memcpy(vb, dev_priv->pci_buf, cmd->size);
 304
 305         dev_priv->dma_low += cmd->size;
 306
 307         /*
 308          * Small submissions somehow stalls the CPU. (AGP cache effects?)
 309          * pad to greater size.
 310          */
 311
 312         if (cmd->size < 0x100)
 313           via_pad_cache(dev_priv,(0x100 - cmd->size) >> 3);
 314         via_cmdbuf_pause(dev_priv);
 315
 316         return 0;
 317 }
 318
 319 int via_driver_dma_quiescent(drm_device_t * dev)
 320 {
 321         drm_via_private_t *dev_priv = dev->dev_private;
 322
 323         if (!via_wait_idle(dev_priv)) {
 324                 return DRM_ERR(EBUSY);
 325         }
 326         return 0;
 327 }
 328
 329 static int via_flush_ioctl(DRM_IOCTL_ARGS)
 330 {
 331         DRM_DEVICE;
 332
 333         LOCK_TEST_WITH_RETURN( dev, filp );
 334
 335         return via_driver_dma_quiescent(dev);
 336 }
 337
 338 static int via_cmdbuffer(DRM_IOCTL_ARGS)
 339 {
 340         DRM_DEVICE;
 341         drm_via_cmdbuffer_t cmdbuf;
 342         int ret;
 343
 344         LOCK_TEST_WITH_RETURN( dev, filp );
 345
 346         DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_via_cmdbuffer_t __user *) data,
 347                                  sizeof(cmdbuf));
 348
 349         DRM_DEBUG("via cmdbuffer, buf %p size %lu\n", cmdbuf.buf, cmdbuf.size);
 350
 351         ret = via_dispatch_cmdbuffer(dev, &cmdbuf);
 352         if (ret) {
 353                 return ret;
 354         }
 355
 356         return 0;
 357 }
 358
 359 static int via_dispatch_pci_cmdbuffer(drm_device_t * dev,
 360                                       drm_via_cmdbuffer_t * cmd)
 361 {
 362         drm_via_private_t *dev_priv = dev->dev_private;
 363         int ret;
 364
 365         if (cmd->size > VIA_PCI_BUF_SIZE) {
 366                 return DRM_ERR(ENOMEM);
 367         }
 368         if (DRM_COPY_FROM_USER(dev_priv->pci_buf, cmd->buf, cmd->size))
 369                 return DRM_ERR(EFAULT);
 370
 371         if ((ret =
 372              via_verify_command_stream((uint32_t *)dev_priv->pci_buf,
 373                                        cmd->size, dev, 0))) {
 374                 return ret;
 375         }
 376
 377         ret =
 378             via_parse_command_stream(dev, (const uint32_t *)dev_priv->pci_buf,
 379                                      cmd->size);
 380         return ret;
 381 }
 382
 383 static int via_pci_cmdbuffer(DRM_IOCTL_ARGS)
 384 {
 385         DRM_DEVICE;
 386         drm_via_cmdbuffer_t cmdbuf;
 387         int ret;
 388
 389         LOCK_TEST_WITH_RETURN( dev, filp );
 390
 391         DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_via_cmdbuffer_t __user *) data,
 392                                  sizeof(cmdbuf));
 393
 394         DRM_DEBUG("via_pci_cmdbuffer, buf %p size %lu\n", cmdbuf.buf,
 395                   cmdbuf.size);
 396
 397         ret = via_dispatch_pci_cmdbuffer(dev, &cmdbuf);
 398         if (ret) {
 399                 return ret;
 400         }
 401
 402         return 0;
 403 }
 404
 405
 406 static inline uint32_t *via_align_buffer(drm_via_private_t * dev_priv,
 407                                          uint32_t * vb, int qw_count)
 408 {
 409         for (; qw_count > 0; --qw_count) {
 410                 VIA_OUT_RING_QW(HC_DUMMY, HC_DUMMY);
 411         }
 412         return vb;
 413 }
 414
 415
 416 /*
 417  * This function is used internally by ring buffer mangement code.
 418  *
 419  * Returns virtual pointer to ring buffer.
 420  */
 421 static inline uint32_t *via_get_dma(drm_via_private_t * dev_priv)
 422 {
 423         return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low);
 424 }
 425
 426 /*
 427  * Hooks a segment of data into the tail of the ring-buffer by
 428  * modifying the pause address stored in the buffer itself. If
 429  * the regulator has already paused, restart it.
 430  */
 431 static int via_hook_segment(drm_via_private_t *dev_priv,
 432                             uint32_t pause_addr_hi, uint32_t pause_addr_lo,
 433                             int no_pci_fire)
 434 {
 435         int paused, count;
 436         volatile uint32_t *paused_at = dev_priv->last_pause_ptr;
 437
 438         via_flush_write_combine();
 439         while(! *(via_get_dma(dev_priv)-1));
 440         *dev_priv->last_pause_ptr = pause_addr_lo;
 441         via_flush_write_combine();
 442
 443         /*
 444          * The below statement is inserted to really force the flush.
 445          * Not sure it is needed.
 446          */
 447
 448         while(! *dev_priv->last_pause_ptr);
 449         dev_priv->last_pause_ptr = via_get_dma(dev_priv) - 1;
 450         while(! *dev_priv->last_pause_ptr);
 451
 452
 453         paused = 0;
 454         count = 20;
 455
 456         while (!(paused = (VIA_READ(0x41c) & 0x80000000)) && count--);
 457         if ((count <= 8) && (count >= 0)) {
 458                 uint32_t rgtr, ptr;
 459                 rgtr = *(dev_priv->hw_addr_ptr);
 460                 ptr = ((volatile char *)dev_priv->last_pause_ptr -
 461                       dev_priv->dma_ptr) + dev_priv->dma_offset +
 462                       (uint32_t) dev_priv->agpAddr + 4 - CMDBUF_ALIGNMENT_SIZE;
 463                 if (rgtr <= ptr) {
 464                         DRM_ERROR
 465                            ("Command regulator\npaused at count %d, address %x, "
 466                             "while current pause address is %x.\n"
 467                             "Please mail this message to "
 468                             "<unichrome-devel@lists.sourceforge.net>\n", count,
 469                             rgtr, ptr);
 470                 }
 471         }
 472
 473         if (paused && !no_pci_fire) {
 474                 uint32_t rgtr,ptr;
 475                 uint32_t ptr_low;
 476
 477                 count = 1000000;
 478                 while ((VIA_READ(VIA_REG_STATUS) & VIA_CMD_RGTR_BUSY)
 479                        && count--);
 480
 481                 rgtr = *(dev_priv->hw_addr_ptr);
 482                 ptr = ((volatile char *)paused_at - dev_priv->dma_ptr) +
 483                         dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4;
 484
 485
 486                 ptr_low = (ptr > 3*CMDBUF_ALIGNMENT_SIZE) ?
 487                         ptr - 3*CMDBUF_ALIGNMENT_SIZE : 0;
 488                 if (rgtr <= ptr && rgtr >= ptr_low) {
 489                         VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
 490                         VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi);
 491                         VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo);
 492                 }
 493         }
 494         return paused;
 495 }
 496
 497
 498
 499 static int via_wait_idle(drm_via_private_t * dev_priv)
 500 {
 501         int count = 10000000;
 502         while (count-- && (VIA_READ(VIA_REG_STATUS) &
 503                            (VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY |
 504                             VIA_3D_ENG_BUSY))) ;
 505         return count;
 506 }
 507
 508 static uint32_t *via_align_cmd(drm_via_private_t * dev_priv, uint32_t cmd_type,
 509                                uint32_t addr, uint32_t *cmd_addr_hi,
 510                                uint32_t *cmd_addr_lo, int skip_wait)
 511 {
 512         uint32_t agp_base;
 513         uint32_t cmd_addr, addr_lo, addr_hi;
 514         uint32_t *vb;
 515         uint32_t qw_pad_count;
 516
 517         if (!skip_wait)
 518                 via_cmdbuf_wait(dev_priv, 2*CMDBUF_ALIGNMENT_SIZE);
 519
 520         vb = via_get_dma(dev_priv);
 521         VIA_OUT_RING_QW( HC_HEADER2 | ((VIA_REG_TRANSET >> 2) << 12) |
 522                          (VIA_REG_TRANSPACE >> 2), HC_ParaType_PreCR << 16);
 523         agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
 524         qw_pad_count = (CMDBUF_ALIGNMENT_SIZE >> 3) -
 525                 ((dev_priv->dma_low & CMDBUF_ALIGNMENT_MASK) >> 3);
 526
 527         cmd_addr = (addr) ? addr :
 528                 agp_base + dev_priv->dma_low - 8 + (qw_pad_count << 3);
 529         addr_lo = ((HC_SubA_HAGPBpL << 24) | (cmd_type & HC_HAGPBpID_MASK) |
 530                    (cmd_addr & HC_HAGPBpL_MASK));
 531         addr_hi = ((HC_SubA_HAGPBpH << 24) | (cmd_addr >> 24));
 532
 533         vb = via_align_buffer(dev_priv, vb, qw_pad_count - 1);
 534         VIA_OUT_RING_QW(*cmd_addr_hi = addr_hi, *cmd_addr_lo = addr_lo);
 535         return vb;
 536 }
 537
 538
 539
 540
 541 static void via_cmdbuf_start(drm_via_private_t * dev_priv)
 542 {
 543         uint32_t pause_addr_lo, pause_addr_hi;
 544         uint32_t start_addr, start_addr_lo;
 545         uint32_t end_addr, end_addr_lo;
 546         uint32_t command;
 547         uint32_t agp_base;
 548
 549
 550         dev_priv->dma_low = 0;
 551
 552         agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
 553         start_addr = agp_base;
 554         end_addr = agp_base + dev_priv->dma_high;
 555
 556         start_addr_lo = ((HC_SubA_HAGPBstL << 24) | (start_addr & 0xFFFFFF));
 557         end_addr_lo = ((HC_SubA_HAGPBendL << 24) | (end_addr & 0xFFFFFF));
 558         command = ((HC_SubA_HAGPCMNT << 24) | (start_addr >> 24) |
 559                    ((end_addr & 0xff000000) >> 16));
 560
 561         dev_priv->last_pause_ptr =
 562                 via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0,
 563                               &pause_addr_hi, & pause_addr_lo, 1) - 1;
 564
 565         via_flush_write_combine();
 566         while(! *dev_priv->last_pause_ptr);
 567
 568         VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
 569         VIA_WRITE(VIA_REG_TRANSPACE, command);
 570         VIA_WRITE(VIA_REG_TRANSPACE, start_addr_lo);
 571         VIA_WRITE(VIA_REG_TRANSPACE, end_addr_lo);
 572
 573         VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi);
 574         VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo);
 575
 576         VIA_WRITE(VIA_REG_TRANSPACE, command | HC_HAGPCMNT_MASK);
 577 }
 578
 579 static void via_pad_cache(drm_via_private_t *dev_priv, int qwords)
 580 {
 581         uint32_t *vb;
 582
 583         via_cmdbuf_wait(dev_priv, qwords + 2);
 584         vb = via_get_dma(dev_priv);
 585         VIA_OUT_RING_QW( HC_HEADER2, HC_ParaType_NotTex << 16);
 586         via_align_buffer(dev_priv,vb,qwords);
 587 }
 588
 589 static inline void via_dummy_bitblt(drm_via_private_t * dev_priv)
 590 {
 591         uint32_t *vb = via_get_dma(dev_priv);
 592         SetReg2DAGP(0x0C, (0 | (0 << 16)));
 593         SetReg2DAGP(0x10, 0 | (0 << 16));
 594         SetReg2DAGP(0x0, 0x1 | 0x2000 | 0xAA000000);
 595 }
 596
 597
 598 static void via_cmdbuf_jump(drm_via_private_t * dev_priv)
 599 {
 600         uint32_t agp_base;
 601         uint32_t pause_addr_lo, pause_addr_hi;
 602         uint32_t jump_addr_lo, jump_addr_hi;
 603         volatile uint32_t *last_pause_ptr;
 604         uint32_t dma_low_save1, dma_low_save2;
 605
 606         agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
 607         via_align_cmd(dev_priv,  HC_HAGPBpID_JUMP, 0, &jump_addr_hi,
 608                       &jump_addr_lo, 0);
 609
 610         dev_priv->dma_wrap = dev_priv->dma_low;
 611
 612
 613         /*
 614          * Wrap command buffer to the beginning.
 615          */
 616
 617         dev_priv->dma_low = 0;
 618         if (via_cmdbuf_wait(dev_priv, CMDBUF_ALIGNMENT_SIZE) != 0) {
 619                 DRM_ERROR("via_cmdbuf_jump failed\n");
 620         }
 621
 622         via_dummy_bitblt(dev_priv);
 623         via_dummy_bitblt(dev_priv);
 624
 625         last_pause_ptr =
 626             via_align_cmd(dev_priv,  HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
 627                                        &pause_addr_lo, 0) -1;
 628         via_align_cmd(dev_priv,  HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
 629                       &pause_addr_lo, 0);
 630
 631         *last_pause_ptr = pause_addr_lo;
 632         dma_low_save1 = dev_priv->dma_low;
 633
 634         /*
 635          * Now, set a trap that will pause the regulator if it tries to rerun the old
 636          * command buffer. (Which may happen if via_hook_segment detecs a command regulator pause
 637          * and reissues the jump command over PCI, while the regulator has already taken the jump
 638          * and actually paused at the current buffer end).
 639          * There appears to be no other way to detect this condition, since the hw_addr_pointer
 640          * does not seem to get updated immediately when a jump occurs.
 641          */
 642
 643         last_pause_ptr =
 644             via_align_cmd(dev_priv,  HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
 645                                        &pause_addr_lo, 0) -1;
 646         via_align_cmd(dev_priv,  HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
 647                       &pause_addr_lo, 0);
 648         *last_pause_ptr = pause_addr_lo;
 649
 650         dma_low_save2 = dev_priv->dma_low;
 651         dev_priv->dma_low = dma_low_save1;
 652         via_hook_segment( dev_priv, jump_addr_hi, jump_addr_lo, 0);
 653         dev_priv->dma_low = dma_low_save2;
 654         via_hook_segment( dev_priv, pause_addr_hi, pause_addr_lo, 0);
 655 }
 656
 657
 658 static void via_cmdbuf_rewind(drm_via_private_t * dev_priv)
 659 {
 660         via_cmdbuf_jump(dev_priv);
 661 }
 662
 663 static void via_cmdbuf_flush(drm_via_private_t * dev_priv, uint32_t cmd_type)
 664 {
 665         uint32_t pause_addr_lo, pause_addr_hi;
 666
 667         via_align_cmd(dev_priv, cmd_type, 0, &pause_addr_hi, &pause_addr_lo, 0);
 668         via_hook_segment( dev_priv, pause_addr_hi, pause_addr_lo, 0);
 669 }
 670
 671
 672 static void via_cmdbuf_pause(drm_via_private_t * dev_priv)
 673 {
 674         via_cmdbuf_flush(dev_priv, HC_HAGPBpID_PAUSE);
 675 }
 676
 677 static void via_cmdbuf_reset(drm_via_private_t * dev_priv)
 678 {
 679         via_cmdbuf_flush(dev_priv, HC_HAGPBpID_STOP);
 680         via_wait_idle(dev_priv);
 681 }
 682
 683 /*
 684  * User interface to the space and lag functions.
 685  */
 686
 687 static int via_cmdbuf_size(DRM_IOCTL_ARGS)
 688 {
 689         DRM_DEVICE;
 690         drm_via_cmdbuf_size_t d_siz;
 691         int ret = 0;
 692         uint32_t tmp_size, count;
 693         drm_via_private_t *dev_priv;
 694
 695         DRM_DEBUG("via cmdbuf_size\n");
 696         LOCK_TEST_WITH_RETURN( dev, filp );
 697
 698         dev_priv = (drm_via_private_t *) dev->dev_private;
 699
 700         if (dev_priv->ring.virtual_start == NULL) {
 701                 DRM_ERROR("%s called without initializing AGP ring buffer.\n",
 702                           __FUNCTION__);
 703                 return DRM_ERR(EFAULT);
 704         }
 705
 706         DRM_COPY_FROM_USER_IOCTL(d_siz, (drm_via_cmdbuf_size_t __user *) data,
 707                                  sizeof(d_siz));
 708
 709
 710         count = 1000000;
 711         tmp_size = d_siz.size;
 712         switch(d_siz.func) {
 713         case VIA_CMDBUF_SPACE:
 714                 while (((tmp_size = via_cmdbuf_space(dev_priv)) < d_siz.size)
 715                        && count--) {
 716                         if (!d_siz.wait) {
 717                                 break;
 718                         }
 719                 }
 720                 if (!count) {
 721                         DRM_ERROR("VIA_CMDBUF_SPACE timed out.\n");
 722                         ret = DRM_ERR(EAGAIN);
 723                 }
 724                 break;
 725         case VIA_CMDBUF_LAG:
 726                 while (((tmp_size = via_cmdbuf_lag(dev_priv)) > d_siz.size)
 727                        && count--) {
 728                         if (!d_siz.wait) {
 729                                 break;
 730                         }
 731                 }
 732                 if (!count) {
 733                         DRM_ERROR("VIA_CMDBUF_LAG timed out.\n");
 734                         ret = DRM_ERR(EAGAIN);
 735                 }
 736                 break;
 737         default:
 738                 ret = DRM_ERR(EFAULT);
 739         }
 740         d_siz.size = tmp_size;
 741
 742         DRM_COPY_TO_USER_IOCTL((drm_via_cmdbuf_size_t __user *) data, d_siz,
 743                                sizeof(d_siz));
 744         return ret;
 745 }
 746
 747 #ifndef VIA_HAVE_DMABLIT
 748 int
 749 via_dma_blit_sync( DRM_IOCTL_ARGS ) {
 750         DRM_ERROR("PCI DMA BitBlt is not implemented for this system.\n");
 751         return DRM_ERR(EINVAL);
 752 }
 753 int
 754 via_dma_blit( DRM_IOCTL_ARGS ) {
 755         DRM_ERROR("PCI DMA BitBlt is not implemented for this system.\n");
 756         return DRM_ERR(EINVAL);
 757 }
 758 #endif
 759
 760 drm_ioctl_desc_t via_ioctls[] = {
 761         [DRM_IOCTL_NR(DRM_VIA_ALLOCMEM)] = {via_mem_alloc, DRM_AUTH},
 762         [DRM_IOCTL_NR(DRM_VIA_FREEMEM)] = {via_mem_free, DRM_AUTH},
 763         [DRM_IOCTL_NR(DRM_VIA_AGP_INIT)] = {via_agp_init, DRM_AUTH|DRM_MASTER},
 764         [DRM_IOCTL_NR(DRM_VIA_FB_INIT)] = {via_fb_init, DRM_AUTH|DRM_MASTER},
 765         [DRM_IOCTL_NR(DRM_VIA_MAP_INIT)] = {via_map_init, DRM_AUTH|DRM_MASTER},
 766         [DRM_IOCTL_NR(DRM_VIA_DEC_FUTEX)] = {via_decoder_futex, DRM_AUTH},
 767         [DRM_IOCTL_NR(DRM_VIA_DMA_INIT)] = {via_dma_init, DRM_AUTH},
 768         [DRM_IOCTL_NR(DRM_VIA_CMDBUFFER)] = {via_cmdbuffer, DRM_AUTH},
 769         [DRM_IOCTL_NR(DRM_VIA_FLUSH)] = {via_flush_ioctl, DRM_AUTH},
 770         [DRM_IOCTL_NR(DRM_VIA_PCICMD)] = {via_pci_cmdbuffer, DRM_AUTH},
 771         [DRM_IOCTL_NR(DRM_VIA_CMDBUF_SIZE)] = {via_cmdbuf_size, DRM_AUTH},
 772         [DRM_IOCTL_NR(DRM_VIA_WAIT_IRQ)] = {via_wait_irq, DRM_AUTH},
 773         [DRM_IOCTL_NR(DRM_VIA_DMA_BLIT)] = {via_dma_blit, DRM_AUTH},
 774         [DRM_IOCTL_NR(DRM_VIA_BLIT_SYNC)] = {via_dma_blit_sync, DRM_AUTH}
 775 };
 776
 777 int via_max_ioctl = DRM_ARRAY_SIZE(via_ioctls);