shared-core/via_dma.c

   1 /* via_dma.c -- DMA support for the VIA Unichrome/Pro
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Copyright 2004 Digeo, Inc., Palo Alto, CA, U.S.A.
   7  * All Rights Reserved.
   8  *
   9  * Copyright 2004 The Unichrome project.
  10  * All Rights Reserved.
  11  *
  12  * Permission is hereby granted, free of charge, to any person obtaining a
  13  * copy of this software and associated documentation files (the "Software"),
  14  * to deal in the Software without restriction, including without limitation
  15  * the rights to use, copy, modify, merge, publish, distribute, sub license,
  16  * and/or sell copies of the Software, and to permit persons to whom the
  17  * Software is furnished to do so, subject to the following conditions:
  18  *
  19  * The above copyright notice and this permission notice (including the
  20  * next paragraph) shall be included in all copies or substantial portions
  21  * of the Software.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  24  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  25  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  26  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  27  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  28  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  29  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  30  *
  31  * Authors:
  32  *    Tungsten Graphics,
  33  *    Erdi Chen,
  34  *    Thomas Hellstrom.
  35  */
  36
  37 #include "drmP.h"
  38 #include "drm.h"
  39 #include "via_drm.h"
  40 #include "via_drv.h"
  41 #include "via_3d_reg.h"
  42
  43 #define CMDBUF_ALIGNMENT_SIZE   (0x100)
  44 #define CMDBUF_ALIGNMENT_MASK   (0x0ff)
  45
  46 /* defines for VIA 3D registers */
  47 #define VIA_REG_STATUS    0x400
  48 #define VIA_REG_TRANSET  0x43C
  49 #define VIA_REG_TRANSPACE       0x440
  50
  51 /* VIA_REG_STATUS(0x400): Engine Status */
  52 #define VIA_CMD_RGTR_BUSY       0x00000080      /* Command Regulator is busy */
  53 #define VIA_2D_ENG_BUSY  0x00000001     /* 2D Engine is busy */
  54 #define VIA_3D_ENG_BUSY  0x00000002     /* 3D Engine is busy */
  55 #define VIA_VR_QUEUE_BUSY       0x00020000      /* Virtual Queue is busy */
  56
  57 #define SetReg2DAGP(nReg, nData) {                              \
  58         *((uint32_t *)(vb)) = ((nReg) >> 2) | HALCYON_HEADER1;  \
  59         *((uint32_t *)(vb) + 1) = (nData);                      \
  60         vb = ((uint32_t *)vb) + 2;                              \
  61         dev_priv->dma_low +=8;                                  \
  62 }
  63
  64 #define via_flush_write_combine() DRM_MEMORYBARRIER()
  65
  66 #define VIA_OUT_RING_QW(w1,w2)                  \
  67         *vb++ = (w1);                           \
  68         *vb++ = (w2);                           \
  69         dev_priv->dma_low += 8;
  70
  71 static void via_cmdbuf_start(drm_via_private_t * dev_priv);
  72 static void via_cmdbuf_pause(drm_via_private_t * dev_priv);
  73 static void via_cmdbuf_reset(drm_via_private_t * dev_priv);
  74 static void via_cmdbuf_rewind(drm_via_private_t * dev_priv);
  75 static int via_wait_idle(drm_via_private_t * dev_priv);
  76 static void via_pad_cache(drm_via_private_t *dev_priv, int qwords);
  77
  78
  79 /*
  80  * Free space in command buffer.
  81  */
  82
  83 static uint32_t via_cmdbuf_space(drm_via_private_t *dev_priv)
  84 {
  85         uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
  86         uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base;
  87
  88         return ((hw_addr <= dev_priv->dma_low) ?
  89                 (dev_priv->dma_high + hw_addr - dev_priv->dma_low) :
  90                 (hw_addr - dev_priv->dma_low));
  91 }
  92
  93 /*
  94  * How much does the command regulator lag behind?
  95  */
  96
  97 static uint32_t via_cmdbuf_lag(drm_via_private_t *dev_priv)
  98 {
  99         uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
 100         uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base;
 101
 102         return ((hw_addr <= dev_priv->dma_low) ?
 103                 (dev_priv->dma_low - hw_addr) :
 104                 (dev_priv->dma_wrap + dev_priv->dma_low - hw_addr));
 105 }
 106
 107 /*
 108  * Check that the given size fits in the buffer, otherwise wait.
 109  */
 110
 111 static inline int
 112 via_cmdbuf_wait(drm_via_private_t * dev_priv, unsigned int size)
 113 {
 114         uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
 115         uint32_t cur_addr, hw_addr, next_addr;
 116         volatile uint32_t *hw_addr_ptr;
 117         uint32_t count;
 118         hw_addr_ptr = dev_priv->hw_addr_ptr;
 119         cur_addr = dev_priv->dma_low;
 120         next_addr = cur_addr + size + 512*1024;
 121         count = 1000000;
 122         do {
 123                 hw_addr = *hw_addr_ptr - agp_base;
 124                 if (count-- == 0) {
 125                         DRM_ERROR
 126                             ("via_cmdbuf_wait timed out hw %x cur_addr %x next_addr %x\n",
 127                             hw_addr, cur_addr, next_addr);
 128                         return -1;
 129                 }
 130         } while ((cur_addr < hw_addr) && (next_addr >= hw_addr));
 131         return 0;
 132 }
 133
 134
 135 /*
 136  * Checks whether buffer head has reach the end. Rewind the ring buffer
 137  * when necessary.
 138  *
 139  * Returns virtual pointer to ring buffer.
 140  */
 141
 142 static inline uint32_t *via_check_dma(drm_via_private_t * dev_priv,
 143                                       unsigned int size)
 144 {
 145         if ((dev_priv->dma_low + size + 4 * CMDBUF_ALIGNMENT_SIZE) >
 146             dev_priv->dma_high) {
 147                 via_cmdbuf_rewind(dev_priv);
 148         }
 149         if (via_cmdbuf_wait(dev_priv, size) != 0) {
 150                 return NULL;
 151         }
 152
 153         return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low);
 154 }
 155
 156 int via_dma_cleanup(drm_device_t * dev)
 157 {
 158         if (dev->dev_private) {
 159                 drm_via_private_t *dev_priv =
 160                         (drm_via_private_t *) dev->dev_private;
 161
 162                 if (dev_priv->ring.virtual_start) {
 163                         via_cmdbuf_reset(dev_priv);
 164
 165                         drm_core_ioremapfree(&dev_priv->ring.map, dev);
 166                         dev_priv->ring.virtual_start = NULL;
 167                 }
 168
 169         }
 170
 171         return 0;
 172 }
 173
 174 static int via_initialize(drm_device_t * dev,
 175                           drm_via_private_t * dev_priv,
 176                           drm_via_dma_init_t * init)
 177 {
 178         if (!dev_priv || !dev_priv->mmio) {
 179                 DRM_ERROR("via_dma_init called before via_map_init\n");
 180                 return DRM_ERR(EFAULT);
 181         }
 182
 183         if (dev_priv->ring.virtual_start != NULL) {
 184                 DRM_ERROR("%s called again without calling cleanup\n",
 185                           __FUNCTION__);
 186                 return DRM_ERR(EFAULT);
 187         }
 188
 189         if (!dev->agp || !dev->agp->base) {
 190                 DRM_ERROR("%s called with no agp memory available\n",
 191                           __FUNCTION__);
 192                 return DRM_ERR(EFAULT);
 193         }
 194
 195         if (dev_priv->chipset == VIA_DX9_0) {
 196                 DRM_ERROR("AGP DMA is not supported on this chip\n");
 197                 return DRM_ERR(EINVAL);
 198         }
 199
 200         dev_priv->ring.map.offset = dev->agp->base + init->offset;
 201         dev_priv->ring.map.size = init->size;
 202         dev_priv->ring.map.type = 0;
 203         dev_priv->ring.map.flags = 0;
 204         dev_priv->ring.map.mtrr = 0;
 205
 206         drm_core_ioremap(&dev_priv->ring.map, dev);
 207
 208         if (dev_priv->ring.map.handle == NULL) {
 209                 via_dma_cleanup(dev);
 210                 DRM_ERROR("can not ioremap virtual address for"
 211                           " ring buffer\n");
 212                 return DRM_ERR(ENOMEM);
 213         }
 214
 215         dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
 216
 217         dev_priv->dma_ptr = dev_priv->ring.virtual_start;
 218         dev_priv->dma_low = 0;
 219         dev_priv->dma_high = init->size;
 220         dev_priv->dma_wrap = init->size;
 221         dev_priv->dma_offset = init->offset;
 222         dev_priv->last_pause_ptr = NULL;
 223         dev_priv->hw_addr_ptr =
 224             (volatile uint32_t *)((char *)dev_priv->mmio->handle +
 225             init->reg_pause_addr);
 226
 227         via_cmdbuf_start(dev_priv);
 228
 229         return 0;
 230 }
 231
 232 static int via_dma_init(DRM_IOCTL_ARGS)
 233 {
 234         DRM_DEVICE;
 235         drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
 236         drm_via_dma_init_t init;
 237         int retcode = 0;
 238
 239         DRM_COPY_FROM_USER_IOCTL(init, (drm_via_dma_init_t __user *) data,
 240                                  sizeof(init));
 241
 242         switch (init.func) {
 243         case VIA_INIT_DMA:
 244                 if (!DRM_SUSER(DRM_CURPROC))
 245                         retcode = DRM_ERR(EPERM);
 246                 else
 247                         retcode = via_initialize(dev, dev_priv, &init);
 248                 break;
 249         case VIA_CLEANUP_DMA:
 250                 if (!DRM_SUSER(DRM_CURPROC))
 251                         retcode = DRM_ERR(EPERM);
 252                 else
 253                         retcode = via_dma_cleanup(dev);
 254                 break;
 255         case VIA_DMA_INITIALIZED:
 256                 retcode = (dev_priv->ring.virtual_start != NULL) ?
 257                         0: DRM_ERR( EFAULT );
 258                 break;
 259         default:
 260                 retcode = DRM_ERR(EINVAL);
 261                 break;
 262         }
 263
 264         return retcode;
 265 }
 266
 267
 268
 269 static int via_dispatch_cmdbuffer(drm_device_t * dev, drm_via_cmdbuffer_t * cmd)
 270 {
 271         drm_via_private_t *dev_priv;
 272         uint32_t *vb;
 273         int ret;
 274
 275         dev_priv = (drm_via_private_t *) dev->dev_private;
 276
 277         if (dev_priv->ring.virtual_start == NULL) {
 278                 DRM_ERROR("%s called without initializing AGP ring buffer.\n",
 279                           __FUNCTION__);
 280                 return DRM_ERR(EFAULT);
 281         }
 282
 283         if (cmd->size > VIA_PCI_BUF_SIZE) {
 284                 return DRM_ERR(ENOMEM);
 285         }
 286
 287
 288         if (DRM_COPY_FROM_USER(dev_priv->pci_buf, cmd->buf, cmd->size))
 289                 return DRM_ERR(EFAULT);
 290
 291         /*
 292          * Running this function on AGP memory is dead slow. Therefore
 293          * we run it on a temporary cacheable system memory buffer and
 294          * copy it to AGP memory when ready.
 295          */
 296
 297         if ((ret =
 298              via_verify_command_stream((uint32_t *)dev_priv->pci_buf,
 299                                        cmd->size, dev, 1))) {
 300                 return ret;
 301         }
 302
 303         vb = via_check_dma(dev_priv, (cmd->size < 0x100) ? 0x102 : cmd->size);
 304         if (vb == NULL) {
 305                 return DRM_ERR(EAGAIN);
 306         }
 307
 308         memcpy(vb, dev_priv->pci_buf, cmd->size);
 309
 310         dev_priv->dma_low += cmd->size;
 311
 312         /*
 313          * Small submissions somehow stalls the CPU. (AGP cache effects?)
 314          * pad to greater size.
 315          */
 316
 317         if (cmd->size < 0x100)
 318           via_pad_cache(dev_priv,(0x100 - cmd->size) >> 3);
 319         via_cmdbuf_pause(dev_priv);
 320
 321         return 0;
 322 }
 323
 324 int via_driver_dma_quiescent(drm_device_t * dev)
 325 {
 326         drm_via_private_t *dev_priv = dev->dev_private;
 327
 328         if (!via_wait_idle(dev_priv)) {
 329                 return DRM_ERR(EBUSY);
 330         }
 331         return 0;
 332 }
 333
 334 static int via_flush_ioctl(DRM_IOCTL_ARGS)
 335 {
 336         DRM_DEVICE;
 337
 338         LOCK_TEST_WITH_RETURN( dev, filp );
 339
 340         return via_driver_dma_quiescent(dev);
 341 }
 342
 343 static int via_cmdbuffer(DRM_IOCTL_ARGS)
 344 {
 345         DRM_DEVICE;
 346         drm_via_cmdbuffer_t cmdbuf;
 347         int ret;
 348
 349         LOCK_TEST_WITH_RETURN( dev, filp );
 350
 351         DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_via_cmdbuffer_t __user *) data,
 352                                  sizeof(cmdbuf));
 353
 354         DRM_DEBUG("via cmdbuffer, buf %p size %lu\n", cmdbuf.buf, cmdbuf.size);
 355
 356         ret = via_dispatch_cmdbuffer(dev, &cmdbuf);
 357         if (ret) {
 358                 return ret;
 359         }
 360
 361         return 0;
 362 }
 363
 364 static int via_dispatch_pci_cmdbuffer(drm_device_t * dev,
 365                                       drm_via_cmdbuffer_t * cmd)
 366 {
 367         drm_via_private_t *dev_priv = dev->dev_private;
 368         int ret;
 369
 370         if (cmd->size > VIA_PCI_BUF_SIZE) {
 371                 return DRM_ERR(ENOMEM);
 372         }
 373         if (DRM_COPY_FROM_USER(dev_priv->pci_buf, cmd->buf, cmd->size))
 374                 return DRM_ERR(EFAULT);
 375
 376         if ((ret =
 377              via_verify_command_stream((uint32_t *)dev_priv->pci_buf,
 378                                        cmd->size, dev, 0))) {
 379                 return ret;
 380         }
 381
 382         ret =
 383             via_parse_command_stream(dev, (const uint32_t *)dev_priv->pci_buf,
 384                                      cmd->size);
 385         return ret;
 386 }
 387
 388 static int via_pci_cmdbuffer(DRM_IOCTL_ARGS)
 389 {
 390         DRM_DEVICE;
 391         drm_via_cmdbuffer_t cmdbuf;
 392         int ret;
 393
 394         LOCK_TEST_WITH_RETURN( dev, filp );
 395
 396         DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_via_cmdbuffer_t __user *) data,
 397                                  sizeof(cmdbuf));
 398
 399         DRM_DEBUG("via_pci_cmdbuffer, buf %p size %lu\n", cmdbuf.buf,
 400                   cmdbuf.size);
 401
 402         ret = via_dispatch_pci_cmdbuffer(dev, &cmdbuf);
 403         if (ret) {
 404                 return ret;
 405         }
 406
 407         return 0;
 408 }
 409
 410
 411 static inline uint32_t *via_align_buffer(drm_via_private_t * dev_priv,
 412                                          uint32_t * vb, int qw_count)
 413 {
 414         for (; qw_count > 0; --qw_count) {
 415                 VIA_OUT_RING_QW(HC_DUMMY, HC_DUMMY);
 416         }
 417         return vb;
 418 }
 419
 420
 421 /*
 422  * This function is used internally by ring buffer mangement code.
 423  *
 424  * Returns virtual pointer to ring buffer.
 425  */
 426 static inline uint32_t *via_get_dma(drm_via_private_t * dev_priv)
 427 {
 428         return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low);
 429 }
 430
 431 /*
 432  * Hooks a segment of data into the tail of the ring-buffer by
 433  * modifying the pause address stored in the buffer itself. If
 434  * the regulator has already paused, restart it.
 435  */
 436
 437 static int via_hook_segment(drm_via_private_t *dev_priv,
 438                             uint32_t pause_addr_hi, uint32_t pause_addr_lo,
 439                             int no_pci_fire)
 440 {
 441         int paused, count;
 442         volatile uint32_t *paused_at = dev_priv->last_pause_ptr;
 443         uint32_t reader,ptr;
 444
 445         paused = 0;
 446         via_flush_write_combine();
 447         *dev_priv->last_pause_ptr = pause_addr_lo;
 448         via_flush_write_combine();
 449         reader = *(dev_priv->hw_addr_ptr);
 450         ptr = ((volatile char *)paused_at - dev_priv->dma_ptr) +
 451                 dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4;
 452         dev_priv->last_pause_ptr = via_get_dma(dev_priv) - 1;
 453
 454         if ((ptr - reader) <= dev_priv->dma_diff ) {
 455                 count = 10000000;
 456                 while (!(paused = (VIA_READ(0x41c) & 0x80000000)) && count--);
 457         }
 458
 459         if (paused && !no_pci_fire) {
 460                 reader = *(dev_priv->hw_addr_ptr);
 461                 if ((ptr - reader) == dev_priv->dma_diff) {
 462
 463                         /*
 464                          * There is a concern that these writes may stall the PCI bus
 465                          * if the GPU is not idle. However, idling the GPU first
 466                          * doesn't make a difference.
 467                          */
 468
 469                         VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
 470                         VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi);
 471                         VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo);
 472                         VIA_READ(VIA_REG_TRANSPACE);
 473                 }
 474         }
 475
 476         return paused;
 477 }
 478
 479
 480
 481 static int via_wait_idle(drm_via_private_t * dev_priv)
 482 {
 483         int count = 10000000;
 484
 485         while (!(VIA_READ(VIA_REG_STATUS) & VIA_VR_QUEUE_BUSY) && count--);
 486
 487         while (count-- && (VIA_READ(VIA_REG_STATUS) &
 488                            (VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY |
 489                             VIA_3D_ENG_BUSY))) ;
 490         return count;
 491 }
 492
 493 static uint32_t *via_align_cmd(drm_via_private_t * dev_priv, uint32_t cmd_type,
 494                                uint32_t addr, uint32_t *cmd_addr_hi,
 495                                uint32_t *cmd_addr_lo, int skip_wait)
 496 {
 497         uint32_t agp_base;
 498         uint32_t cmd_addr, addr_lo, addr_hi;
 499         uint32_t *vb;
 500         uint32_t qw_pad_count;
 501
 502         if (!skip_wait)
 503                 via_cmdbuf_wait(dev_priv, 2*CMDBUF_ALIGNMENT_SIZE);
 504
 505         vb = via_get_dma(dev_priv);
 506         VIA_OUT_RING_QW( HC_HEADER2 | ((VIA_REG_TRANSET >> 2) << 12) |
 507                          (VIA_REG_TRANSPACE >> 2), HC_ParaType_PreCR << 16);
 508         agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
 509         qw_pad_count = (CMDBUF_ALIGNMENT_SIZE >> 3) -
 510                 ((dev_priv->dma_low & CMDBUF_ALIGNMENT_MASK) >> 3);
 511
 512         cmd_addr = (addr) ? addr :
 513                 agp_base + dev_priv->dma_low - 8 + (qw_pad_count << 3);
 514         addr_lo = ((HC_SubA_HAGPBpL << 24) | (cmd_type & HC_HAGPBpID_MASK) |
 515                    (cmd_addr & HC_HAGPBpL_MASK));
 516         addr_hi = ((HC_SubA_HAGPBpH << 24) | (cmd_addr >> 24));
 517
 518         vb = via_align_buffer(dev_priv, vb, qw_pad_count - 1);
 519         VIA_OUT_RING_QW(*cmd_addr_hi = addr_hi, *cmd_addr_lo = addr_lo);
 520         return vb;
 521 }
 522
 523
 524
 525
 526 static void via_cmdbuf_start(drm_via_private_t * dev_priv)
 527 {
 528         uint32_t pause_addr_lo, pause_addr_hi;
 529         uint32_t start_addr, start_addr_lo;
 530         uint32_t end_addr, end_addr_lo;
 531         uint32_t command;
 532         uint32_t agp_base;
 533         uint32_t ptr;
 534         uint32_t reader;
 535         int count;
 536
 537         dev_priv->dma_low = 0;
 538
 539         agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
 540         start_addr = agp_base;
 541         end_addr = agp_base + dev_priv->dma_high;
 542
 543         start_addr_lo = ((HC_SubA_HAGPBstL << 24) | (start_addr & 0xFFFFFF));
 544         end_addr_lo = ((HC_SubA_HAGPBendL << 24) | (end_addr & 0xFFFFFF));
 545         command = ((HC_SubA_HAGPCMNT << 24) | (start_addr >> 24) |
 546                    ((end_addr & 0xff000000) >> 16));
 547
 548         dev_priv->last_pause_ptr =
 549                 via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0,
 550                               &pause_addr_hi, & pause_addr_lo, 1) - 1;
 551
 552         via_flush_write_combine();
 553         while(! *dev_priv->last_pause_ptr);
 554
 555         VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
 556         VIA_WRITE(VIA_REG_TRANSPACE, command);
 557         VIA_WRITE(VIA_REG_TRANSPACE, start_addr_lo);
 558         VIA_WRITE(VIA_REG_TRANSPACE, end_addr_lo);
 559
 560         VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi);
 561         VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo);
 562         DRM_WRITEMEMORYBARRIER();
 563         VIA_WRITE(VIA_REG_TRANSPACE, command | HC_HAGPCMNT_MASK);
 564         VIA_READ(VIA_REG_TRANSPACE);
 565
 566         dev_priv->dma_diff = 0;
 567
 568         count = 10000000;
 569         while (!(VIA_READ(0x41c) & 0x80000000) && count--);
 570
 571         reader = *(dev_priv->hw_addr_ptr);
 572         ptr = ((volatile char *)dev_priv->last_pause_ptr - dev_priv->dma_ptr) +
 573             dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4;
 574
 575         /*
 576          * This is the difference between where we tell the
 577          * command reader to pause and where it actually pauses.
 578          * This differs between hw implementation so we need to
 579          * detect it.
 580          */
 581
 582         dev_priv->dma_diff = ptr - reader;
 583 }
 584
 585 static void via_pad_cache(drm_via_private_t *dev_priv, int qwords)
 586 {
 587         uint32_t *vb;
 588
 589         via_cmdbuf_wait(dev_priv, qwords + 2);
 590         vb = via_get_dma(dev_priv);
 591         VIA_OUT_RING_QW( HC_HEADER2, HC_ParaType_NotTex << 16);
 592         via_align_buffer(dev_priv,vb,qwords);
 593 }
 594
 595 static inline void via_dummy_bitblt(drm_via_private_t * dev_priv)
 596 {
 597         uint32_t *vb = via_get_dma(dev_priv);
 598         SetReg2DAGP(0x0C, (0 | (0 << 16)));
 599         SetReg2DAGP(0x10, 0 | (0 << 16));
 600         SetReg2DAGP(0x0, 0x1 | 0x2000 | 0xAA000000);
 601 }
 602
 603 static void via_cmdbuf_jump(drm_via_private_t * dev_priv)
 604 {
 605         uint32_t agp_base;
 606         uint32_t pause_addr_lo, pause_addr_hi;
 607         uint32_t jump_addr_lo, jump_addr_hi;
 608         volatile uint32_t *last_pause_ptr;
 609
 610         agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
 611         via_align_cmd(dev_priv,  HC_HAGPBpID_JUMP, 0, &jump_addr_hi,
 612                       &jump_addr_lo, 0);
 613
 614         dev_priv->dma_wrap = dev_priv->dma_low;
 615
 616
 617         /*
 618          * Wrap command buffer to the beginning.
 619          */
 620
 621         dev_priv->dma_low = 0;
 622         if (via_cmdbuf_wait(dev_priv, CMDBUF_ALIGNMENT_SIZE) != 0) {
 623                 DRM_ERROR("via_cmdbuf_jump failed\n");
 624         }
 625
 626         via_dummy_bitblt(dev_priv);
 627         via_dummy_bitblt(dev_priv);
 628         last_pause_ptr = via_align_cmd(dev_priv,  HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
 629                                        &pause_addr_lo, 0) -1;
 630         via_align_cmd(dev_priv,  HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
 631                       &pause_addr_lo, 0);
 632         *last_pause_ptr = pause_addr_lo;
 633
 634         via_hook_segment( dev_priv, jump_addr_hi, jump_addr_lo, 0);
 635 }
 636
 637
 638 static void via_cmdbuf_rewind(drm_via_private_t * dev_priv)
 639 {
 640         via_cmdbuf_jump(dev_priv);
 641 }
 642
 643 static void via_cmdbuf_flush(drm_via_private_t * dev_priv, uint32_t cmd_type)
 644 {
 645         uint32_t pause_addr_lo, pause_addr_hi;
 646
 647         via_align_cmd(dev_priv, cmd_type, 0, &pause_addr_hi, &pause_addr_lo, 0);
 648         via_hook_segment( dev_priv, pause_addr_hi, pause_addr_lo, 0);
 649 }
 650
 651
 652 static void via_cmdbuf_pause(drm_via_private_t * dev_priv)
 653 {
 654         via_cmdbuf_flush(dev_priv, HC_HAGPBpID_PAUSE);
 655 }
 656
 657 static void via_cmdbuf_reset(drm_via_private_t * dev_priv)
 658 {
 659         via_cmdbuf_flush(dev_priv, HC_HAGPBpID_STOP);
 660         via_wait_idle(dev_priv);
 661 }
 662
 663 /*
 664  * User interface to the space and lag functions.
 665  */
 666
 667 static int via_cmdbuf_size(DRM_IOCTL_ARGS)
 668 {
 669         DRM_DEVICE;
 670         drm_via_cmdbuf_size_t d_siz;
 671         int ret = 0;
 672         uint32_t tmp_size, count;
 673         drm_via_private_t *dev_priv;
 674
 675         DRM_DEBUG("via cmdbuf_size\n");
 676         LOCK_TEST_WITH_RETURN( dev, filp );
 677
 678         dev_priv = (drm_via_private_t *) dev->dev_private;
 679
 680         if (dev_priv->ring.virtual_start == NULL) {
 681                 DRM_ERROR("%s called without initializing AGP ring buffer.\n",
 682                           __FUNCTION__);
 683                 return DRM_ERR(EFAULT);
 684         }
 685
 686         DRM_COPY_FROM_USER_IOCTL(d_siz, (drm_via_cmdbuf_size_t __user *) data,
 687                                  sizeof(d_siz));
 688
 689
 690         count = 1000000;
 691         tmp_size = d_siz.size;
 692         switch(d_siz.func) {
 693         case VIA_CMDBUF_SPACE:
 694                 while (((tmp_size = via_cmdbuf_space(dev_priv)) < d_siz.size)
 695                        && count--) {
 696                         if (!d_siz.wait) {
 697                                 break;
 698                         }
 699                 }
 700                 if (!count) {
 701                         DRM_ERROR("VIA_CMDBUF_SPACE timed out.\n");
 702                         ret = DRM_ERR(EAGAIN);
 703                 }
 704                 break;
 705         case VIA_CMDBUF_LAG:
 706                 while (((tmp_size = via_cmdbuf_lag(dev_priv)) > d_siz.size)
 707                        && count--) {
 708                         if (!d_siz.wait) {
 709                                 break;
 710                         }
 711                 }
 712                 if (!count) {
 713                         DRM_ERROR("VIA_CMDBUF_LAG timed out.\n");
 714                         ret = DRM_ERR(EAGAIN);
 715                 }
 716                 break;
 717         default:
 718                 ret = DRM_ERR(EFAULT);
 719         }
 720         d_siz.size = tmp_size;
 721
 722         DRM_COPY_TO_USER_IOCTL((drm_via_cmdbuf_size_t __user *) data, d_siz,
 723                                sizeof(d_siz));
 724         return ret;
 725 }
 726
 727 #ifndef VIA_HAVE_DMABLIT
 728 int
 729 via_dma_blit_sync( DRM_IOCTL_ARGS ) {
 730         DRM_ERROR("PCI DMA BitBlt is not implemented for this system.\n");
 731         return DRM_ERR(EINVAL);
 732 }
 733 int
 734 via_dma_blit( DRM_IOCTL_ARGS ) {
 735         DRM_ERROR("PCI DMA BitBlt is not implemented for this system.\n");
 736         return DRM_ERR(EINVAL);
 737 }
 738 #endif
 739
 740 drm_ioctl_desc_t via_ioctls[] = {
 741         [DRM_IOCTL_NR(DRM_VIA_ALLOCMEM)] = {via_mem_alloc, DRM_AUTH},
 742         [DRM_IOCTL_NR(DRM_VIA_FREEMEM)] = {via_mem_free, DRM_AUTH},
 743         [DRM_IOCTL_NR(DRM_VIA_AGP_INIT)] = {via_agp_init, DRM_AUTH|DRM_MASTER},
 744         [DRM_IOCTL_NR(DRM_VIA_FB_INIT)] = {via_fb_init, DRM_AUTH|DRM_MASTER},
 745         [DRM_IOCTL_NR(DRM_VIA_MAP_INIT)] = {via_map_init, DRM_AUTH|DRM_MASTER},
 746         [DRM_IOCTL_NR(DRM_VIA_DEC_FUTEX)] = {via_decoder_futex, DRM_AUTH},
 747         [DRM_IOCTL_NR(DRM_VIA_DMA_INIT)] = {via_dma_init, DRM_AUTH},
 748         [DRM_IOCTL_NR(DRM_VIA_CMDBUFFER)] = {via_cmdbuffer, DRM_AUTH},
 749         [DRM_IOCTL_NR(DRM_VIA_FLUSH)] = {via_flush_ioctl, DRM_AUTH},
 750         [DRM_IOCTL_NR(DRM_VIA_PCICMD)] = {via_pci_cmdbuffer, DRM_AUTH},
 751         [DRM_IOCTL_NR(DRM_VIA_CMDBUF_SIZE)] = {via_cmdbuf_size, DRM_AUTH},
 752         [DRM_IOCTL_NR(DRM_VIA_WAIT_IRQ)] = {via_wait_irq, DRM_AUTH},
 753         [DRM_IOCTL_NR(DRM_VIA_DMA_BLIT)] = {via_dma_blit, DRM_AUTH},
 754         [DRM_IOCTL_NR(DRM_VIA_BLIT_SYNC)] = {via_dma_blit_sync, DRM_AUTH}
 755 };
 756
 757 int via_max_ioctl = DRM_ARRAY_SIZE(via_ioctls);