2 * Copyright 2007 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 #ifndef __RADEON_REG_H__
23 #define __RADEON_REG_H__
25 #define MC_FB_LOCATION 0x00000148
26 #define MC_FB_LOCATION__MC_FB_START__MASK 0x0000FFFF
27 #define MC_FB_LOCATION__MC_FB_START__SHIFT 0
28 #define MC_FB_LOCATION__MC_FB_TOP__MASK 0xFFFF0000
29 #define MC_FB_LOCATION__MC_FB_TOP__SHIFT 16
30 #define MC_AGP_LOCATION 0x0000014C
31 #define MC_AGP_LOCATION__MC_AGP_START__MASK 0x0000FFFF
32 #define MC_AGP_LOCATION__MC_AGP_START__SHIFT 0
33 #define MC_AGP_LOCATION__MC_AGP_TOP__MASK 0xFFFF0000
34 #define MC_AGP_LOCATION__MC_AGP_TOP__SHIFT 16
35 #define AGP_COMMAND 0x00000F60
36 #define AGP_COMMAND__DATA_RATE__MASK 0x00000007
37 #define AGP_COMMAND__DATA_RATE__SHIFT 0
38 #define DATA_RATE__v2_1X 0x1
39 #define DATA_RATE__v2_2X 0x2
40 #define DATA_RATE__v2_4X 0x4
41 #define DATA_RATE__v3_4X 0x1
42 #define DATA_RATE__v3_8X 0x2
43 #define AGP_COMMAND__AGP_EN 0x00000100
44 #define AGP_COMMAND__SBA_EN 0x00000200
45 #define AGP_COMMAND__RQ_DEPTH__MASK 0xFF000000
46 #define AGP_COMMAND__RQ_DEPTH__SHIFT 24
47 #define AGP_COMMAND__FW_EN 0x00000010
48 #define AGP_COMMAND__MODE_4G_EN 0x00000020
49 #define AGP_COMMAND__PARQSZ__MASK 0x0000E000
50 #define AGP_COMMAND__PARQSZ__SHIFT 13
51 #define AGP_STATUS 0x00000F5C
52 #define AGP_STATUS__RATE1X 0x00000001
53 #define AGP_STATUS__RATE2X 0x00000002
54 #define AGP_STATUS__RATE4X 0x00000004
55 #define AGP_STATUS__SBA 0x00000200
56 #define AGP_STATUS__RQ__MASK 0xFF000000
57 #define AGP_STATUS__RQ__SHIFT 24
58 #define AGP_STATUS__FW 0x00000010
59 #define AGP_STATUS__MODE_4G 0x00000020
60 #define AGP_STATUS__RATE1X_4X 0x00000001
61 #define AGP_STATUS__RATE2X_8X 0x00000002
62 #define AGP_STATUS__MODE_AGP30 0x00000008
63 #define AGP_STATUS__CAL_CYCLE__MASK 0x00001C00
64 #define AGP_STATUS__CAL_CYCLE__SHIFT 10
65 #define AGP_STATUS__ISOCH_SUPPORT 0x00020000
66 #define AGP_BASE 0x00000170
67 #define AGP_BASE__AGP_BASE_ADDR__MASK 0xFFFFFFFF
68 #define AGP_BASE__AGP_BASE_ADDR__SHIFT 0
69 #define AGP_BASE_2 0x0000015C
70 #define AGP_BASE_2__AGP_BASE_ADDR_2__MASK 0x0000000F
71 #define AGP_BASE_2__AGP_BASE_ADDR_2__SHIFT 0
72 #define CONFIG_MEMSIZE 0x000000F8
73 #define CONFIG_MEMSIZE__CONFIG_MEMSIZE__MASK 0x1F000000
74 #define CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 24
75 #define CONFIG_MEMSIZE__CONFIG_MEMSIZE_R2__MASK 0x1FF00000
76 #define CONFIG_MEMSIZE__CONFIG_MEMSIZE_R2__SHIFT 20
77 #define CONFIG_APER_0_BASE 0x00000100
78 #define CONFIG_APER_0_BASE__APER_0_BASE__MASK 0xFE000000
79 #define CONFIG_APER_0_BASE__APER_0_BASE__SHIFT 25
80 #define CONFIG_APER_1_BASE 0x00000104
81 #define CONFIG_APER_1_BASE__APER_1_BASE__MASK 0xFF000000
82 #define CONFIG_APER_1_BASE__APER_1_BASE__SHIFT 24
83 #define CONFIG_APER_SIZE 0x00000108
84 #define CONFIG_APER_SIZE__APER_SIZE__MASK 0x0F000000
85 #define CONFIG_APER_SIZE__APER_SIZE__SHIFT 24
86 #define GEN_INT_CNTL 0x00000040
87 #define GEN_INT_CNTL__CRTC_VBLANK 0x00000001
88 #define GEN_INT_CNTL__CRTC_VLINE 0x00000002
89 #define GEN_INT_CNTL__CRTC_VSYNC 0x00000004
90 #define GEN_INT_CNTL__SNAPSHOT 0x00000008
91 #define GEN_INT_CNTL__FP_DETECT 0x00000010
92 #define GEN_INT_CNTL__CRTC2_VLINE 0x00000020
93 #define GEN_INT_CNTL__DMA_VIPH0_INT_EN 0x00001000
94 #define GEN_INT_CNTL__CRTC2_VSYNC 0x00000040
95 #define GEN_INT_CNTL__SNAPSHOT2 0x00000080
96 #define GEN_INT_CNTL__CRTC2_VBLANK 0x00000200
97 #define GEN_INT_CNTL__FP2_DETECT 0x00000400
98 #define GEN_INT_CNTL__VSYNC_DIFF_OVER_LIMIT 0x00000800
99 #define GEN_INT_CNTL__DMA_VIPH1_INT_EN 0x00002000
100 #define GEN_INT_CNTL__DMA_VIPH2_INT_EN 0x00004000
101 #define GEN_INT_CNTL__DMA_VIPH3_INT_EN 0x00008000
102 #define GEN_INT_CNTL__I2C_INT_EN 0x00020000
103 #define GEN_INT_CNTL__GUI_IDLE 0x00080000
104 #define GEN_INT_CNTL__VIPH_INT_EN 0x01000000
105 #define GEN_INT_CNTL__SW_INT_EN 0x02000000
106 #define GEN_INT_CNTL__GEYSERVILLE 0x08000000
107 #define GEN_INT_CNTL__DVI_I2C_INT 0x20000000
108 #define GEN_INT_CNTL__GUIDMA 0x40000000
109 #define GEN_INT_CNTL__VIDDMA 0x80000000
110 #define GEN_INT_CNTL__TIMER_INT 0x00010000
111 #define GEN_INT_CNTL__IDCT_INT_EN 0x08000000
112 #define GEN_INT_STATUS 0x00000044
113 #define GEN_INT_STATUS__CRTC_VBLANK_STAT 0x00000001
114 #define GEN_INT_STATUS__CRTC_VBLANK_STAT_AK 0x00000001
115 #define GEN_INT_STATUS__CRTC_VLINE_STAT 0x00000002
116 #define GEN_INT_STATUS__CRTC_VLINE_STAT_AK 0x00000002
117 #define GEN_INT_STATUS__CRTC_VSYNC_STAT 0x00000004
118 #define GEN_INT_STATUS__CRTC_VSYNC_STAT_AK 0x00000004
119 #define GEN_INT_STATUS__SNAPSHOT_STAT 0x00000008
120 #define GEN_INT_STATUS__SNAPSHOT_STAT_AK 0x00000008
121 #define GEN_INT_STATUS__FP_DETECT_STAT 0x00000010
122 #define GEN_INT_STATUS__FP_DETECT_STAT_AK 0x00000010
123 #define GEN_INT_STATUS__CRTC2_VLINE_STAT 0x00000020
124 #define GEN_INT_STATUS__CRTC2_VLINE_STAT_AK 0x00000020
125 #define GEN_INT_STATUS__CRTC2_VSYNC_STAT 0x00000040
126 #define GEN_INT_STATUS__CRTC2_VSYNC_STAT_AK 0x00000040
127 #define GEN_INT_STATUS__SNAPSHOT2_STAT 0x00000080
128 #define GEN_INT_STATUS__SNAPSHOT2_STAT_AK 0x00000080
129 #define GEN_INT_STATUS__CAP0_INT_ACTIVE 0x00000100
130 #define GEN_INT_STATUS__CRTC2_VBLANK_STAT 0x00000200
131 #define GEN_INT_STATUS__CRTC2_VBLANK_STAT_AK 0x00000200
132 #define GEN_INT_STATUS__FP2_DETECT_STAT 0x00000400
133 #define GEN_INT_STATUS__FP2_DETECT_STAT_AK 0x00000400
134 #define GEN_INT_STATUS__VSYNC_DIFF_OVER_LIMIT_STAT 0x00000800
135 #define GEN_INT_STATUS__VSYNC_DIFF_OVER_LIMIT_STAT_AK 0x00000800
136 #define GEN_INT_STATUS__DMA_VIPH0_INT 0x00001000
137 #define GEN_INT_STATUS__DMA_VIPH0_INT_AK 0x00001000
138 #define GEN_INT_STATUS__DMA_VIPH1_INT 0x00002000
139 #define GEN_INT_STATUS__DMA_VIPH1_INT_AK 0x00002000
140 #define GEN_INT_STATUS__DMA_VIPH2_INT 0x00004000
141 #define GEN_INT_STATUS__DMA_VIPH2_INT_AK 0x00004000
142 #define GEN_INT_STATUS__DMA_VIPH3_INT 0x00008000
143 #define GEN_INT_STATUS__DMA_VIPH3_INT_AK 0x00008000
144 #define GEN_INT_STATUS__I2C_INT 0x00020000
145 #define GEN_INT_STATUS__I2C_INT_AK 0x00020000
146 #define GEN_INT_STATUS__GUI_IDLE_STAT 0x00080000
147 #define GEN_INT_STATUS__GUI_IDLE_STAT_AK 0x00080000
148 #define GEN_INT_STATUS__VIPH_INT 0x01000000
149 #define GEN_INT_STATUS__SW_INT 0x02000000
150 #define GEN_INT_STATUS__SW_INT_AK 0x02000000
151 #define GEN_INT_STATUS__SW_INT_SET 0x04000000
152 #define GEN_INT_STATUS__GEYSERVILLE_STAT 0x08000000
153 #define GEN_INT_STATUS__GEYSERVILLE_STAT_AK 0x08000000
154 #define GEN_INT_STATUS__DVI_I2C_INT_STAT 0x20000000
155 #define GEN_INT_STATUS__DVI_I2C_INT_AK 0x20000000
156 #define GEN_INT_STATUS__GUIDMA_STAT 0x40000000
157 #define GEN_INT_STATUS__GUIDMA_AK 0x40000000
158 #define GEN_INT_STATUS__VIDDMA_STAT 0x80000000
159 #define GEN_INT_STATUS__VIDDMA_AK 0x80000000
160 #define GEN_INT_STATUS__TIMER_INT_STAT 0x00010000
161 #define GEN_INT_STATUS__TIMER_INT_STAT_AK 0x00010000
162 #define GEN_INT_STATUS__IDCT_INT_STAT 0x08000000
163 #define GEN_INT_STATUS__IDCT_INT_STAT_AK 0x08000000
164 #define RB2D_DSTCACHE_MODE 0x00003428
165 #define RB2D_DSTCACHE_MODE__DC_BYPASS__MASK 0x00000003
166 #define RB2D_DSTCACHE_MODE__DC_BYPASS__SHIFT 0
167 #define RB2D_DSTCACHE_MODE__DC_LINE_SIZE__MASK 0x0000000C
168 #define RB2D_DSTCACHE_MODE__DC_LINE_SIZE__SHIFT 2
169 #define RB2D_DSTCACHE_MODE__DC_AUTOFLUSH_ENABLE__MASK 0x00000300
170 #define RB2D_DSTCACHE_MODE__DC_AUTOFLUSH_ENABLE__SHIFT 8
171 #define RB2D_DSTCACHE_MODE__DC_FORCE_RMW 0x00010000
172 #define RB2D_DSTCACHE_MODE__DC_DISABLE_RI_FILL 0x01000000
173 #define RB2D_DSTCACHE_MODE__DC_DISABLE_RI_READ 0x02000000
174 #define RB2D_DSTCACHE_MODE__DC_AUTOFREE_ENABLE__MASK 0x00000C00
175 #define RB2D_DSTCACHE_MODE__DC_AUTOFREE_ENABLE__SHIFT 10
176 #define RB2D_DSTCACHE_MODE__DC_DISABLE 0x04000000
177 #define RB2D_DSTCACHE_MODE__DC_DISABLE_IGNORE_PE 0x00020000
178 #define RB2D_DSTCACHE_CTLSTAT 0x0000342C
179 #define RB2D_DSTCACHE_CTLSTAT__DC_FLUSH__MASK 0x00000003
180 #define RB2D_DSTCACHE_CTLSTAT__DC_FLUSH__SHIFT 0
181 #define RB2D_DSTCACHE_CTLSTAT__DC_FREE__MASK 0x0000000C
182 #define RB2D_DSTCACHE_CTLSTAT__DC_FREE__SHIFT 2
183 #define RB2D_DSTCACHE_CTLSTAT__DC_BUSY 0x80000000
184 #define RB3D_DSTCACHE_CTLSTAT 0x0000325C
185 #define RB3D_DSTCACHE_CTLSTAT__DC_FLUSH__MASK 0x00000003
186 #define RB3D_DSTCACHE_CTLSTAT__DC_FLUSH__SHIFT 0
187 #define RB3D_DSTCACHE_CTLSTAT__DC_FREE__MASK 0x0000000C
188 #define RB3D_DSTCACHE_CTLSTAT__DC_FREE__SHIFT 2
189 #define RB3D_DSTCACHE_CTLSTAT__DC_BUSY 0x80000000
190 #define RB3D_DSTCACHE_CTLSTAT_R3 0x00004E4C
191 #define RB3D_DSTCACHE_CTLSTAT_R3__DC_FLUSH__MASK 0x00000003
192 #define RB3D_DSTCACHE_CTLSTAT_R3__DC_FLUSH__SHIFT 0
193 #define RB3D_DSTCACHE_CTLSTAT_R3__DC_FREE__MASK 0x0000000C
194 #define RB3D_DSTCACHE_CTLSTAT_R3__DC_FREE__SHIFT 2
195 #define RB3D_DSTCACHE_CTLSTAT_R3__DC_FINISH 0x00000010
196 #define RB3D_ZCACHE_CTLSTAT 0x00003254
197 #define RB3D_ZCACHE_CTLSTAT__ZC_FLUSH 0x00000001
198 #define RB3D_ZCACHE_CTLSTAT__ZC_FREE 0x00000004
199 #define RB3D_ZCACHE_CTLSTAT__ZC_DIRTY 0x40000000
200 #define RB3D_ZCACHE_CTLSTAT__ZC_BUSY 0x80000000
201 #define RB3D_ZCACHE_CTLSTAT_R3 0x00004F18
202 #define RB3D_ZCACHE_CTLSTAT_R3__ZC_FLUSH 0x00000001
203 #define RB3D_ZCACHE_CTLSTAT_R3__ZC_FREE 0x00000002
204 #define RB3D_ZCACHE_CTLSTAT_R3__ZC_BUSY 0x80000000
205 #define SCRATCH_REG0 0x000015E0
206 #define SCRATCH_REG0__SCRATCH_REG0__MASK 0xFFFFFFFF
207 #define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0
208 #define SCRATCH_REG1 0x000015E4
209 #define SCRATCH_REG1__SCRATCH_REG1__MASK 0xFFFFFFFF
210 #define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0
211 #define SCRATCH_REG2 0x000015E8
212 #define SCRATCH_REG2__SCRATCH_REG2__MASK 0xFFFFFFFF
213 #define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0
214 #define SCRATCH_REG3 0x000015EC
215 #define SCRATCH_REG3__SCRATCH_REG3__MASK 0xFFFFFFFF
216 #define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0
217 #define SCRATCH_REG4 0x000015F0
218 #define SCRATCH_REG4__SCRATCH_REG4__MASK 0xFFFFFFFF
219 #define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0
220 #define SCRATCH_REG5 0x000015F4
221 #define SCRATCH_REG5__SCRATCH_REG5__MASK 0xFFFFFFFF
222 #define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0
223 #define SCRATCH_REG6 0x000015F8
224 #define SCRATCH_REG6__SCRATCH_REG6__MASK 0xFFFFFFFF
225 #define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0
226 #define SCRATCH_REG7 0x000015FC
227 #define SCRATCH_REG7__SCRATCH_REG7__MASK 0xFFFFFFFF
228 #define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0
229 #define SC_SCISSOR0 0x000043E0
230 #define SC_SCISSOR0__XS0__MASK 0x00001FFF
231 #define SC_SCISSOR0__XS0__SHIFT 0
232 #define SC_SCISSOR0__YS0__MASK 0x03FFE000
233 #define SC_SCISSOR0__YS0__SHIFT 13
234 #define SC_SCISSOR1 0x000043E4
235 #define SC_SCISSOR1__XS1__MASK 0x00001FFF
236 #define SC_SCISSOR1__XS1__SHIFT 0
237 #define SC_SCISSOR1__YS1__MASK 0x03FFE000
238 #define SC_SCISSOR1__YS1__SHIFT 13
239 #define PCIE_INDEX 0x00000030
240 #define PCIE_INDEX__PCIE_INDEX__MASK 0x000007FF
241 #define PCIE_INDEX__PCIE_INDEX__SHIFT 0
242 #define PCIE_DATA 0x00000034
243 #define PCIE_DATA__PCIE_DATA__MASK 0xFFFFFFFF
244 #define PCIE_DATA__PCIE_DATA__SHIFT 0
245 #define PCIE_TX_GART_CNTL 0x00000010
246 #define PCIE_TX_GART_CNTL__GART_EN 0x00000001
247 #define PCIE_TX_GART_CNTL__GART_UNMAPPED_ACCESS__MASK 0x00000006
248 #define PCIE_TX_GART_CNTL__GART_UNMAPPED_ACCESS__SHIFT 1
249 #define GART_UNMAPPED_ACCESS__PTHRU 0x0
250 #define GART_UNMAPPED_ACCESS__CLAMP 0x1
251 #define GART_UNMAPPED_ACCESS__DISCARD 0x3
252 #define PCIE_TX_GART_CNTL__GART_MODE__MASK 0x00000018
253 #define PCIE_TX_GART_CNTL__GART_MODE__SHIFT 3
254 #define GART_MODE__CACHE_32x128 0x0
255 #define GART_MODE__CACHE_8x4x128 0x1
256 #define PCIE_TX_GART_CNTL__GART_CHK_RW_VALID_EN 0x00000020
257 #define PCIE_TX_GART_CNTL__GART_RDREQPATH_SEL__MASK 0x00000040
258 #define PCIE_TX_GART_CNTL__GART_RDREQPATH_SEL__SHIFT 6
259 #define GART_RDREQPATH_SEL__HDP 0x0
260 #define GART_RDREQPATH_SEL__DRQMC 0x1
261 #define PCIE_TX_GART_CNTL__GART_INVALIDATE_TLB 0x00000100
262 #define PCIE_TX_GART_DISCARD_RD_ADDR_LO 0x00000011
263 #define PCIE_TX_GART_DISCARD_RD_ADDR_LO__GART_DISCARD_RD_ADDR_LO__MASK 0xFFFFFFFF
264 #define PCIE_TX_GART_DISCARD_RD_ADDR_LO__GART_DISCARD_RD_ADDR_LO__SHIFT 0
265 #define PCIE_TX_GART_DISCARD_RD_ADDR_HI 0x00000012
266 #define PCIE_TX_GART_DISCARD_RD_ADDR_HI__GART_DISCARD_RD_ADDR_HI__MASK 0x000000FF
267 #define PCIE_TX_GART_DISCARD_RD_ADDR_HI__GART_DISCARD_RD_ADDR_HI__SHIFT 0
268 #define PCIE_TX_GART_BASE 0x00000013
269 #define PCIE_TX_GART_BASE__GART_BASE__MASK 0xFFFFFFFF
270 #define PCIE_TX_GART_BASE__GART_BASE__SHIFT 0
271 #define PCIE_TX_GART_START_LO 0x00000014
272 #define PCIE_TX_GART_START_LO__GART_START_LO__MASK 0xFFFFFFFF
273 #define PCIE_TX_GART_START_LO__GART_START_LO__SHIFT 0
274 #define PCIE_TX_GART_START_HI 0x00000015
275 #define PCIE_TX_GART_START_HI__GART_START_HI__MASK 0x000000FF
276 #define PCIE_TX_GART_START_HI__GART_START_HI__SHIFT 0
277 #define PCIE_TX_GART_END_LO 0x00000016
278 #define PCIE_TX_GART_END_LO__GART_END_LO__MASK 0xFFFFFFFF
279 #define PCIE_TX_GART_END_LO__GART_END_LO__SHIFT 0
280 #define PCIE_TX_GART_END_HI 0x00000017
281 #define PCIE_TX_GART_END_HI__GART_END_HI__MASK 0x000000FF
282 #define PCIE_TX_GART_END_HI__GART_END_HI__SHIFT 0
283 #define PCIE_TX_GART_ERROR 0x00000018
284 #define PCIE_TX_GART_ERROR__GART_UNMAPPED 0x00000002
285 #define PCIE_TX_GART_ERROR__GART_INVALID_READ 0x00000004
286 #define PCIE_TX_GART_ERROR__GART_INVALID_WRITE 0x00000008
287 #define PCIE_TX_GART_ERROR__GART_INVALID_ADDR__MASK 0xFFFFFFF0
288 #define PCIE_TX_GART_ERROR__GART_INVALID_ADDR__SHIFT 4
289 #define CP_CSQ_MODE 0x00000744
290 #define CP_CSQ_MODE__INDIRECT2_START__MASK 0x0000007F
291 #define CP_CSQ_MODE__INDIRECT2_START__SHIFT 0
292 #define CP_CSQ_MODE__INDIRECT1_START__MASK 0x00007F00
293 #define CP_CSQ_MODE__INDIRECT1_START__SHIFT 8
294 #define CP_CSQ_MODE__CSQ_INDIRECT2_MODE 0x04000000
295 #define CP_CSQ_MODE__CSQ_INDIRECT2_ENABLE 0x08000000
296 #define CP_CSQ_MODE__CSQ_INDIRECT1_MODE 0x10000000
297 #define CP_CSQ_MODE__CSQ_INDIRECT1_ENABLE 0x20000000
298 #define CP_CSQ_MODE__CSQ_PRIMARY_MODE 0x40000000
299 #define CP_CSQ_MODE__CSQ_PRIMARY_ENABLE 0x80000000
300 #define CP_RB_CNTL 0x00000704
301 #define CP_RB_CNTL__RB_BUFSZ__MASK 0x0000003F
302 #define CP_RB_CNTL__RB_BUFSZ__SHIFT 0
303 #define CP_RB_CNTL__RB_BLKSZ__MASK 0x00003F00
304 #define CP_RB_CNTL__RB_BLKSZ__SHIFT 8
305 #define CP_RB_CNTL__BUF_SWAP__MASK 0x00030000
306 #define CP_RB_CNTL__BUF_SWAP__SHIFT 16
307 #define CP_RB_CNTL__MAX_FETCH__MASK 0x000C0000
308 #define CP_RB_CNTL__MAX_FETCH__SHIFT 18
309 #define CP_RB_CNTL__RB_NO_UPDATE 0x08000000
310 #define CP_RB_CNTL__RB_RPTR_WR_ENA 0x80000000
311 #define CP_RB_BASE 0x00000700
312 #define CP_RB_BASE__RB_BASE__MASK 0xFFFFFFFC
313 #define CP_RB_BASE__RB_BASE__SHIFT 2
314 #define CP_RB_RPTR_ADDR 0x0000070C
315 #define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__MASK 0x00000003
316 #define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0
317 #define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__MASK 0xFFFFFFFC
318 #define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 2
319 #define CP_RB_RPTR 0x00000710
320 #define CP_RB_RPTR__RB_RPTR__MASK 0x007FFFFF
321 #define CP_RB_RPTR__RB_RPTR__SHIFT 0
322 #define CP_RB_RPTR_WR 0x0000071C
323 #define CP_RB_RPTR_WR__RB_RPTR_WR__MASK 0x007FFFFF
324 #define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0
325 #define CP_RB_WPTR 0x00000714
326 #define CP_RB_WPTR__RB_WPTR__MASK 0x007FFFFF
327 #define CP_RB_WPTR__RB_WPTR__SHIFT 0
328 #define CP_RB_WPTR_DELAY 0x00000718
329 #define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__MASK 0x0FFFFFFF
330 #define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0
331 #define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__MASK 0xF0000000
332 #define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 28
333 #define SCRATCH_UMSK 0x00000770
334 #define SCRATCH_UMSK__SCRATCH_UMSK__MASK 0x0000003F
335 #define SCRATCH_UMSK__SCRATCH_UMSK__SHIFT 0
336 #define SCRATCH_UMSK__SCRATCH_SWAP__MASK 0x00030000
337 #define SCRATCH_UMSK__SCRATCH_SWAP__SHIFT 16
338 #define SCRATCH_UMSK__SCRATCH_UMSK_R2__MASK 0x000000FF
339 #define SCRATCH_UMSK__SCRATCH_UMSK_R2__SHIFT 0
340 #define SCRATCH_ADDR 0x00000774
341 #define SCRATCH_ADDR__SCRATCH_ADDR__MASK 0xFFFFFFE0
342 #define SCRATCH_ADDR__SCRATCH_ADDR__SHIFT 5
343 #define CP_ME_RAM_ADDR 0x000007D4
344 #define CP_ME_RAM_ADDR__ME_RAM_ADDR__MASK 0x000000FF
345 #define CP_ME_RAM_ADDR__ME_RAM_ADDR__SHIFT 0
346 #define CP_ME_RAM_DATAH 0x000007DC
347 #define CP_ME_RAM_DATAH__ME_RAM_DATAH__MASK 0x0000003F
348 #define CP_ME_RAM_DATAH__ME_RAM_DATAH__SHIFT 0
349 #define CP_ME_RAM_DATAH__ME_RAM_DATAH_R3__MASK 0x000000FF
350 #define CP_ME_RAM_DATAH__ME_RAM_DATAH_R3__SHIFT 0
351 #define CP_ME_RAM_DATAL 0x000007E0
352 #define CP_ME_RAM_DATAL__ME_RAM_DATAL__MASK 0xFFFFFFFF
353 #define CP_ME_RAM_DATAL__ME_RAM_DATAL__SHIFT 0
354 #define CP_CSQ_CNTL 0x00000740
355 #define CP_CSQ_CNTL__CSQ_CNT_PRIMARY__MASK 0x000000FF
356 #define CP_CSQ_CNTL__CSQ_CNT_PRIMARY__SHIFT 0
357 #define CP_CSQ_CNTL__CSQ_CNT_INDIRECT__MASK 0x0000FF00
358 #define CP_CSQ_CNTL__CSQ_CNT_INDIRECT__SHIFT 8
359 #define CP_CSQ_CNTL__CSQ_MODE__MASK 0xF0000000
360 #define CP_CSQ_CNTL__CSQ_MODE__SHIFT 28
361 #define CSQ_MODE__CSQ_PRIDIS_INDDIS 0x0
362 #define CSQ_MODE__CSQ_PRIPIO_INDDIS 0x1
363 #define CSQ_MODE__CSQ_PRIBM_INDDIS 0x2
364 #define CSQ_MODE__CSQ_PRIPIO_INDBM 0x3
365 #define CSQ_MODE__CSQ_PRIBM_INDBM 0x4
366 #define CSQ_MODE__CSQ_PRIPIO_INDPIO 0xF
367 #define CP_CSQ_CNTL__CSQ_CNT_PRIMARY_R2__MASK 0x000001FF
368 #define CP_CSQ_CNTL__CSQ_CNT_PRIMARY_R2__SHIFT 0
369 #define CP_CSQ_CNTL__CSQ_CNT_INDIRECT_R2__MASK 0x0003FE00
370 #define CP_CSQ_CNTL__CSQ_CNT_INDIRECT_R2__SHIFT 9
371 #define CP_CSQ_CNTL__CSQ_CNT_INDIRECT2__MASK 0x07FC0000
372 #define CP_CSQ_CNTL__CSQ_CNT_INDIRECT2__SHIFT 18
373 #define CRTC_GEN_CNTL 0x00000050
374 #define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN 0x00000001
375 #define CRTC_GEN_CNTL__CRTC_INTERLACE_EN 0x00000002
376 #define CRTC_GEN_CNTL__CRTC_C_SYNC_EN 0x00000010
377 #define CRTC_GEN_CNTL__CRTC_PIX_WIDTH__MASK 0x00000F00
378 #define CRTC_GEN_CNTL__CRTC_PIX_WIDTH__SHIFT 8
379 #define CRTC_PIX_WIDTH__4BPP 0x100
380 #define CRTC_PIX_WIDTH__8BPP 0x200
381 #define CRTC_PIX_WIDTH__15BPP 0x300
382 #define CRTC_PIX_WIDTH__16BPP 0x400
383 #define CRTC_PIX_WIDTH__24BPP 0x500
384 #define CRTC_PIX_WIDTH__34BPP 0x600
385 #define CRTC_PIX_WIDTH__16BPP_4444 0x700
386 #define CRTC_PIX_WIDTH__16BPP_88 0x800
387 #define CRTC_GEN_CNTL__CRTC_ICON_EN 0x00008000
388 #define CRTC_GEN_CNTL__CRTC_CUR_EN 0x00010000
389 #define CRTC_GEN_CNTL__CRTC_VSTAT_MODE__MASK 0x00060000
390 #define CRTC_GEN_CNTL__CRTC_VSTAT_MODE__SHIFT 17
391 #define CRTC_GEN_CNTL__CRTC_CUR_MODE__MASK 0x00700000
392 #define CRTC_GEN_CNTL__CRTC_CUR_MODE__SHIFT 20
393 #define CRTC_CUR_MODE__PREMULTI_ALPHA 0x2
394 #define CRTC_CUR_MODE__COLOR24BPP 0x1
395 #define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN 0x01000000
396 #define CRTC_GEN_CNTL__CRTC_EN 0x02000000
397 #define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B 0x04000000
398 #define CRTC_GEN_CNTL__CRTC_MODE9_COLOR_ORDER 0x00001000
399 #define CRTC_EXT_CNTL 0x00000054
400 #define CRTC_EXT_CNTL__CRTC_VGA_XOVERSCAN 0x00000001
401 #define CRTC_EXT_CNTL__VGA_BLINK_RATE__MASK 0x00000006
402 #define CRTC_EXT_CNTL__VGA_BLINK_RATE__SHIFT 1
403 #define CRTC_EXT_CNTL__VGA_ATI_LINEAR 0x00000008
404 #define CRTC_EXT_CNTL__VGA_128KAP_PAGING 0x00000010
405 #define CRTC_EXT_CNTL__VGA_TEXT_132 0x00000020
406 #define CRTC_EXT_CNTL__VGA_XCRT_CNT_EN 0x00000040
407 #define CRTC_EXT_CNTL__CRTC_HSYNC_DIS 0x00000100
408 #define CRTC_EXT_CNTL__CRTC_VSYNC_DIS 0x00000200
409 #define CRTC_EXT_CNTL__CRTC_DISPLAY_DIS 0x00000400
410 #define CRTC_EXT_CNTL__CRTC_SYNC_TRISTATE 0x00000800
411 #define CRTC_EXT_CNTL__CRTC_HSYNC_TRISTATE 0x00001000
412 #define CRTC_EXT_CNTL__CRTC_VSYNC_TRISTATE 0x00002000
413 #define CRTC_EXT_CNTL__CRT_ON 0x00008000
414 #define CRTC_EXT_CNTL__VGA_CUR_B_TEST 0x00020000
415 #define CRTC_EXT_CNTL__VGA_PACK_DIS 0x00040000
416 #define CRTC_EXT_CNTL__VGA_MEM_PS_EN 0x00080000
417 #define CRTC_EXT_CNTL__VCRTC_IDX_MASTER__MASK 0x7F000000
418 #define CRTC_EXT_CNTL__VCRTC_IDX_MASTER__SHIFT 24
419 #define CRTC_H_TOTAL_DISP 0x00000200
420 #define CRTC_H_TOTAL_DISP__CRTC_H_TOTAL__MASK 0x000003FF
421 #define CRTC_H_TOTAL_DISP__CRTC_H_TOTAL__SHIFT 0
422 #define CRTC_H_TOTAL_DISP__CRTC_H_DISP__MASK 0x01FF0000
423 #define CRTC_H_TOTAL_DISP__CRTC_H_DISP__SHIFT 16
424 #define CRTC_H_SYNC_STRT_WID 0x00000204
425 #define CRTC_H_SYNC_STRT_WID__CRTC_H_SYNC_STRT_PIX__MASK 0x00000007
426 #define CRTC_H_SYNC_STRT_WID__CRTC_H_SYNC_STRT_PIX__SHIFT 0
427 #define CRTC_H_SYNC_STRT_WID__CRTC_H_SYNC_STRT_CHAR__MASK 0x00001FF8
428 #define CRTC_H_SYNC_STRT_WID__CRTC_H_SYNC_STRT_CHAR__SHIFT 3
429 #define CRTC_H_SYNC_STRT_WID__CRTC_H_SYNC_WID__MASK 0x003F0000
430 #define CRTC_H_SYNC_STRT_WID__CRTC_H_SYNC_WID__SHIFT 16
431 #define CRTC_H_SYNC_STRT_WID__CRTC_H_SYNC_POL 0x00800000
432 #define CRTC_H_SYNC_STRT_WID__CRTC_H_SYNC_SKEW_TUNE__MASK 0x07000000
433 #define CRTC_H_SYNC_STRT_WID__CRTC_H_SYNC_SKEW_TUNE__SHIFT 24
434 #define CRTC_H_SYNC_STRT_WID__CRTC_H_SYNC_SKEW_TUNE_MODE 0x10000000
435 #define CRTC_V_TOTAL_DISP 0x00000208
436 #define CRTC_V_TOTAL_DISP__CRTC_V_TOTAL__MASK 0x00000FFF
437 #define CRTC_V_TOTAL_DISP__CRTC_V_TOTAL__SHIFT 0
438 #define CRTC_V_TOTAL_DISP__CRTC_V_DISP__MASK 0x0FFF0000
439 #define CRTC_V_TOTAL_DISP__CRTC_V_DISP__SHIFT 16
440 #define CRTC_V_SYNC_STRT_WID 0x0000020C
441 #define CRTC_V_SYNC_STRT_WID__CRTC_V_SYNC_STRT__MASK 0x00000FFF
442 #define CRTC_V_SYNC_STRT_WID__CRTC_V_SYNC_STRT__SHIFT 0
443 #define CRTC_V_SYNC_STRT_WID__CRTC_V_SYNC_WID__MASK 0x001F0000
444 #define CRTC_V_SYNC_STRT_WID__CRTC_V_SYNC_WID__SHIFT 16
445 #define CRTC_V_SYNC_STRT_WID__CRTC_V_SYNC_POL 0x00800000
446 #define CRTC_OFFSET 0x00000224
447 #define CRTC_OFFSET__CRTC_OFFSET__MASK 0x07FFFFFF
448 #define CRTC_OFFSET__CRTC_OFFSET__SHIFT 0
449 #define CRTC_OFFSET__CRTC_GUI_TRIG_OFFSET 0x40000000
450 #define CRTC_OFFSET__CRTC_OFFSET_LOCK 0x80000000
451 #define CRTC_OFFSET__CRTC_OFFSET_R3__MASK 0x0FFFFFFF
452 #define CRTC_OFFSET__CRTC_OFFSET_R3__SHIFT 0
453 #define CRTC_OFFSET_CNTL 0x00000228
454 #define CRTC_OFFSET_CNTL__CRTC_TILE_LINE__MASK 0x0000000F
455 #define CRTC_OFFSET_CNTL__CRTC_TILE_LINE__SHIFT 0
456 #define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_RIGHT__MASK 0x000000F0
457 #define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_RIGHT__SHIFT 4
458 #define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT 0x00004000
459 #define CRTC_OFFSET_CNTL__CRTC_TILE_EN 0x00008000
460 #define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL 0x00010000
461 #define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN 0x00020000
462 #define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_EN__MASK 0x000C0000
463 #define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_EN__SHIFT 18
464 #define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN 0x00100000
465 #define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC 0x00200000
466 #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN 0x10000000
467 #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN 0x20000000
468 #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET 0x40000000
469 #define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK 0x80000000
470 #define CRTC_OFFSET_CNTL__CRTC_X_Y_MODE_EN_RIGHT 0x00000040
471 #define CRTC_OFFSET_CNTL__CRTC_MICRO_TILE_BUFFER_MODE_RIGHT__MASK 0x00000180
472 #define CRTC_OFFSET_CNTL__CRTC_MICRO_TILE_BUFFER_MODE_RIGHT__SHIFT 7
473 #define CRTC_OFFSET_CNTL__CRTC_X_Y_MODE_EN 0x00000200
474 #define CRTC_OFFSET_CNTL__CRTC_MICRO_TILE_BUFFER_MODE__MASK 0x00000C00
475 #define CRTC_OFFSET_CNTL__CRTC_MICRO_TILE_BUFFER_MODE__SHIFT 10
476 #define CRTC_MICRO_TILE_BUFFER_MODE__AUTO 0x0
477 #define CRTC_MICRO_TILE_BUFFER_MODE__SLINE 0x1
478 #define CRTC_MICRO_TILE_BUFFER_MODE__DLINE 0x2
479 #define CRTC_MICRO_TILE_BUFFER_MODE__DIS 0x3
480 #define CRTC_OFFSET_CNTL__CRTC_MICRO_TILE_EN_RIGHT 0x00001000
481 #define CRTC_OFFSET_CNTL__CRTC_MICRO_TILE_EN 0x00002000
482 #define CRTC_OFFSET_CNTL__CRTC_MACRO_TILE_EN_RIGHT 0x00004000
483 #define CRTC_OFFSET_CNTL__CRTC_MACRO_TILE_EN 0x00008000
484 #define CRTC_PITCH 0x0000022C
485 #define CRTC_PITCH__CRTC_PITCH__MASK 0x000007FF
486 #define CRTC_PITCH__CRTC_PITCH__SHIFT 0
487 #define CRTC_PITCH__CRTC_PITCH_RIGHT__MASK 0x07FF0000
488 #define CRTC_PITCH__CRTC_PITCH_RIGHT__SHIFT 16
489 #define CRTC_MORE_CNTL 0x0000027C
490 #define CRTC_MORE_CNTL__CRTC_HORZ_BLANK_MODE_SEL 0x00000001
491 #define CRTC_MORE_CNTL__CRTC_VERT_BLANK_MODE_SEL 0x00000002
492 #define CRTC_MORE_CNTL__CRTC_AUTO_HORZ_CENTER_EN 0x00000004
493 #define CRTC_MORE_CNTL__CRTC_AUTO_VERT_CENTER_EN 0x00000008
494 #define CRTC_MORE_CNTL__CRTC_H_CUTOFF_ACTIVE_EN 0x00000010
495 #define CRTC_MORE_CNTL__CRTC_V_CUTOFF_ACTIVE_EN 0x00000020
496 #define CRTC_MORE_CNTL__FORCE_H_EVEN_PIXEL_COUNT 0x00000040
497 #define CRTC_MORE_CNTL__RMX_H_FILT_COEFFICIENT__MASK 0x07000000
498 #define CRTC_MORE_CNTL__RMX_H_FILT_COEFFICIENT__SHIFT 24
499 #define CRTC_MORE_CNTL__RMX_H_FILTER_EN 0x08000000
500 #define CRTC_MORE_CNTL__RMX_V_FILT_COEFFICIENT__MASK 0x70000000
501 #define CRTC_MORE_CNTL__RMX_V_FILT_COEFFICIENT__SHIFT 28
502 #define CRTC_MORE_CNTL__RMX_V_FILTER_EN 0x80000000
503 #define CRTC_MORE_CNTL__DSP_RST_HCOUNT 0x00000100
504 #define CRTC_MORE_CNTL__DSP_RST_VCOUNT 0x00000200
505 #define CRTC_MORE_CNTL__HCOUNT_RST_POS 0x00000400
506 #define CRTC_MORE_CNTL__VCOUNT_RST_POS 0x00000800
507 #define CRTC_MORE_CNTL__CRTC_FIX_VSYNC_EDGE_POSITION_EN 0x00001000
508 #define CRTC_TILE_X0_Y0 0x00000350
509 #define CRTC_TILE_X0_Y0__CRTC_TILE_X0__MASK 0x00000FFF
510 #define CRTC_TILE_X0_Y0__CRTC_TILE_X0__SHIFT 0
511 #define CRTC_TILE_X0_Y0__CRTC_TILE_Y0__MASK 0x0FFF0000
512 #define CRTC_TILE_X0_Y0__CRTC_TILE_Y0__SHIFT 16
513 #define CRTC_TILE_X0_Y0__CRTC_GUI_TRIG_OFFSET 0x40000000
514 #define CRTC_TILE_X0_Y0__CRTC_OFFSET_LOCK 0x80000000
515 #define DAC_CNTL 0x00000058
516 #define DAC_CNTL__DAC_RANGE_CNTL__MASK 0x00000003
517 #define DAC_CNTL__DAC_RANGE_CNTL__SHIFT 0
518 #define DAC_RANGE_CNTL__PS2 0x2
519 #define DAC_RANGE_CNTL__YPbPr 0x3
520 #define DAC_CNTL__DAC_BLANKING 0x00000004
521 #define DAC_CNTL__DAC_CMP_EN 0x00000008
522 #define DAC_CNTL__DAC_CMP_OUT_R 0x00000010
523 #define DAC_CNTL__DAC_CMP_OUT_G 0x00000020
524 #define DAC_CNTL__DAC_CMP_OUT_B 0x00000040
525 #define DAC_CNTL__DAC_CMP_OUTPUT 0x00000080
526 #define DAC_CNTL__DAC_8BIT_EN 0x00000100
527 #define DAC_CNTL__DAC_4BPP_PIX_ORDER 0x00000200
528 #define DAC_CNTL__DAC_TVO_EN 0x00000400
529 #define DAC_CNTL__DAC_VGA_ADR_EN 0x00002000
530 #define DAC_CNTL__DAC_EXPAND_MODE 0x00004000
531 #define DAC_CNTL__DAC_PDWN 0x00008000
532 #define DAC_CNTL__CRT_SENSE 0x00010000
533 #define DAC_CNTL__CRT_DETECTION_ON 0x00020000
534 #define DAC_CNTL__DAC_CRC_CONT_EN 0x00040000
535 #define DAC_CNTL__DAC_CRC_EN 0x00080000
536 #define DAC_CNTL__DAC_CRC_FIELD 0x00100000
537 #define DAC_CNTL__DAC_LUT_COUNTER_LIMIT__MASK 0x00600000
538 #define DAC_CNTL__DAC_LUT_COUNTER_LIMIT__SHIFT 21
539 #define DAC_CNTL__DAC_LUT_READ_SEL 0x00800000
540 #define DAC_CNTL__DAC__MASK 0xFF000000
541 #define DAC_CNTL__DAC__SHIFT 24
542 #define DAC_CNTL__DAC_CRC_BLANKb_ONLY 0x00000800
543 #define DAC_CNTL2 0x0000007C
544 #define DAC_CNTL2__DAC_CLK_SEL 0x00000001
545 #define DAC_CNTL2__DAC2_CLK_SEL 0x00000002
546 #define DAC_CNTL2__PALETTE_ACCESS_CNTL 0x00000020
547 #define DAC_CNTL2__DAC2_CMP_EN 0x00000080
548 #define DAC_CNTL2__DAC2_CMP_OUT_R 0x00000100
549 #define DAC_CNTL2__DAC2_CMP_OUT_G 0x00000200
550 #define DAC_CNTL2__DAC2_CMP_OUT_B 0x00000400
551 #define DAC_CNTL2__DAC2_CMP_OUTPUT 0x00000800
552 #define DAC_CNTL2__DAC2_EXPAND_MODE 0x00004000
553 #define DAC_CNTL2__CRT2_SENSE 0x00010000
554 #define DAC_CNTL2__CRT2_DETECTION_ON 0x00020000
555 #define DAC_CNTL2__DAC_CRC2_CONT_EN 0x00040000
556 #define DAC_CNTL2__DAC_CRC2_EN 0x00080000
557 #define DAC_CNTL2__DAC_CRC2_FIELD 0x00100000
558 #define DAC_CNTL2__DAC2_LUT_COUNTER_LIMIT__MASK 0x00600000
559 #define DAC_CNTL2__DAC2_LUT_COUNTER_LIMIT__SHIFT 21
560 #define DAC_CNTL2__PALETTE_AUTOFILL_PRIMARY_W 0x00000800
561 #define DAC_CNTL2__PALETTE_AUTOFILL_PRIMARY_R 0x00000800
562 #define DAC_CNTL2__PALETTE_AUTOFILL_SECONDARY_W 0x00001000
563 #define DAC_CNTL2__PALETTE_AUTOFILL_SECONDARY_R 0x00001000
564 #define DAC_CNTL2__DAC2_CMP_EN_R3 0x00000040
565 #define DAC_CNTL2__DAC2_CMP_OUT_R_R3 0x00000080
566 #define DAC_CNTL2__DAC2_CMP_OUT_G_R3 0x00000100
567 #define DAC_CNTL2__DAC2_CMP_OUT_B_R3 0x00000200
568 #define DAC_CNTL2__DAC2_CMP_OUTPUT_R3 0x00000400
569 #define DAC_CNTL2__DAC_CRC2_BLANKb_ONLY 0x00020000
570 #define DAC_EXT_CNTL 0x00000280
571 #define DAC_EXT_CNTL__DAC2_FORCE_BLANK_OFF_EN 0x00000001
572 #define DAC_EXT_CNTL__DAC2_FORCE_DATA_EN 0x00000002
573 #define DAC_EXT_CNTL__DAC_FORCE_BLANK_OFF_EN 0x00000010
574 #define DAC_EXT_CNTL__DAC_FORCE_DATA_EN 0x00000020
575 #define DAC_EXT_CNTL__DAC_FORCE_DATA_SEL__MASK 0x000000C0
576 #define DAC_EXT_CNTL__DAC_FORCE_DATA_SEL__SHIFT 6
577 #define DAC_EXT_CNTL__DAC_FORCE_DATA__MASK 0x0003FF00
578 #define DAC_EXT_CNTL__DAC_FORCE_DATA__SHIFT 8
579 #define DISP_MISC_CNTL 0x00000D00
580 #define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP 0x00000001
581 #define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP 0x00000002
582 #define DISP_MISC_CNTL__SOFT_RESET_OV0_PP 0x00000004
583 #define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK 0x00000010
584 #define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK 0x00000020
585 #define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK 0x00000040
586 #define DISP_MISC_CNTL__SYNC_STRENGTH__MASK 0x00000300
587 #define DISP_MISC_CNTL__SYNC_STRENGTH__SHIFT 8
588 #define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN 0x00000400
589 #define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP 0x00001000
590 #define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK 0x00008000
591 #define DISP_MISC_CNTL__SOFT_RESET_LVDS 0x00010000
592 #define DISP_MISC_CNTL__SOFT_RESET_TMDS 0x00020000
593 #define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS 0x00040000
594 #define DISP_MISC_CNTL__SOFT_RESET_TV 0x00080000
595 #define DISP_MISC_CNTL__PALETTE2_MEM_RD_MARGIN__MASK 0x00F00000
596 #define DISP_MISC_CNTL__PALETTE2_MEM_RD_MARGIN__SHIFT 20
597 #define DISP_MISC_CNTL__PALETTE_MEM_RD_MARGIN__MASK 0x0F000000
598 #define DISP_MISC_CNTL__PALETTE_MEM_RD_MARGIN__SHIFT 24
599 #define DISP_MISC_CNTL__RMX_BUF_MEM_RD_MARGIN__MASK 0xF0000000
600 #define DISP_MISC_CNTL__RMX_BUF_MEM_RD_MARGIN__SHIFT 28
601 #define DISP_MISC_CNTL__SOFT_RESET_DVO 0x00040000
602 #define DISP_MISC_CNTL__SOFT_RESET_TV_R2 0x00000800
603 #define DAC_MACRO_CNTL 0x00000D04
604 #define DAC_MACRO_CNTL__DAC_WHITE_CNTL__MASK 0x0000000F
605 #define DAC_MACRO_CNTL__DAC_WHITE_CNTL__SHIFT 0
606 #define DAC_MACRO_CNTL__DAC_BG_ADJ__MASK 0x00000F00
607 #define DAC_MACRO_CNTL__DAC_BG_ADJ__SHIFT 8
608 #define DAC_MACRO_CNTL__DAC_PDWN_R 0x00010000
609 #define DAC_MACRO_CNTL__DAC_PDWN_G 0x00020000
610 #define DAC_MACRO_CNTL__DAC_PDWN_B 0x00040000
611 #define DISP_PWR_MAN 0x00000D08
612 #define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN 0x00000001
613 #define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN 0x00000010
614 #define DISP_PWR_MAN__DISP_PWR_MAN_DPMS__MASK 0x00000300
615 #define DISP_PWR_MAN__DISP_PWR_MAN_DPMS__SHIFT 8
616 #define DISP_PWR_MAN_DPMS__ON 0x0
617 #define DISP_PWR_MAN_DPMS__STANDBY 0x1
618 #define DISP_PWR_MAN_DPMS__SUSPEND 0x2
619 #define DISP_PWR_MAN_DPMS__OFF 0x3
620 #define DISP_PWR_MAN__DISP_D3_RST 0x00010000
621 #define DISP_PWR_MAN__DISP_D3_REG_RST 0x00020000
622 #define DISP_PWR_MAN__DISP_D3_GRPH_RST 0x00040000
623 #define DISP_PWR_MAN__DISP_D3_SUBPIC_RST 0x00080000
624 #define DISP_PWR_MAN__DISP_D3_OV0_RST 0x00100000
625 #define DISP_PWR_MAN__DISP_D1D2_GRPH_RST 0x00200000
626 #define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST 0x00400000
627 #define DISP_PWR_MAN__DISP_D1D2_OV0_RST 0x00800000
628 #define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST 0x01000000
629 #define DISP_PWR_MAN__TV_ENABLE_RST 0x02000000
630 #define DISP_PWR_MAN__AUTO_PWRUP_EN 0x04000000
631 #define DISP_PWR_MAN__DISP_DVO_ENABLE_RST 0x01000000
632 #define DISP_MERGE_CNTL 0x00000D60
633 #define DISP_MERGE_CNTL__DISP_ALPHA_MODE__MASK 0x00000003
634 #define DISP_MERGE_CNTL__DISP_ALPHA_MODE__SHIFT 0
635 #define DISP_MERGE_CNTL__DISP_ALPHA_INV 0x00000004
636 #define DISP_MERGE_CNTL__DISP_ALPHA_PREMULT 0x00000008
637 #define DISP_MERGE_CNTL__DISP_RGB_OFFSET_EN 0x00000100
638 #define DISP_MERGE_CNTL__DISP_LIN_TRANS_BYPASS 0x00000200
639 #define DISP_MERGE_CNTL__DISP_GRPH_ALPHA__MASK 0x00FF0000
640 #define DISP_MERGE_CNTL__DISP_GRPH_ALPHA__SHIFT 16
641 #define DISP_MERGE_CNTL__DISP_OV0_ALPHA__MASK 0xFF000000
642 #define DISP_MERGE_CNTL__DISP_OV0_ALPHA__SHIFT 24
643 #define DISP_OUTPUT_CNTL 0x00000D64
644 #define DISP_OUTPUT_CNTL__DISP_DAC_SOURCE__MASK 0x00000003
645 #define DISP_OUTPUT_CNTL__DISP_DAC_SOURCE__SHIFT 0
646 #define DISP_DAC_SOURCE__YPbPr 0x3
647 #define DISP_DAC_SOURCE__PRIMARYCRTC 0x0
648 #define DISP_DAC_SOURCE__SECONDARYCRTC 0x1
649 #define DISP_DAC_SOURCE__RMX 0x2
650 #define DISP_OUTPUT_CNTL__DISP_TRANS_MATRIX_SEL__MASK 0x00000030
651 #define DISP_OUTPUT_CNTL__DISP_TRANS_MATRIX_SEL__SHIFT 4
652 #define DISP_OUTPUT_CNTL__DISP_RMX_SOURCE 0x00000100
653 #define DISP_OUTPUT_CNTL__DISP_RMX_HTAP_SEL 0x00000200
654 #define DISP_OUTPUT_CNTL__DISP_RMX_DITH_EN 0x00000400
655 #define DISP_OUTPUT_CNTL__DISP_TV_SOURCE 0x00010000
656 #define DISP_OUTPUT_CNTL__DISP_TV_MODE__MASK 0x00060000
657 #define DISP_OUTPUT_CNTL__DISP_TV_MODE__SHIFT 17
658 #define DISP_OUTPUT_CNTL__DISP_TV_YG_DITH_EN 0x00080000
659 #define DISP_OUTPUT_CNTL__DISP_TV_CbB_CrR_DITH_EN 0x00100000
660 #define DISP_OUTPUT_CNTL__DISP_TV_BIT_WIDTH 0x00200000
661 #define DISP_OUTPUT_CNTL__DISP_TV_SYNC_MODE__MASK 0x00C00000
662 #define DISP_OUTPUT_CNTL__DISP_TV_SYNC_MODE__SHIFT 22
663 #define DISP_OUTPUT_CNTL__DISP_TV_SYNC_FORCE 0x01000000
664 #define DISP_OUTPUT_CNTL__DISP_TV_SYNC_COLOR__MASK 0x06000000
665 #define DISP_OUTPUT_CNTL__DISP_TV_SYNC_COLOR__SHIFT 25
666 #define DISP_OUTPUT_CNTL__DISP_TV_EVEN_FLAG_CNTL__MASK 0x18000000
667 #define DISP_OUTPUT_CNTL__DISP_TV_EVEN_FLAG_CNTL__SHIFT 27
668 #define DISP_OUTPUT_CNTL__DISP_TV_SYNC_STATUS 0x20000000
669 #define DISP_OUTPUT_CNTL__DISP_TV_H_DOWNSCALE 0x40000000
670 #define DISP_OUTPUT_CNTL__DISP_TRANS_SOURCE__MASK 0x00003000
671 #define DISP_OUTPUT_CNTL__DISP_TRANS_SOURCE__SHIFT 12
672 #define DISP_TRANS_SOURCE__PRIMARYCRTC 0x0
673 #define DISP_TRANS_SOURCE__SECONDARYCRTC 0x1
674 #define DISP_TRANS_SOURCE__RMX 0x2
675 #define DISP_OUTPUT_CNTL__DISP_TVDAC_SOURCE__MASK 0x0000000C
676 #define DISP_OUTPUT_CNTL__DISP_TVDAC_SOURCE__SHIFT 2
677 #define DISP_TVDAC_SOURCE__PRIMARYCRTC 0x0
678 #define DISP_TVDAC_SOURCE__SECONDARYCRTC 0x1
679 #define DISP_TVDAC_SOURCE__RMX 0x2
680 #define DISP_TVDAC_SOURCE__YPbPr 0x3
681 #define DISP2_MERGE_CNTL 0x00000D68
682 #define DISP2_MERGE_CNTL__DISP2_RGB_OFFSET_EN 0x00000100
683 #define DAC_EMBEDDED_SYNC_CNTL 0x00000DC0
684 #define DAC_EMBEDDED_SYNC_CNTL__DAC_EMBED_SYNC_EN_Y_G 0x00000001
685 #define DAC_EMBEDDED_SYNC_CNTL__DAC_EMBED_SYNC_EN_Cb_B 0x00000002
686 #define DAC_EMBEDDED_SYNC_CNTL__DAC_EMBED_SYNC_EN_Cr_R 0x00000004
687 #define DAC_EMBEDDED_SYNC_CNTL__DAC_TRILEVEL_SYNC_EN 0x00000008
688 #define DAC_EMBEDDED_SYNC_CNTL__DAC_EMBED_VSYNC_EN_Y_G 0x00000010
689 #define DAC_EMBEDDED_SYNC_CNTL__DAC_EMBED_VSYNC_EN_CbCr_BR 0x00000020
690 #define DAC_EMBEDDED_SYNC_CNTL__DAC_HSYNC_WID_LSB__MASK 0x00070000
691 #define DAC_EMBEDDED_SYNC_CNTL__DAC_HSYNC_WID_LSB__SHIFT 16
692 #define DAC_BROAD_PULSE 0x00000DC4
693 #define DAC_BROAD_PULSE__DAC_BROAD_PULSE_START__MASK 0x00001FFF
694 #define DAC_BROAD_PULSE__DAC_BROAD_PULSE_START__SHIFT 0
695 #define DAC_BROAD_PULSE__DAC_BROAD_PULSE_END__MASK 0x1FFF0000
696 #define DAC_BROAD_PULSE__DAC_BROAD_PULSE_END__SHIFT 16
697 #define DAC_BROAD_PULSE__DAC_BROAD_PULSE_START_R2__MASK 0x00000FFF
698 #define DAC_BROAD_PULSE__DAC_BROAD_PULSE_START_R2__SHIFT 0
699 #define DAC_BROAD_PULSE__DAC_BROAD_PULSE_END_R2__MASK 0x0FFF0000
700 #define DAC_BROAD_PULSE__DAC_BROAD_PULSE_END_R2__SHIFT 16
701 #define DAC_SKEW_CLKS 0x00000DC8
702 #define DAC_SKEW_CLKS__DAC_SKEW_CLKS__MASK 0x000000FF
703 #define DAC_SKEW_CLKS__DAC_SKEW_CLKS__SHIFT 0
704 #define DAC_INCR 0x00000DCC
705 #define DAC_INCR__DAC_INCR_Y_G__MASK 0x000003FF
706 #define DAC_INCR__DAC_INCR_Y_G__SHIFT 0
707 #define DAC_INCR__DAC_INCR_CrCb_RB__MASK 0x03FF0000
708 #define DAC_INCR__DAC_INCR_CrCb_RB__SHIFT 16
709 #define DAC_NEG_SYNC_LEVEL 0x00000DD0
710 #define DAC_NEG_SYNC_LEVEL__DAC_NEG_SYNC_LEVEL_Y_G__MASK 0x000003FF
711 #define DAC_NEG_SYNC_LEVEL__DAC_NEG_SYNC_LEVEL_Y_G__SHIFT 0
712 #define DAC_NEG_SYNC_LEVEL__DAC_NEG_SYNC_LEVEL_CrCb_RB__MASK 0x03FF0000
713 #define DAC_NEG_SYNC_LEVEL__DAC_NEG_SYNC_LEVEL_CrCb_RB__SHIFT 16
714 #define DAC_POS_SYNC_LEVEL 0x00000DD4
715 #define DAC_POS_SYNC_LEVEL__DAC_POS_SYNC_LEVEL_Y_G__MASK 0x000003FF
716 #define DAC_POS_SYNC_LEVEL__DAC_POS_SYNC_LEVEL_Y_G__SHIFT 0
717 #define DAC_POS_SYNC_LEVEL__DAC_POS_SYNC_LEVEL_CrCb_RB__MASK 0x03FF0000
718 #define DAC_POS_SYNC_LEVEL__DAC_POS_SYNC_LEVEL_CrCb_RB__SHIFT 16
719 #define DAC_BLANK_LEVEL 0x00000DD8
720 #define DAC_BLANK_LEVEL__DAC_BLANK_LEVEL_Y_G__MASK 0x000003FF
721 #define DAC_BLANK_LEVEL__DAC_BLANK_LEVEL_Y_G__SHIFT 0
722 #define DAC_BLANK_LEVEL__DAC_BLANK_LEVEL_CrCb_RB__MASK 0x03FF0000
723 #define DAC_BLANK_LEVEL__DAC_BLANK_LEVEL_CrCb_RB__SHIFT 16
724 #define DAC_SYNC_EQUALIZATION 0x00000DDC
725 #define DAC_SYNC_EQUALIZATION__DAC_SYNC_EQ_START__MASK 0x000007FF
726 #define DAC_SYNC_EQUALIZATION__DAC_SYNC_EQ_START__SHIFT 0
727 #define DAC_SYNC_EQUALIZATION__DAC_SYNC_EQ_END__MASK 0x07FF0000
728 #define DAC_SYNC_EQUALIZATION__DAC_SYNC_EQ_END__SHIFT 16
729 #define TV_MASTER_CNTL 0x00000800
730 #define TV_MASTER_CNTL__TV_ASYNC_RST 0x00000001
731 #define TV_MASTER_CNTL__CRT_ASYNC_RST 0x00000002
732 #define TV_MASTER_CNTL__RESTART_PHASE_FIX 0x00000008
733 #define TV_MASTER_CNTL__TV_FIFO_ASYNC_RST 0x00000010
734 #define TV_MASTER_CNTL__MV_BP_LEVEL_FIX_EN 0x00000020
735 #define TV_MASTER_CNTL__EXTRA_BIT_ONE_0 0x00000040
736 #define TV_MASTER_CNTL__CRT_FIFO_CE_EN 0x00000200
737 #define TV_MASTER_CNTL__TV_FIFO_CE_EN 0x00000400
738 #define TV_MASTER_CNTL__RE_SYNC_NOW_SEL__MASK 0x0000C000
739 #define TV_MASTER_CNTL__RE_SYNC_NOW_SEL__SHIFT 14
740 #define TV_MASTER_CNTL__EXTRA_BIT_ZERO_1 0x00010000
741 #define TV_MASTER_CNTL__EXTRA_BIT_ONE_1 0x00020000
742 #define TV_MASTER_CNTL__EXTRA_BIT_ZERO_2 0x00040000
743 #define TV_MASTER_CNTL__EXTRA_BIT_ONE_2 0x00080000
744 #define TV_MASTER_CNTL__TVCLK_ALWAYS_ONb 0x40000000
745 #define TV_MASTER_CNTL__TV_ON 0x80000000
746 #define TV_DAC_CNTL 0x0000088C
747 #define TV_DAC_CNTL__NBLANK 0x00000001
748 #define TV_DAC_CNTL__NHOLD 0x00000002
749 #define TV_DAC_CNTL__PEDESTAL 0x00000004
750 #define TV_DAC_CNTL__DETECT 0x00000010
751 #define TV_DAC_CNTL__CMPOUT 0x00000020
752 #define TV_DAC_CNTL__BGSLEEP 0x00000040
753 #define TV_DAC_CNTL__STD__MASK 0x00000300
754 #define TV_DAC_CNTL__STD__SHIFT 8
756 #define STD__NTSC 0x1
758 #define STD__RS343 0x3
759 #define TV_DAC_CNTL__MON__MASK 0x0000F000
760 #define TV_DAC_CNTL__MON__SHIFT 12
761 #define TV_DAC_CNTL__BGADJ__MASK 0x000F0000
762 #define TV_DAC_CNTL__BGADJ__SHIFT 16
763 #define TV_DAC_CNTL__DACADJ__MASK 0x00F00000
764 #define TV_DAC_CNTL__DACADJ__SHIFT 20
765 #define TV_DAC_CNTL__RDACPD 0x01000000
766 #define TV_DAC_CNTL__GDACPD 0x02000000
767 #define TV_DAC_CNTL__BDACPD 0x04000000
768 #define TV_DAC_CNTL__RDACDET 0x20000000
769 #define TV_DAC_CNTL__GDACDET 0x40000000
770 #define TV_DAC_CNTL__BDACDET 0x80000000
771 #define TV_DAC_CNTL__DACADJ_R4__MASK 0x01F00000
772 #define TV_DAC_CNTL__DACADJ_R4__SHIFT 20
773 #define TV_DAC_CNTL__RDACPD_R4 0x02000000
774 #define TV_DAC_CNTL__GDACPD_R4 0x04000000
775 #define TV_DAC_CNTL__BDACPD_R4 0x08000000
776 #define TV_DAC_CNTL__TVENABLE_R4 0x10000000
777 #define VIPPAD_EN 0x000001A0
778 #define VIPPAD_EN__VIPPAD_EN__MASK 0x0007FFFF
779 #define VIPPAD_EN__VIPPAD_EN__SHIFT 0
780 #define VIPPAD_EN__VIPPAD_EN_TVODATA__MASK 0x000003FF
781 #define VIPPAD_EN__VIPPAD_EN_TVODATA__SHIFT 0
782 #define VIPPAD_EN__VIPPAD_EN_TVOCLKO 0x00000400
783 #define VIPPAD_EN__VIPPAD_EN_ROMCSb 0x00000800
784 #define VIPPAD_EN__VIPPAD_EN_VHAD__MASK 0x00003000
785 #define VIPPAD_EN__VIPPAD_EN_VHAD__SHIFT 12
786 #define VIPPAD_EN__VIPPAD_EN_VPHCTL 0x00010000
787 #define VIPPAD_EN__VIPPAD_EN_VIPCLK 0x00020000
788 #define VIPPAD_EN__VIPPAD_EN_SI 0x00080000
789 #define VIPPAD_EN__VIPPAD_EN_SO 0x00100000
790 #define VIPPAD_EN__VIPPAD_EN_SCK 0x00200000
791 #define VIPPAD_Y 0x000001A4
792 #define VIPPAD_Y__VIPPAD_Y__MASK 0x0007FFFF
793 #define VIPPAD_Y__VIPPAD_Y__SHIFT 0
794 #define VIPPAD_Y__VIPPAD_Y_TVODATA__MASK 0x000003FF
795 #define VIPPAD_Y__VIPPAD_Y_TVODATA__SHIFT 0
796 #define VIPPAD_Y__VIPPAD_Y_TVOCLKO 0x00000400
797 #define VIPPAD_Y__VIPPAD_Y_ROMCSb 0x00000800
798 #define VIPPAD_Y__VIPPAD_Y_VHAD__MASK 0x00003000
799 #define VIPPAD_Y__VIPPAD_Y_VHAD__SHIFT 12
800 #define VIPPAD_Y__VIPPAD_Y_VPHCTL 0x00010000
801 #define VIPPAD_Y__VIPPAD_Y_VIPCLK 0x00020000
802 #define VIPPAD_Y__VIPPAD_Y_SI 0x00080000
803 #define VIPPAD_Y__VIPPAD_Y_SO 0x00100000
804 #define VIPPAD_Y__VIPPAD_Y_SCK 0x00200000
805 #define VIPPAD1_EN 0x000001B0
806 #define VIPPAD1_EN__VIPPAD1_EN__MASK 0x0003FFFF
807 #define VIPPAD1_EN__VIPPAD1_EN__SHIFT 0
808 #define VIPPAD1_EN__VIPPAD_EN_VID__MASK 0x000000FF
809 #define VIPPAD1_EN__VIPPAD_EN_VID__SHIFT 0
810 #define VIPPAD1_EN__VIPPAD_EN_VPCLK0 0x00000100
811 #define VIPPAD1_EN__VIPPAD_EN_DVALID 0x00000200
812 #define VIPPAD1_EN__VIPPAD_EN_PSYNC 0x00000400
813 #define VIPPAD1_EN__VIPPAD_EN_DVODATA__MASK 0x0FFF0000
814 #define VIPPAD1_EN__VIPPAD_EN_DVODATA__SHIFT 16
815 #define VIPPAD1_EN__VIPPAD_EN_DVOCNTL__MASK 0x70000000
816 #define VIPPAD1_EN__VIPPAD_EN_DVOCNTL__SHIFT 28
817 #define VIPPAD1_Y 0x000001B4
818 #define VIPPAD1_Y__VIPPAD1_Y__MASK 0x0003FFFF
819 #define VIPPAD1_Y__VIPPAD1_Y__SHIFT 0
820 #define VIPPAD1_Y__VIPPAD_Y_VID__MASK 0x000000FF
821 #define VIPPAD1_Y__VIPPAD_Y_VID__SHIFT 0
822 #define VIPPAD1_Y__VIPPAD_Y_VPCLK0 0x00000100
823 #define VIPPAD1_Y__VIPPAD_Y_DVALID 0x00000200
824 #define VIPPAD1_Y__VIPPAD_Y_PSYNC 0x00000400
825 #define VIPPAD1_Y__VIPPAD_Y_DVODATA__MASK 0x0FFF0000
826 #define VIPPAD1_Y__VIPPAD_Y_DVODATA__SHIFT 16
827 #define VIPPAD1_Y__VIPPAD_Y_DVOCNTL__MASK 0x70000000
828 #define VIPPAD1_Y__VIPPAD_Y_DVOCNTL__SHIFT 28
829 #define GPIO_DDC1 0x00000060
830 #define GPIO_DDC1__DDC1_DATA_OUTPUT 0x00000001
831 #define GPIO_DDC1__DDC1_CLK_OUTPUT 0x00000002
832 #define GPIO_DDC1__DDC1_DATA_INPUT 0x00000100
833 #define GPIO_DDC1__DDC1_CLK_INPUT 0x00000200
834 #define GPIO_DDC1__DDC1_DATA_OUT_EN 0x00010000
835 #define GPIO_DDC1__DDC1_CLK_OUT_EN 0x00020000
836 #define GPIO_DDC1__SW_WANTS_TO_USE_DVI_I2C 0x00100000
837 #define GPIO_DDC1__SW_CAN_USE_DVI_I2C 0x00100000
838 #define GPIO_DDC1__SW_DONE_USING_DVI_I2C 0x00200000
839 #define GPIO_DDC1__HW_USING_DVI_I2C 0x00400000
840 #define GPIO_DDC2 0x00000064
841 #define GPIO_DDC2__DDC2_DATA_OUTPUT 0x00000001
842 #define GPIO_DDC2__DDC2_CLK_OUTPUT 0x00000002
843 #define GPIO_DDC2__DDC2_DATA_INPUT 0x00000100
844 #define GPIO_DDC2__DDC2_CLK_INPUT 0x00000200
845 #define GPIO_DDC2__DDC2_DATA_OUT_EN 0x00010000
846 #define GPIO_DDC2__DDC2_CLK_OUT_EN 0x00020000
847 #define GPIO_DDC2__SW_WANTS_TO_USE_DVI_I2C 0x00100000
848 #define GPIO_DDC2__SW_CAN_USE_DVI_I2C 0x00100000
849 #define GPIO_DDC2__SW_DONE_USING_DVI_I2C 0x00200000
850 #define GPIO_DDC2__HW_USING_DVI_I2C 0x00400000
851 #define GPIO_DVI_DDC 0x00000064
852 #define GPIO_DVI_DDC__DVI_DDC_DATA_OUTPUT 0x00000001
853 #define GPIO_DVI_DDC__DVI_DCC_DATA_OUTPUT 0x00000001
854 #define GPIO_DVI_DDC__DVI_DDC_CLK_OUTPUT 0x00000002
855 #define GPIO_DVI_DDC__DVI_DDC_DATA_INPUT 0x00000100
856 #define GPIO_DVI_DDC__DVI_DDC_CLK_INPUT 0x00000200
857 #define GPIO_DVI_DDC__DVI_DDC_DATA_OUT_EN 0x00010000
858 #define GPIO_DVI_DDC__DVI_DDC_CLK_OUT_EN 0x00020000
859 #define GPIO_DVI_DDC__SW_WANTS_TO_USE_DVI_I2C 0x00100000
860 #define GPIO_DVI_DDC__SW_CAN_USE_DVI_I2C 0x00100000
861 #define GPIO_DVI_DDC__SW_DONE_USING_DVI_I2C 0x00200000
862 #define GPIO_DVI_DDC__HW_USING_DVI_I2C 0x00400000
863 #define GPIO_MONID 0x00000068
864 #define GPIO_MONID__GPIO_MONID_0_OUTPUT 0x00000001
865 #define GPIO_MONID__GPIO_MONID_1_OUTPUT 0x00000002
866 #define GPIO_MONID__GPIO_MONID_0_INPUT 0x00000100
867 #define GPIO_MONID__GPIO_MONID_1_INPUT 0x00000200
868 #define GPIO_MONID__GPIO_MONID_0_OUT_EN 0x00010000
869 #define GPIO_MONID__GPIO_MONID_1_OUT_EN 0x00020000
870 #define GPIO_CRT2_DDC 0x0000006C
871 #define GPIO_CRT2_DDC__CRT2_DDC_DATA_OUTPUT 0x00000001
872 #define GPIO_CRT2_DDC__CRT2_DDC_CLK_OUTPUT 0x00000002
873 #define GPIO_CRT2_DDC__CRT2_DDC_DATA_INPUT 0x00000100
874 #define GPIO_CRT2_DDC__CRT2_DDC_CLK_INPUT 0x00000200
875 #define GPIO_CRT2_DDC__CRT2_DDC_DATA_OUT_EN 0x00010000
876 #define GPIO_CRT2_DDC__CRT2_DDC_CLK_OUT_EN 0x00020000
877 #define CLOCK_CNTL_INDEX 0x00000008
878 #define CLOCK_CNTL_INDEX__PLL_ADDR__MASK 0x0000001F
879 #define CLOCK_CNTL_INDEX__PLL_ADDR__SHIFT 0
880 #define CLOCK_CNTL_INDEX__PLL_WR_EN 0x00000080
881 #define CLOCK_CNTL_INDEX__PPLL_DIV_SEL__MASK 0x00000300
882 #define CLOCK_CNTL_INDEX__PPLL_DIV_SEL__SHIFT 8
883 #define CLOCK_CNTL_INDEX__PLL_ADDR_R2__MASK 0x0000003F
884 #define CLOCK_CNTL_INDEX__PLL_ADDR_R2__SHIFT 0
885 #define CLOCK_CNTL_DATA 0x0000000C
886 #define CLOCK_CNTL_DATA__PLL_DATA__MASK 0xFFFFFFFF
887 #define CLOCK_CNTL_DATA__PLL_DATA__SHIFT 0
888 #define MCLK_CNTL 0x00000012
889 #define MCLK_CNTL__MCLKA_SRC_SEL__MASK 0x00000007
890 #define MCLK_CNTL__MCLKA_SRC_SEL__SHIFT 0
891 #define MCLK_CNTL__YCLKA_SRC_SEL__MASK 0x00000070
892 #define MCLK_CNTL__YCLKA_SRC_SEL__SHIFT 4
893 #define MCLK_CNTL__MCLKB_SRC_SEL__MASK 0x00000700
894 #define MCLK_CNTL__MCLKB_SRC_SEL__SHIFT 8
895 #define MCLK_CNTL__YCLKB_SRC_SEL__MASK 0x00007000
896 #define MCLK_CNTL__YCLKB_SRC_SEL__SHIFT 12
897 #define MCLK_CNTL__FORCE_MCLKA 0x00010000
898 #define MCLK_CNTL__FORCE_MCLKB 0x00020000
899 #define MCLK_CNTL__FORCE_YCLKA 0x00040000
900 #define MCLK_CNTL__FORCE_YCLKB 0x00080000
901 #define MCLK_CNTL__FORCE_MC 0x00100000
902 #define MCLK_CNTL__FORCE_AIC 0x00200000
903 #define MCLK_CNTL__MRDCKA0_SOUTSEL__MASK 0x03000000
904 #define MCLK_CNTL__MRDCKA0_SOUTSEL__SHIFT 24
905 #define MCLK_CNTL__MRDCKA1_SOUTSEL__MASK 0x0C000000
906 #define MCLK_CNTL__MRDCKA1_SOUTSEL__SHIFT 26
907 #define MCLK_CNTL__MRDCKB0_SOUTSEL__MASK 0x30000000
908 #define MCLK_CNTL__MRDCKB0_SOUTSEL__SHIFT 28
909 #define MCLK_CNTL__MRDCKB1_SOUTSEL__MASK 0xC0000000
910 #define MCLK_CNTL__MRDCKB1_SOUTSEL__SHIFT 30
911 #define MCLK_CNTL__FORCE_MC_MCLKA 0x00010000
912 #define MCLK_CNTL__FORCE_MC_MCLKB 0x00020000
913 #define MCLK_CNTL__FORCE_MC_MCLK 0x00100000
914 #define MCLK_CNTL__DISABLE_MC_MCLKA 0x00200000
915 #define MCLK_CNTL__DISABLE_MC_MCLKB 0x00400000
916 #define SCLK_CNTL 0x0000000D
917 #define SCLK_CNTL__SCLK_SRC_SEL__MASK 0x00000007
918 #define SCLK_CNTL__SCLK_SRC_SEL__SHIFT 0
919 #define SCLK_CNTL__TCLK_SRC_SEL__MASK 0x00000700
920 #define SCLK_CNTL__TCLK_SRC_SEL__SHIFT 8
921 #define SCLK_CNTL__FORCE_CP 0x00010000
922 #define SCLK_CNTL__FORCE_HDP 0x00020000
923 #define SCLK_CNTL__FORCE_DISP 0x00040000
924 #define SCLK_CNTL__FORCE_TOP 0x00080000
925 #define SCLK_CNTL__FORCE_E2 0x00100000
926 #define SCLK_CNTL__FORCE_SE 0x00200000
927 #define SCLK_CNTL__FORCE_IDCT 0x00400000
928 #define SCLK_CNTL__FORCE_VIP 0x00800000
929 #define SCLK_CNTL__FORCE_RE 0x01000000
930 #define SCLK_CNTL__FORCE_PB 0x02000000
931 #define SCLK_CNTL__FORCE_TAM 0x04000000
932 #define SCLK_CNTL__FORCE_TDM 0x08000000
933 #define SCLK_CNTL__FORCE_RB 0x10000000
934 #define SCLK_CNTL__CP_MAX_DYN_STOP_LAT 0x00000008
935 #define SCLK_CNTL__HDP_MAX_DYN_STOP_LAT 0x00000010
936 #define SCLK_CNTL__E2_MAX_DYN_STOP_LAT 0x00000040
937 #define SCLK_CNTL__SE_MAX_DYN_STOP_LAT 0x00000080
938 #define SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT 0x00000100
939 #define SCLK_CNTL__VIP_MAX_DYN_STOP_LAT 0x00000200
940 #define SCLK_CNTL__RE_MAX_DYN_STOP_LAT 0x00000400
941 #define SCLK_CNTL__PB_MAX_DYN_STOP_LAT 0x00000800
942 #define SCLK_CNTL__TAM_MAX_DYN_STOP_LAT 0x00001000
943 #define SCLK_CNTL__TDM_MAX_DYN_STOP_LAT 0x00002000
944 #define SCLK_CNTL__RB_MAX_DYN_STOP_LAT 0x00004000
945 #define SCLK_CNTL__FORCE_DISP2 0x00008000
946 #define SCLK_CNTL__FORCE_DISP1 0x00040000
947 #define SCLK_CNTL__FORCE_SUBPIC 0x40000000
948 #define SCLK_CNTL__FORCE_OV0 0x80000000
949 #define SCLK_CNTL__TV_MAX_DYN_STOP_LAT 0x00000020
950 #define SCLK_CNTL__FORCE_TV_SCLK 0x20000000
951 #define SCLK_CNTL__VAP_MAX_DYN_STOP_LAT 0x00000080
952 #define SCLK_CNTL__SR_MAX_DYN_STOP_LAT 0x00000400
953 #define SCLK_CNTL__PX_MAX_DYN_STOP_LAT 0x00000800
954 #define SCLK_CNTL__TX_MAX_DYN_STOP_LAT 0x00001000
955 #define SCLK_CNTL__US_MAX_DYN_STOP_LAT 0x00002000
956 #define SCLK_CNTL__SU_MAX_DYN_STOP_LAT 0x00004000
957 #define SCLK_CNTL__FORCE_VAP 0x00200000
958 #define SCLK_CNTL__FORCE_SR 0x02000000
959 #define SCLK_CNTL__FORCE_PX 0x04000000
960 #define SCLK_CNTL__FORCE_TX 0x08000000
961 #define SCLK_CNTL__FORCE_US 0x10000000
962 #define SCLK_CNTL__FORCE_SU 0x40000000
963 #define PPLL_CNTL 0x00000002
964 #define PPLL_CNTL__PPLL_RESET 0x00000001
965 #define PPLL_CNTL__PPLL_SLEEP 0x00000002
966 #define PPLL_CNTL__PPLL_TST_EN 0x00000004
967 #define PPLL_CNTL__PPLL_REFCLK_SEL 0x00000010
968 #define PPLL_CNTL__PPLL_FBCLK_SEL 0x00000020
969 #define PPLL_CNTL__PPLL_TCPOFF 0x00000040
970 #define PPLL_CNTL__PPLL_TVCOMAX 0x00000080
971 #define PPLL_CNTL__PPLL_PCP__MASK 0x00000700
972 #define PPLL_CNTL__PPLL_PCP__SHIFT 8
973 #define PPLL_CNTL__PPLL_PVG__MASK 0x00003800
974 #define PPLL_CNTL__PPLL_PVG__SHIFT 11
975 #define PPLL_CNTL__PPLL_PDC__MASK 0x0000C000
976 #define PPLL_CNTL__PPLL_PDC__SHIFT 14
977 #define PPLL_CNTL__PPLL_ATOMIC_UPDATE_EN 0x00010000
978 #define PPLL_CNTL__PPLL_VGA_ATOMIC_UPDATE_EN 0x00020000
979 #define PPLL_CNTL__PPLL_ATOMIC_UPDATE_SYNC 0x00040000
980 #define PPLL_CNTL__PPLL_DISABLE_AUTO_RESET 0x00080000
981 #define PPLL_CNTL__PPLL_DIV_RESET 0x00000008
982 #define PPLL_REF_DIV 0x00000003
983 #define PPLL_REF_DIV__PPLL_REF_DIV__MASK 0x000003FF
984 #define PPLL_REF_DIV__PPLL_REF_DIV__SHIFT 0
985 #define PPLL_REF_DIV__PPLL_ATOMIC_UPDATE_W 0x00008000
986 #define PPLL_REF_DIV__PPLL_ATOMIC_UPDATE_R 0x00008000
987 #define PPLL_REF_DIV__PPLL_REF_DIV_SRC__MASK 0x00030000
988 #define PPLL_REF_DIV__PPLL_REF_DIV_SRC__SHIFT 16
989 #define PPLL_REF_DIV_SRC__XTALIN 0x0
990 #define PPLL_REF_DIV_SRC__PLLSCLK_2 0x1
991 #define PPLL_REF_DIV_SRC__PLLSCLK_4 0x2
992 #define PPLL_REF_DIV_SRC__SREFCLK 0x3
993 #define PPLL_REF_DIV__PPLL_REF_DIV_ACC__MASK 0x0FFC0000
994 #define PPLL_REF_DIV__PPLL_REF_DIV_ACC__SHIFT 18
995 #define PPLL_DIV_0 0x00000004
996 #define PPLL_DIV_0__PPLL_FB0_DIV__MASK 0x000007FF
997 #define PPLL_DIV_0__PPLL_FB0_DIV__SHIFT 0
998 #define PPLL_DIV_0__PPLL_ATOMIC_UPDATE_W 0x00008000
999 #define PPLL_DIV_0__PPLL_ATOMIC_UPDATE_R 0x00008000
1000 #define PPLL_DIV_0__PPLL_POST0_DIV__MASK 0x00070000
1001 #define PPLL_DIV_0__PPLL_POST0_DIV__SHIFT 16
1002 #define PPLL_DIV_0__PPLL_FB_DIV_FRACTION__MASK 0x00380000
1003 #define PPLL_DIV_0__PPLL_FB_DIV_FRACTION__SHIFT 19
1004 #define PPLL_DIV_0__PPLL_FB_DIV_FRACTION_UPDATE 0x00400000
1005 #define PPLL_DIV_0__PPLL_FB_DIV_FRACTION_EN 0x00800000
1006 #define PPLL_DIV_1 0x00000005
1007 #define PPLL_DIV_1__PPLL_FB1_DIV__MASK 0x000007FF
1008 #define PPLL_DIV_1__PPLL_FB1_DIV__SHIFT 0
1009 #define PPLL_DIV_1__PPLL_ATOMIC_UPDATE_W 0x00008000
1010 #define PPLL_DIV_1__PPLL_ATOMIC_UPDATE_R 0x00008000
1011 #define PPLL_DIV_1__PPLL_POST1_DIV__MASK 0x00070000
1012 #define PPLL_DIV_1__PPLL_POST1_DIV__SHIFT 16
1013 #define PPLL_DIV_2 0x00000006
1014 #define PPLL_DIV_2__PPLL_FB2_DIV__MASK 0x000007FF
1015 #define PPLL_DIV_2__PPLL_FB2_DIV__SHIFT 0
1016 #define PPLL_DIV_2__PPLL_ATOMIC_UPDATE_W 0x00008000
1017 #define PPLL_DIV_2__PPLL_ATOMIC_UPDATE_R 0x00008000
1018 #define PPLL_DIV_2__PPLL_POST2_DIV__MASK 0x00070000
1019 #define PPLL_DIV_2__PPLL_POST2_DIV__SHIFT 16
1020 #define PPLL_DIV_3 0x00000007
1021 #define PPLL_DIV_3__PPLL_FB3_DIV__MASK 0x000007FF
1022 #define PPLL_DIV_3__PPLL_FB3_DIV__SHIFT 0
1023 #define PPLL_DIV_3__PPLL_ATOMIC_UPDATE_W 0x00008000
1024 #define PPLL_DIV_3__PPLL_ATOMIC_UPDATE_R 0x00008000
1025 #define PPLL_DIV_3__PPLL_POST3_DIV__MASK 0x00070000
1026 #define PPLL_DIV_3__PPLL_POST3_DIV__SHIFT 16
1027 #define VCLK_ECP_CNTL 0x00000008
1028 #define VCLK_ECP_CNTL__VCLK_SRC_SEL__MASK 0x00000003
1029 #define VCLK_ECP_CNTL__VCLK_SRC_SEL__SHIFT 0
1030 #define VCLK_SRC_SEL__CPUCLK 0x0
1031 #define VCLK_SRC_SEL__PSCANCLK 0x1
1032 #define VCLK_SRC_SEL__BYTE_CLK 0x2
1033 #define VCLK_SRC_SEL__PPLLCLK 0x3
1034 #define VCLK_ECP_CNTL__VCLK_INVERT 0x00000010
1035 #define VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb 0x00000040
1036 #define VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb 0x00000080
1037 #define VCLK_ECP_CNTL__ECP_DIV__MASK 0x00000300
1038 #define VCLK_ECP_CNTL__ECP_DIV__SHIFT 8
1039 #define VCLK_ECP_CNTL__ECP_FORCE_ON 0x00040000
1040 #define VCLK_ECP_CNTL__SUBCLK_FORCE_ON 0x00080000
1041 #define VCLK_ECP_CNTL__BYTE_CLK_POST_DIV__MASK 0x00030000
1042 #define VCLK_ECP_CNTL__BYTE_CLK_POST_DIV__SHIFT 16
1043 #define VCLK_ECP_CNTL__BYTE_CLK_OUT_EN 0x00100000
1044 #define VCLK_ECP_CNTL__BYTE_CLK_SKEW__MASK 0x07000000
1045 #define VCLK_ECP_CNTL__BYTE_CLK_SKEW__SHIFT 24
1046 #define VCLK_ECP_CNTL__PCICLK_INVERT 0x00000020
1047 #define VCLK_ECP_CNTL__PIXCLK_SRC_INVERT 0x00000020
1048 #define VCLK_ECP_CNTL__PIXCLK_SRC_INVERT_R3 0x08000000
1049 #define VCLK_ECP_CNTL__DISP_DAC_PIXCLK_DAC_BLANK_OFF 0x00800000
1050 #define HTOTAL_CNTL 0x00000009
1051 #define HTOTAL_CNTL__HTOT_PIX_SLIP__MASK 0x0000000F
1052 #define HTOTAL_CNTL__HTOT_PIX_SLIP__SHIFT 0
1053 #define HTOTAL_CNTL__HTOT_VCLK_SLIP__MASK 0x00000F00
1054 #define HTOTAL_CNTL__HTOT_VCLK_SLIP__SHIFT 8
1055 #define HTOTAL_CNTL__HTOT_PPLL_SLIP__MASK 0x00070000
1056 #define HTOTAL_CNTL__HTOT_PPLL_SLIP__SHIFT 16
1057 #define HTOTAL_CNTL__HTOT_CNTL_EDGE 0x01000000
1058 #define HTOTAL_CNTL__HTOT_CNTL_VGA_EN 0x10000000
1059 #define FP_H_SYNC_STRT_WID 0x000002C4
1060 #define FP_H_SYNC_STRT_WID__FP_H_SYNC_STRT_PIX__MASK 0x00000007
1061 #define FP_H_SYNC_STRT_WID__FP_H_SYNC_STRT_PIX__SHIFT 0
1062 #define FP_H_SYNC_STRT_WID__FP_H_SYNC_STRT_CHAR__MASK 0x00001FF8
1063 #define FP_H_SYNC_STRT_WID__FP_H_SYNC_STRT_CHAR__SHIFT 3
1064 #define FP_H_SYNC_STRT_WID__FP_H_SYNC_WID__MASK 0x003F0000
1065 #define FP_H_SYNC_STRT_WID__FP_H_SYNC_WID__SHIFT 16
1066 #define FP_H_SYNC_STRT_WID__FP_H_SYNC_POL 0x00800000
1067 #define FP_V_SYNC_STRT_WID 0x000002C8
1068 #define FP_V_SYNC_STRT_WID__FP_V_SYNC_STRT__MASK 0x00000FFF
1069 #define FP_V_SYNC_STRT_WID__FP_V_SYNC_STRT__SHIFT 0
1070 #define FP_V_SYNC_STRT_WID__FP_V_SYNC_WID__MASK 0x001F0000
1071 #define FP_V_SYNC_STRT_WID__FP_V_SYNC_WID__SHIFT 16
1072 #define FP_V_SYNC_STRT_WID__FP_V_SYNC_POL 0x00800000
1073 #define FP_CRTC_H_TOTAL_DISP 0x00000250
1074 #define FP_CRTC_H_TOTAL_DISP__FP_CRTC_H_TOTAL__MASK 0x000003FF
1075 #define FP_CRTC_H_TOTAL_DISP__FP_CRTC_H_TOTAL__SHIFT 0
1076 #define FP_CRTC_H_TOTAL_DISP__FP_CRTC_H_DISP__MASK 0x01FF0000
1077 #define FP_CRTC_H_TOTAL_DISP__FP_CRTC_H_DISP__SHIFT 16
1078 #define FP_CRTC_V_TOTAL_DISP 0x00000254
1079 #define FP_CRTC_V_TOTAL_DISP__FP_CRTC_V_TOTAL__MASK 0x00000FFF
1080 #define FP_CRTC_V_TOTAL_DISP__FP_CRTC_V_TOTAL__SHIFT 0
1081 #define FP_CRTC_V_TOTAL_DISP__FP_CRTC_V_DISP__MASK 0x0FFF0000
1082 #define FP_CRTC_V_TOTAL_DISP__FP_CRTC_V_DISP__SHIFT 16
1083 #define PALETTE_INDEX 0x000000B0
1084 #define PALETTE_INDEX__PALETTE_W_INDEX__MASK 0x000000FF
1085 #define PALETTE_INDEX__PALETTE_W_INDEX__SHIFT 0
1086 #define PALETTE_INDEX__PALETTE_R_INDEX__MASK 0x00FF0000
1087 #define PALETTE_INDEX__PALETTE_R_INDEX__SHIFT 16
1088 #define PALETTE_DATA 0x000000B4
1089 #define PALETTE_DATA__PALETTE_DATA_B__MASK 0x000000FF
1090 #define PALETTE_DATA__PALETTE_DATA_B__SHIFT 0
1091 #define PALETTE_DATA__PALETTE_DATA_G__MASK 0x0000FF00
1092 #define PALETTE_DATA__PALETTE_DATA_G__SHIFT 8
1093 #define PALETTE_DATA__PALETTE_DATA_R__MASK 0x00FF0000
1094 #define PALETTE_DATA__PALETTE_DATA_R__SHIFT 16
1095 #define PALETTE_30_DATA 0x000000B8
1096 #define PALETTE_30_DATA__PALETTE_DATA_B__MASK 0x000003FF
1097 #define PALETTE_30_DATA__PALETTE_DATA_B__SHIFT 0
1098 #define PALETTE_30_DATA__PALETTE_DATA_G__MASK 0x000FFC00
1099 #define PALETTE_30_DATA__PALETTE_DATA_G__SHIFT 10
1100 #define PALETTE_30_DATA__PALETTE_DATA_R__MASK 0x3FF00000
1101 #define PALETTE_30_DATA__PALETTE_DATA_R__SHIFT 20
1102 #define SURFACE_CNTL 0x00000B00
1103 #define SURFACE_CNTL__SURF_TRANSLATION_DIS 0x00000100
1104 #define SURFACE_CNTL__NONSURF_AP0_SWP__MASK 0x00300000
1105 #define SURFACE_CNTL__NONSURF_AP0_SWP__SHIFT 20
1106 #define SURFACE_CNTL__NONSURF_AP1_SWP__MASK 0x00C00000
1107 #define SURFACE_CNTL__NONSURF_AP1_SWP__SHIFT 22
1108 #define SURFACE0_INFO 0x00000B0C
1109 #define SURFACE0_INFO__SURF0_PITCHSEL__MASK 0x000003FF
1110 #define SURFACE0_INFO__SURF0_PITCHSEL__SHIFT 0
1111 #define SURFACE0_INFO__SURF0_TILE_MODE__MASK 0x00030000
1112 #define SURFACE0_INFO__SURF0_TILE_MODE__SHIFT 16
1113 #define SURF0_TILE_MODE__NO_TILING(p) 0x0
1114 #define SURF0_TILE_MODE__MACRO_TILING(p) 0x0
1115 #define SURF0_TILE_MODE__MICRO_TILING(p) 0x0
1116 #define SURF0_TILE_MODE__MACRO_MICRO_TILING(p) 0x0
1117 #define SURF0_TILE_MODE__32_BIT_Z_TILING(p) 0x0
1118 #define SURF0_TILE_MODE__16_BIT_Z_TILING(p) 0x0
1119 #define SURFACE0_INFO__SURF0_AP0_SWP__MASK 0x00300000
1120 #define SURFACE0_INFO__SURF0_AP0_SWP__SHIFT 20
1121 #define SURFACE0_INFO__SURF0_AP1_SWP__MASK 0x00C00000
1122 #define SURFACE0_INFO__SURF0_AP1_SWP__SHIFT 22
1123 #define SURFACE0_INFO__SURF0_WRITE_FLAG 0x01000000
1124 #define SURFACE0_INFO__SURF0_READ_FLAG 0x02000000
1125 #define SURFACE0_INFO__SURF0_TILE_MODE_R2__MASK 0x00070000
1126 #define SURFACE0_INFO__SURF0_TILE_MODE_R2__SHIFT 16
1127 #define SURFACE0_INFO__SURF0_PITCHSEL_R3__MASK 0x00001FFF
1128 #define SURFACE0_INFO__SURF0_PITCHSEL_R3__SHIFT 0
1129 #define SURFACE0_LOWER_BOUND 0x00000B04
1130 #define SURFACE0_LOWER_BOUND__SURF_LOWER__MASK 0x0FFFFFFF
1131 #define SURFACE0_LOWER_BOUND__SURF_LOWER__SHIFT 0
1132 #define SURFACE0_UPPER_BOUND 0x00000B08
1133 #define SURFACE0_UPPER_BOUND__SURF_UPPER__MASK 0x0FFFFFFF
1134 #define SURFACE0_UPPER_BOUND__SURF_UPPER__SHIFT 0
1135 #define SURFACE1_INFO 0x00000B1C
1136 #define SURFACE1_INFO__SURF1_PITCHSEL__MASK 0x000003FF
1137 #define SURFACE1_INFO__SURF1_PITCHSEL__SHIFT 0
1138 #define SURFACE1_INFO__SURF1_TILE_MODE__MASK 0x00030000
1139 #define SURFACE1_INFO__SURF1_TILE_MODE__SHIFT 16
1140 #define SURFACE1_INFO__SURF1_AP0_SWP__MASK 0x00300000
1141 #define SURFACE1_INFO__SURF1_AP0_SWP__SHIFT 20
1142 #define SURFACE1_INFO__SURF1_AP1_SWP__MASK 0x00C00000
1143 #define SURFACE1_INFO__SURF1_AP1_SWP__SHIFT 22
1144 #define SURFACE1_INFO__SURF1_WRITE_FLAG 0x01000000
1145 #define SURFACE1_INFO__SURF1_READ_FLAG 0x02000000
1146 #define SURFACE1_INFO__SURF1_TILE_MODE_R2__MASK 0x00070000
1147 #define SURFACE1_INFO__SURF1_TILE_MODE_R2__SHIFT 16
1148 #define SURFACE1_INFO__SURF1_PITCHSEL_R3__MASK 0x00001FFF
1149 #define SURFACE1_INFO__SURF1_PITCHSEL_R3__SHIFT 0
1150 #define SURFACE1_LOWER_BOUND 0x00000B14
1151 #define SURFACE1_LOWER_BOUND__SURF_LOWER__MASK 0x0FFFFFFF
1152 #define SURFACE1_LOWER_BOUND__SURF_LOWER__SHIFT 0
1153 #define SURFACE1_UPPER_BOUND 0x00000B18
1154 #define SURFACE1_UPPER_BOUND__SURF_UPPER__MASK 0x0FFFFFFF
1155 #define SURFACE1_UPPER_BOUND__SURF_UPPER__SHIFT 0
1156 #define SURFACE2_INFO 0x00000B2C
1157 #define SURFACE2_INFO__SURF2_PITCHSEL__MASK 0x000003FF
1158 #define SURFACE2_INFO__SURF2_PITCHSEL__SHIFT 0
1159 #define SURFACE2_INFO__SURF2_TILE_MODE__MASK 0x00030000
1160 #define SURFACE2_INFO__SURF2_TILE_MODE__SHIFT 16
1161 #define SURFACE2_INFO__SURF2_AP0_SWP__MASK 0x00300000
1162 #define SURFACE2_INFO__SURF2_AP0_SWP__SHIFT 20
1163 #define SURFACE2_INFO__SURF2_AP1_SWP__MASK 0x00C00000
1164 #define SURFACE2_INFO__SURF2_AP1_SWP__SHIFT 22
1165 #define SURFACE2_INFO__SURF2_WRITE_FLAG 0x01000000
1166 #define SURFACE2_INFO__SURF2_READ_FLAG 0x02000000
1167 #define SURFACE2_INFO__SURF2_TILE_MODE_R2__MASK 0x00070000
1168 #define SURFACE2_INFO__SURF2_TILE_MODE_R2__SHIFT 16
1169 #define SURFACE2_INFO__SURF2_PITCHSEL_R3__MASK 0x00001FFF
1170 #define SURFACE2_INFO__SURF2_PITCHSEL_R3__SHIFT 0
1171 #define SURFACE2_LOWER_BOUND 0x00000B24
1172 #define SURFACE2_LOWER_BOUND__SURF_LOWER__MASK 0x0FFFFFFF
1173 #define SURFACE2_LOWER_BOUND__SURF_LOWER__SHIFT 0
1174 #define SURFACE2_UPPER_BOUND 0x00000B28
1175 #define SURFACE2_UPPER_BOUND__SURF_UPPER__MASK 0x0FFFFFFF
1176 #define SURFACE2_UPPER_BOUND__SURF_UPPER__SHIFT 0
1177 #define SURFACE3_INFO 0x00000B3C
1178 #define SURFACE3_INFO__SURF3_PITCHSEL__MASK 0x000003FF
1179 #define SURFACE3_INFO__SURF3_PITCHSEL__SHIFT 0
1180 #define SURFACE3_INFO__SURF3_TILE_MODE__MASK 0x00030000
1181 #define SURFACE3_INFO__SURF3_TILE_MODE__SHIFT 16
1182 #define SURFACE3_INFO__SURF3_AP0_SWP__MASK 0x00300000
1183 #define SURFACE3_INFO__SURF3_AP0_SWP__SHIFT 20
1184 #define SURFACE3_INFO__SURF3_AP1_SWP__MASK 0x00C00000
1185 #define SURFACE3_INFO__SURF3_AP1_SWP__SHIFT 22
1186 #define SURFACE3_INFO__SURF3_WRITE_FLAG 0x01000000
1187 #define SURFACE3_INFO__SURF3_READ_FLAG 0x02000000
1188 #define SURFACE3_INFO__SURF3_TILE_MODE_R2__MASK 0x00070000
1189 #define SURFACE3_INFO__SURF3_TILE_MODE_R2__SHIFT 16
1190 #define SURFACE3_INFO__SURF3_PITCHSEL_R3__MASK 0x00001FFF
1191 #define SURFACE3_INFO__SURF3_PITCHSEL_R3__SHIFT 0
1192 #define SURFACE3_LOWER_BOUND 0x00000B34
1193 #define SURFACE3_LOWER_BOUND__SURF_LOWER__MASK 0x0FFFFFFF
1194 #define SURFACE3_LOWER_BOUND__SURF_LOWER__SHIFT 0
1195 #define SURFACE3_UPPER_BOUND 0x00000B38
1196 #define SURFACE3_UPPER_BOUND__SURF_UPPER__MASK 0x0FFFFFFF
1197 #define SURFACE3_UPPER_BOUND__SURF_UPPER__SHIFT 0
1198 #define SURFACE4_INFO 0x00000B4C
1199 #define SURFACE4_INFO__SURF4_PITCHSEL__MASK 0x000003FF
1200 #define SURFACE4_INFO__SURF4_PITCHSEL__SHIFT 0
1201 #define SURFACE4_INFO__SURF4_TILE_MODE__MASK 0x00030000
1202 #define SURFACE4_INFO__SURF4_TILE_MODE__SHIFT 16
1203 #define SURFACE4_INFO__SURF4_AP0_SWP__MASK 0x00300000
1204 #define SURFACE4_INFO__SURF4_AP0_SWP__SHIFT 20
1205 #define SURFACE4_INFO__SURF4_AP1_SWP__MASK 0x00C00000
1206 #define SURFACE4_INFO__SURF4_AP1_SWP__SHIFT 22
1207 #define SURFACE4_INFO__SURF4_WRITE_FLAG 0x01000000
1208 #define SURFACE4_INFO__SURF4_READ_FLAG 0x02000000
1209 #define SURFACE4_INFO__SURF4_TILE_MODE_R2__MASK 0x00070000
1210 #define SURFACE4_INFO__SURF4_TILE_MODE_R2__SHIFT 16
1211 #define SURFACE4_INFO__SURF4_PITCHSEL_R3__MASK 0x00001FFF
1212 #define SURFACE4_INFO__SURF4_PITCHSEL_R3__SHIFT 0
1213 #define SURFACE4_LOWER_BOUND 0x00000B44
1214 #define SURFACE4_LOWER_BOUND__SURF_LOWER__MASK 0x0FFFFFFF
1215 #define SURFACE4_LOWER_BOUND__SURF_LOWER__SHIFT 0
1216 #define SURFACE4_UPPER_BOUND 0x00000B48
1217 #define SURFACE4_UPPER_BOUND__SURF_UPPER__MASK 0x0FFFFFFF
1218 #define SURFACE4_UPPER_BOUND__SURF_UPPER__SHIFT 0
1219 #define SURFACE5_INFO 0x00000B5C
1220 #define SURFACE5_INFO__SURF5_PITCHSEL__MASK 0x000003FF
1221 #define SURFACE5_INFO__SURF5_PITCHSEL__SHIFT 0
1222 #define SURFACE5_INFO__SURF5_TILE_MODE__MASK 0x00030000
1223 #define SURFACE5_INFO__SURF5_TILE_MODE__SHIFT 16
1224 #define SURFACE5_INFO__SURF5_AP0_SWP__MASK 0x00300000
1225 #define SURFACE5_INFO__SURF5_AP0_SWP__SHIFT 20
1226 #define SURFACE5_INFO__SURF5_AP1_SWP__MASK 0x00C00000
1227 #define SURFACE5_INFO__SURF5_AP1_SWP__SHIFT 22
1228 #define SURFACE5_INFO__SURF5_WRITE_FLAG 0x01000000
1229 #define SURFACE5_INFO__SURF5_READ_FLAG 0x02000000
1230 #define SURFACE5_INFO__SURF5_TILE_MODE_R2__MASK 0x00070000
1231 #define SURFACE5_INFO__SURF5_TILE_MODE_R2__SHIFT 16
1232 #define SURFACE5_INFO__SURF5_PITCHSEL_R3__MASK 0x00001FFF
1233 #define SURFACE5_INFO__SURF5_PITCHSEL_R3__SHIFT 0
1234 #define SURFACE5_LOWER_BOUND 0x00000B54
1235 #define SURFACE5_LOWER_BOUND__SURF_LOWER__MASK 0x0FFFFFFF
1236 #define SURFACE5_LOWER_BOUND__SURF_LOWER__SHIFT 0
1237 #define SURFACE5_UPPER_BOUND 0x00000B58
1238 #define SURFACE5_UPPER_BOUND__SURF_UPPER__MASK 0x0FFFFFFF
1239 #define SURFACE5_UPPER_BOUND__SURF_UPPER__SHIFT 0
1240 #define SURFACE6_INFO 0x00000B6C
1241 #define SURFACE6_INFO__SURF6_PITCHSEL__MASK 0x000003FF
1242 #define SURFACE6_INFO__SURF6_PITCHSEL__SHIFT 0
1243 #define SURFACE6_INFO__SURF6_TILE_MODE__MASK 0x00030000
1244 #define SURFACE6_INFO__SURF6_TILE_MODE__SHIFT 16
1245 #define SURFACE6_INFO__SURF6_AP0_SWP__MASK 0x00300000
1246 #define SURFACE6_INFO__SURF6_AP0_SWP__SHIFT 20
1247 #define SURFACE6_INFO__SURF6_AP1_SWP__MASK 0x00C00000
1248 #define SURFACE6_INFO__SURF6_AP1_SWP__SHIFT 22
1249 #define SURFACE6_INFO__SURF6_WRITE_FLAG 0x01000000
1250 #define SURFACE6_INFO__SURF6_READ_FLAG 0x02000000
1251 #define SURFACE6_INFO__SURF6_TILE_MODE_R2__MASK 0x00070000
1252 #define SURFACE6_INFO__SURF6_TILE_MODE_R2__SHIFT 16
1253 #define SURFACE6_INFO__SURF6_PITCHSEL_R3__MASK 0x00001FFF
1254 #define SURFACE6_INFO__SURF6_PITCHSEL_R3__SHIFT 0
1255 #define SURFACE6_LOWER_BOUND 0x00000B64
1256 #define SURFACE6_LOWER_BOUND__SURF_LOWER__MASK 0x0FFFFFFF
1257 #define SURFACE6_LOWER_BOUND__SURF_LOWER__SHIFT 0
1258 #define SURFACE6_UPPER_BOUND 0x00000B68
1259 #define SURFACE6_UPPER_BOUND__SURF_UPPER__MASK 0x0FFFFFFF
1260 #define SURFACE6_UPPER_BOUND__SURF_UPPER__SHIFT 0
1261 #define SURFACE7_INFO 0x00000B7C
1262 #define SURFACE7_INFO__SURF7_PITCHSEL__MASK 0x000003FF
1263 #define SURFACE7_INFO__SURF7_PITCHSEL__SHIFT 0
1264 #define SURFACE7_INFO__SURF7_TILE_MODE__MASK 0x00030000
1265 #define SURFACE7_INFO__SURF7_TILE_MODE__SHIFT 16
1266 #define SURFACE7_INFO__SURF7_AP0_SWP__MASK 0x00300000
1267 #define SURFACE7_INFO__SURF7_AP0_SWP__SHIFT 20
1268 #define SURFACE7_INFO__SURF7_AP1_SWP__MASK 0x00C00000
1269 #define SURFACE7_INFO__SURF7_AP1_SWP__SHIFT 22
1270 #define SURFACE7_INFO__SURF7_WRITE_FLAG 0x01000000
1271 #define SURFACE7_INFO__SURF7_READ_FLAG 0x02000000
1272 #define SURFACE7_INFO__SURF7_TILE_MODE_R2__MASK 0x00070000
1273 #define SURFACE7_INFO__SURF7_TILE_MODE_R2__SHIFT 16
1274 #define SURFACE7_INFO__SURF7_PITCHSEL_R3__MASK 0x00001FFF
1275 #define SURFACE7_INFO__SURF7_PITCHSEL_R3__SHIFT 0
1276 #define SURFACE7_LOWER_BOUND 0x00000B74
1277 #define SURFACE7_LOWER_BOUND__SURF_LOWER__MASK 0x0FFFFFFF
1278 #define SURFACE7_LOWER_BOUND__SURF_LOWER__SHIFT 0
1279 #define SURFACE7_UPPER_BOUND 0x00000B78
1280 #define SURFACE7_UPPER_BOUND__SURF_UPPER__MASK 0x0FFFFFFF
1281 #define SURFACE7_UPPER_BOUND__SURF_UPPER__SHIFT 0
1282 #define ISYNC_CNTL 0x00001724
1283 #define ISYNC_CNTL__ISYNC_ANY2D_IDLE3D 0x00000001
1284 #define ISYNC_CNTL__ISYNC_ANY3D_IDLE2D 0x00000002
1285 #define ISYNC_CNTL__ISYNC_TRIG2D_IDLE3D 0x00000004
1286 #define ISYNC_CNTL__ISYNC_TRIG3D_IDLE2D 0x00000008
1287 #define ISYNC_CNTL__ISYNC_WAIT_IDLEGUI 0x00000010
1288 #define ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI 0x00000020
1289 #define GA_SOFT_RESET 0x0000429C
1290 #define GA_SOFT_RESET__SOFT_RESET_COUNT__MASK 0x0000FFFF
1291 #define GA_SOFT_RESET__SOFT_RESET_COUNT__SHIFT 0
1292 #define RBBM_CNTL 0x000000EC
1293 #define RBBM_CNTL__RB_SETTLE__MASK 0x0000000F
1294 #define RBBM_CNTL__RB_SETTLE__SHIFT 0
1295 #define RBBM_CNTL__ABORTCLKS_HI__MASK 0x00000070
1296 #define RBBM_CNTL__ABORTCLKS_HI__SHIFT 4
1297 #define RBBM_CNTL__ABORTCLKS_CP__MASK 0x00000700
1298 #define RBBM_CNTL__ABORTCLKS_CP__SHIFT 8
1299 #define RBBM_CNTL__ABORTCLKS_CFIFO__MASK 0x00007000
1300 #define RBBM_CNTL__ABORTCLKS_CFIFO__SHIFT 12
1301 #define RBBM_CNTL__CPQ_DATA_SWAP 0x00020000
1302 #define RBBM_CNTL__NO_ABORT_IDCT 0x00200000
1303 #define RBBM_CNTL__NO_ABORT_BIOS 0x00400000
1304 #define RBBM_CNTL__NO_ABORT_FB 0x00800000
1305 #define RBBM_CNTL__NO_ABORT_CP 0x01000000
1306 #define RBBM_CNTL__NO_ABORT_HI 0x02000000
1307 #define RBBM_CNTL__NO_ABORT_HDP 0x04000000
1308 #define RBBM_CNTL__NO_ABORT_MC 0x08000000
1309 #define RBBM_CNTL__NO_ABORT_AIC 0x10000000
1310 #define RBBM_CNTL__NO_ABORT_VIP 0x20000000
1311 #define RBBM_CNTL__NO_ABORT_DISP 0x40000000
1312 #define RBBM_CNTL__NO_ABORT_CG 0x80000000
1313 #define RBBM_CNTL__NO_ABORT_VAP 0x00080000
1314 #define RBBM_CNTL__NO_ABORT_GA 0x00100000
1315 #define RBBM_CNTL__NO_ABORT_TVOUT 0x00800000
1316 #define RBBM_STATUS 0x00000E40
1317 #define RBBM_STATUS__CMDFIFO_AVAIL__MASK 0x0000007F
1318 #define RBBM_STATUS__CMDFIFO_AVAIL__SHIFT 0
1319 #define RBBM_STATUS__HIRQ_ON_RBB 0x00000100
1320 #define RBBM_STATUS__CPRQ_ON_RBB 0x00000200
1321 #define RBBM_STATUS__CFRQ_ON_RBB 0x00000400
1322 #define RBBM_STATUS__HIRQ_IN_RTBUF 0x00000800
1323 #define RBBM_STATUS__CPRQ_IN_RTBUF 0x00001000
1324 #define RBBM_STATUS__CFRQ_IN_RTBUF 0x00002000
1325 #define RBBM_STATUS__CF_PIPE_BUSY 0x00004000
1326 #define RBBM_STATUS__ENG_EV_BUSY 0x00008000
1327 #define RBBM_STATUS__CP_CMDSTRM_BUSY 0x00010000
1328 #define RBBM_STATUS__E2_BUSY 0x00020000
1329 #define RBBM_STATUS__RB2D_BUSY 0x00040000
1330 #define RBBM_STATUS__RB3D_BUSY 0x00080000
1331 #define RBBM_STATUS__SE_BUSY 0x00100000
1332 #define RBBM_STATUS__RE_BUSY 0x00200000
1333 #define RBBM_STATUS__TAM_BUSY 0x00400000
1334 #define RBBM_STATUS__TDM_BUSY 0x00800000
1335 #define RBBM_STATUS__PB_BUSY 0x01000000
1336 #define RBBM_STATUS__GUI_ACTIVE 0x80000000
1337 #define RBBM_STATUS__VAP_BUSY 0x00100000
1338 #define RBBM_STATUS__TIM_BUSY 0x02000000
1339 #define RBBM_STATUS__GA_BUSY 0x04000000
1340 #define RBBM_STATUS__CBA2D_BUSY 0x08000000
1341 #define RBBM_SOFT_RESET 0x000000F0
1342 #define RBBM_SOFT_RESET__SOFT_RESET_CP 0x00000001
1343 #define RBBM_SOFT_RESET__SOFT_RESET_HI 0x00000002
1344 #define RBBM_SOFT_RESET__SOFT_RESET_SE 0x00000004
1345 #define RBBM_SOFT_RESET__SOFT_RESET_RE 0x00000008
1346 #define RBBM_SOFT_RESET__SOFT_RESET_PP 0x00000010
1347 #define RBBM_SOFT_RESET__SOFT_RESET_E2 0x00000020
1348 #define RBBM_SOFT_RESET__SOFT_RESET_RB 0x00000040
1349 #define RBBM_SOFT_RESET__SOFT_RESET_HDP 0x00000080
1350 #define RBBM_SOFT_RESET__SOFT_RESET_MC 0x00000100
1351 #define RBBM_SOFT_RESET__SOFT_RESET_AIC 0x00000200
1352 #define RBBM_SOFT_RESET__SOFT_RESET_VIP 0x00000400
1353 #define RBBM_SOFT_RESET__SOFT_RESET_DISP 0x00000800
1354 #define RBBM_SOFT_RESET__SOFT_RESET_CG 0x00001000
1355 #define RBBM_SOFT_RESET__SOFT_RESET_VAP 0x00000004
1356 #define RBBM_SOFT_RESET__SOFT_RESET_GA 0x00002000
1357 #define RBBM_SOFT_RESET__SOFT_RESET_IDCT 0x00004000
1358 #define RBBM_CMDFIFO_ADDR 0x00000E70
1359 #define RBBM_CMDFIFO_ADDR__CMDFIFO_ADDR__MASK 0x0000003F
1360 #define RBBM_CMDFIFO_ADDR__CMDFIFO_ADDR__SHIFT 0
1361 #define RBBM_CMDFIFO_ADDR__CMDFIFO_ADDR_R3__MASK 0x000001FF
1362 #define RBBM_CMDFIFO_ADDR__CMDFIFO_ADDR_R3__SHIFT 0
1363 #define RBBM_CMDFIFO_DATA 0x00000E74
1364 #define RBBM_CMDFIFO_DATA__CMDFIFO_DATA__MASK 0xFFFFFFFF
1365 #define RBBM_CMDFIFO_DATA__CMDFIFO_DATA__SHIFT 0
1366 #define RBBM_CMDFIFO_STAT 0x00000E7C
1367 #define RBBM_CMDFIFO_STAT__CMDFIFO_RPTR__MASK 0x0000003F
1368 #define RBBM_CMDFIFO_STAT__CMDFIFO_RPTR__SHIFT 0
1369 #define RBBM_CMDFIFO_STAT__CMDFIFO_WPTR__MASK 0x00003F00
1370 #define RBBM_CMDFIFO_STAT__CMDFIFO_WPTR__SHIFT 8
1371 #define WAIT_UNTIL 0x00001720
1372 #define WAIT_UNTIL__WAIT_CRTC_PFLIP 0x00000001
1373 #define WAIT_UNTIL__WAIT_RE_CRTC_VLINE 0x00000002
1374 #define WAIT_UNTIL__WAIT_FE_CRTC_VLINE 0x00000004
1375 #define WAIT_UNTIL__WAIT_CRTC_VLINE 0x00000008
1376 #define WAIT_UNTIL__WAIT_DMA_VIPH0_IDLE 0x00000010
1377 #define WAIT_UNTIL__WAIT_DMA_VIPH1_IDLE 0x00000020
1378 #define WAIT_UNTIL__WAIT_DMA_VIPH2_IDLE 0x00000040
1379 #define WAIT_UNTIL__WAIT_DMA_VIPH3_IDLE 0x00000080
1380 #define WAIT_UNTIL__WAIT_DMA_VID_IDLE 0x00000100
1381 #define WAIT_UNTIL__WAIT_DMA_GUI_IDLE 0x00000200
1382 #define WAIT_UNTIL__WAIT_CMDFIFO 0x00000400
1383 #define WAIT_UNTIL__WAIT_OV0_FLIP 0x00000800
1384 #define WAIT_UNTIL__WAIT_OV0_SLICEDONE 0x00001000
1385 #define WAIT_UNTIL__WAIT_2D_IDLE 0x00004000
1386 #define WAIT_UNTIL__WAIT_3D_IDLE 0x00008000
1387 #define WAIT_UNTIL__WAIT_2D_IDLECLEAN 0x00010000
1388 #define WAIT_UNTIL__WAIT_3D_IDLECLEAN 0x00020000
1389 #define WAIT_UNTIL__WAIT_HOST_IDLECLEAN 0x00040000
1390 #define WAIT_UNTIL__WAIT_EXTERN_SIG 0x00080000
1391 #define WAIT_UNTIL__CMDFIFO_ENTRIES__MASK 0x07F00000
1392 #define WAIT_UNTIL__CMDFIFO_ENTRIES__SHIFT 20
1393 #define WAIT_UNTIL__WAIT_BOTH_CRTC_PFLIP 0x40000000
1394 #define WAIT_UNTIL__ENG_DISPLAY_SELECT 0x80000000
1395 #define WAIT_UNTIL__WAIT_AGP_FLUSH 0x00002000
1396 #define WAIT_UNTIL__WAIT_IDCT_SEMAPHORE 0x08000000
1397 #define WAIT_UNTIL__WAIT_VAP_IDLE 0x10000000
1398 #define DISPLAY_BASE_ADDR 0x0000023C
1399 #define DISPLAY_BASE_ADDR__DISPLAY_BASE_ADDR__MASK 0xFFFFFFFF
1400 #define DISPLAY_BASE_ADDR__DISPLAY_BASE_ADDR__SHIFT 0
1401 #define CRTC2_DISPLAY_BASE_ADDR 0x0000033C
1402 #define CRTC2_DISPLAY_BASE_ADDR__CRTC2_DISPLAY_BASE_ADDR__MASK 0xFFFFFFFF
1403 #define CRTC2_DISPLAY_BASE_ADDR__CRTC2_DISPLAY_BASE_ADDR__SHIFT 0
1404 #define AIC_CTRL 0x000001D0
1405 #define AIC_CTRL__TRANSLATE_EN 0x00000001
1406 #define AIC_CTRL__HW_0_DEBUG 0x00000002
1407 #define AIC_CTRL__HW_1_DEBUG 0x00000004
1408 #define AIC_CTRL__HW_2_DEBUG 0x00000008
1409 #define AIC_CTRL__HW_3_DEBUG 0x00000010
1410 #define AIC_CTRL__HW_4_DEBUG 0x00000020
1411 #define AIC_CTRL__HW_5_DEBUG 0x00000040
1412 #define AIC_CTRL__HW_6_DEBUG 0x00000080
1413 #define AIC_CTRL__HW_7_DEBUG 0x00000100
1414 #define AIC_CTRL__HW_8_DEBUG 0x00000200
1415 #define AIC_CTRL__HW_9_DEBUG 0x00000400
1416 #define AIC_CTRL__HW_A_DEBUG 0x00000800
1417 #define AIC_CTRL__HW_B_DEBUG 0x00001000
1418 #define AIC_CTRL__HW_C_DEBUG 0x00002000
1419 #define AIC_CTRL__HW_D_DEBUG 0x00004000
1420 #define AIC_CTRL__HW_E_DEBUG 0x00008000
1421 #define AIC_CTRL__HW_F_DEBUG 0x00010000
1422 #define AIC_CTRL__HW_10_DEBUG 0x00020000
1423 #define AIC_CTRL__HW_11_DEBUG 0x00040000
1424 #define AIC_CTRL__HW_12_DEBUG 0x00080000
1425 #define AIC_CTRL__HW_13_DEBUG 0x00100000
1426 #define AIC_CTRL__HW_14_DEBUG 0x00200000
1427 #define AIC_CTRL__HW_15_DEBUG 0x00400000
1428 #define AIC_CTRL__HW_16_DEBUG 0x00800000
1429 #define AIC_CTRL__HW_17_DEBUG 0x01000000
1430 #define AIC_CTRL__HW_18_DEBUG 0x02000000
1431 #define AIC_CTRL__HW_19_DEBUG 0x04000000
1432 #define AIC_CTRL__HW_1A_DEBUG 0x08000000
1433 #define AIC_CTRL__HW_1B_DEBUG 0x10000000
1434 #define AIC_CTRL__HW_1C_DEBUG 0x20000000
1435 #define AIC_CTRL__HW_1D_DEBUG 0x40000000
1436 #define AIC_CTRL__HW_1E_DEBUG 0x80000000
1437 #define AIC_CTRL__DIS_OUT_OF_PCI_GART_ACCESS 0x00000002
1438 #define AIC_CTRL__HW_02_DEBUG 0x00000004
1439 #define AIC_CTRL__HW_03_DEBUG 0x00000008
1440 #define AIC_CTRL__TEST_RBF_DIV_VAL__MASK 0x00000070
1441 #define AIC_CTRL__TEST_RBF_DIV_VAL__SHIFT 4
1442 #define AIC_CTRL__TEST_RBF_EN 0x00000080
1443 #define AIC_CTRL__HW_08_DEBUG 0x00000100
1444 #define AIC_CTRL__HW_09_DEBUG 0x00000200
1445 #define AIC_CTRL__HW_10_DEBUG_R3 0x00000400
1446 #define AIC_CTRL__HW_11_DEBUG_R3 0x00000800
1447 #define AIC_CTRL__HW_12_DEBUG_R3 0x00001000
1448 #define AIC_CTRL__HW_13_DEBUG_R3 0x00002000
1449 #define AIC_CTRL__HW_14_DEBUG_R3 0x00004000
1450 #define AIC_CTRL__HW_15_DEBUG_R3 0x00008000
1451 #define AIC_CTRL__HW_16_DEBUG_R3 0x00010000
1452 #define AIC_CTRL__HW_17_DEBUG_R3 0x00020000
1453 #define AIC_CTRL__HW_18_DEBUG_R3 0x00040000
1454 #define AIC_CTRL__HW_19_DEBUG_R3 0x00080000
1455 #define AIC_CTRL__HW_20_DEBUG 0x00100000
1456 #define AIC_CTRL__HW_21_DEBUG 0x00200000
1457 #define AIC_CTRL__HW_22_DEBUG 0x00400000
1458 #define AIC_CTRL__HW_23_DEBUG 0x00800000
1459 #define AIC_CTRL__HW_24_DEBUG 0x01000000
1460 #define AIC_CTRL__HW_25_DEBUG 0x02000000
1461 #define AIC_CTRL__HW_26_DEBUG 0x04000000
1462 #define AIC_CTRL__HW_27_DEBUG 0x08000000
1463 #define AIC_CTRL__HW_28_DEBUG 0x10000000
1464 #define AIC_CTRL__HW_29_DEBUG 0x20000000
1465 #define AIC_CTRL__HW_30_DEBUG 0x40000000
1466 #define AIC_CTRL__HW_31_DEBUG 0x80000000
1467 #define BUS_CNTL 0x00000030
1468 #define BUS_CNTL__BUS_DBL_RESYNC 0x00000001
1469 #define BUS_CNTL__BUS_MSTR_RESET 0x00000002
1470 #define BUS_CNTL__BUS_FLUSH_BUF 0x00000004
1471 #define BUS_CNTL__BUS_STOP_REQ_DIS 0x00000008
1472 #define BUS_CNTL__BUS_READ_COMBINE_EN 0x00000010
1473 #define BUS_CNTL__BUS_WRT_COMBINE_EN 0x00000020
1474 #define BUS_CNTL__BUS_MASTER_DIS 0x00000040
1475 #define BUS_CNTL__BIOS_ROM_WRT_EN 0x00000080
1476 #define BUS_CNTL__BUS_PREFETCH_MODE__MASK 0x00000300
1477 #define BUS_CNTL__BUS_PREFETCH_MODE__SHIFT 8
1478 #define BUS_CNTL__BUS_VGA_PREFETCH_EN 0x00000400
1479 #define BUS_CNTL__BUS_SGL_READ_DISABLE 0x00000800
1480 #define BUS_CNTL__BIOS_DIS_ROM 0x00001000
1481 #define BUS_CNTL__BUS_PCI_READ_RETRY_EN 0x00002000
1482 #define BUS_CNTL__BUS_AGP_AD_STEPPING_EN 0x00004000
1483 #define BUS_CNTL__BUS_PCI_WRT_RETRY_EN 0x00008000
1484 #define BUS_CNTL__BUS_RETRY_WS__MASK 0x000F0000
1485 #define BUS_CNTL__BUS_RETRY_WS__SHIFT 16
1486 #define BUS_CNTL__BUS_MSTR_RD_MULT 0x00100000
1487 #define BUS_CNTL__BUS_MSTR_RD_LINE 0x00200000
1488 #define BUS_CNTL__BUS_SUSPEND 0x00400000
1489 #define BUS_CNTL__LAT_16X 0x00800000
1490 #define BUS_CNTL__BUS_RD_DISCARD_EN 0x01000000
1491 #define BUS_CNTL__ENFRCWRDY 0x02000000
1492 #define BUS_CNTL__BUS_MSTR_WS 0x04000000
1493 #define BUS_CNTL__BUS_PARKING_DIS 0x08000000
1494 #define BUS_CNTL__BUS_MSTR_DISCONNECT_EN 0x10000000
1495 #define BUS_CNTL__SERR_EN 0x20000000
1496 #define BUS_CNTL__BUS_READ_BURST 0x40000000
1497 #define BUS_CNTL__BUS_RDY_READ_DLY 0x80000000
1498 #define BUS_CNTL__BUS_PM4_READ_COMBINE_EN 0x00000010
1499 #define BUS_CNTL__BM_DAC_CRIPPLE 0x00000100
1500 #define BUS_CNTL__BUS_NON_PM4_READ_COMBINE_EN 0x00000200
1501 #define BUS_CNTL__BUS_XFERD_DISCARD_EN 0x00000400
1502 #define MC_STATUS 0x00000150
1503 #define MC_STATUS__MEM_PWRUP_COMPL_A 0x00000001
1504 #define MC_STATUS__MEM_PWRUP_COMPL_B 0x00000002
1505 #define MC_STATUS__MC_IDLE 0x00000004
1506 #define MC_STATUS__SPARE__MASK 0x0000FFF8
1507 #define MC_STATUS__SPARE__SHIFT 3
1508 #define MC_STATUS__IMP_N_VALUE_R_BACK__MASK 0x00000078
1509 #define MC_STATUS__IMP_N_VALUE_R_BACK__SHIFT 3
1510 #define MC_STATUS__IMP_P_VALUE_R_BACK__MASK 0x00000780
1511 #define MC_STATUS__IMP_P_VALUE_R_BACK__SHIFT 7
1512 #define MC_STATUS__TEST_OUT_R_BACK 0x00000800
1513 #define MC_STATUS__DUMMY_OUT_R_BACK 0x00001000
1514 #define MC_STATUS__IMP_N_VALUE_A_R_BACK__MASK 0x0001E000
1515 #define MC_STATUS__IMP_N_VALUE_A_R_BACK__SHIFT 13
1516 #define MC_STATUS__IMP_P_VALUE_A_R_BACK__MASK 0x001E0000
1517 #define MC_STATUS__IMP_P_VALUE_A_R_BACK__SHIFT 17
1518 #define MC_STATUS__IMP_N_VALUE_CK_R_BACK__MASK 0x01E00000
1519 #define MC_STATUS__IMP_N_VALUE_CK_R_BACK__SHIFT 21
1520 #define MC_STATUS__IMP_P_VALUE_CK_R_BACK__MASK 0x1E000000
1521 #define MC_STATUS__IMP_P_VALUE_CK_R_BACK__SHIFT 25
1522 #define MC_STATUS__MEM_PWRUP_COMPL_C 0x00000004
1523 #define MC_STATUS__MEM_PWRUP_COMPL_D 0x00000008
1524 #define MC_STATUS__MC_IDLE_R3 0x00000010
1525 #define MC_STATUS__IMP_CAL_COUNT__MASK 0x0000F000
1526 #define MC_STATUS__IMP_CAL_COUNT__SHIFT 12
1527 #define OV0_SCALE_CNTL 0x00000420
1528 #define OV0_SCALE_CNTL__OV0_NO_READ_BEHIND_SCAN 0x00000002
1529 #define OV0_SCALE_CNTL__OV0_HORZ_PICK_NEAREST 0x00000004
1530 #define OV0_SCALE_CNTL__OV0_VERT_PICK_NEAREST 0x00000008
1531 #define OV0_SCALE_CNTL__OV0_SIGNED_UV 0x00000010
1532 #define OV0_SCALE_CNTL__OV0_GAMMA_SEL__MASK 0x000000E0
1533 #define OV0_SCALE_CNTL__OV0_GAMMA_SEL__SHIFT 5
1534 #define OV0_SCALE_CNTL__OV0_SURFACE_FORMAT__MASK 0x00000F00
1535 #define OV0_SCALE_CNTL__OV0_SURFACE_FORMAT__SHIFT 8
1536 #define OV0_SURFACE_FORMAT__RESERVED0 0x0
1537 #define OV0_SURFACE_FORMAT__RESERVED1 0x100
1538 #define OV0_SURFACE_FORMAT__RESERVED2 0x200
1539 #define OV0_SURFACE_FORMAT__16BPP_ARGB 0x300
1540 #define OV0_SURFACE_FORMAT__16BPP_RGB 0x400
1541 #define OV0_SURFACE_FORMAT__RESERVED5 0x500
1542 #define OV0_SURFACE_FORMAT__32BPP_ARGB 0x600
1543 #define OV0_SURFACE_FORMAT__RESERVED7 0x700
1544 #define OV0_SURFACE_FORMAT__RESERVED8 0x800
1545 #define OV0_SURFACE_FORMAT__IF09_PLANAR 0x900
1546 #define OV0_SURFACE_FORMAT__YV12_PLANAR 0xA00
1547 #define OV0_SURFACE_FORMAT__YUY2_PACKED 0xB00
1548 #define OV0_SURFACE_FORMAT__UYVY_PACKED 0xC00
1549 #define OV0_SURFACE_FORMAT__YYUV9_PLANAR 0xD00
1550 #define OV0_SURFACE_FORMAT__YYUV12_PLANAR 0xE00
1551 #define OV0_SURFACE_FORMAT__RESERVED15 0xF00
1552 #define OV0_SCALE_CNTL__OV0_ADAPTIVE_DEINT 0x00001000
1553 #define OV0_SCALE_CNTL__OV0_CRTC_SEL 0x00004000
1554 #define OV0_SCALE_CNTL__OV0_BURST_PER_PLANE__MASK 0x007F0000
1555 #define OV0_SCALE_CNTL__OV0_BURST_PER_PLANE__SHIFT 16
1556 #define OV0_SCALE_CNTL__OV0_DOUBLE_BUFFER_REGS 0x01000000
1557 #define OV0_SCALE_CNTL__OV0_BANDWIDTH 0x04000000
1558 #define OV0_SCALE_CNTL__OV0_LIN_TRANS_BYPASS 0x10000000
1559 #define OV0_SCALE_CNTL__OV0_INT_EMU 0x20000000
1560 #define OV0_SCALE_CNTL__OV0_OVERLAY_EN__MASK 0x40000000
1561 #define OV0_SCALE_CNTL__OV0_OVERLAY_EN__SHIFT 30
1562 #define OV0_OVERLAY_EN__ENABLE 0x40000000
1563 #define OV0_SCALE_CNTL__OV0_SOFT_RESET__MASK 0x80000000
1564 #define OV0_SCALE_CNTL__OV0_SOFT_RESET__SHIFT 31
1565 #define OV0_SOFT_RESET__RESET 0x80000000
1566 #define OV0_SCALE_CNTL__OV0_TEMPORAL_DEINT 0x00002000
1567 #define OV0_SCALE_CNTL__OV0_PULLDOWN_ON_P1_ONLY 0x00008000
1568 #define OV0_SCALE_CNTL__OV0_FULL_BYPASS 0x00000020
1569 #define OV0_SCALE_CNTL__OV0_DYNAMIC_EXT 0x00000040
1570 #define OV0_SCALE_CNTL__OV0_RGB30_ON 0x00000080
1571 #define CRTC2_GEN_CNTL 0x000003F8
1572 #define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN 0x00000001
1573 #define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN 0x00000002
1574 #define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE 0x00000010
1575 #define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE 0x00000020
1576 #define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE 0x00000040
1577 #define CRTC2_GEN_CNTL__CRT2_ON 0x00000080
1578 #define CRTC2_GEN_CNTL__CRTC2_PIX_WIDTH__MASK 0x00000F00
1579 #define CRTC2_GEN_CNTL__CRTC2_PIX_WIDTH__SHIFT 8
1580 #define CRTC2_GEN_CNTL__CRTC2_ICON_EN 0x00008000
1581 #define CRTC2_GEN_CNTL__CRTC2_CUR_EN 0x00010000
1582 #define CRTC2_GEN_CNTL__CRTC2_CUR_MODE__MASK 0x00700000
1583 #define CRTC2_GEN_CNTL__CRTC2_CUR_MODE__SHIFT 20
1584 #define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS 0x00800000
1585 #define CRTC2_GEN_CNTL__CRTC2_EN 0x02000000
1586 #define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B 0x04000000
1587 #define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN 0x08000000
1588 #define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS 0x10000000
1589 #define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS 0x20000000
1590 #define CRTC2_GEN_CNTL__CRTC2_MODE9_COLOR_ORDER 0x00001000
1591 #define CRTC2_GEN_CNTL__CRTC2_FIX_VSYNC_EDGE_POSITION_EN 0x40000000
1592 #define CRTC2_OFFSET 0x00000324
1593 #define CRTC2_OFFSET__CRTC2_OFFSET__MASK 0x07FFFFFF
1594 #define CRTC2_OFFSET__CRTC2_OFFSET__SHIFT 0
1595 #define CRTC2_OFFSET__CRTC2_GUI_TRIG_OFFSET 0x40000000
1596 #define CRTC2_OFFSET__CRTC2_OFFSET_LOCK 0x80000000
1597 #define CRTC2_OFFSET__CRTC2_OFFSET_R3__MASK 0x0FFFFFFF
1598 #define CRTC2_OFFSET__CRTC2_OFFSET_R3__SHIFT 0
1599 #define CRTC2_OFFSET_CNTL 0x00000328
1600 #define CRTC2_OFFSET_CNTL__CRTC2_TILE_LINE__MASK 0x0000000F
1601 #define CRTC2_OFFSET_CNTL__CRTC2_TILE_LINE__SHIFT 0
1602 #define CRTC2_OFFSET_CNTL__CRTC2_TILE_EN 0x00008000
1603 #define CRTC2_OFFSET_CNTL__CRTC2_OFFSET_FLIP_CNTL 0x00010000
1604 #define CRTC2_OFFSET_CNTL__CRTC2_GUI_TRIG_OFFSET_LEFT_EN 0x10000000
1605 #define CRTC2_OFFSET_CNTL__CRTC2_GUI_TRIG_OFFSET 0x40000000
1606 #define CRTC2_OFFSET_CNTL__CRTC2_OFFSET_LOCK 0x80000000
1607 #define CRTC2_OFFSET_CNTL__CRTC2_TILE_LINE_RIGHT__MASK 0x000000F0
1608 #define CRTC2_OFFSET_CNTL__CRTC2_TILE_LINE_RIGHT__SHIFT 4
1609 #define CRTC2_OFFSET_CNTL__CRTC2_TILE_EN_RIGHT 0x00004000
1610 #define CRTC2_OFFSET_CNTL__CRTC2_STEREO_OFFSET_EN 0x00020000
1611 #define CRTC2_OFFSET_CNTL__CRTC2_STEREO_SYNC_EN__MASK 0x000C0000
1612 #define CRTC2_OFFSET_CNTL__CRTC2_STEREO_SYNC_EN__SHIFT 18
1613 #define CRTC2_OFFSET_CNTL__CRTC2_STEREO_SYNC 0x00200000
1614 #define CRTC2_OFFSET_CNTL__CRTC2_GUI_TRIG_OFFSET_RIGHT_EN 0x20000000
1615 #define CRTC2_OFFSET_CNTL__CRTC2_X_Y_MODE_EN_RIGHT 0x00000100
1616 #define CRTC2_OFFSET_CNTL__CRTC2_X_Y_MODE_EN 0x00000200
1617 #define CRTC2_OFFSET_CNTL__CRTC2_MICRO_TILE_EN_RIGHT 0x00001000
1618 #define CRTC2_OFFSET_CNTL__CRTC2_MICRO_TILE_EN 0x00002000
1619 #define CRTC2_OFFSET_CNTL__CRTC2_MACRO_TILE_EN_RIGHT 0x00004000
1620 #define CRTC2_OFFSET_CNTL__CRTC2_MACRO_TILE_EN 0x00008000
1621 #define CUR_OFFSET 0x00000260
1622 #define CUR_OFFSET__CUR_OFFSET__MASK 0x07FFFFFF
1623 #define CUR_OFFSET__CUR_OFFSET__SHIFT 0
1624 #define CUR_OFFSET__CUR_LOCK 0x80000000
1625 #define CUR2_OFFSET 0x00000360
1626 #define CUR2_OFFSET__CUR2_OFFSET__MASK 0x07FFFFFF
1627 #define CUR2_OFFSET__CUR2_OFFSET__SHIFT 0
1628 #define CUR2_OFFSET__CUR2_LOCK 0x80000000
1629 #define HOST_PATH_CNTL 0x00000130
1630 #define HOST_PATH_CNTL__HDP_APER_CNTL 0x00800000
1631 #define HOST_PATH_CNTL__HP_LIN_RD_CACHE_DIS 0x01000000
1632 #define HOST_PATH_CNTL__HP_RBBM_LOCK_DIS 0x02000000
1633 #define HOST_PATH_CNTL__HDP_SOFT_RESET 0x04000000
1634 #define HOST_PATH_CNTL__HDP_WRITE_COMBINER_TIMEOUT__MASK 0x70000000
1635 #define HOST_PATH_CNTL__HDP_WRITE_COMBINER_TIMEOUT__SHIFT 28
1636 #define HOST_PATH_CNTL__HP_TEST_RST_CNTL 0x80000000
1637 #define HOST_PATH_CNTL__HDP_WRITE_THROUGH_CACHE_DIS 0x00400000
1638 #define HOST_PATH_CNTL__HDP_READ_BUFFER_INVALIDATE 0x08000000
1639 #define DST_PITCH_OFFSET 0x0000142C
1640 #define DST_PITCH_OFFSET__DST_OFFSET__MASK 0x003FFFFF
1641 #define DST_PITCH_OFFSET__DST_OFFSET__SHIFT 0
1642 #define DST_PITCH_OFFSET__DST_PITCH__MASK 0x3FC00000
1643 #define DST_PITCH_OFFSET__DST_PITCH__SHIFT 22
1644 #define DST_PITCH_OFFSET__DST_TILE__MASK 0xC0000000
1645 #define DST_PITCH_OFFSET__DST_TILE__SHIFT 30
1646 #define DST_TILE__MACRO 0x1
1647 #define DST_TILE__MICRO 0x2
1648 #define SRC_PITCH_OFFSET 0x00001428
1649 #define SRC_PITCH_OFFSET__SRC_OFFSET__MASK 0x003FFFFF
1650 #define SRC_PITCH_OFFSET__SRC_OFFSET__SHIFT 0
1651 #define SRC_PITCH_OFFSET__SRC_PITCH__MASK 0x3FC00000
1652 #define SRC_PITCH_OFFSET__SRC_PITCH__SHIFT 22
1653 #define SRC_PITCH_OFFSET__SRC_TILE 0x40000000
1654 #define DEFAULT_SC_BOTTOM_RIGHT 0x000016E8
1655 #define DEFAULT_SC_BOTTOM_RIGHT__DEFAULT_SC_RIGHT__MASK 0x00003FFF
1656 #define DEFAULT_SC_BOTTOM_RIGHT__DEFAULT_SC_RIGHT__SHIFT 0
1657 #define DEFAULT_SC_BOTTOM_RIGHT__DEFAULT_SC_BOTTOM__MASK 0x3FFF0000
1658 #define DEFAULT_SC_BOTTOM_RIGHT__DEFAULT_SC_BOTTOM__SHIFT 16
1659 #define DEFAULT2_SC_BOTTOM_RIGHT 0x000016DC
1660 #define DEFAULT2_SC_BOTTOM_RIGHT__DEFAULT_SC_RIGHT__MASK 0x00003FFF
1661 #define DEFAULT2_SC_BOTTOM_RIGHT__DEFAULT_SC_RIGHT__SHIFT 0
1662 #define DEFAULT2_SC_BOTTOM_RIGHT__DEFAULT_SC_BOTTOM__MASK 0x3FFF0000
1663 #define DEFAULT2_SC_BOTTOM_RIGHT__DEFAULT_SC_BOTTOM__SHIFT 16
1664 #define DP_DATATYPE 0x000016C4
1665 #define DP_DATATYPE__DP_DST_DATATYPE__MASK 0x0000000F
1666 #define DP_DATATYPE__DP_DST_DATATYPE__SHIFT 0
1667 #define DP_DATATYPE__DP_BRUSH_DATATYPE__MASK 0x00000F00
1668 #define DP_DATATYPE__DP_BRUSH_DATATYPE__SHIFT 8
1669 #define DP_DATATYPE__DP_SRC_DATATYPE__MASK 0x00070000
1670 #define DP_DATATYPE__DP_SRC_DATATYPE__SHIFT 16
1671 #define DP_DATATYPE__DP_BYTE_PIX_ORDER 0x40000000
1672 #define DP_GUI_MASTER_CNTL 0x0000146C
1673 #define DP_GUI_MASTER_CNTL__GMC_SRC_PITCH_OFFSET_CNTL 0x00000001
1674 #define DP_GUI_MASTER_CNTL__GMC_DST_PITCH_OFFSET_CNTL 0x00000002
1675 #define DP_GUI_MASTER_CNTL__GMC_SRC_CLIPPING 0x00000004
1676 #define DP_GUI_MASTER_CNTL__GMC_DST_CLIPPING 0x00000008
1677 #define DP_GUI_MASTER_CNTL__GMC_BRUSH_DATATYPE__MASK 0x000000F0
1678 #define DP_GUI_MASTER_CNTL__GMC_BRUSH_DATATYPE__SHIFT 4
1679 #define GMC_BRUSH_DATATYPE__8X8_MONO_FG_BG 0x0
1680 #define GMC_BRUSH_DATATYPE__8X8_MONO_FG 0x1
1681 #define GMC_BRUSH_DATATYPE__32X1_MONO_LINE_FG_BG 0x6
1682 #define GMC_BRUSH_DATATYPE__32X1_MONO_LINE_FG 0x7
1683 #define GMC_BRUSH_DATATYPE__8X8_COLOR 0xA
1684 #define GMC_BRUSH_DATATYPE__SOLID_COLOR_FG 0xD
1685 #define GMC_BRUSH_DATATYPE__SOLID_COLOR_RESERVED 0xF
1686 #define GMC_BRUSH_DATATYPE__SOLID 0xD0
1687 #define GMC_BRUSH_DATATYPE__MONO8x8 0x0
1688 #define GMC_BRUSH_DATATYPE__COLOR8x8 0xA0
1689 #define DP_GUI_MASTER_CNTL__GMC_DST_DATATYPE__MASK 0x00000F00
1690 #define DP_GUI_MASTER_CNTL__GMC_DST_DATATYPE__SHIFT 8
1691 #define GMC_DST_DATATYPE__8BPP_CLUT 0x2
1692 #define GMC_DST_DATATYPE__16BPP_1555 0x3
1693 #define GMC_DST_DATATYPE__16BPP_565 0x4
1694 #define GMC_DST_DATATYPE__32BPP_8888 0x6
1695 #define GMC_DST_DATATYPE__CI8 0x200
1696 #define GMC_DST_DATATYPE__RGB16_1555 0x300
1697 #define GMC_DST_DATATYPE__RGB16_565 0x400
1698 #define GMC_DST_DATATYPE__RGB32 0x600
1699 #define DP_GUI_MASTER_CNTL__GMC_SRC_DATATYPE__MASK 0x00003000
1700 #define DP_GUI_MASTER_CNTL__GMC_SRC_DATATYPE__SHIFT 12
1701 #define GMC_SRC_DATATYPE__BUILD(x) 0x0
1702 #define GMC_SRC_DATATYPE__MONO_OPAQUE 0x0
1703 #define GMC_SRC_DATATYPE__MONO_TRANSPARENT 0x0
1704 #define GMC_SRC_DATATYPE__SAME_AS_DST 0x0
1705 #define GMC_SRC_DATATYPE__8BPP_CLUT_XLAT 0x0
1706 #define GMC_SRC_DATATYPE__32BPP_CLUT_XLAT 0x0
1707 #define GMC_SRC_DATATYPE__MONO_FG_BG 0x0
1708 #define GMC_SRC_DATATYPE__MONO_FG 0x1000
1709 #define GMC_SRC_DATATYPE__COLOR 0x3000
1710 #define GMC_SRC_DATATYPE__DST 0x3000
1711 #define DP_GUI_MASTER_CNTL__GMC_BYTE_PIX_ORDER 0x00004000
1712 #define DP_GUI_MASTER_CNTL__GMC_DEFAULT_SEL 0x00008000
1713 #define DP_GUI_MASTER_CNTL__GMC_ROP3__MASK 0x00FF0000
1714 #define DP_GUI_MASTER_CNTL__GMC_ROP3__SHIFT 16
1715 #define GMC_ROP3__SRCCPY 0xCC
1716 #define GMC_ROP3__WHITENESS 0xFF
1717 #define GMC_ROP3__BLACKNESS 0x0
1718 #define DP_GUI_MASTER_CNTL__GMC_DP_SRC_SOURCE__MASK 0x07000000
1719 #define DP_GUI_MASTER_CNTL__GMC_DP_SRC_SOURCE__SHIFT 24
1720 #define GMC_DP_SRC_SOURCE__VIDEO_MEM 0x2
1721 #define GMC_DP_SRC_SOURCE__HOSTDATA 0x3
1722 #define GMC_DP_SRC_SOURCE__HOSTDATA_BYTE 0x4
1723 #define DP_GUI_MASTER_CNTL__GMC_SRC_DATATYPE2 0x08000000
1724 #define DP_GUI_MASTER_CNTL__GMC_CLR_CMP_FCN_DIS 0x10000000
1725 #define DP_GUI_MASTER_CNTL__GMC_WR_MSK_DIS 0x40000000
1726 #define DP_BRUSH_FRGD_CLR 0x0000147C
1727 #define DP_BRUSH_FRGD_CLR__DP_BRUSH_FRGD_CLR__MASK 0xFFFFFFFF
1728 #define DP_BRUSH_FRGD_CLR__DP_BRUSH_FRGD_CLR__SHIFT 0
1729 #define DP_BRUSH_BKGD_CLR 0x00001478
1730 #define DP_BRUSH_BKGD_CLR__DP_BRUSH_BKGD_CLR__MASK 0xFFFFFFFF
1731 #define DP_BRUSH_BKGD_CLR__DP_BRUSH_BKGD_CLR__SHIFT 0
1732 #define DP_SRC_FRGD_CLR 0x000015D8
1733 #define DP_SRC_FRGD_CLR__DP_SRC_FRGD_CLR__MASK 0xFFFFFFFF
1734 #define DP_SRC_FRGD_CLR__DP_SRC_FRGD_CLR__SHIFT 0
1735 #define DP_SRC_BKGD_CLR 0x000015DC
1736 #define DP_SRC_BKGD_CLR__DP_SRC_BKGD_CLR__MASK 0xFFFFFFFF
1737 #define DP_SRC_BKGD_CLR__DP_SRC_BKGD_CLR__SHIFT 0
1738 #define DP_WRITE_MSK 0x000016CC
1739 #define DP_WRITE_MSK__DP_WRITE_MSK__MASK 0xFFFFFFFF
1740 #define DP_WRITE_MSK__DP_WRITE_MSK__SHIFT 0
1741 #define US_CONFIG 0x00004600
1742 #define US_CONFIG__NLEVEL__MASK 0x00000007
1743 #define US_CONFIG__NLEVEL__SHIFT 0
1744 #define US_CONFIG__FIRST_TEX 0x00000008
1745 #define US_CONFIG__PERF0__MASK 0x000001F0
1746 #define US_CONFIG__PERF0__SHIFT 4
1747 #define US_CONFIG__PERF1__MASK 0x00003E00
1748 #define US_CONFIG__PERF1__SHIFT 9
1749 #define US_CONFIG__PERF2__MASK 0x0007C000
1750 #define US_CONFIG__PERF2__SHIFT 14
1751 #define US_CONFIG__PERF3__MASK 0x00F80000
1752 #define US_CONFIG__PERF3__SHIFT 19
1753 #define US_RESET 0x0000460C
1754 #define VAP_PVS_STATE_FLUSH_REG 0x00002284
1755 #define VAP_PVS_STATE_FLUSH_REG__DATA_REGISTER__MASK 0xFFFFFFFF
1756 #define VAP_PVS_STATE_FLUSH_REG__DATA_REGISTER__SHIFT 0