2 * Copyright 2007 Jérôme Glisse
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
26 * Jerome Glisse <glisse@freedesktop.org>
30 #include "radeon_ms.h"
32 static struct radeon_ms_output radeon_ms_dac1 = {
36 radeon_ms_dac1_initialize,
37 radeon_ms_dac1_detect,
39 radeon_ms_dac1_get_modes,
40 radeon_ms_dac1_mode_fixup,
41 radeon_ms_dac1_mode_set,
42 radeon_ms_dac1_restore,
46 static struct radeon_ms_output radeon_ms_dac2 = {
50 radeon_ms_dac2_initialize,
51 radeon_ms_dac2_detect,
53 radeon_ms_dac2_get_modes,
54 radeon_ms_dac2_mode_fixup,
55 radeon_ms_dac2_mode_set,
56 radeon_ms_dac2_restore,
60 static struct radeon_ms_connector radeon_ms_vga = {
61 NULL, NULL, NULL, ConnectorVGA, MT_NONE, 0, GPIO_DDC1,
63 0, -1, -1, -1, -1, -1, -1, -1
67 static struct radeon_ms_connector radeon_ms_dvi_i_2 = {
68 NULL, NULL, NULL, ConnectorDVII, MT_NONE, 0, GPIO_DDC2,
70 1, -1, -1, -1, -1, -1, -1, -1
74 static struct radeon_ms_properties properties[] = {
75 /* default only one VGA connector */
77 0, 0, 27000, 25000, 200000, 1, 1, 1, 1,
79 &radeon_ms_dac1, NULL, NULL, NULL, NULL, NULL, NULL,
83 &radeon_ms_vga, NULL, NULL, NULL, NULL, NULL, NULL,
88 0x1043, 0x176, 27000, 25000, 200000, 1, 1, 1, 1,
90 &radeon_ms_dac1, &radeon_ms_dac2, NULL, NULL, NULL,
94 &radeon_ms_vga, &radeon_ms_dvi_i_2, NULL, NULL, NULL,
99 0x1002, 0x4150, 27000, 25000, 200000, 1, 1, 1, 1,
101 &radeon_ms_dac1, &radeon_ms_dac2, NULL, NULL, NULL,
105 &radeon_ms_vga, &radeon_ms_dvi_i_2, NULL, NULL, NULL,
111 extern const uint32_t radeon_cp_microcode[];
112 extern const uint32_t r200_cp_microcode[];
113 extern const uint32_t r300_cp_microcode[];
115 static void radeon_flush_cache(struct drm_device *dev)
117 struct drm_radeon_private *dev_priv = dev->dev_private;
121 cmd[0] = CP_PACKET0(RB2D_DSTCACHE_CTLSTAT, 0);
122 cmd[1] = REG_S(RB2D_DSTCACHE_CTLSTAT, DC_FLUSH, 3);
123 cmd[2] = CP_PACKET0(RB3D_DSTCACHE_CTLSTAT, 0);
124 cmd[3] = REG_S(RB3D_DSTCACHE_CTLSTAT, DC_FLUSH, 3);
125 cmd[4] = CP_PACKET0(RB3D_ZCACHE_CTLSTAT, 0);
126 cmd[5] = RB3D_ZCACHE_CTLSTAT__ZC_FLUSH;
127 /* try to wait but if we timeout we likely are in bad situation */
128 for (i = 0; i < dev_priv->usec_timeout; i++) {
129 ret = radeon_ms_ring_emit(dev, cmd, 6);
136 static void r300_flush_cache(struct drm_device *dev)
138 struct drm_radeon_private *dev_priv = dev->dev_private;
142 cmd[0] = CP_PACKET0(RB2D_DSTCACHE_CTLSTAT, 0);
143 cmd[1] = REG_S(RB2D_DSTCACHE_CTLSTAT, DC_FLUSH, 3);
144 cmd[2] = CP_PACKET0(RB3D_DSTCACHE_CTLSTAT_R3, 0);
145 cmd[3] = REG_S(RB3D_DSTCACHE_CTLSTAT_R3, DC_FLUSH, 3);
146 cmd[4] = CP_PACKET0(RB3D_ZCACHE_CTLSTAT_R3, 0);
147 cmd[5] = RB3D_ZCACHE_CTLSTAT_R3__ZC_FLUSH;
148 /* try to wait but if we timeout we likely are in bad situation */
149 for (i = 0; i < dev_priv->usec_timeout; i++) {
150 ret = radeon_ms_ring_emit(dev, cmd, 6);
157 int radeon_ms_family_init(struct drm_device *dev)
159 struct drm_radeon_private *dev_priv = dev->dev_private;
162 dev_priv->microcode = radeon_cp_microcode;
163 dev_priv->irq_emit = radeon_ms_irq_emit;
165 switch (dev_priv->family) {
168 dev_priv->microcode = radeon_cp_microcode;
169 dev_priv->flush_cache = radeon_flush_cache;
175 dev_priv->microcode = r200_cp_microcode;
176 dev_priv->flush_cache = radeon_flush_cache;
189 dev_priv->microcode = r300_cp_microcode;
190 dev_priv->flush_cache = r300_flush_cache;
193 DRM_ERROR("Unknown radeon family, aborting\n");
196 switch (dev_priv->bus_type) {
198 dev_priv->create_ttm = drm_agp_init_ttm;
199 dev_priv->bus_init = radeon_ms_agp_init;
200 dev_priv->bus_restore = radeon_ms_agp_restore;
201 dev_priv->bus_save = radeon_ms_agp_save;
204 dev_priv->create_ttm = radeon_ms_pcie_create_ttm;
205 dev_priv->bus_finish = radeon_ms_pcie_finish;
206 dev_priv->bus_init = radeon_ms_pcie_init;
207 dev_priv->bus_restore = radeon_ms_pcie_restore;
208 dev_priv->bus_save = radeon_ms_pcie_save;
211 DRM_ERROR("Unknown radeon bus type, aborting\n");
214 dev_priv->properties = NULL;
215 for (i = 1; i < sizeof(properties)/sizeof(properties[0]); i++) {
216 if (dev->pdev->subsystem_vendor == properties[i].subvendor &&
217 dev->pdev->subsystem_device == properties[i].subdevice) {
218 DRM_INFO("[radeon_ms] found properties for 0x%04X:0x%04X\n",
219 properties[i].subvendor, properties[i].subdevice);
220 dev_priv->properties = &properties[i];
223 if (dev_priv->properties == NULL) {
224 dev_priv->properties = &properties[0];