2 * Copyright 2007 Jérôme Glisse
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
26 * Jerome Glisse <glisse@freedesktop.org>
30 #include "radeon_ms.h"
32 extern const uint32_t radeon_cp_microcode[];
33 extern const uint32_t r200_cp_microcode[];
34 extern const uint32_t r300_cp_microcode[];
36 static void radeon_flush_cache(struct drm_device *dev)
38 struct drm_radeon_private *dev_priv = dev->dev_private;
42 cmd[0] = CP_PACKET0(RB2D_DSTCACHE_CTLSTAT, 0);
43 cmd[1] = REG_S(RB2D_DSTCACHE_CTLSTAT, DC_FLUSH, 3);
44 cmd[2] = CP_PACKET0(RB3D_DSTCACHE_CTLSTAT, 0);
45 cmd[3] = REG_S(RB3D_DSTCACHE_CTLSTAT, DC_FLUSH, 3);
46 cmd[4] = CP_PACKET0(RB3D_ZCACHE_CTLSTAT, 0);
47 cmd[5] = RB3D_ZCACHE_CTLSTAT__ZC_FLUSH;
48 /* try to wait but if we timeout we likely are in bad situation */
49 for (i = 0; i < dev_priv->usec_timeout; i++) {
50 ret = radeon_ms_ring_emit(dev, cmd, 6);
57 static void r300_flush_cache(struct drm_device *dev)
59 struct drm_radeon_private *dev_priv = dev->dev_private;
63 cmd[0] = CP_PACKET0(RB2D_DSTCACHE_CTLSTAT, 0);
64 cmd[1] = REG_S(RB2D_DSTCACHE_CTLSTAT, DC_FLUSH, 3);
65 cmd[2] = CP_PACKET0(RB3D_DSTCACHE_CTLSTAT_R3, 0);
66 cmd[3] = REG_S(RB3D_DSTCACHE_CTLSTAT_R3, DC_FLUSH, 3);
67 cmd[4] = CP_PACKET0(RB3D_ZCACHE_CTLSTAT_R3, 0);
68 cmd[5] = RB3D_ZCACHE_CTLSTAT_R3__ZC_FLUSH;
69 /* try to wait but if we timeout we likely are in bad situation */
70 for (i = 0; i < dev_priv->usec_timeout; i++) {
71 ret = radeon_ms_ring_emit(dev, cmd, 6);
78 int radeon_ms_family_init(struct drm_device *dev)
80 struct drm_radeon_private *dev_priv = dev->dev_private;
83 dev_priv->microcode = radeon_cp_microcode;
84 dev_priv->irq_emit = radeon_ms_irq_emit;
86 switch (dev_priv->family) {
89 dev_priv->microcode = radeon_cp_microcode;
90 dev_priv->flush_cache = radeon_flush_cache;
96 dev_priv->microcode = r200_cp_microcode;
97 dev_priv->flush_cache = radeon_flush_cache;
110 dev_priv->microcode = r300_cp_microcode;
111 dev_priv->flush_cache = r300_flush_cache;
114 DRM_ERROR("Unknown radeon family, aborting\n");
117 switch (dev_priv->bus_type) {
119 dev_priv->create_ttm = drm_agp_init_ttm;
120 dev_priv->bus_init = radeon_ms_agp_init;
121 dev_priv->bus_restore = radeon_ms_agp_restore;
122 dev_priv->bus_save = radeon_ms_agp_save;
125 dev_priv->create_ttm = radeon_ms_pcie_create_ttm;
126 dev_priv->bus_finish = radeon_ms_pcie_finish;
127 dev_priv->bus_init = radeon_ms_pcie_init;
128 dev_priv->bus_restore = radeon_ms_pcie_restore;
129 dev_priv->bus_save = radeon_ms_pcie_save;
132 DRM_ERROR("Unknown radeon bus type, aborting\n");
135 ret = radeon_ms_rom_init(dev);
139 ret = radeon_ms_properties_init(dev);