2 * Copyright 2007 Jérôme Glisse
3 * Copyright 2007 Dave Airlie
4 * Copyright 2007 Alex Deucher
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
28 * Jerome Glisse <glisse@freedesktop.org>
30 #include "radeon_ms.h"
32 static int radeon_ms_test_ring_buffer(struct drm_device *dev)
34 struct drm_radeon_private *dev_priv = dev->dev_private;
38 MMIO_W(SCRATCH_REG4, 0);
39 cmd[0] = CP_PACKET0(SCRATCH_REG4, 0);
41 cmd[2] = CP_PACKET0(WAIT_UNTIL, 0);
42 cmd[3] = WAIT_UNTIL__WAIT_2D_IDLECLEAN |
43 WAIT_UNTIL__WAIT_HOST_IDLECLEAN;
45 ret = radeon_ms_ring_emit(dev, cmd, 4);
51 for (i = 0; i < dev_priv->usec_timeout; i++) {
52 if (MMIO_R(SCRATCH_REG4) == 0xdeadbeef) {
53 DRM_INFO("[radeon_ms] cp test succeeded in %d usecs\n",
59 DRM_INFO("[radeon_ms] cp test failed\n");
63 static int radeon_ms_test_write_back(struct drm_device *dev)
65 struct drm_radeon_private *dev_priv = dev->dev_private;
68 if (dev_priv->ring_buffer_object == NULL ||
69 dev_priv->ring_buffer == NULL)
71 dev_priv->write_back_area[0] = 0x0;
72 MMIO_W(SCRATCH_REG0, 0xdeadbeef);
73 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
74 if (dev_priv->write_back_area[0] == 0xdeadbeef)
78 if (tmp < dev_priv->usec_timeout) {
79 DRM_INFO("[radeon_ms] writeback test succeeded in %d usecs\n",
83 MMIO_W(SCRATCH_UMSK, 0x0);
84 DRM_INFO("[radeon_ms] writeback test failed\n");
88 static __inline__ void radeon_ms_load_mc(struct drm_device *dev)
90 struct drm_radeon_private *dev_priv = dev->dev_private;
93 MMIO_W(CP_ME_RAM_ADDR, 0);
94 for (i = 0; i < 256; i++) {
95 MMIO_W(CP_ME_RAM_DATAH, dev_priv->microcode[(i * 2) + 1]);
96 MMIO_W(CP_ME_RAM_DATAL, dev_priv->microcode[(i * 2) + 0]);
100 int radeon_ms_cp_finish(struct drm_device *dev)
102 struct drm_radeon_private *dev_priv = dev->dev_private;
104 if (!dev_priv->cp_ready) {
107 dev_priv->cp_ready = 0;
108 radeon_ms_wait_for_idle(dev);
109 DRM_INFO("[radeon_ms] cp idle\n");
110 radeon_ms_cp_stop(dev);
112 DRM_INFO("[radeon_ms] ring buffer %p\n", dev_priv->ring_buffer);
113 if (dev_priv->ring_buffer) {
114 drm_bo_kunmap(&dev_priv->ring_buffer_map);
116 dev_priv->ring_buffer = NULL;
117 DRM_INFO("[radeon_ms] ring buffer object %p\n", dev_priv->ring_buffer_object);
118 if (dev_priv->ring_buffer_object) {
119 mutex_lock(&dev->struct_mutex);
120 drm_bo_usage_deref_locked(&dev_priv->ring_buffer_object);
121 mutex_unlock(&dev->struct_mutex);
126 int radeon_ms_cp_init(struct drm_device *dev)
128 struct drm_radeon_private *dev_priv = dev->dev_private;
129 struct radeon_state *state = &dev_priv->driver_state;
132 dev_priv->cp_ready = -1;
133 if (dev_priv->microcode == NULL) {
134 DRM_INFO("[radeon_ms] no microcode not starting cp");
137 /* we allocate an extra page for all write back stuff */
138 ret = drm_buffer_object_create(dev,
139 dev_priv->ring_buffer_size +
140 dev_priv->write_back_area_size,
145 DRM_BO_FLAG_NO_EVICT,
146 DRM_BO_HINT_DONT_FENCE,
149 &dev_priv->ring_buffer_object);
153 memset(&dev_priv->ring_buffer_map, 0, sizeof(struct drm_bo_kmap_obj));
154 ret = drm_bo_kmap(dev_priv->ring_buffer_object,
155 dev_priv->ring_buffer_object->mem.mm_node->start,
156 dev_priv->ring_buffer_object->mem.num_pages,
157 &dev_priv->ring_buffer_map);
159 DRM_ERROR("[radeon_ms] error mapping ring buffer: %d\n", ret);
162 dev_priv->ring_buffer = dev_priv->ring_buffer_map.virtual;
163 dev_priv->write_back_area =
164 &dev_priv->ring_buffer[dev_priv->ring_buffer_size >> 2];
165 /* setup write back offset */
166 state->scratch_umsk = 0x7;
167 state->scratch_addr =
168 REG_S(SCRATCH_ADDR, SCRATCH_ADDR,
169 (dev_priv->ring_buffer_object->offset +
170 dev_priv->ring_buffer_size +
171 dev_priv->gpu_gart_start) >> 5);
172 MMIO_W(SCRATCH_ADDR, state->scratch_addr);
173 MMIO_W(SCRATCH_UMSK, REG_S(SCRATCH_UMSK, SCRATCH_UMSK, 0x7));
174 DRM_INFO("[radeon_ms] write back at 0x%08X in gpu space\n",
175 MMIO_R(SCRATCH_ADDR));
176 dev_priv->write_back = radeon_ms_test_write_back(dev);
178 /* stop cp so it's in know state */
179 radeon_ms_cp_stop(dev);
180 if (dev_priv->ring_rptr) {
181 DRM_INFO("[radeon_ms] failed to set cp read ptr to 0\n");
183 DRM_INFO("[radeon_ms] set cp read ptr to 0\n");
185 dev_priv->ring_mask = (dev_priv->ring_buffer_size / 4) - 1;
188 DRM_INFO("[radeon_ms] load microcode\n");
189 radeon_ms_load_mc(dev);
190 /* initialize CP registers */
192 REG_S(CP_RB_CNTL, RB_BUFSZ,
193 drm_order(dev_priv->ring_buffer_size / 8)) |
194 REG_S(CP_RB_CNTL, RB_BLKSZ, drm_order(4096 / 8)) |
195 REG_S(CP_RB_CNTL, MAX_FETCH, 2);
196 if (!dev_priv->write_back) {
197 state->cp_rb_cntl |= CP_RB_CNTL__RB_NO_UPDATE;
200 REG_S(CP_RB_BASE, RB_BASE,
201 (dev_priv->ring_buffer_object->offset +
202 dev_priv->gpu_gart_start) >> 2);
203 /* read ptr writeback just after the
204 * 8 scratch registers 32 = 8*4 */
205 state->cp_rb_rptr_addr =
206 REG_S(CP_RB_RPTR_ADDR, RB_RPTR_ADDR,
207 (dev_priv->ring_buffer_object->offset +
208 dev_priv->ring_buffer_size + 32 +
209 dev_priv->gpu_gart_start) >> 2);
210 state->cp_rb_wptr = dev_priv->ring_wptr;
211 state->cp_rb_wptr_delay =
212 REG_S(CP_RB_WPTR_DELAY, PRE_WRITE_TIMER, 64) |
213 REG_S(CP_RB_WPTR_DELAY, PRE_WRITE_LIMIT, 8);
214 state->cp_rb_wptr_delay = 0;
216 radeon_ms_cp_restore(dev, state);
217 DRM_INFO("[radeon_ms] ring buffer at 0x%08X in gpu space\n",
220 /* compute free space */
221 dev_priv->ring_free = 0;
222 ret = radeon_ms_cp_wait(dev, 64);
224 /* we shouldn't fail here */
225 DRM_INFO("[radeon_ms] failed to get ring free space\n");
228 DRM_INFO("[radeon_ms] free ring size: %d\n", dev_priv->ring_free * 4);
230 MMIO_W(CP_CSQ_CNTL, REG_S(CP_CSQ_CNTL, CSQ_MODE,
231 CSQ_MODE__CSQ_PRIBM_INDBM));
232 if (!radeon_ms_test_ring_buffer(dev)) {
233 DRM_INFO("[radeon_ms] cp doesn't work\n");
234 /* disable ring should wait idle before */
235 radeon_ms_cp_stop(dev);
238 /* waaooo the cp is ready & working */
239 DRM_INFO("[radeon_ms] cp ready, enjoy\n");
240 dev_priv->cp_ready = 1;
244 void radeon_ms_cp_restore(struct drm_device *dev, struct radeon_state *state)
246 struct drm_radeon_private *dev_priv = dev->dev_private;
248 radeon_ms_wait_for_idle(dev);
249 MMIO_W(SCRATCH_ADDR, state->scratch_addr);
250 MMIO_W(SCRATCH_UMSK, state->scratch_umsk);
251 MMIO_W(CP_RB_BASE, state->cp_rb_base);
252 MMIO_W(CP_RB_RPTR_ADDR, state->cp_rb_rptr_addr);
253 MMIO_W(CP_RB_WPTR_DELAY, state->cp_rb_wptr_delay);
254 MMIO_W(CP_RB_CNTL, state->cp_rb_cntl);
255 /* Sync everything up */
256 MMIO_W(ISYNC_CNTL, ISYNC_CNTL__ISYNC_ANY2D_IDLE3D |
257 ISYNC_CNTL__ISYNC_ANY3D_IDLE2D |
258 ISYNC_CNTL__ISYNC_WAIT_IDLEGUI |
259 ISYNC_CNTL__ISYNC_CPSCRATCH_IDLEGUI);
262 void radeon_ms_cp_save(struct drm_device *dev, struct radeon_state *state)
264 struct drm_radeon_private *dev_priv = dev->dev_private;
266 state->scratch_addr = MMIO_R(SCRATCH_ADDR);
267 state->scratch_umsk = MMIO_R(SCRATCH_UMSK);
268 state->cp_rb_base = MMIO_R(CP_RB_BASE);
269 state->cp_rb_rptr_addr = MMIO_R(CP_RB_RPTR_ADDR);
270 state->cp_rb_wptr_delay = MMIO_R(CP_RB_WPTR_DELAY);
271 state->cp_rb_wptr = MMIO_R(CP_RB_WPTR);
272 state->cp_rb_cntl = MMIO_R(CP_RB_CNTL);
275 void radeon_ms_cp_stop(struct drm_device *dev)
277 struct drm_radeon_private *dev_priv = dev->dev_private;
279 MMIO_W(CP_CSQ_CNTL, REG_S(CP_CSQ_CNTL, CSQ_MODE,
280 CSQ_MODE__CSQ_PRIDIS_INDDIS));
281 MMIO_W(CP_RB_CNTL, CP_RB_CNTL__RB_RPTR_WR_ENA);
282 MMIO_W(CP_RB_RPTR_WR, 0);
283 MMIO_W(CP_RB_WPTR, 0);
285 dev_priv->ring_wptr = dev_priv->ring_rptr = MMIO_R(CP_RB_RPTR);
286 MMIO_W(CP_RB_WPTR, dev_priv->ring_wptr);
289 int radeon_ms_cp_wait(struct drm_device *dev, int n)
291 struct drm_radeon_private *dev_priv = dev->dev_private;
292 uint32_t i, last_rptr, p = 0;
294 last_rptr = MMIO_R(CP_RB_RPTR);
295 for (i = 0; i < dev_priv->usec_timeout; i++) {
296 dev_priv->ring_rptr = MMIO_R(CP_RB_RPTR);
297 if (last_rptr != dev_priv->ring_rptr) {
298 /* the ring is progressing no lockup */
301 dev_priv->ring_free = (((int)dev_priv->ring_rptr) -
302 ((int)dev_priv->ring_wptr));
303 if (dev_priv->ring_free <= 0)
304 dev_priv->ring_free += (dev_priv->ring_buffer_size / 4);
305 if (dev_priv->ring_free > n)
307 last_rptr = dev_priv->ring_rptr;
311 DRM_INFO("[radeon_ms] timed out waiting free slot\n");
313 DRM_INFO("[radeon_ms] cp have lickely locked up\n");
318 int radeon_ms_ring_emit(struct drm_device *dev, uint32_t *cmd, uint32_t count)
320 static spinlock_t ring_lock = SPIN_LOCK_UNLOCKED;
321 struct drm_radeon_private *dev_priv = dev->dev_private;
327 spin_lock(&ring_lock);
328 if (dev_priv->ring_free <= (count)) {
329 spin_unlock(&ring_lock);
332 dev_priv->ring_free -= count;
333 for (i = 0; i < count; i++) {
334 dev_priv->ring_buffer[dev_priv->ring_wptr] = cmd[i];
335 dev_priv->ring_wptr++;
336 dev_priv->ring_wptr &= dev_priv->ring_mask;
340 MMIO_W(CP_RB_WPTR, REG_S(CP_RB_WPTR, RB_WPTR, dev_priv->ring_wptr));
341 /* read from PCI bus to ensure correct posting */
343 spin_unlock(&ring_lock);