2 * Copyright 2007 Jérôme Glisse
3 * Copyright 2007 Dave Airlie
4 * Copyright 2007 Alex Deucher
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
28 * Jérôme Glisse <glisse@freedesktop.org>
30 #ifndef __RADEON_MS_H__
31 #define __RADEON_MS_H__
33 #include "radeon_ms_drv.h"
34 #include "radeon_ms_reg.h"
35 #include "radeon_ms_drm.h"
36 #include "radeon_ms_rom.h"
37 #include "radeon_ms_properties.h"
39 #define DRIVER_AUTHOR "Jerome Glisse, Dave Airlie, Gareth Hughes, "\
40 "Keith Whitwell, others."
41 #define DRIVER_NAME "radeon_ms"
42 #define DRIVER_DESC "radeon kernel modesetting"
43 #define DRIVER_DATE "20071108"
44 #define DRIVER_MAJOR 1
45 #define DRIVER_MINOR 0
46 #define DRIVER_PATCHLEVEL 0
48 enum radeon_bus_type {
51 RADEON_PCIE = 0x30000,
78 enum radeon_monitor_type {
88 enum radeon_connector_type {
90 CONNECTOR_PROPRIETARY,
99 enum radeon_output_type {
109 struct radeon_ms_crtc {
116 struct radeon_ms_i2c {
117 struct drm_device *drm_dev;
119 struct i2c_adapter adapter;
120 struct i2c_algo_bit_data algo;
123 struct radeon_ms_connector {
124 struct radeon_ms_i2c *i2c;
126 struct drm_output *output;
131 char outputs[RADEON_MAX_OUTPUTS];
135 struct radeon_ms_output {
137 struct drm_device *dev;
138 struct radeon_ms_connector *connector;
139 int (*initialize)(struct radeon_ms_output *output);
140 enum drm_output_status (*detect)(struct radeon_ms_output *output);
141 void (*dpms)(struct radeon_ms_output *output, int mode);
142 int (*get_modes)(struct radeon_ms_output *output);
143 bool (*mode_fixup)(struct radeon_ms_output *output,
144 struct drm_display_mode *mode,
145 struct drm_display_mode *adjusted_mode);
146 int (*mode_set)(struct radeon_ms_output *output,
147 struct drm_display_mode *mode,
148 struct drm_display_mode *adjusted_mode);
149 void (*restore)(struct radeon_ms_output *output,
150 struct radeon_state *state);
151 void (*save)(struct radeon_ms_output *output,
152 struct radeon_state *state);
155 struct radeon_state {
157 uint32_t config_aper_0_base;
158 uint32_t config_aper_1_base;
159 uint32_t config_aper_size;
160 uint32_t mc_fb_location;
161 uint32_t display_base_addr;
163 uint32_t gen_int_cntl;
166 uint32_t aic_pt_base;
167 uint32_t aic_pt_base_lo;
168 uint32_t aic_pt_base_hi;
169 uint32_t aic_lo_addr;
170 uint32_t aic_hi_addr;
173 uint32_t agp_command;
177 uint32_t mc_agp_location;
181 uint32_t cp_rb_rptr_addr;
183 uint32_t cp_rb_wptr_delay;
184 uint32_t scratch_umsk;
185 uint32_t scratch_addr;
187 uint32_t pcie_tx_gart_cntl;
188 uint32_t pcie_tx_gart_discard_rd_addr_lo;
189 uint32_t pcie_tx_gart_discard_rd_addr_hi;
190 uint32_t pcie_tx_gart_base;
191 uint32_t pcie_tx_gart_start_lo;
192 uint32_t pcie_tx_gart_start_hi;
193 uint32_t pcie_tx_gart_end_lo;
194 uint32_t pcie_tx_gart_end_hi;
196 uint32_t surface_cntl;
197 uint32_t surface0_info;
198 uint32_t surface0_lower_bound;
199 uint32_t surface0_upper_bound;
200 uint32_t surface1_info;
201 uint32_t surface1_lower_bound;
202 uint32_t surface1_upper_bound;
203 uint32_t surface2_info;
204 uint32_t surface2_lower_bound;
205 uint32_t surface2_upper_bound;
206 uint32_t surface3_info;
207 uint32_t surface3_lower_bound;
208 uint32_t surface3_upper_bound;
209 uint32_t surface4_info;
210 uint32_t surface4_lower_bound;
211 uint32_t surface4_upper_bound;
212 uint32_t surface5_info;
213 uint32_t surface5_lower_bound;
214 uint32_t surface5_upper_bound;
215 uint32_t surface6_info;
216 uint32_t surface6_lower_bound;
217 uint32_t surface6_upper_bound;
218 uint32_t surface7_info;
219 uint32_t surface7_lower_bound;
220 uint32_t surface7_upper_bound;
222 uint32_t crtc_gen_cntl;
223 uint32_t crtc_ext_cntl;
224 uint32_t crtc_h_total_disp;
225 uint32_t crtc_h_sync_strt_wid;
226 uint32_t crtc_v_total_disp;
227 uint32_t crtc_v_sync_strt_wid;
228 uint32_t crtc_offset;
229 uint32_t crtc_offset_cntl;
231 uint32_t crtc_more_cntl;
232 uint32_t crtc_tile_x0_y0;
233 uint32_t fp_h_sync_strt_wid;
234 uint32_t fp_v_sync_strt_wid;
235 uint32_t fp_crtc_h_total_disp;
236 uint32_t fp_crtc_v_total_disp;
238 uint32_t clock_cntl_index;
240 uint32_t ppll_ref_div;
245 uint32_t vclk_ecp_cntl;
246 uint32_t htotal_cntl;
250 uint32_t dac_ext_cntl;
251 uint32_t disp_misc_cntl;
252 uint32_t dac_macro_cntl;
253 uint32_t disp_pwr_man;
254 uint32_t disp_merge_cntl;
255 uint32_t disp_output_cntl;
256 uint32_t disp2_merge_cntl;
257 uint32_t dac_embedded_sync_cntl;
258 uint32_t dac_broad_pulse;
259 uint32_t dac_skew_clks;
261 uint32_t dac_neg_sync_level;
262 uint32_t dac_pos_sync_level;
263 uint32_t dac_blank_level;
264 uint32_t dac_sync_equalization;
265 uint32_t tv_dac_cntl;
266 uint32_t tv_master_cntl;
269 struct drm_radeon_private {
270 /* driver family specific functions */
271 int (*bus_finish)(struct drm_device *dev);
272 int (*bus_init)(struct drm_device *dev);
273 void (*bus_restore)(struct drm_device *dev, struct radeon_state *state);
274 void (*bus_save)(struct drm_device *dev, struct radeon_state *state);
275 struct drm_ttm_backend *(*create_ttm)(struct drm_device *dev);
276 void (*irq_emit)(struct drm_device *dev);
277 void (*flush_cache)(struct drm_device *dev);
278 /* bus informations */
282 uint32_t ring_buffer_size;
287 uint32_t ring_tail_mask;
288 uint32_t write_back_area_size;
289 struct drm_buffer_object *ring_buffer_object;
290 struct drm_bo_kmap_obj ring_buffer_map;
291 uint32_t *ring_buffer;
292 uint32_t *write_back_area;
293 const uint32_t *microcode;
295 uint32_t usec_timeout;
297 struct radeon_ms_output *outputs[RADEON_MAX_OUTPUTS];
298 struct radeon_ms_connector *connectors[RADEON_MAX_CONNECTORS];
299 /* drm map (MMIO, FB) */
302 /* gpu address space */
303 uint32_t gpu_vram_size;
304 uint32_t gpu_vram_start;
305 uint32_t gpu_vram_end;
306 uint32_t gpu_gart_size;
307 uint32_t gpu_gart_start;
308 uint32_t gpu_gart_end;
309 /* state of the card when module was loaded */
310 struct radeon_state load_state;
311 /* state the driver wants */
312 struct radeon_state driver_state;
313 /* last emitted fence */
314 uint32_t fence_id_last;
316 /* when doing gpu stop we save here current state */
317 uint32_t crtc_ext_cntl;
318 uint32_t crtc_gen_cntl;
319 uint32_t crtc2_gen_cntl;
320 uint32_t ov0_scale_cntl;
321 /* bool & type on the hw */
324 uint8_t restore_state;
328 /* abstract asic specific structures */
329 struct radeon_ms_rom rom;
330 struct radeon_ms_properties properties;
336 int radeon_ms_bo_get_gpu_addr(struct drm_device *dev,
337 struct drm_bo_mem_reg *mem,
339 int radeon_ms_bo_move(struct drm_buffer_object * bo, int evict,
340 int no_wait, struct drm_bo_mem_reg * new_mem);
341 struct drm_ttm_backend *radeon_ms_create_ttm_backend(struct drm_device * dev);
342 uint64_t radeon_ms_evict_flags(struct drm_buffer_object *bo);
343 int radeon_ms_init_mem_type(struct drm_device * dev, uint32_t type,
344 struct drm_mem_type_manager * man);
345 int radeon_ms_invalidate_caches(struct drm_device * dev, uint64_t flags);
346 void radeon_ms_ttm_flush(struct drm_ttm *ttm);
348 /* radeon_ms_bus.c */
349 int radeon_ms_agp_finish(struct drm_device *dev);
350 int radeon_ms_agp_init(struct drm_device *dev);
351 void radeon_ms_agp_restore(struct drm_device *dev, struct radeon_state *state);
352 void radeon_ms_agp_save(struct drm_device *dev, struct radeon_state *state);
353 struct drm_ttm_backend *radeon_ms_pcie_create_ttm(struct drm_device *dev);
354 int radeon_ms_pcie_finish(struct drm_device *dev);
355 int radeon_ms_pcie_init(struct drm_device *dev);
356 void radeon_ms_pcie_restore(struct drm_device *dev, struct radeon_state *state);
357 void radeon_ms_pcie_save(struct drm_device *dev, struct radeon_state *state);
359 /* radeon_ms_combios.c */
360 int radeon_ms_combios_get_properties(struct drm_device *dev);
361 int radeon_ms_connectors_from_combios(struct drm_device *dev);
362 int radeon_ms_outputs_from_combios(struct drm_device *dev);
364 /* radeon_ms_compat.c */
365 long radeon_ms_compat_ioctl(struct file *filp, unsigned int cmd,
369 int radeon_ms_cp_finish(struct drm_device *dev);
370 int radeon_ms_cp_init(struct drm_device *dev);
371 void radeon_ms_cp_restore(struct drm_device *dev, struct radeon_state *state);
372 void radeon_ms_cp_save(struct drm_device *dev, struct radeon_state *state);
373 void radeon_ms_cp_stop(struct drm_device *dev);
374 int radeon_ms_cp_wait(struct drm_device *dev, int n);
375 int radeon_ms_ring_emit(struct drm_device *dev, uint32_t *cmd, uint32_t count);
376 int radeon_ms_resetcp(struct drm_device *dev, void *data,
377 struct drm_file *file_priv);
379 /* radeon_ms_crtc.c */
380 int radeon_ms_crtc_create(struct drm_device *dev, int crtc);
381 void radeon_ms_crtc1_restore(struct drm_device *dev,
382 struct radeon_state *state);
383 void radeon_ms_crtc1_save(struct drm_device *dev, struct radeon_state *state);
385 /* radeon_ms_dac.c */
386 int radeon_ms_dac1_initialize(struct radeon_ms_output *output);
387 enum drm_output_status radeon_ms_dac1_detect(struct radeon_ms_output *output);
388 void radeon_ms_dac1_dpms(struct radeon_ms_output *output, int mode);
389 int radeon_ms_dac1_get_modes(struct radeon_ms_output *output);
390 bool radeon_ms_dac1_mode_fixup(struct radeon_ms_output *output,
391 struct drm_display_mode *mode,
392 struct drm_display_mode *adjusted_mode);
393 int radeon_ms_dac1_mode_set(struct radeon_ms_output *output,
394 struct drm_display_mode *mode,
395 struct drm_display_mode *adjusted_mode);
396 void radeon_ms_dac1_restore(struct radeon_ms_output *output,
397 struct radeon_state *state);
398 void radeon_ms_dac1_save(struct radeon_ms_output *output,
399 struct radeon_state *state);
400 int radeon_ms_dac2_initialize(struct radeon_ms_output *output);
401 enum drm_output_status radeon_ms_dac2_detect(struct radeon_ms_output *output);
402 void radeon_ms_dac2_dpms(struct radeon_ms_output *output, int mode);
403 int radeon_ms_dac2_get_modes(struct radeon_ms_output *output);
404 bool radeon_ms_dac2_mode_fixup(struct radeon_ms_output *output,
405 struct drm_display_mode *mode,
406 struct drm_display_mode *adjusted_mode);
407 int radeon_ms_dac2_mode_set(struct radeon_ms_output *output,
408 struct drm_display_mode *mode,
409 struct drm_display_mode *adjusted_mode);
410 void radeon_ms_dac2_restore(struct radeon_ms_output *output,
411 struct radeon_state *state);
412 void radeon_ms_dac2_save(struct radeon_ms_output *output,
413 struct radeon_state *state);
415 /* radeon_ms_drm.c */
416 int radeon_ms_driver_dma_ioctl(struct drm_device *dev, void *data,
417 struct drm_file *file_priv);
418 void radeon_ms_driver_lastclose(struct drm_device * dev);
419 int radeon_ms_driver_load(struct drm_device *dev, unsigned long flags);
420 int radeon_ms_driver_open(struct drm_device * dev, struct drm_file *file_priv);
421 int radeon_ms_driver_unload(struct drm_device *dev);
423 /* radeon_ms_exec.c */
424 int radeon_ms_execbuffer(struct drm_device *dev, void *data,
425 struct drm_file *file_priv);
427 /* radeon_ms_family.c */
428 int radeon_ms_family_init(struct drm_device *dev);
430 /* radeon_ms_fence.c */
431 void r3xx_fence_handler(struct drm_device * dev);
432 int r3xx_fence_types(struct drm_buffer_object *bo,
433 uint32_t * class, uint32_t * type);
436 int radeonfb_probe(struct drm_device *dev, struct drm_crtc *crtc);
437 int radeonfb_remove(struct drm_device *dev, struct drm_crtc *crtc);
439 /* radeon_ms_gpu.c */
440 int radeon_ms_gpu_initialize(struct drm_device *dev);
441 void radeon_ms_gpu_dpms(struct drm_device *dev);
442 void radeon_ms_gpu_flush(struct drm_device *dev);
443 void radeon_ms_gpu_restore(struct drm_device *dev, struct radeon_state *state);
444 void radeon_ms_gpu_save(struct drm_device *dev, struct radeon_state *state);
445 int radeon_ms_wait_for_idle(struct drm_device *dev);
447 /* radeon_ms_i2c.c */
448 void radeon_ms_i2c_destroy(struct radeon_ms_i2c *i2c);
449 struct radeon_ms_i2c *radeon_ms_i2c_create(struct drm_device *dev,
453 /* radeon_ms_irq.c */
454 void radeon_ms_irq_emit(struct drm_device *dev);
455 irqreturn_t radeon_ms_irq_handler(DRM_IRQ_ARGS);
456 void radeon_ms_irq_preinstall(struct drm_device * dev);
457 int radeon_ms_irq_postinstall(struct drm_device * dev);
458 int radeon_ms_irq_init(struct drm_device *dev);
459 void radeon_ms_irq_restore(struct drm_device *dev, struct radeon_state *state);
460 void radeon_ms_irq_save(struct drm_device *dev, struct radeon_state *state);
461 void radeon_ms_irq_uninstall(struct drm_device * dev);
463 /* radeon_ms_output.c */
464 void radeon_ms_connectors_destroy(struct drm_device *dev);
465 int radeon_ms_connectors_from_properties(struct drm_device *dev);
466 int radeon_ms_connectors_from_rom(struct drm_device *dev);
467 void radeon_ms_outputs_destroy(struct drm_device *dev);
468 int radeon_ms_outputs_from_properties(struct drm_device *dev);
469 int radeon_ms_outputs_from_rom(struct drm_device *dev);
470 void radeon_ms_outputs_restore(struct drm_device *dev,
471 struct radeon_state *state);
472 void radeon_ms_outputs_save(struct drm_device *dev, struct radeon_state *state);
474 /* radeon_ms_properties.c */
475 int radeon_ms_properties_init(struct drm_device *dev);
477 /* radeon_ms_rom.c */
478 int radeon_ms_rom_get_properties(struct drm_device *dev);
479 int radeon_ms_rom_init(struct drm_device *dev);
481 /* radeon_ms_state.c */
482 void radeon_ms_state_save(struct drm_device *dev, struct radeon_state *state);
483 void radeon_ms_state_restore(struct drm_device *dev,
484 struct radeon_state *state);
487 /* packect stuff **************************************************************/
488 #define RADEON_CP_PACKET0 0x00000000
489 #define CP_PACKET0(reg, n) \
490 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
491 #define CP_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00
492 # define GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
493 # define GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
494 # define GMC_BRUSH_NONE (15 << 4)
495 # define GMC_SRC_DATATYPE_COLOR (3 << 12)
496 # define ROP3_S 0x00cc0000
497 # define DP_SRC_SOURCE_MEMORY (2 << 24)
498 # define GMC_CLR_CMP_CNTL_DIS (1 << 28)
499 # define GMC_WR_MSK_DIS (1 << 30)
501 /* helper macro & functions ***************************************************/
502 #define REG_S(rn, bn, v) (((v) << rn##__##bn##__SHIFT) & rn##__##bn##__MASK)
503 #define REG_G(rn, bn, v) (((v) & rn##__##bn##__MASK) >> rn##__##bn##__SHIFT)
504 #define MMIO_R(rid) mmio_read(dev_priv, rid)
505 #define MMIO_W(rid, v) mmio_write(dev_priv, rid, v)
506 #define PCIE_R(rid) pcie_read(dev_priv, rid)
507 #define PCIE_W(rid, v) pcie_write(dev_priv, rid, v)
508 #define PPLL_R(rid) pll_read(dev_priv, rid)
509 #define PPLL_W(rid, v) pll_write(dev_priv, rid, v)
511 static __inline__ uint32_t mmio_read(struct drm_radeon_private *dev_priv,
514 return DRM_READ32(&dev_priv->mmio, offset);
518 static __inline__ void mmio_write(struct drm_radeon_private *dev_priv,
519 uint32_t offset, uint32_t v)
521 DRM_WRITE32(&dev_priv->mmio, offset, v);
524 static __inline__ uint32_t pcie_read(struct drm_radeon_private *dev_priv,
527 MMIO_W(PCIE_INDEX, REG_S(PCIE_INDEX, PCIE_INDEX, offset));
528 return MMIO_R(PCIE_DATA);
531 static __inline__ void pcie_write(struct drm_radeon_private *dev_priv,
532 uint32_t offset, uint32_t v)
534 MMIO_W(PCIE_INDEX, REG_S(PCIE_INDEX, PCIE_INDEX, offset));
535 MMIO_W(PCIE_DATA, v);
538 static __inline__ void pll_index_errata(struct drm_radeon_private *dev_priv)
542 /* This workaround is necessary on rv200 and RS200 or PLL
543 * reads may return garbage (among others...)
545 if (dev_priv->properties.pll_dummy_reads) {
546 tmp = MMIO_R(CLOCK_CNTL_DATA);
547 tmp = MMIO_R(CRTC_GEN_CNTL);
549 /* This function is required to workaround a hardware bug in some (all?)
550 * revisions of the R300. This workaround should be called after every
551 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
552 * may not be correct.
554 if (dev_priv->properties.pll_r300_errata) {
555 tmp = save = MMIO_R(CLOCK_CNTL_INDEX);
556 tmp = tmp & ~CLOCK_CNTL_INDEX__PLL_ADDR__MASK;
557 tmp = tmp & ~CLOCK_CNTL_INDEX__PLL_WR_EN;
558 MMIO_W(CLOCK_CNTL_INDEX, tmp);
559 tmp = MMIO_R(CLOCK_CNTL_DATA);
560 MMIO_W(CLOCK_CNTL_INDEX, save);
564 static __inline__ void pll_data_errata(struct drm_radeon_private *dev_priv)
566 /* This workarounds is necessary on RV100, RS100 and RS200 chips
567 * or the chip could hang on a subsequent access
569 if (dev_priv->properties.pll_delay) {
570 /* we can't deal with posted writes here ... */
575 static __inline__ uint32_t pll_read(struct drm_radeon_private *dev_priv,
578 uint32_t clock_cntl_index = dev_priv->driver_state.clock_cntl_index;
581 clock_cntl_index &= ~CLOCK_CNTL_INDEX__PLL_ADDR__MASK;
582 clock_cntl_index |= REG_S(CLOCK_CNTL_INDEX, PLL_ADDR, offset);
583 MMIO_W(CLOCK_CNTL_INDEX, clock_cntl_index);
584 pll_index_errata(dev_priv);
585 data = MMIO_R(CLOCK_CNTL_DATA);
586 pll_data_errata(dev_priv);
590 static __inline__ void pll_write(struct drm_radeon_private *dev_priv,
591 uint32_t offset, uint32_t value)
593 uint32_t clock_cntl_index = dev_priv->driver_state.clock_cntl_index;
595 clock_cntl_index &= ~CLOCK_CNTL_INDEX__PLL_ADDR__MASK;
596 clock_cntl_index |= REG_S(CLOCK_CNTL_INDEX, PLL_ADDR, offset);
597 clock_cntl_index |= CLOCK_CNTL_INDEX__PLL_WR_EN;
598 MMIO_W(CLOCK_CNTL_INDEX, clock_cntl_index);
599 pll_index_errata(dev_priv);
600 MMIO_W(CLOCK_CNTL_DATA, value);
601 pll_data_errata(dev_priv);