shared-core/radeon_irq.c

   1 /* radeon_irq.c -- IRQ handling for radeon -*- linux-c -*- */
   2 /*
   3  * Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   4  *
   5  * The Weather Channel (TM) funded Tungsten Graphics to develop the
   6  * initial release of the Radeon 8500 driver under the XFree86 license.
   7  * This notice must be preserved.
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  24  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  25  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  26  * DEALINGS IN THE SOFTWARE.
  27  *
  28  * Authors:
  29  *    Keith Whitwell <keith@tungstengraphics.com>
  30  *    Michel D�zer <michel@daenzer.net>
  31  */
  32
  33 #include "drmP.h"
  34 #include "drm.h"
  35 #include "radeon_drm.h"
  36 #include "radeon_drv.h"
  37
  38 static void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state)
  39 {
  40         drm_radeon_private_t *dev_priv = dev->dev_private;
  41
  42         if (state)
  43                 dev_priv->irq_enable_reg |= mask;
  44         else
  45                 dev_priv->irq_enable_reg &= ~mask;
  46
  47         RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
  48 }
  49
  50 static void r500_vbl_irq_set_state(struct drm_device *dev, u32 mask, int state)
  51 {
  52         drm_radeon_private_t *dev_priv = dev->dev_private;
  53
  54         if (state)
  55                 dev_priv->r500_disp_irq_reg |= mask;
  56         else
  57                 dev_priv->r500_disp_irq_reg &= ~mask;
  58
  59         RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg);
  60 }
  61
  62 int radeon_enable_vblank(struct drm_device *dev, int crtc)
  63 {
  64         drm_radeon_private_t *dev_priv = dev->dev_private;
  65
  66         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) {
  67                 switch (crtc) {
  68                 case 0:
  69                         r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 1);
  70                         break;
  71                 case 1:
  72                         r500_vbl_irq_set_state(dev, R500_D2MODE_INT_MASK, 1);
  73                         break;
  74                 default:
  75                         DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
  76                                   crtc);
  77                         return EINVAL;
  78                 }
  79         } else {
  80                 switch (crtc) {
  81                 case 0:
  82                         radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 1);
  83                         break;
  84                 case 1:
  85                         radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 1);
  86                         break;
  87                 default:
  88                         DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
  89                                   crtc);
  90                         return EINVAL;
  91                 }
  92         }
  93
  94         return 0;
  95 }
  96
  97 void radeon_disable_vblank(struct drm_device *dev, int crtc)
  98 {
  99         drm_radeon_private_t *dev_priv = dev->dev_private;
 100
 101         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) {
 102                 switch (crtc) {
 103                 case 0:
 104                         r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 0);
 105                         break;
 106                 case 1:
 107                         r500_vbl_irq_set_state(dev, R500_D2MODE_INT_MASK, 0);
 108                         break;
 109                 default:
 110                         DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
 111                                   crtc);
 112                         break;
 113                 }
 114         } else {
 115                 switch (crtc) {
 116                 case 0:
 117                         radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 0);
 118                         break;
 119                 case 1:
 120                         radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 0);
 121                         break;
 122                 default:
 123                         DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
 124                                   crtc);
 125                         break;
 126                 }
 127         }
 128 }
 129
 130 static __inline__ u32 radeon_acknowledge_irqs(drm_radeon_private_t * dev_priv, u32 *r500_disp_int)
 131 {
 132         u32 irqs = RADEON_READ(RADEON_GEN_INT_STATUS);
 133         u32 irq_mask = RADEON_SW_INT_TEST;
 134
 135         *r500_disp_int = 0;
 136         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) {
 137                 /* vbl interrupts in a different place */
 138
 139                 if (irqs & R500_DISPLAY_INT_STATUS) {
 140                         /* if a display interrupt */
 141                         u32 disp_irq;
 142
 143                         disp_irq = RADEON_READ(R500_DISP_INTERRUPT_STATUS);
 144
 145                         *r500_disp_int = disp_irq;
 146                         if (disp_irq & R500_D1_VBLANK_INTERRUPT) {
 147                                 RADEON_WRITE(R500_D1MODE_VBLANK_STATUS, R500_VBLANK_ACK);
 148                         }
 149                         if (disp_irq & R500_D2_VBLANK_INTERRUPT) {
 150                                 RADEON_WRITE(R500_D2MODE_VBLANK_STATUS, R500_VBLANK_ACK);
 151                         }
 152                 }
 153                 irq_mask |= R500_DISPLAY_INT_STATUS;
 154         } else
 155                 irq_mask |= RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT;
 156
 157         irqs &= irq_mask;
 158
 159         if (irqs)
 160                 RADEON_WRITE(RADEON_GEN_INT_STATUS, irqs);
 161
 162         return irqs;
 163 }
 164
 165 /* Interrupts - Used for device synchronization and flushing in the
 166  * following circumstances:
 167  *
 168  * - Exclusive FB access with hw idle:
 169  *    - Wait for GUI Idle (?) interrupt, then do normal flush.
 170  *
 171  * - Frame throttling, NV_fence:
 172  *    - Drop marker irq's into command stream ahead of time.
 173  *    - Wait on irq's with lock *not held*
 174  *    - Check each for termination condition
 175  *
 176  * - Internally in cp_getbuffer, etc:
 177  *    - as above, but wait with lock held???
 178  *
 179  * NOTE: These functions are misleadingly named -- the irq's aren't
 180  * tied to dma at all, this is just a hangover from dri prehistory.
 181  */
 182
 183 irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS)
 184 {
 185         struct drm_device *dev = (struct drm_device *) arg;
 186         drm_radeon_private_t *dev_priv =
 187             (drm_radeon_private_t *) dev->dev_private;
 188         u32 stat;
 189         u32 r500_disp_int;
 190
 191         /* Only consider the bits we're interested in - others could be used
 192          * outside the DRM
 193          */
 194         stat = radeon_acknowledge_irqs(dev_priv, &r500_disp_int);
 195         if (!stat)
 196                 return IRQ_NONE;
 197
 198         stat &= dev_priv->irq_enable_reg;
 199
 200         /* SW interrupt */
 201         if (stat & RADEON_SW_INT_TEST) {
 202                 DRM_WAKEUP(&dev_priv->swi_queue);
 203                 radeon_fence_handler(dev);
 204         }
 205
 206         /* VBLANK interrupt */
 207         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) {
 208                 if (r500_disp_int & R500_D1_VBLANK_INTERRUPT)
 209                         drm_handle_vblank(dev, 0);
 210                 if (r500_disp_int & R500_D2_VBLANK_INTERRUPT)
 211                         drm_handle_vblank(dev, 1);
 212         } else {
 213                 if (stat & RADEON_CRTC_VBLANK_STAT)
 214                         drm_handle_vblank(dev, 0);
 215                 if (stat & RADEON_CRTC2_VBLANK_STAT)
 216                         drm_handle_vblank(dev, 1);
 217         }
 218         return IRQ_HANDLED;
 219 }
 220
 221 int radeon_emit_irq(struct drm_device * dev)
 222 {
 223         drm_radeon_private_t *dev_priv = dev->dev_private;
 224         unsigned int ret;
 225         RING_LOCALS;
 226
 227         ret = radeon_update_breadcrumb(dev);
 228
 229         BEGIN_RING(4);
 230         OUT_RING_REG(RADEON_LAST_SWI_REG, ret);
 231         OUT_RING_REG(RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE);
 232         ADVANCE_RING();
 233         COMMIT_RING();
 234
 235         return ret;
 236 }
 237
 238 static int radeon_wait_irq(struct drm_device * dev, int swi_nr)
 239 {
 240         drm_radeon_private_t *dev_priv =
 241             (drm_radeon_private_t *) dev->dev_private;
 242         int ret = 0;
 243
 244         if (READ_BREADCRUMB(dev_priv) >= swi_nr)
 245                 return 0;
 246
 247         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 248
 249         DRM_WAIT_ON(ret, dev_priv->swi_queue, 3 * DRM_HZ,
 250                     READ_BREADCRUMB(dev_priv) >= swi_nr);
 251
 252         return ret;
 253 }
 254
 255 u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc)
 256 {
 257         drm_radeon_private_t *dev_priv = dev->dev_private;
 258         u32 crtc_cnt_reg, crtc_status_reg;
 259
 260         if (!dev_priv) {
 261                 DRM_ERROR("called with no initialization\n");
 262                 return -EINVAL;
 263         }
 264
 265         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) {
 266                 if (crtc == 0) {
 267                         crtc_cnt_reg = R500_D1CRTC_FRAME_COUNT;
 268                         crtc_status_reg = R500_D1CRTC_STATUS;
 269                 } else if (crtc == 1) {
 270                         crtc_cnt_reg = R500_D2CRTC_FRAME_COUNT;
 271                         crtc_status_reg = R500_D2CRTC_STATUS;
 272                 } else
 273                         return -EINVAL;
 274                 return RADEON_READ(crtc_cnt_reg) + (RADEON_READ(crtc_status_reg) & 1);
 275
 276         } else {
 277                 if (crtc == 0) {
 278                         crtc_cnt_reg = RADEON_CRTC_CRNT_FRAME;
 279                         crtc_status_reg = RADEON_CRTC_STATUS;
 280                 } else if (crtc == 1) {
 281                         crtc_cnt_reg = RADEON_CRTC2_CRNT_FRAME;
 282                         crtc_status_reg = RADEON_CRTC2_STATUS;
 283                 } else {
 284                         return -EINVAL;
 285                 }
 286                 return RADEON_READ(crtc_cnt_reg) + (RADEON_READ(crtc_status_reg) & 1);
 287         }
 288 }
 289
 290 /* Needs the lock as it touches the ring.
 291  */
 292 int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv)
 293 {
 294         drm_radeon_private_t *dev_priv = dev->dev_private;
 295         drm_radeon_irq_emit_t *emit = data;
 296         int result;
 297
 298         LOCK_TEST_WITH_RETURN(dev, file_priv);
 299
 300         if (!dev_priv) {
 301                 DRM_ERROR("called with no initialization\n");
 302                 return -EINVAL;
 303         }
 304
 305         result = radeon_emit_irq(dev);
 306
 307         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
 308                 DRM_ERROR("copy_to_user\n");
 309                 return -EFAULT;
 310         }
 311
 312         return 0;
 313 }
 314
 315 /* Doesn't need the hardware lock.
 316  */
 317 int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv)
 318 {
 319         drm_radeon_private_t *dev_priv = dev->dev_private;
 320         drm_radeon_irq_wait_t *irqwait = data;
 321
 322         if (!dev_priv) {
 323                 DRM_ERROR("called with no initialization\n");
 324                 return -EINVAL;
 325         }
 326
 327         return radeon_wait_irq(dev, irqwait->irq_seq);
 328 }
 329
 330 /* drm_dma.h hooks
 331 */
 332 void radeon_driver_irq_preinstall(struct drm_device * dev)
 333 {
 334         drm_radeon_private_t *dev_priv =
 335             (drm_radeon_private_t *) dev->dev_private;
 336         u32 dummy;
 337
 338         /* Disable *all* interrupts */
 339         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690)
 340                 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
 341         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
 342
 343         /* Clear bits if they're already high */
 344         radeon_acknowledge_irqs(dev_priv, &dummy);
 345 }
 346
 347 int radeon_driver_irq_postinstall(struct drm_device * dev)
 348 {
 349         drm_radeon_private_t *dev_priv =
 350             (drm_radeon_private_t *) dev->dev_private;
 351         int ret;
 352
 353         DRM_INIT_WAITQUEUE(&dev_priv->swi_queue);
 354
 355         ret = drm_vblank_init(dev, 2);
 356         if (ret)
 357                 return ret;
 358
 359         dev->max_vblank_count = 0x001fffff;
 360
 361         radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
 362
 363         return 0;
 364 }
 365
 366 void radeon_driver_irq_uninstall(struct drm_device * dev)
 367 {
 368         drm_radeon_private_t *dev_priv =
 369             (drm_radeon_private_t *) dev->dev_private;
 370         if (!dev_priv)
 371                 return;
 372
 373         dev_priv->irq_enabled = 0;
 374
 375         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690)
 376                 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
 377         /* Disable *all* interrupts */
 378         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
 379 }
 380
 381
 382 int radeon_vblank_crtc_get(struct drm_device *dev)
 383 {
 384         drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
 385         u32 flag;
 386         u32 value;
 387
 388         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) {
 389                 flag = RADEON_READ(R500_DxMODE_INT_MASK);
 390                 value = 0;
 391                 if (flag & R500_D1MODE_INT_MASK)
 392                         value |= DRM_RADEON_VBLANK_CRTC1;
 393
 394                 if (flag & R500_D2MODE_INT_MASK)
 395                         value |= DRM_RADEON_VBLANK_CRTC2;
 396         } else {
 397                 flag = RADEON_READ(RADEON_GEN_INT_CNTL);
 398                 value = 0;
 399                 if (flag & RADEON_CRTC_VBLANK_MASK)
 400                         value |= DRM_RADEON_VBLANK_CRTC1;
 401
 402                 if (flag & RADEON_CRTC2_VBLANK_MASK)
 403                         value |= DRM_RADEON_VBLANK_CRTC2;
 404         }
 405         return value;
 406 }
 407
 408 int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value)
 409 {
 410         drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
 411         if (value & ~(DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) {
 412                 DRM_ERROR("called with invalid crtc 0x%x\n", (unsigned int)value);
 413                 return -EINVAL;
 414         }
 415         dev_priv->vblank_crtc = (unsigned int)value;
 416         return 0;
 417 }