1 /* radeon_irq.c -- IRQ handling for radeon -*- linux-c -*- */
3 * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
5 * The Weather Channel (TM) funded Tungsten Graphics to develop the
6 * initial release of the Radeon 8500 driver under the XFree86 license.
7 * This notice must be preserved.
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
29 * Keith Whitwell <keith@tungstengraphics.com>
30 * Michel D�zer <michel@daenzer.net>
35 #include "radeon_drm.h"
36 #include "radeon_drv.h"
38 static void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state)
40 drm_radeon_private_t *dev_priv = dev->dev_private;
43 dev_priv->irq_enable_reg |= mask;
45 dev_priv->irq_enable_reg &= ~mask;
47 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
50 static void r500_vbl_irq_set_state(struct drm_device *dev, u32 mask, int state)
52 drm_radeon_private_t *dev_priv = dev->dev_private;
55 dev_priv->r500_disp_irq_reg |= mask;
57 dev_priv->r500_disp_irq_reg &= ~mask;
59 RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg);
62 int radeon_enable_vblank(struct drm_device *dev, int crtc)
64 drm_radeon_private_t *dev_priv = dev->dev_private;
66 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) {
69 r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 1);
72 r500_vbl_irq_set_state(dev, R500_D2MODE_INT_MASK, 1);
75 DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
82 radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 1);
85 radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 1);
88 DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
97 void radeon_disable_vblank(struct drm_device *dev, int crtc)
99 drm_radeon_private_t *dev_priv = dev->dev_private;
101 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) {
104 r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 0);
107 r500_vbl_irq_set_state(dev, R500_D2MODE_INT_MASK, 0);
110 DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
117 radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 0);
120 radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 0);
123 DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
130 static __inline__ u32 radeon_acknowledge_irqs(drm_radeon_private_t * dev_priv, u32 *r500_disp_int)
132 u32 irqs = RADEON_READ(RADEON_GEN_INT_STATUS);
133 u32 irq_mask = RADEON_SW_INT_TEST;
136 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) {
137 /* vbl interrupts in a different place */
139 if (irqs & R500_DISPLAY_INT_STATUS) {
140 /* if a display interrupt */
143 disp_irq = RADEON_READ(R500_DISP_INTERRUPT_STATUS);
145 *r500_disp_int = disp_irq;
146 if (disp_irq & R500_D1_VBLANK_INTERRUPT) {
147 RADEON_WRITE(R500_D1MODE_VBLANK_STATUS, R500_VBLANK_ACK);
149 if (disp_irq & R500_D2_VBLANK_INTERRUPT) {
150 RADEON_WRITE(R500_D2MODE_VBLANK_STATUS, R500_VBLANK_ACK);
153 irq_mask |= R500_DISPLAY_INT_STATUS;
155 irq_mask |= RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT;
160 RADEON_WRITE(RADEON_GEN_INT_STATUS, irqs);
165 /* Interrupts - Used for device synchronization and flushing in the
166 * following circumstances:
168 * - Exclusive FB access with hw idle:
169 * - Wait for GUI Idle (?) interrupt, then do normal flush.
171 * - Frame throttling, NV_fence:
172 * - Drop marker irq's into command stream ahead of time.
173 * - Wait on irq's with lock *not held*
174 * - Check each for termination condition
176 * - Internally in cp_getbuffer, etc:
177 * - as above, but wait with lock held???
179 * NOTE: These functions are misleadingly named -- the irq's aren't
180 * tied to dma at all, this is just a hangover from dri prehistory.
183 irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS)
185 struct drm_device *dev = (struct drm_device *) arg;
186 drm_radeon_private_t *dev_priv =
187 (drm_radeon_private_t *) dev->dev_private;
191 /* Only consider the bits we're interested in - others could be used
194 stat = radeon_acknowledge_irqs(dev_priv, &r500_disp_int);
198 stat &= dev_priv->irq_enable_reg;
201 if (stat & RADEON_SW_INT_TEST) {
202 DRM_WAKEUP(&dev_priv->swi_queue);
203 radeon_fence_handler(dev);
206 /* VBLANK interrupt */
207 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) {
208 if (r500_disp_int & R500_D1_VBLANK_INTERRUPT)
209 drm_handle_vblank(dev, 0);
210 if (r500_disp_int & R500_D2_VBLANK_INTERRUPT)
211 drm_handle_vblank(dev, 1);
213 if (stat & RADEON_CRTC_VBLANK_STAT)
214 drm_handle_vblank(dev, 0);
215 if (stat & RADEON_CRTC2_VBLANK_STAT)
216 drm_handle_vblank(dev, 1);
221 int radeon_emit_irq(struct drm_device * dev)
223 drm_radeon_private_t *dev_priv = dev->dev_private;
227 ret = radeon_update_breadcrumb(dev);
230 OUT_RING_REG(RADEON_LAST_SWI_REG, ret);
231 OUT_RING_REG(RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE);
238 static int radeon_wait_irq(struct drm_device * dev, int swi_nr)
240 drm_radeon_private_t *dev_priv =
241 (drm_radeon_private_t *) dev->dev_private;
244 if (READ_BREADCRUMB(dev_priv) >= swi_nr)
247 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
249 DRM_WAIT_ON(ret, dev_priv->swi_queue, 3 * DRM_HZ,
250 READ_BREADCRUMB(dev_priv) >= swi_nr);
255 u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc)
257 drm_radeon_private_t *dev_priv = dev->dev_private;
258 u32 crtc_cnt_reg, crtc_status_reg;
261 DRM_ERROR("called with no initialization\n");
265 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) {
267 crtc_cnt_reg = R500_D1CRTC_FRAME_COUNT;
268 crtc_status_reg = R500_D1CRTC_STATUS;
269 } else if (crtc == 1) {
270 crtc_cnt_reg = R500_D2CRTC_FRAME_COUNT;
271 crtc_status_reg = R500_D2CRTC_STATUS;
274 return RADEON_READ(crtc_cnt_reg) + (RADEON_READ(crtc_status_reg) & 1);
278 crtc_cnt_reg = RADEON_CRTC_CRNT_FRAME;
279 crtc_status_reg = RADEON_CRTC_STATUS;
280 } else if (crtc == 1) {
281 crtc_cnt_reg = RADEON_CRTC2_CRNT_FRAME;
282 crtc_status_reg = RADEON_CRTC2_STATUS;
286 return RADEON_READ(crtc_cnt_reg) + (RADEON_READ(crtc_status_reg) & 1);
290 /* Needs the lock as it touches the ring.
292 int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv)
294 drm_radeon_private_t *dev_priv = dev->dev_private;
295 drm_radeon_irq_emit_t *emit = data;
298 LOCK_TEST_WITH_RETURN(dev, file_priv);
301 DRM_ERROR("called with no initialization\n");
305 result = radeon_emit_irq(dev);
307 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
308 DRM_ERROR("copy_to_user\n");
315 /* Doesn't need the hardware lock.
317 int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv)
319 drm_radeon_private_t *dev_priv = dev->dev_private;
320 drm_radeon_irq_wait_t *irqwait = data;
323 DRM_ERROR("called with no initialization\n");
327 return radeon_wait_irq(dev, irqwait->irq_seq);
332 void radeon_driver_irq_preinstall(struct drm_device * dev)
334 drm_radeon_private_t *dev_priv =
335 (drm_radeon_private_t *) dev->dev_private;
338 /* Disable *all* interrupts */
339 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690)
340 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
341 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
343 /* Clear bits if they're already high */
344 radeon_acknowledge_irqs(dev_priv, &dummy);
347 int radeon_driver_irq_postinstall(struct drm_device * dev)
349 drm_radeon_private_t *dev_priv =
350 (drm_radeon_private_t *) dev->dev_private;
353 DRM_INIT_WAITQUEUE(&dev_priv->swi_queue);
355 ret = drm_vblank_init(dev, 2);
359 dev->max_vblank_count = 0x001fffff;
361 radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
366 void radeon_driver_irq_uninstall(struct drm_device * dev)
368 drm_radeon_private_t *dev_priv =
369 (drm_radeon_private_t *) dev->dev_private;
373 dev_priv->irq_enabled = 0;
375 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690)
376 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
377 /* Disable *all* interrupts */
378 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
382 int radeon_vblank_crtc_get(struct drm_device *dev)
384 drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
388 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) {
389 flag = RADEON_READ(R500_DxMODE_INT_MASK);
391 if (flag & R500_D1MODE_INT_MASK)
392 value |= DRM_RADEON_VBLANK_CRTC1;
394 if (flag & R500_D2MODE_INT_MASK)
395 value |= DRM_RADEON_VBLANK_CRTC2;
397 flag = RADEON_READ(RADEON_GEN_INT_CNTL);
399 if (flag & RADEON_CRTC_VBLANK_MASK)
400 value |= DRM_RADEON_VBLANK_CRTC1;
402 if (flag & RADEON_CRTC2_VBLANK_MASK)
403 value |= DRM_RADEON_VBLANK_CRTC2;
408 int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value)
410 drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
411 if (value & ~(DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) {
412 DRM_ERROR("called with invalid crtc 0x%x\n", (unsigned int)value);
415 dev_priv->vblank_crtc = (unsigned int)value;