1 /* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
31 #ifndef __RADEON_DRV_H__
32 #define __RADEON_DRV_H__
34 /* General customization:
37 #define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."
39 #define DRIVER_NAME "radeon"
40 #define DRIVER_DESC "ATI Radeon"
41 #define DRIVER_DATE "20060524"
46 * 1.2 - Add vertex2 ioctl (keith)
47 * - Add stencil capability to clear ioctl (gareth, keith)
48 * - Increase MAX_TEXTURE_LEVELS (brian)
49 * 1.3 - Add cmdbuf ioctl (keith)
50 * - Add support for new radeon packets (keith)
51 * - Add getparam ioctl (keith)
52 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
53 * 1.4 - Add scratch registers to get_param ioctl.
54 * 1.5 - Add r200 packets to cmdbuf ioctl
55 * - Add r200 function to init ioctl
56 * - Add 'scalar2' instruction to cmdbuf
57 * 1.6 - Add static GART memory manager
58 * Add irq handler (won't be turned on unless X server knows to)
59 * Add irq ioctls and irq_active getparam.
60 * Add wait command for cmdbuf ioctl
61 * Add GART offset query for getparam
62 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
63 * and R200_PP_CUBIC_OFFSET_F1_[0..5].
64 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
65 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian)
66 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
67 * Add 'GET' queries for starting additional clients on different VT's.
68 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
69 * Add texture rectangle support for r100.
70 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
71 * clients use to tell the DRM where they think the framebuffer is
72 * located in the card's address space
73 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
74 * and GL_EXT_blend_[func|equation]_separate on r200
75 * 1.12- Add R300 CP microcode support - this just loads the CP on r300
76 * (No 3D support yet - just microcode loading).
77 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
78 * - Add hyperz support, add hyperz flags to clear ioctl.
79 * 1.14- Add support for color tiling
80 * - Add R100/R200 surface allocation/free support
81 * 1.15- Add support for texture micro tiling
82 * - Add support for r100 cube maps
83 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear
84 * texture filtering on r200
85 * 1.17- Add initial support for R300 (3D).
86 * 1.18- Add support for GL_ATI_fragment_shader, new packets
87 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces
88 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR
89 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6)
90 * 1.19- Add support for gart table in FB memory and PCIE r300
91 * 1.20- Add support for r300 texrect
92 * 1.21- Add support for card type getparam
93 * 1.22- Add support for texture cache flushes (R300_TX_CNTL)
94 * 1.23- Add new radeon memory map work from benh
95 * 1.24- Add general-purpose packet for manipulating scratch registers (r300)
96 * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL,
100 #define DRIVER_MAJOR 1
101 #define DRIVER_MINOR 25
102 #define DRIVER_PATCHLEVEL 0
105 * Radeon chip families
127 enum radeon_cp_microcode_version {
136 enum radeon_chip_flags {
137 CHIP_FAMILY_MASK = 0x0000ffffUL,
138 CHIP_FLAGS_MASK = 0xffff0000UL,
139 CHIP_IS_MOBILITY = 0x00010000UL,
140 CHIP_IS_IGP = 0x00020000UL,
141 CHIP_SINGLE_CRTC = 0x00040000UL,
142 CHIP_IS_AGP = 0x00080000UL,
143 CHIP_HAS_HIERZ = 0x00100000UL,
144 CHIP_IS_PCIE = 0x00200000UL,
145 CHIP_NEW_MEMMAP = 0x00400000UL,
148 #define GET_RING_HEAD(dev_priv) (dev_priv->writeback_works ? \
149 DRM_READ32( (dev_priv)->ring_rptr, 0 ) : RADEON_READ(RADEON_CP_RB_RPTR))
150 #define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) )
152 typedef struct drm_radeon_freelist {
155 struct drm_radeon_freelist *next;
156 struct drm_radeon_freelist *prev;
157 } drm_radeon_freelist_t;
159 typedef struct drm_radeon_ring_buffer {
170 } drm_radeon_ring_buffer_t;
172 typedef struct drm_radeon_depth_clear_t {
174 u32 rb3d_zstencilcntl;
176 } drm_radeon_depth_clear_t;
178 struct drm_radeon_driver_file_fields {
179 int64_t radeon_fb_delta;
183 struct mem_block *next;
184 struct mem_block *prev;
187 DRMFILE filp; /* 0: free, -1: heap, other: real files */
190 struct radeon_surface {
197 struct radeon_virt_surface {
205 typedef struct drm_radeon_private {
207 drm_radeon_ring_buffer_t ring;
208 drm_radeon_sarea_t *sarea_priv;
216 unsigned long gart_buffers_offset;
221 drm_radeon_freelist_t *head;
222 drm_radeon_freelist_t *tail;
224 volatile u32 *scratch;
229 int microcode_version;
233 int freelist_timeouts;
236 int last_frame_reads;
237 int last_clear_reads;
247 unsigned int front_offset;
248 unsigned int front_pitch;
249 unsigned int back_offset;
250 unsigned int back_pitch;
253 unsigned int depth_offset;
254 unsigned int depth_pitch;
256 u32 front_pitch_offset;
257 u32 back_pitch_offset;
258 u32 depth_pitch_offset;
260 drm_radeon_depth_clear_t depth_clear;
262 unsigned long ring_offset;
263 unsigned long ring_rptr_offset;
264 unsigned long buffers_offset;
265 unsigned long gart_textures_offset;
267 drm_local_map_t *sarea;
268 drm_local_map_t *mmio;
269 drm_local_map_t *cp_ring;
270 drm_local_map_t *ring_rptr;
271 drm_local_map_t *gart_textures;
273 struct mem_block *gart_heap;
274 struct mem_block *fb_heap;
277 wait_queue_head_t swi_queue;
278 atomic_t swi_emitted;
280 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
281 struct radeon_virt_surface virt_surfaces[2*RADEON_MAX_SURFACES];
283 unsigned long pcigart_offset;
284 drm_ati_pcigart_info gart_info;
288 /* starting from here on, data is preserved accross an open */
289 uint32_t flags; /* see radeon_chip_flags */
291 } drm_radeon_private_t;
293 typedef struct drm_radeon_buf_priv {
295 } drm_radeon_buf_priv_t;
297 typedef struct drm_radeon_kcmd_buffer {
301 drm_clip_rect_t __user *boxes;
302 } drm_radeon_kcmd_buffer_t;
304 extern int radeon_no_wb;
305 extern drm_ioctl_desc_t radeon_ioctls[];
306 extern int radeon_max_ioctl;
309 extern int radeon_cp_init(DRM_IOCTL_ARGS);
310 extern int radeon_cp_start(DRM_IOCTL_ARGS);
311 extern int radeon_cp_stop(DRM_IOCTL_ARGS);
312 extern int radeon_cp_reset(DRM_IOCTL_ARGS);
313 extern int radeon_cp_idle(DRM_IOCTL_ARGS);
314 extern int radeon_cp_resume(DRM_IOCTL_ARGS);
315 extern int radeon_engine_reset(DRM_IOCTL_ARGS);
316 extern int radeon_fullscreen(DRM_IOCTL_ARGS);
317 extern int radeon_cp_buffers(DRM_IOCTL_ARGS);
319 extern void radeon_freelist_reset(drm_device_t * dev);
320 extern drm_buf_t *radeon_freelist_get(drm_device_t * dev);
322 extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
324 extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv);
326 extern int radeon_mem_alloc(DRM_IOCTL_ARGS);
327 extern int radeon_mem_free(DRM_IOCTL_ARGS);
328 extern int radeon_mem_init_heap(DRM_IOCTL_ARGS);
329 extern void radeon_mem_takedown(struct mem_block **heap);
330 extern void radeon_mem_release(DRMFILE filp, struct mem_block *heap);
333 extern int radeon_irq_emit(DRM_IOCTL_ARGS);
334 extern int radeon_irq_wait(DRM_IOCTL_ARGS);
336 extern void radeon_do_release(drm_device_t * dev);
337 extern int radeon_driver_vblank_wait(drm_device_t * dev,
338 unsigned int *sequence);
339 extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
340 extern void radeon_driver_irq_preinstall(drm_device_t * dev);
341 extern void radeon_driver_irq_postinstall(drm_device_t * dev);
342 extern void radeon_driver_irq_uninstall(drm_device_t * dev);
344 extern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
345 extern int radeon_driver_unload(struct drm_device *dev);
346 extern int radeon_driver_firstopen(struct drm_device *dev);
347 extern void radeon_driver_preclose(drm_device_t * dev, DRMFILE filp);
348 extern void radeon_driver_postclose(drm_device_t * dev, drm_file_t * filp);
349 extern void radeon_driver_lastclose(drm_device_t * dev);
350 extern int radeon_driver_open(drm_device_t * dev, drm_file_t * filp_priv);
351 extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
355 extern void r300_init_reg_flags(void);
357 extern int r300_do_cp_cmdbuf(drm_device_t *dev, DRMFILE filp,
358 drm_file_t* filp_priv,
359 drm_radeon_kcmd_buffer_t* cmdbuf);
361 /* Flags for stats.boxes
363 #define RADEON_BOX_DMA_IDLE 0x1
364 #define RADEON_BOX_RING_FULL 0x2
365 #define RADEON_BOX_FLIP 0x4
366 #define RADEON_BOX_WAIT_IDLE 0x8
367 #define RADEON_BOX_TEXTURE_LOAD 0x10
369 /* Register definitions, register access macros and drmAddMap constants
370 * for Radeon kernel driver.
372 #define RADEON_AGP_COMMAND 0x0f60
373 #define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
374 # define RADEON_AGP_ENABLE (1<<8)
375 #define RADEON_AUX_SCISSOR_CNTL 0x26f0
376 # define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
377 # define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
378 # define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
379 # define RADEON_SCISSOR_0_ENABLE (1 << 28)
380 # define RADEON_SCISSOR_1_ENABLE (1 << 29)
381 # define RADEON_SCISSOR_2_ENABLE (1 << 30)
383 #define RADEON_BUS_CNTL 0x0030
384 # define RADEON_BUS_MASTER_DIS (1 << 6)
386 #define RADEON_CLOCK_CNTL_DATA 0x000c
387 # define RADEON_PLL_WR_EN (1 << 7)
388 #define RADEON_CLOCK_CNTL_INDEX 0x0008
389 #define RADEON_CONFIG_APER_SIZE 0x0108
390 #define RADEON_CONFIG_MEMSIZE 0x00f8
391 #define RADEON_CRTC_OFFSET 0x0224
392 #define RADEON_CRTC_OFFSET_CNTL 0x0228
393 # define RADEON_CRTC_TILE_EN (1 << 15)
394 # define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
395 #define RADEON_CRTC2_OFFSET 0x0324
396 #define RADEON_CRTC2_OFFSET_CNTL 0x0328
398 #define RADEON_PCIE_INDEX 0x0030
399 #define RADEON_PCIE_DATA 0x0034
400 #define RADEON_PCIE_TX_GART_CNTL 0x10
401 # define RADEON_PCIE_TX_GART_EN (1 << 0)
402 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1)
403 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1<<1)
404 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3<<1)
405 # define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0<<3)
406 # define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1<<3)
407 # define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1<<5)
408 # define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1<<8)
409 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
410 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
411 #define RADEON_PCIE_TX_GART_BASE 0x13
412 #define RADEON_PCIE_TX_GART_START_LO 0x14
413 #define RADEON_PCIE_TX_GART_START_HI 0x15
414 #define RADEON_PCIE_TX_GART_END_LO 0x16
415 #define RADEON_PCIE_TX_GART_END_HI 0x17
417 #define RADEON_MPP_TB_CONFIG 0x01c0
418 #define RADEON_MEM_CNTL 0x0140
419 #define RADEON_MEM_SDRAM_MODE_REG 0x0158
420 #define RADEON_AGP_BASE 0x0170
422 #define RADEON_RB3D_COLOROFFSET 0x1c40
423 #define RADEON_RB3D_COLORPITCH 0x1c48
425 #define RADEON_DP_GUI_MASTER_CNTL 0x146c
426 # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
427 # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
428 # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
429 # define RADEON_GMC_BRUSH_NONE (15 << 4)
430 # define RADEON_GMC_DST_16BPP (4 << 8)
431 # define RADEON_GMC_DST_24BPP (5 << 8)
432 # define RADEON_GMC_DST_32BPP (6 << 8)
433 # define RADEON_GMC_DST_DATATYPE_SHIFT 8
434 # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
435 # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
436 # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
437 # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
438 # define RADEON_GMC_WR_MSK_DIS (1 << 30)
439 # define RADEON_ROP3_S 0x00cc0000
440 # define RADEON_ROP3_P 0x00f00000
441 #define RADEON_DP_WRITE_MASK 0x16cc
442 #define RADEON_DST_PITCH_OFFSET 0x142c
443 #define RADEON_DST_PITCH_OFFSET_C 0x1c80
444 # define RADEON_DST_TILE_LINEAR (0 << 30)
445 # define RADEON_DST_TILE_MACRO (1 << 30)
446 # define RADEON_DST_TILE_MICRO (2 << 30)
447 # define RADEON_DST_TILE_BOTH (3 << 30)
449 #define RADEON_SCRATCH_REG0 0x15e0
450 #define RADEON_SCRATCH_REG1 0x15e4
451 #define RADEON_SCRATCH_REG2 0x15e8
452 #define RADEON_SCRATCH_REG3 0x15ec
453 #define RADEON_SCRATCH_REG4 0x15f0
454 #define RADEON_SCRATCH_REG5 0x15f4
455 #define RADEON_SCRATCH_UMSK 0x0770
456 #define RADEON_SCRATCH_ADDR 0x0774
458 #define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
460 #define GET_SCRATCH( x ) (dev_priv->writeback_works \
461 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \
462 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) )
464 #define RADEON_GEN_INT_CNTL 0x0040
465 # define RADEON_CRTC_VBLANK_MASK (1 << 0)
466 # define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
467 # define RADEON_SW_INT_ENABLE (1 << 25)
469 #define RADEON_GEN_INT_STATUS 0x0044
470 # define RADEON_CRTC_VBLANK_STAT (1 << 0)
471 # define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
472 # define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
473 # define RADEON_SW_INT_TEST (1 << 25)
474 # define RADEON_SW_INT_TEST_ACK (1 << 25)
475 # define RADEON_SW_INT_FIRE (1 << 26)
477 #define RADEON_HOST_PATH_CNTL 0x0130
478 # define RADEON_HDP_SOFT_RESET (1 << 26)
479 # define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
480 # define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
482 #define RADEON_ISYNC_CNTL 0x1724
483 # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
484 # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
485 # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
486 # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
487 # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
488 # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
490 #define RADEON_RBBM_GUICNTL 0x172c
491 # define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
492 # define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
493 # define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
494 # define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
496 #define RADEON_MC_AGP_LOCATION 0x014c
497 #define RADEON_MC_FB_LOCATION 0x0148
498 #define RADEON_MCLK_CNTL 0x0012
499 # define RADEON_FORCEON_MCLKA (1 << 16)
500 # define RADEON_FORCEON_MCLKB (1 << 17)
501 # define RADEON_FORCEON_YCLKA (1 << 18)
502 # define RADEON_FORCEON_YCLKB (1 << 19)
503 # define RADEON_FORCEON_MC (1 << 20)
504 # define RADEON_FORCEON_AIC (1 << 21)
506 #define RADEON_PP_BORDER_COLOR_0 0x1d40
507 #define RADEON_PP_BORDER_COLOR_1 0x1d44
508 #define RADEON_PP_BORDER_COLOR_2 0x1d48
509 #define RADEON_PP_CNTL 0x1c38
510 # define RADEON_SCISSOR_ENABLE (1 << 1)
511 #define RADEON_PP_LUM_MATRIX 0x1d00
512 #define RADEON_PP_MISC 0x1c14
513 #define RADEON_PP_ROT_MATRIX_0 0x1d58
514 #define RADEON_PP_TXFILTER_0 0x1c54
515 #define RADEON_PP_TXOFFSET_0 0x1c5c
516 #define RADEON_PP_TXFILTER_1 0x1c6c
517 #define RADEON_PP_TXFILTER_2 0x1c84
519 #define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
520 # define RADEON_RB2D_DC_FLUSH (3 << 0)
521 # define RADEON_RB2D_DC_FREE (3 << 2)
522 # define RADEON_RB2D_DC_FLUSH_ALL 0xf
523 # define RADEON_RB2D_DC_BUSY (1 << 31)
524 #define RADEON_RB3D_CNTL 0x1c3c
525 # define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
526 # define RADEON_PLANE_MASK_ENABLE (1 << 1)
527 # define RADEON_DITHER_ENABLE (1 << 2)
528 # define RADEON_ROUND_ENABLE (1 << 3)
529 # define RADEON_SCALE_DITHER_ENABLE (1 << 4)
530 # define RADEON_DITHER_INIT (1 << 5)
531 # define RADEON_ROP_ENABLE (1 << 6)
532 # define RADEON_STENCIL_ENABLE (1 << 7)
533 # define RADEON_Z_ENABLE (1 << 8)
534 # define RADEON_ZBLOCK16 (1 << 15)
535 #define RADEON_RB3D_DEPTHOFFSET 0x1c24
536 #define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
537 #define RADEON_RB3D_DEPTHPITCH 0x1c28
538 #define RADEON_RB3D_PLANEMASK 0x1d84
539 #define RADEON_RB3D_STENCILREFMASK 0x1d7c
540 #define RADEON_RB3D_ZCACHE_MODE 0x3250
541 #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
542 # define RADEON_RB3D_ZC_FLUSH (1 << 0)
543 # define RADEON_RB3D_ZC_FREE (1 << 2)
544 # define RADEON_RB3D_ZC_FLUSH_ALL 0x5
545 # define RADEON_RB3D_ZC_BUSY (1 << 31)
546 #define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c
547 # define RADEON_RB3D_DC_FLUSH (3 << 0)
548 # define RADEON_RB3D_DC_FREE (3 << 2)
549 # define RADEON_RB3D_DC_FLUSH_ALL 0xf
550 # define RADEON_RB3D_DC_BUSY (1 << 31)
551 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
552 # define RADEON_Z_TEST_MASK (7 << 4)
553 # define RADEON_Z_TEST_ALWAYS (7 << 4)
554 # define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
555 # define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
556 # define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
557 # define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
558 # define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
559 # define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
560 # define RADEON_FORCE_Z_DIRTY (1 << 29)
561 # define RADEON_Z_WRITE_ENABLE (1 << 30)
562 # define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
563 #define RADEON_RBBM_SOFT_RESET 0x00f0
564 # define RADEON_SOFT_RESET_CP (1 << 0)
565 # define RADEON_SOFT_RESET_HI (1 << 1)
566 # define RADEON_SOFT_RESET_SE (1 << 2)
567 # define RADEON_SOFT_RESET_RE (1 << 3)
568 # define RADEON_SOFT_RESET_PP (1 << 4)
569 # define RADEON_SOFT_RESET_E2 (1 << 5)
570 # define RADEON_SOFT_RESET_RB (1 << 6)
571 # define RADEON_SOFT_RESET_HDP (1 << 7)
572 #define RADEON_RBBM_STATUS 0x0e40
573 # define RADEON_RBBM_FIFOCNT_MASK 0x007f
574 # define RADEON_RBBM_ACTIVE (1 << 31)
575 #define RADEON_RE_LINE_PATTERN 0x1cd0
576 #define RADEON_RE_MISC 0x26c4
577 #define RADEON_RE_TOP_LEFT 0x26c0
578 #define RADEON_RE_WIDTH_HEIGHT 0x1c44
579 #define RADEON_RE_STIPPLE_ADDR 0x1cc8
580 #define RADEON_RE_STIPPLE_DATA 0x1ccc
582 #define RADEON_SCISSOR_TL_0 0x1cd8
583 #define RADEON_SCISSOR_BR_0 0x1cdc
584 #define RADEON_SCISSOR_TL_1 0x1ce0
585 #define RADEON_SCISSOR_BR_1 0x1ce4
586 #define RADEON_SCISSOR_TL_2 0x1ce8
587 #define RADEON_SCISSOR_BR_2 0x1cec
588 #define RADEON_SE_COORD_FMT 0x1c50
589 #define RADEON_SE_CNTL 0x1c4c
590 # define RADEON_FFACE_CULL_CW (0 << 0)
591 # define RADEON_BFACE_SOLID (3 << 1)
592 # define RADEON_FFACE_SOLID (3 << 3)
593 # define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
594 # define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
595 # define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
596 # define RADEON_ALPHA_SHADE_FLAT (1 << 10)
597 # define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
598 # define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
599 # define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
600 # define RADEON_FOG_SHADE_FLAT (1 << 14)
601 # define RADEON_FOG_SHADE_GOURAUD (2 << 14)
602 # define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
603 # define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
604 # define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
605 # define RADEON_ROUND_MODE_TRUNC (0 << 28)
606 # define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
607 #define RADEON_SE_CNTL_STATUS 0x2140
608 #define RADEON_SE_LINE_WIDTH 0x1db8
609 #define RADEON_SE_VPORT_XSCALE 0x1d98
610 #define RADEON_SE_ZBIAS_FACTOR 0x1db0
611 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
612 #define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
613 #define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
614 # define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
615 # define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
616 #define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
617 #define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
618 # define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
619 #define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
620 #define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
621 #define RADEON_SURFACE_ACCESS_CLR 0x0bfc
622 #define RADEON_SURFACE_CNTL 0x0b00
623 # define RADEON_SURF_TRANSLATION_DIS (1 << 8)
624 # define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
625 # define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
626 # define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
627 # define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
628 # define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
629 # define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
630 # define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
631 # define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
632 #define RADEON_SURFACE0_INFO 0x0b0c
633 # define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
634 # define RADEON_SURF_TILE_MODE_MASK (3 << 16)
635 # define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
636 # define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
637 # define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
638 # define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
639 #define RADEON_SURFACE0_LOWER_BOUND 0x0b04
640 #define RADEON_SURFACE0_UPPER_BOUND 0x0b08
641 # define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0)
642 #define RADEON_SURFACE1_INFO 0x0b1c
643 #define RADEON_SURFACE1_LOWER_BOUND 0x0b14
644 #define RADEON_SURFACE1_UPPER_BOUND 0x0b18
645 #define RADEON_SURFACE2_INFO 0x0b2c
646 #define RADEON_SURFACE2_LOWER_BOUND 0x0b24
647 #define RADEON_SURFACE2_UPPER_BOUND 0x0b28
648 #define RADEON_SURFACE3_INFO 0x0b3c
649 #define RADEON_SURFACE3_LOWER_BOUND 0x0b34
650 #define RADEON_SURFACE3_UPPER_BOUND 0x0b38
651 #define RADEON_SURFACE4_INFO 0x0b4c
652 #define RADEON_SURFACE4_LOWER_BOUND 0x0b44
653 #define RADEON_SURFACE4_UPPER_BOUND 0x0b48
654 #define RADEON_SURFACE5_INFO 0x0b5c
655 #define RADEON_SURFACE5_LOWER_BOUND 0x0b54
656 #define RADEON_SURFACE5_UPPER_BOUND 0x0b58
657 #define RADEON_SURFACE6_INFO 0x0b6c
658 #define RADEON_SURFACE6_LOWER_BOUND 0x0b64
659 #define RADEON_SURFACE6_UPPER_BOUND 0x0b68
660 #define RADEON_SURFACE7_INFO 0x0b7c
661 #define RADEON_SURFACE7_LOWER_BOUND 0x0b74
662 #define RADEON_SURFACE7_UPPER_BOUND 0x0b78
663 #define RADEON_SW_SEMAPHORE 0x013c
665 #define RADEON_WAIT_UNTIL 0x1720
666 # define RADEON_WAIT_CRTC_PFLIP (1 << 0)
667 # define RADEON_WAIT_2D_IDLE (1 << 14)
668 # define RADEON_WAIT_3D_IDLE (1 << 15)
669 # define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
670 # define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
671 # define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
673 #define RADEON_RB3D_ZMASKOFFSET 0x3234
674 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
675 # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
676 # define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
679 #define RADEON_CP_ME_RAM_ADDR 0x07d4
680 #define RADEON_CP_ME_RAM_RADDR 0x07d8
681 #define RADEON_CP_ME_RAM_DATAH 0x07dc
682 #define RADEON_CP_ME_RAM_DATAL 0x07e0
684 #define RADEON_CP_RB_BASE 0x0700
685 #define RADEON_CP_RB_CNTL 0x0704
686 # define RADEON_BUF_SWAP_32BIT (2 << 16)
687 # define RADEON_RB_NO_UPDATE (1 << 27)
688 #define RADEON_CP_RB_RPTR_ADDR 0x070c
689 #define RADEON_CP_RB_RPTR 0x0710
690 #define RADEON_CP_RB_WPTR 0x0714
692 #define RADEON_CP_RB_WPTR_DELAY 0x0718
693 # define RADEON_PRE_WRITE_TIMER_SHIFT 0
694 # define RADEON_PRE_WRITE_LIMIT_SHIFT 23
696 #define RADEON_CP_IB_BASE 0x0738
698 #define RADEON_CP_CSQ_CNTL 0x0740
699 # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
700 # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
701 # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
702 # define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
703 # define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
704 # define RADEON_CSQ_PRIBM_INDBM (4 << 28)
705 # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
707 #define RADEON_AIC_CNTL 0x01d0
708 # define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
709 #define RADEON_AIC_STAT 0x01d4
710 #define RADEON_AIC_PT_BASE 0x01d8
711 #define RADEON_AIC_LO_ADDR 0x01dc
712 #define RADEON_AIC_HI_ADDR 0x01e0
713 #define RADEON_AIC_TLB_ADDR 0x01e4
714 #define RADEON_AIC_TLB_DATA 0x01e8
716 /* CP command packets */
717 #define RADEON_CP_PACKET0 0x00000000
718 # define RADEON_ONE_REG_WR (1 << 15)
719 #define RADEON_CP_PACKET1 0x40000000
720 #define RADEON_CP_PACKET2 0x80000000
721 #define RADEON_CP_PACKET3 0xC0000000
722 # define RADEON_CP_NOP 0x00001000
723 # define RADEON_CP_NEXT_CHAR 0x00001900
724 # define RADEON_CP_PLY_NEXTSCAN 0x00001D00
725 # define RADEON_CP_SET_SCISSORS 0x00001E00
726 /* GEN_INDX_PRIM is unsupported starting with R300 */
727 # define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
728 # define RADEON_WAIT_FOR_IDLE 0x00002600
729 # define RADEON_3D_DRAW_VBUF 0x00002800
730 # define RADEON_3D_DRAW_IMMD 0x00002900
731 # define RADEON_3D_DRAW_INDX 0x00002A00
732 # define RADEON_CP_LOAD_PALETTE 0x00002C00
733 # define RADEON_3D_LOAD_VBPNTR 0x00002F00
734 # define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000
735 # define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100
736 # define RADEON_3D_CLEAR_ZMASK 0x00003200
737 # define RADEON_CP_INDX_BUFFER 0x00003300
738 # define RADEON_CP_3D_DRAW_VBUF_2 0x00003400
739 # define RADEON_CP_3D_DRAW_IMMD_2 0x00003500
740 # define RADEON_CP_3D_DRAW_INDX_2 0x00003600
741 # define RADEON_3D_CLEAR_HIZ 0x00003700
742 # define RADEON_CP_3D_CLEAR_CMASK 0x00003802
743 # define RADEON_CNTL_HOSTDATA_BLT 0x00009400
744 # define RADEON_CNTL_PAINT_MULTI 0x00009A00
745 # define RADEON_CNTL_BITBLT_MULTI 0x00009B00
746 # define RADEON_CNTL_SET_SCISSORS 0xC0001E00
748 #define RADEON_CP_PACKET_MASK 0xC0000000
749 #define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
750 #define RADEON_CP_PACKET0_REG_MASK 0x000007ff
751 #define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
752 #define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
754 #define RADEON_VTX_Z_PRESENT (1 << 31)
755 #define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
757 #define RADEON_PRIM_TYPE_NONE (0 << 0)
758 #define RADEON_PRIM_TYPE_POINT (1 << 0)
759 #define RADEON_PRIM_TYPE_LINE (2 << 0)
760 #define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
761 #define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
762 #define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
763 #define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
764 #define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
765 #define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
766 #define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
767 #define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
768 #define RADEON_PRIM_TYPE_MASK 0xf
769 #define RADEON_PRIM_WALK_IND (1 << 4)
770 #define RADEON_PRIM_WALK_LIST (2 << 4)
771 #define RADEON_PRIM_WALK_RING (3 << 4)
772 #define RADEON_COLOR_ORDER_BGRA (0 << 6)
773 #define RADEON_COLOR_ORDER_RGBA (1 << 6)
774 #define RADEON_MAOS_ENABLE (1 << 7)
775 #define RADEON_VTX_FMT_R128_MODE (0 << 8)
776 #define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
777 #define RADEON_NUM_VERTICES_SHIFT 16
779 #define RADEON_COLOR_FORMAT_CI8 2
780 #define RADEON_COLOR_FORMAT_ARGB1555 3
781 #define RADEON_COLOR_FORMAT_RGB565 4
782 #define RADEON_COLOR_FORMAT_ARGB8888 6
783 #define RADEON_COLOR_FORMAT_RGB332 7
784 #define RADEON_COLOR_FORMAT_RGB8 9
785 #define RADEON_COLOR_FORMAT_ARGB4444 15
787 #define RADEON_TXFORMAT_I8 0
788 #define RADEON_TXFORMAT_AI88 1
789 #define RADEON_TXFORMAT_RGB332 2
790 #define RADEON_TXFORMAT_ARGB1555 3
791 #define RADEON_TXFORMAT_RGB565 4
792 #define RADEON_TXFORMAT_ARGB4444 5
793 #define RADEON_TXFORMAT_ARGB8888 6
794 #define RADEON_TXFORMAT_RGBA8888 7
795 #define RADEON_TXFORMAT_Y8 8
796 #define RADEON_TXFORMAT_VYUY422 10
797 #define RADEON_TXFORMAT_YVYU422 11
798 #define RADEON_TXFORMAT_DXT1 12
799 #define RADEON_TXFORMAT_DXT23 14
800 #define RADEON_TXFORMAT_DXT45 15
802 #define R200_PP_TXCBLEND_0 0x2f00
803 #define R200_PP_TXCBLEND_1 0x2f10
804 #define R200_PP_TXCBLEND_2 0x2f20
805 #define R200_PP_TXCBLEND_3 0x2f30
806 #define R200_PP_TXCBLEND_4 0x2f40
807 #define R200_PP_TXCBLEND_5 0x2f50
808 #define R200_PP_TXCBLEND_6 0x2f60
809 #define R200_PP_TXCBLEND_7 0x2f70
810 #define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
811 #define R200_PP_TFACTOR_0 0x2ee0
812 #define R200_SE_VTX_FMT_0 0x2088
813 #define R200_SE_VAP_CNTL 0x2080
814 #define R200_SE_TCL_MATRIX_SEL_0 0x2230
815 #define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
816 #define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
817 #define R200_PP_TXFILTER_5 0x2ca0
818 #define R200_PP_TXFILTER_4 0x2c80
819 #define R200_PP_TXFILTER_3 0x2c60
820 #define R200_PP_TXFILTER_2 0x2c40
821 #define R200_PP_TXFILTER_1 0x2c20
822 #define R200_PP_TXFILTER_0 0x2c00
823 #define R200_PP_TXOFFSET_5 0x2d78
824 #define R200_PP_TXOFFSET_4 0x2d60
825 #define R200_PP_TXOFFSET_3 0x2d48
826 #define R200_PP_TXOFFSET_2 0x2d30
827 #define R200_PP_TXOFFSET_1 0x2d18
828 #define R200_PP_TXOFFSET_0 0x2d00
830 #define R200_PP_CUBIC_FACES_0 0x2c18
831 #define R200_PP_CUBIC_FACES_1 0x2c38
832 #define R200_PP_CUBIC_FACES_2 0x2c58
833 #define R200_PP_CUBIC_FACES_3 0x2c78
834 #define R200_PP_CUBIC_FACES_4 0x2c98
835 #define R200_PP_CUBIC_FACES_5 0x2cb8
836 #define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
837 #define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
838 #define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
839 #define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
840 #define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
841 #define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
842 #define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
843 #define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
844 #define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
845 #define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
846 #define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
847 #define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
848 #define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
849 #define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
850 #define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
851 #define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
852 #define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
853 #define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
854 #define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
855 #define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
856 #define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
857 #define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
858 #define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
859 #define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
860 #define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
861 #define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
862 #define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
863 #define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
864 #define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
865 #define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
867 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
868 #define R200_SE_VTE_CNTL 0x20b0
869 #define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
870 #define R200_PP_TAM_DEBUG3 0x2d9c
871 #define R200_PP_CNTL_X 0x2cc4
872 #define R200_SE_VAP_CNTL_STATUS 0x2140
873 #define R200_RE_SCISSOR_TL_0 0x1cd8
874 #define R200_RE_SCISSOR_TL_1 0x1ce0
875 #define R200_RE_SCISSOR_TL_2 0x1ce8
876 #define R200_RB3D_DEPTHXY_OFFSET 0x1d60
877 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
878 #define R200_SE_VTX_STATE_CNTL 0x2180
879 #define R200_RE_POINTSIZE 0x2648
880 #define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
882 #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
883 #define RADEON_PP_TEX_SIZE_1 0x1d0c
884 #define RADEON_PP_TEX_SIZE_2 0x1d14
886 #define RADEON_PP_CUBIC_FACES_0 0x1d24
887 #define RADEON_PP_CUBIC_FACES_1 0x1d28
888 #define RADEON_PP_CUBIC_FACES_2 0x1d2c
889 #define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
890 #define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
891 #define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
893 #define RADEON_SE_TCL_STATE_FLUSH 0x2284
895 #define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
896 #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
897 #define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
898 #define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
899 #define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
900 #define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
901 #define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
902 #define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
903 #define R200_3D_DRAW_IMMD_2 0xC0003500
904 #define R200_SE_VTX_FMT_1 0x208c
905 #define R200_RE_CNTL 0x1c50
907 #define R200_RB3D_BLENDCOLOR 0x3218
909 #define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
911 #define R200_PP_TRI_PERF 0x2cf8
913 #define R200_PP_AFS_0 0x2f80
914 #define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */
916 #define R200_VAP_PVS_CNTL_1 0x22D0
918 /* MPEG settings from VHA code */
919 #define RADEON_VHA_SETTO16_1 0x2694
920 #define RADEON_VHA_SETTO16_2 0x2680
921 #define RADEON_VHA_SETTO0_1 0x1840
922 #define RADEON_VHA_FB_OFFSET 0x19e4
923 #define RADEON_VHA_SETTO1AND70S 0x19d8
924 #define RADEON_VHA_DST_PITCH 0x1408
926 // set as reference header
927 #define RADEON_VHA_BACKFRAME0_OFF_Y 0x1840
928 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_Y 0x1844
929 #define RADEON_VHA_BACKFRAME0_OFF_U 0x1848
930 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_U 0x184c
931 #define RADOEN_VHA_BACKFRAME0_OFF_V 0x1850
932 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_V 0x1854
933 #define RADEON_VHA_FORWFRAME0_OFF_Y 0x1858
934 #define RADEON_VHA_FORWFRAME1_OFF_PITCH_Y 0x185c
935 #define RADEON_VHA_FORWFRAME0_OFF_U 0x1860
936 #define RADEON_VHA_FORWFRAME1_OFF_PITCH_U 0x1864
937 #define RADEON_VHA_FORWFRAME0_OFF_V 0x1868
938 #define RADEON_VHA_FORWFRAME0_OFF_PITCH_V 0x1880
939 #define RADEON_VHA_BACKFRAME0_OFF_Y_2 0x1884
940 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_Y_2 0x1888
941 #define RADEON_VHA_BACKFRAME0_OFF_U_2 0x188c
942 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_U_2 0x1890
943 #define RADEON_VHA_BACKFRAME0_OFF_V_2 0x1894
944 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_V_2 0x1898
949 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
951 #define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
952 #define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
953 #define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
954 #define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
955 #define RADEON_LAST_DISPATCH 1
957 #define RADEON_MAX_VB_AGE 0x7fffffff
958 #define RADEON_MAX_VB_VERTS (0xffff)
960 #define RADEON_RING_HIGH_MARK 128
962 #define RADEON_PCIGART_TABLE_SIZE (32*1024)
964 #define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
965 #define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
966 #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
967 #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
969 #define RADEON_WRITE_PLL( addr, val ) \
971 RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \
972 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
973 RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \
976 #define RADEON_WRITE_PCIE( addr, val ) \
978 RADEON_WRITE8( RADEON_PCIE_INDEX, \
980 RADEON_WRITE( RADEON_PCIE_DATA, (val) ); \
983 #define CP_PACKET0( reg, n ) \
984 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
985 #define CP_PACKET0_TABLE( reg, n ) \
986 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
987 #define CP_PACKET1( reg0, reg1 ) \
988 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
989 #define CP_PACKET2() \
991 #define CP_PACKET3( pkt, n ) \
992 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
994 /* ================================================================
995 * Engine control helper macros
998 #define RADEON_WAIT_UNTIL_2D_IDLE() do { \
999 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1000 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1001 RADEON_WAIT_HOST_IDLECLEAN) ); \
1004 #define RADEON_WAIT_UNTIL_3D_IDLE() do { \
1005 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1006 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
1007 RADEON_WAIT_HOST_IDLECLEAN) ); \
1010 #define RADEON_WAIT_UNTIL_IDLE() do { \
1011 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1012 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1013 RADEON_WAIT_3D_IDLECLEAN | \
1014 RADEON_WAIT_HOST_IDLECLEAN) ); \
1017 #define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
1018 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1019 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
1022 #define RADEON_FLUSH_CACHE() do { \
1023 OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \
1024 OUT_RING( RADEON_RB3D_DC_FLUSH ); \
1027 #define RADEON_PURGE_CACHE() do { \
1028 OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \
1029 OUT_RING( RADEON_RB3D_DC_FLUSH_ALL ); \
1032 #define RADEON_FLUSH_ZCACHE() do { \
1033 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
1034 OUT_RING( RADEON_RB3D_ZC_FLUSH ); \
1037 #define RADEON_PURGE_ZCACHE() do { \
1038 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
1039 OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \
1042 /* ================================================================
1043 * Misc helper macros
1046 /* Perfbox functionality only.
1048 #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
1050 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
1051 u32 head = GET_RING_HEAD( dev_priv ); \
1052 if (head == dev_priv->ring.tail) \
1053 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
1057 #define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
1059 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \
1060 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
1061 int __ret = radeon_do_cp_idle( dev_priv ); \
1062 if ( __ret ) return __ret; \
1063 sarea_priv->last_dispatch = 0; \
1064 radeon_freelist_reset( dev ); \
1068 #define RADEON_DISPATCH_AGE( age ) do { \
1069 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
1073 #define RADEON_FRAME_AGE( age ) do { \
1074 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
1078 #define RADEON_CLEAR_AGE( age ) do { \
1079 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
1083 /* ================================================================
1087 #define RADEON_VERBOSE 0
1089 #define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring;
1091 #define BEGIN_RING( n ) do { \
1092 if ( RADEON_VERBOSE ) { \
1093 DRM_INFO( "BEGIN_RING( %d ) in %s\n", \
1094 n, __FUNCTION__ ); \
1096 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
1098 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \
1100 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
1101 ring = dev_priv->ring.start; \
1102 write = dev_priv->ring.tail; \
1103 mask = dev_priv->ring.tail_mask; \
1106 #define ADVANCE_RING() do { \
1107 if ( RADEON_VERBOSE ) { \
1108 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
1109 write, dev_priv->ring.tail ); \
1111 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
1113 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
1114 ((dev_priv->ring.tail + _nr) & mask), \
1117 dev_priv->ring.tail = write; \
1120 #define COMMIT_RING() do { \
1121 /* Flush writes to ring */ \
1122 DRM_MEMORYBARRIER(); \
1123 GET_RING_HEAD( dev_priv ); \
1124 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
1125 /* read from PCI bus to ensure correct posting */ \
1126 RADEON_READ( RADEON_CP_RB_RPTR ); \
1129 #define OUT_RING( x ) do { \
1130 if ( RADEON_VERBOSE ) { \
1131 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
1132 (unsigned int)(x), write ); \
1134 ring[write++] = (x); \
1138 #define OUT_RING_REG( reg, val ) do { \
1139 OUT_RING( CP_PACKET0( reg, 0 ) ); \
1143 #define OUT_RING_TABLE( tab, sz ) do { \
1145 int *_tab = (int *)(tab); \
1147 if (write + _size > mask) { \
1148 int _i = (mask+1) - write; \
1151 *(int *)(ring + write) = *_tab++; \
1158 while (_size > 0) { \
1159 *(ring + write) = *_tab++; \
1166 #endif /* __RADEON_DRV_H__ */