1 /* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
31 #ifndef __RADEON_DRV_H__
32 #define __RADEON_DRV_H__
35 #include "radeon_i2c.h"
36 #endif /* __linux__ */
38 /* General customization:
41 #define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."
43 #define DRIVER_NAME "radeon"
44 #define DRIVER_DESC "ATI Radeon"
45 #define DRIVER_DATE "20050208"
50 * 1.2 - Add vertex2 ioctl (keith)
51 * - Add stencil capability to clear ioctl (gareth, keith)
52 * - Increase MAX_TEXTURE_LEVELS (brian)
53 * 1.3 - Add cmdbuf ioctl (keith)
54 * - Add support for new radeon packets (keith)
55 * - Add getparam ioctl (keith)
56 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
57 * 1.4 - Add scratch registers to get_param ioctl.
58 * 1.5 - Add r200 packets to cmdbuf ioctl
59 * - Add r200 function to init ioctl
60 * - Add 'scalar2' instruction to cmdbuf
61 * 1.6 - Add static GART memory manager
62 * Add irq handler (won't be turned on unless X server knows to)
63 * Add irq ioctls and irq_active getparam.
64 * Add wait command for cmdbuf ioctl
65 * Add GART offset query for getparam
66 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
67 * and R200_PP_CUBIC_OFFSET_F1_[0..5].
68 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
69 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian)
70 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
71 * Add 'GET' queries for starting additional clients on different VT's.
72 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
73 * Add texture rectangle support for r100.
74 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
75 * clients use to tell the DRM where they think the framebuffer is
76 * located in the card's address space
77 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
78 * and GL_EXT_blend_[func|equation]_separate on r200
79 * 1.12- Add R300 CP microcode support - this just loads the CP on r300
80 * (No 3D support yet - just microcode loading).
81 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
82 * - Add hyperz support, add hyperz flags to clear ioctl.
83 * 1.14- Add support for color tiling
84 * - Add R100/R200 surface allocation/free support
85 * 1.15- Add support for texture micro tiling
86 * - Add support for r100 cube maps
89 #define DRIVER_MAJOR 1
90 #define DRIVER_MINOR 15
91 #define DRIVER_PATCHLEVEL 0
110 enum radeon_cp_microcode_version {
119 enum radeon_chip_flags {
120 CHIP_FAMILY_MASK = 0x0000ffffUL,
121 CHIP_FLAGS_MASK = 0xffff0000UL,
122 CHIP_IS_MOBILITY = 0x00010000UL,
123 CHIP_IS_IGP = 0x00020000UL,
124 CHIP_SINGLE_CRTC = 0x00040000UL,
125 CHIP_IS_AGP = 0x00080000UL,
126 CHIP_HAS_HIERZ = 0x00100000UL,
129 #define GET_RING_HEAD(dev_priv) DRM_READ32( (dev_priv)->ring_rptr, 0 )
130 #define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) )
132 typedef struct drm_radeon_freelist {
135 struct drm_radeon_freelist *next;
136 struct drm_radeon_freelist *prev;
137 } drm_radeon_freelist_t;
139 typedef struct drm_radeon_ring_buffer {
150 } drm_radeon_ring_buffer_t;
152 typedef struct drm_radeon_depth_clear_t {
154 u32 rb3d_zstencilcntl;
156 } drm_radeon_depth_clear_t;
158 struct drm_radeon_driver_file_fields {
159 int64_t radeon_fb_delta;
163 struct mem_block *next;
164 struct mem_block *prev;
167 DRMFILE filp; /* 0: free, -1: heap, other: real files */
170 struct radeon_surface {
177 struct radeon_virt_surface {
185 typedef struct drm_radeon_private {
187 drm_radeon_ring_buffer_t ring;
188 drm_radeon_sarea_t *sarea_priv;
194 unsigned long gart_buffers_offset;
199 drm_radeon_freelist_t *head;
200 drm_radeon_freelist_t *tail;
202 volatile u32 *scratch;
207 int microcode_version;
209 unsigned long phys_pci_gart;
210 dma_addr_t bus_pci_gart;
214 int freelist_timeouts;
217 int last_frame_reads;
218 int last_clear_reads;
228 unsigned int front_offset;
229 unsigned int front_pitch;
230 unsigned int back_offset;
231 unsigned int back_pitch;
234 unsigned int depth_offset;
235 unsigned int depth_pitch;
237 u32 front_pitch_offset;
238 u32 back_pitch_offset;
239 u32 depth_pitch_offset;
241 drm_radeon_depth_clear_t depth_clear;
243 unsigned long fb_offset;
244 unsigned long mmio_offset;
245 unsigned long ring_offset;
246 unsigned long ring_rptr_offset;
247 unsigned long buffers_offset;
248 unsigned long gart_textures_offset;
250 drm_local_map_t *sarea;
251 drm_local_map_t *mmio;
252 drm_local_map_t *cp_ring;
253 drm_local_map_t *ring_rptr;
254 drm_local_map_t *gart_textures;
256 struct mem_block *gart_heap;
257 struct mem_block *fb_heap;
260 wait_queue_head_t swi_queue;
261 atomic_t swi_emitted;
263 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
264 struct radeon_virt_surface virt_surfaces[2*RADEON_MAX_SURFACES];
266 /* starting from here on, data is preserved accross an open */
267 uint32_t flags; /* see radeon_chip_flags */
270 struct radeon_i2c_chan i2c[4];
271 #endif /* __linux__ */
272 } drm_radeon_private_t;
274 typedef struct drm_radeon_buf_priv {
276 } drm_radeon_buf_priv_t;
279 extern int radeon_cp_init(DRM_IOCTL_ARGS);
280 extern int radeon_cp_start(DRM_IOCTL_ARGS);
281 extern int radeon_cp_stop(DRM_IOCTL_ARGS);
282 extern int radeon_cp_reset(DRM_IOCTL_ARGS);
283 extern int radeon_cp_idle(DRM_IOCTL_ARGS);
284 extern int radeon_cp_resume(DRM_IOCTL_ARGS);
285 extern int radeon_engine_reset(DRM_IOCTL_ARGS);
286 extern int radeon_fullscreen(DRM_IOCTL_ARGS);
287 extern int radeon_cp_buffers(DRM_IOCTL_ARGS);
289 extern void radeon_freelist_reset(drm_device_t * dev);
290 extern drm_buf_t *radeon_freelist_get(drm_device_t * dev);
292 extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
294 extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv);
296 extern int radeon_mem_alloc(DRM_IOCTL_ARGS);
297 extern int radeon_mem_free(DRM_IOCTL_ARGS);
298 extern int radeon_mem_init_heap(DRM_IOCTL_ARGS);
299 extern void radeon_mem_takedown(struct mem_block **heap);
300 extern void radeon_mem_release(DRMFILE filp, struct mem_block *heap);
303 extern int radeon_irq_emit(DRM_IOCTL_ARGS);
304 extern int radeon_irq_wait(DRM_IOCTL_ARGS);
306 extern void radeon_do_release(drm_device_t * dev);
307 extern int radeon_driver_vblank_wait(drm_device_t * dev,
308 unsigned int *sequence);
309 extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
310 extern void radeon_driver_irq_preinstall(drm_device_t * dev);
311 extern void radeon_driver_irq_postinstall(drm_device_t * dev);
312 extern void radeon_driver_irq_uninstall(drm_device_t * dev);
313 extern void radeon_driver_prerelease(drm_device_t * dev, DRMFILE filp);
314 extern void radeon_driver_pretakedown(drm_device_t * dev);
315 extern int radeon_driver_open_helper(drm_device_t * dev,
316 drm_file_t * filp_priv);
317 extern void radeon_driver_free_filp_priv(drm_device_t * dev,
318 drm_file_t * filp_priv);
320 /* Flags for stats.boxes
322 #define RADEON_BOX_DMA_IDLE 0x1
323 #define RADEON_BOX_RING_FULL 0x2
324 #define RADEON_BOX_FLIP 0x4
325 #define RADEON_BOX_WAIT_IDLE 0x8
326 #define RADEON_BOX_TEXTURE_LOAD 0x10
328 /* Register definitions, register access macros and drmAddMap constants
329 * for Radeon kernel driver.
331 #define RADEON_AGP_COMMAND 0x0f60
332 #define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
333 # define RADEON_AGP_ENABLE (1<<8)
335 #define RADEON_AUX_SCISSOR_CNTL 0x26f0
336 # define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
337 # define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
338 # define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
339 # define RADEON_SCISSOR_0_ENABLE (1 << 28)
340 # define RADEON_SCISSOR_1_ENABLE (1 << 29)
341 # define RADEON_SCISSOR_2_ENABLE (1 << 30)
343 #define RADEON_BUS_CNTL 0x0030
344 # define RADEON_BUS_MASTER_DIS (1 << 6)
346 #define RADEON_CLOCK_CNTL_DATA 0x000c
347 # define RADEON_PLL_WR_EN (1 << 7)
348 #define RADEON_CLOCK_CNTL_INDEX 0x0008
349 #define RADEON_CONFIG_APER_SIZE 0x0108
350 #define RADEON_CRTC_OFFSET 0x0224
351 #define RADEON_CRTC_OFFSET_CNTL 0x0228
352 # define RADEON_CRTC_TILE_EN (1 << 15)
353 # define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
354 #define RADEON_CRTC2_OFFSET 0x0324
355 #define RADEON_CRTC2_OFFSET_CNTL 0x0328
357 #define RADEON_MPP_TB_CONFIG 0x01c0
358 #define RADEON_MEM_CNTL 0x0140
359 #define RADEON_MEM_SDRAM_MODE_REG 0x0158
360 #define RADEON_AGP_BASE 0x0170
362 #define RADEON_RB3D_COLOROFFSET 0x1c40
363 #define RADEON_RB3D_COLORPITCH 0x1c48
365 #define RADEON_DP_GUI_MASTER_CNTL 0x146c
366 # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
367 # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
368 # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
369 # define RADEON_GMC_BRUSH_NONE (15 << 4)
370 # define RADEON_GMC_DST_16BPP (4 << 8)
371 # define RADEON_GMC_DST_24BPP (5 << 8)
372 # define RADEON_GMC_DST_32BPP (6 << 8)
373 # define RADEON_GMC_DST_DATATYPE_SHIFT 8
374 # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
375 # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
376 # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
377 # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
378 # define RADEON_GMC_WR_MSK_DIS (1 << 30)
379 # define RADEON_ROP3_S 0x00cc0000
380 # define RADEON_ROP3_P 0x00f00000
381 #define RADEON_DP_WRITE_MASK 0x16cc
382 #define RADEON_DST_PITCH_OFFSET 0x142c
383 #define RADEON_DST_PITCH_OFFSET_C 0x1c80
384 # define RADEON_DST_TILE_LINEAR (0 << 30)
385 # define RADEON_DST_TILE_MACRO (1 << 30)
386 # define RADEON_DST_TILE_MICRO (2 << 30)
387 # define RADEON_DST_TILE_BOTH (3 << 30)
389 #define RADEON_SCRATCH_REG0 0x15e0
390 #define RADEON_SCRATCH_REG1 0x15e4
391 #define RADEON_SCRATCH_REG2 0x15e8
392 #define RADEON_SCRATCH_REG3 0x15ec
393 #define RADEON_SCRATCH_REG4 0x15f0
394 #define RADEON_SCRATCH_REG5 0x15f4
395 #define RADEON_SCRATCH_UMSK 0x0770
396 #define RADEON_SCRATCH_ADDR 0x0774
398 #define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
400 #define GET_SCRATCH( x ) (dev_priv->writeback_works \
401 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \
402 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) )
404 #define RADEON_GEN_INT_CNTL 0x0040
405 # define RADEON_CRTC_VBLANK_MASK (1 << 0)
406 # define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
407 # define RADEON_SW_INT_ENABLE (1 << 25)
409 #define RADEON_GEN_INT_STATUS 0x0044
410 # define RADEON_CRTC_VBLANK_STAT (1 << 0)
411 # define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
412 # define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
413 # define RADEON_SW_INT_TEST (1 << 25)
414 # define RADEON_SW_INT_TEST_ACK (1 << 25)
415 # define RADEON_SW_INT_FIRE (1 << 26)
417 #define RADEON_HOST_PATH_CNTL 0x0130
418 # define RADEON_HDP_SOFT_RESET (1 << 26)
419 # define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
420 # define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
422 #define RADEON_ISYNC_CNTL 0x1724
423 # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
424 # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
425 # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
426 # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
427 # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
428 # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
430 #define RADEON_RBBM_GUICNTL 0x172c
431 # define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
432 # define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
433 # define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
434 # define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
436 #define RADEON_MC_AGP_LOCATION 0x014c
437 #define RADEON_MC_FB_LOCATION 0x0148
438 #define RADEON_MCLK_CNTL 0x0012
439 # define RADEON_FORCEON_MCLKA (1 << 16)
440 # define RADEON_FORCEON_MCLKB (1 << 17)
441 # define RADEON_FORCEON_YCLKA (1 << 18)
442 # define RADEON_FORCEON_YCLKB (1 << 19)
443 # define RADEON_FORCEON_MC (1 << 20)
444 # define RADEON_FORCEON_AIC (1 << 21)
446 #define RADEON_PP_BORDER_COLOR_0 0x1d40
447 #define RADEON_PP_BORDER_COLOR_1 0x1d44
448 #define RADEON_PP_BORDER_COLOR_2 0x1d48
449 #define RADEON_PP_CNTL 0x1c38
450 # define RADEON_SCISSOR_ENABLE (1 << 1)
451 #define RADEON_PP_LUM_MATRIX 0x1d00
452 #define RADEON_PP_MISC 0x1c14
453 #define RADEON_PP_ROT_MATRIX_0 0x1d58
454 #define RADEON_PP_TXFILTER_0 0x1c54
455 #define RADEON_PP_TXOFFSET_0 0x1c5c
456 #define RADEON_PP_TXFILTER_1 0x1c6c
457 #define RADEON_PP_TXFILTER_2 0x1c84
459 #define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
460 # define RADEON_RB2D_DC_FLUSH (3 << 0)
461 # define RADEON_RB2D_DC_FREE (3 << 2)
462 # define RADEON_RB2D_DC_FLUSH_ALL 0xf
463 # define RADEON_RB2D_DC_BUSY (1 << 31)
464 #define RADEON_RB3D_CNTL 0x1c3c
465 # define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
466 # define RADEON_PLANE_MASK_ENABLE (1 << 1)
467 # define RADEON_DITHER_ENABLE (1 << 2)
468 # define RADEON_ROUND_ENABLE (1 << 3)
469 # define RADEON_SCALE_DITHER_ENABLE (1 << 4)
470 # define RADEON_DITHER_INIT (1 << 5)
471 # define RADEON_ROP_ENABLE (1 << 6)
472 # define RADEON_STENCIL_ENABLE (1 << 7)
473 # define RADEON_Z_ENABLE (1 << 8)
474 # define RADEON_ZBLOCK16 (1 << 15)
475 #define RADEON_RB3D_DEPTHOFFSET 0x1c24
476 #define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
477 #define RADEON_RB3D_DEPTHPITCH 0x1c28
478 #define RADEON_RB3D_PLANEMASK 0x1d84
479 #define RADEON_RB3D_STENCILREFMASK 0x1d7c
480 #define RADEON_RB3D_ZCACHE_MODE 0x3250
481 #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
482 # define RADEON_RB3D_ZC_FLUSH (1 << 0)
483 # define RADEON_RB3D_ZC_FREE (1 << 2)
484 # define RADEON_RB3D_ZC_FLUSH_ALL 0x5
485 # define RADEON_RB3D_ZC_BUSY (1 << 31)
486 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
487 # define RADEON_Z_TEST_MASK (7 << 4)
488 # define RADEON_Z_TEST_ALWAYS (7 << 4)
489 # define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
490 # define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
491 # define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
492 # define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
493 # define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
494 # define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
495 # define RADEON_FORCE_Z_DIRTY (1 << 29)
496 # define RADEON_Z_WRITE_ENABLE (1 << 30)
497 # define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
498 #define RADEON_RBBM_SOFT_RESET 0x00f0
499 # define RADEON_SOFT_RESET_CP (1 << 0)
500 # define RADEON_SOFT_RESET_HI (1 << 1)
501 # define RADEON_SOFT_RESET_SE (1 << 2)
502 # define RADEON_SOFT_RESET_RE (1 << 3)
503 # define RADEON_SOFT_RESET_PP (1 << 4)
504 # define RADEON_SOFT_RESET_E2 (1 << 5)
505 # define RADEON_SOFT_RESET_RB (1 << 6)
506 # define RADEON_SOFT_RESET_HDP (1 << 7)
507 #define RADEON_RBBM_STATUS 0x0e40
508 # define RADEON_RBBM_FIFOCNT_MASK 0x007f
509 # define RADEON_RBBM_ACTIVE (1 << 31)
510 #define RADEON_RE_LINE_PATTERN 0x1cd0
511 #define RADEON_RE_MISC 0x26c4
512 #define RADEON_RE_TOP_LEFT 0x26c0
513 #define RADEON_RE_WIDTH_HEIGHT 0x1c44
514 #define RADEON_RE_STIPPLE_ADDR 0x1cc8
515 #define RADEON_RE_STIPPLE_DATA 0x1ccc
517 #define RADEON_SCISSOR_TL_0 0x1cd8
518 #define RADEON_SCISSOR_BR_0 0x1cdc
519 #define RADEON_SCISSOR_TL_1 0x1ce0
520 #define RADEON_SCISSOR_BR_1 0x1ce4
521 #define RADEON_SCISSOR_TL_2 0x1ce8
522 #define RADEON_SCISSOR_BR_2 0x1cec
523 #define RADEON_SE_COORD_FMT 0x1c50
524 #define RADEON_SE_CNTL 0x1c4c
525 # define RADEON_FFACE_CULL_CW (0 << 0)
526 # define RADEON_BFACE_SOLID (3 << 1)
527 # define RADEON_FFACE_SOLID (3 << 3)
528 # define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
529 # define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
530 # define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
531 # define RADEON_ALPHA_SHADE_FLAT (1 << 10)
532 # define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
533 # define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
534 # define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
535 # define RADEON_FOG_SHADE_FLAT (1 << 14)
536 # define RADEON_FOG_SHADE_GOURAUD (2 << 14)
537 # define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
538 # define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
539 # define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
540 # define RADEON_ROUND_MODE_TRUNC (0 << 28)
541 # define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
542 #define RADEON_SE_CNTL_STATUS 0x2140
543 #define RADEON_SE_LINE_WIDTH 0x1db8
544 #define RADEON_SE_VPORT_XSCALE 0x1d98
545 #define RADEON_SE_ZBIAS_FACTOR 0x1db0
546 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
547 #define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
548 #define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
549 # define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
550 # define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
551 #define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
552 #define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
553 # define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
554 #define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
555 #define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
556 #define RADEON_SURFACE_ACCESS_CLR 0x0bfc
557 #define RADEON_SURFACE_CNTL 0x0b00
558 # define RADEON_SURF_TRANSLATION_DIS (1 << 8)
559 # define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
560 # define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
561 # define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
562 # define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
563 # define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
564 # define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
565 # define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
566 # define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
567 #define RADEON_SURFACE0_INFO 0x0b0c
568 # define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
569 # define RADEON_SURF_TILE_MODE_MASK (3 << 16)
570 # define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
571 # define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
572 # define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
573 # define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
574 #define RADEON_SURFACE0_LOWER_BOUND 0x0b04
575 #define RADEON_SURFACE0_UPPER_BOUND 0x0b08
576 # define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0)
577 #define RADEON_SURFACE1_INFO 0x0b1c
578 #define RADEON_SURFACE1_LOWER_BOUND 0x0b14
579 #define RADEON_SURFACE1_UPPER_BOUND 0x0b18
580 #define RADEON_SURFACE2_INFO 0x0b2c
581 #define RADEON_SURFACE2_LOWER_BOUND 0x0b24
582 #define RADEON_SURFACE2_UPPER_BOUND 0x0b28
583 #define RADEON_SURFACE3_INFO 0x0b3c
584 #define RADEON_SURFACE3_LOWER_BOUND 0x0b34
585 #define RADEON_SURFACE3_UPPER_BOUND 0x0b38
586 #define RADEON_SURFACE4_INFO 0x0b4c
587 #define RADEON_SURFACE4_LOWER_BOUND 0x0b44
588 #define RADEON_SURFACE4_UPPER_BOUND 0x0b48
589 #define RADEON_SURFACE5_INFO 0x0b5c
590 #define RADEON_SURFACE5_LOWER_BOUND 0x0b54
591 #define RADEON_SURFACE5_UPPER_BOUND 0x0b58
592 #define RADEON_SURFACE6_INFO 0x0b6c
593 #define RADEON_SURFACE6_LOWER_BOUND 0x0b64
594 #define RADEON_SURFACE6_UPPER_BOUND 0x0b68
595 #define RADEON_SURFACE7_INFO 0x0b7c
596 #define RADEON_SURFACE7_LOWER_BOUND 0x0b74
597 #define RADEON_SURFACE7_UPPER_BOUND 0x0b78
598 #define RADEON_SW_SEMAPHORE 0x013c
600 #define RADEON_WAIT_UNTIL 0x1720
601 # define RADEON_WAIT_CRTC_PFLIP (1 << 0)
602 # define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
603 # define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
604 # define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
606 #define RADEON_RB3D_ZMASKOFFSET 0x3234
607 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
608 # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
609 # define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
612 #define RADEON_CP_ME_RAM_ADDR 0x07d4
613 #define RADEON_CP_ME_RAM_RADDR 0x07d8
614 #define RADEON_CP_ME_RAM_DATAH 0x07dc
615 #define RADEON_CP_ME_RAM_DATAL 0x07e0
617 #define RADEON_CP_RB_BASE 0x0700
618 #define RADEON_CP_RB_CNTL 0x0704
619 # define RADEON_BUF_SWAP_32BIT (2 << 16)
620 #define RADEON_CP_RB_RPTR_ADDR 0x070c
621 #define RADEON_CP_RB_RPTR 0x0710
622 #define RADEON_CP_RB_WPTR 0x0714
624 #define RADEON_CP_RB_WPTR_DELAY 0x0718
625 # define RADEON_PRE_WRITE_TIMER_SHIFT 0
626 # define RADEON_PRE_WRITE_LIMIT_SHIFT 23
628 #define RADEON_CP_IB_BASE 0x0738
630 #define RADEON_CP_CSQ_CNTL 0x0740
631 # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
632 # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
633 # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
634 # define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
635 # define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
636 # define RADEON_CSQ_PRIBM_INDBM (4 << 28)
637 # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
639 #define RADEON_AIC_CNTL 0x01d0
640 # define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
641 #define RADEON_AIC_STAT 0x01d4
642 #define RADEON_AIC_PT_BASE 0x01d8
643 #define RADEON_AIC_LO_ADDR 0x01dc
644 #define RADEON_AIC_HI_ADDR 0x01e0
645 #define RADEON_AIC_TLB_ADDR 0x01e4
646 #define RADEON_AIC_TLB_DATA 0x01e8
648 /* CP command packets */
649 #define RADEON_CP_PACKET0 0x00000000
650 # define RADEON_ONE_REG_WR (1 << 15)
651 #define RADEON_CP_PACKET1 0x40000000
652 #define RADEON_CP_PACKET2 0x80000000
653 #define RADEON_CP_PACKET3 0xC0000000
654 # define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
655 # define RADEON_WAIT_FOR_IDLE 0x00002600
656 # define RADEON_3D_DRAW_VBUF 0x00002800
657 # define RADEON_3D_DRAW_IMMD 0x00002900
658 # define RADEON_3D_DRAW_INDX 0x00002A00
659 # define RADEON_3D_LOAD_VBPNTR 0x00002F00
660 # define RADEON_3D_CLEAR_ZMASK 0x00003200
661 # define RADEON_3D_CLEAR_HIZ 0x00003700
662 # define RADEON_CNTL_HOSTDATA_BLT 0x00009400
663 # define RADEON_CNTL_PAINT_MULTI 0x00009A00
664 # define RADEON_CNTL_BITBLT_MULTI 0x00009B00
665 # define RADEON_CNTL_SET_SCISSORS 0xC0001E00
667 #define RADEON_CP_PACKET_MASK 0xC0000000
668 #define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
669 #define RADEON_CP_PACKET0_REG_MASK 0x000007ff
670 #define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
671 #define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
673 #define RADEON_VTX_Z_PRESENT (1 << 31)
674 #define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
676 #define RADEON_PRIM_TYPE_NONE (0 << 0)
677 #define RADEON_PRIM_TYPE_POINT (1 << 0)
678 #define RADEON_PRIM_TYPE_LINE (2 << 0)
679 #define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
680 #define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
681 #define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
682 #define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
683 #define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
684 #define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
685 #define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
686 #define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
687 #define RADEON_PRIM_TYPE_MASK 0xf
688 #define RADEON_PRIM_WALK_IND (1 << 4)
689 #define RADEON_PRIM_WALK_LIST (2 << 4)
690 #define RADEON_PRIM_WALK_RING (3 << 4)
691 #define RADEON_COLOR_ORDER_BGRA (0 << 6)
692 #define RADEON_COLOR_ORDER_RGBA (1 << 6)
693 #define RADEON_MAOS_ENABLE (1 << 7)
694 #define RADEON_VTX_FMT_R128_MODE (0 << 8)
695 #define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
696 #define RADEON_NUM_VERTICES_SHIFT 16
698 #define RADEON_COLOR_FORMAT_CI8 2
699 #define RADEON_COLOR_FORMAT_ARGB1555 3
700 #define RADEON_COLOR_FORMAT_RGB565 4
701 #define RADEON_COLOR_FORMAT_ARGB8888 6
702 #define RADEON_COLOR_FORMAT_RGB332 7
703 #define RADEON_COLOR_FORMAT_RGB8 9
704 #define RADEON_COLOR_FORMAT_ARGB4444 15
706 #define RADEON_TXFORMAT_I8 0
707 #define RADEON_TXFORMAT_AI88 1
708 #define RADEON_TXFORMAT_RGB332 2
709 #define RADEON_TXFORMAT_ARGB1555 3
710 #define RADEON_TXFORMAT_RGB565 4
711 #define RADEON_TXFORMAT_ARGB4444 5
712 #define RADEON_TXFORMAT_ARGB8888 6
713 #define RADEON_TXFORMAT_RGBA8888 7
714 #define RADEON_TXFORMAT_Y8 8
715 #define RADEON_TXFORMAT_VYUY422 10
716 #define RADEON_TXFORMAT_YVYU422 11
717 #define RADEON_TXFORMAT_DXT1 12
718 #define RADEON_TXFORMAT_DXT23 14
719 #define RADEON_TXFORMAT_DXT45 15
721 #define R200_PP_TXCBLEND_0 0x2f00
722 #define R200_PP_TXCBLEND_1 0x2f10
723 #define R200_PP_TXCBLEND_2 0x2f20
724 #define R200_PP_TXCBLEND_3 0x2f30
725 #define R200_PP_TXCBLEND_4 0x2f40
726 #define R200_PP_TXCBLEND_5 0x2f50
727 #define R200_PP_TXCBLEND_6 0x2f60
728 #define R200_PP_TXCBLEND_7 0x2f70
729 #define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
730 #define R200_PP_TFACTOR_0 0x2ee0
731 #define R200_SE_VTX_FMT_0 0x2088
732 #define R200_SE_VAP_CNTL 0x2080
733 #define R200_SE_TCL_MATRIX_SEL_0 0x2230
734 #define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
735 #define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
736 #define R200_PP_TXFILTER_5 0x2ca0
737 #define R200_PP_TXFILTER_4 0x2c80
738 #define R200_PP_TXFILTER_3 0x2c60
739 #define R200_PP_TXFILTER_2 0x2c40
740 #define R200_PP_TXFILTER_1 0x2c20
741 #define R200_PP_TXFILTER_0 0x2c00
742 #define R200_PP_TXOFFSET_5 0x2d78
743 #define R200_PP_TXOFFSET_4 0x2d60
744 #define R200_PP_TXOFFSET_3 0x2d48
745 #define R200_PP_TXOFFSET_2 0x2d30
746 #define R200_PP_TXOFFSET_1 0x2d18
747 #define R200_PP_TXOFFSET_0 0x2d00
749 #define R200_PP_CUBIC_FACES_0 0x2c18
750 #define R200_PP_CUBIC_FACES_1 0x2c38
751 #define R200_PP_CUBIC_FACES_2 0x2c58
752 #define R200_PP_CUBIC_FACES_3 0x2c78
753 #define R200_PP_CUBIC_FACES_4 0x2c98
754 #define R200_PP_CUBIC_FACES_5 0x2cb8
755 #define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
756 #define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
757 #define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
758 #define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
759 #define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
760 #define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
761 #define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
762 #define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
763 #define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
764 #define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
765 #define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
766 #define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
767 #define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
768 #define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
769 #define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
770 #define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
771 #define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
772 #define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
773 #define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
774 #define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
775 #define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
776 #define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
777 #define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
778 #define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
779 #define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
780 #define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
781 #define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
782 #define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
783 #define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
784 #define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
786 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
787 #define R200_SE_VTE_CNTL 0x20b0
788 #define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
789 #define R200_PP_TAM_DEBUG3 0x2d9c
790 #define R200_PP_CNTL_X 0x2cc4
791 #define R200_SE_VAP_CNTL_STATUS 0x2140
792 #define R200_RE_SCISSOR_TL_0 0x1cd8
793 #define R200_RE_SCISSOR_TL_1 0x1ce0
794 #define R200_RE_SCISSOR_TL_2 0x1ce8
795 #define R200_RB3D_DEPTHXY_OFFSET 0x1d60
796 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
797 #define R200_SE_VTX_STATE_CNTL 0x2180
798 #define R200_RE_POINTSIZE 0x2648
799 #define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
801 #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
802 #define RADEON_PP_TEX_SIZE_1 0x1d0c
803 #define RADEON_PP_TEX_SIZE_2 0x1d14
805 #define RADEON_PP_CUBIC_FACES_0 0x1d24
806 #define RADEON_PP_CUBIC_FACES_1 0x1d28
807 #define RADEON_PP_CUBIC_FACES_2 0x1d2c
808 #define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
809 #define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
810 #define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
812 #define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
813 #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
814 #define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
815 #define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
816 #define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
817 #define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
818 #define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
819 #define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
820 #define R200_3D_DRAW_IMMD_2 0xC0003500
821 #define R200_SE_VTX_FMT_1 0x208c
822 #define R200_RE_CNTL 0x1c50
824 #define R200_RB3D_BLENDCOLOR 0x3218
826 #define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
829 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
831 #define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
832 #define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
833 #define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
834 #define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
835 #define RADEON_LAST_DISPATCH 1
837 #define RADEON_MAX_VB_AGE 0x7fffffff
838 #define RADEON_MAX_VB_VERTS (0xffff)
840 #define RADEON_RING_HIGH_MARK 128
842 #define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
843 #define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
844 #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
845 #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
847 #define RADEON_WRITE_PLL( addr, val ) \
849 RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \
850 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
851 RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \
854 extern int radeon_preinit(struct drm_device *dev, unsigned long flags);
855 extern int radeon_postcleanup(struct drm_device *dev);
857 #define CP_PACKET0( reg, n ) \
858 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
859 #define CP_PACKET0_TABLE( reg, n ) \
860 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
861 #define CP_PACKET1( reg0, reg1 ) \
862 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
863 #define CP_PACKET2() \
865 #define CP_PACKET3( pkt, n ) \
866 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
868 /* ================================================================
869 * Engine control helper macros
872 #define RADEON_WAIT_UNTIL_2D_IDLE() do { \
873 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
874 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
875 RADEON_WAIT_HOST_IDLECLEAN) ); \
878 #define RADEON_WAIT_UNTIL_3D_IDLE() do { \
879 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
880 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
881 RADEON_WAIT_HOST_IDLECLEAN) ); \
884 #define RADEON_WAIT_UNTIL_IDLE() do { \
885 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
886 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
887 RADEON_WAIT_3D_IDLECLEAN | \
888 RADEON_WAIT_HOST_IDLECLEAN) ); \
891 #define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
892 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
893 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
896 #define RADEON_FLUSH_CACHE() do { \
897 OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \
898 OUT_RING( RADEON_RB2D_DC_FLUSH ); \
901 #define RADEON_PURGE_CACHE() do { \
902 OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) ); \
903 OUT_RING( RADEON_RB2D_DC_FLUSH_ALL ); \
906 #define RADEON_FLUSH_ZCACHE() do { \
907 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
908 OUT_RING( RADEON_RB3D_ZC_FLUSH ); \
911 #define RADEON_PURGE_ZCACHE() do { \
912 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
913 OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \
916 /* ================================================================
920 /* Perfbox functionality only.
922 #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
924 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
925 u32 head = GET_RING_HEAD( dev_priv ); \
926 if (head == dev_priv->ring.tail) \
927 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
931 #define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
933 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \
934 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
935 int __ret = radeon_do_cp_idle( dev_priv ); \
936 if ( __ret ) return __ret; \
937 sarea_priv->last_dispatch = 0; \
938 radeon_freelist_reset( dev ); \
942 #define RADEON_DISPATCH_AGE( age ) do { \
943 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
947 #define RADEON_FRAME_AGE( age ) do { \
948 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
952 #define RADEON_CLEAR_AGE( age ) do { \
953 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
957 /* ================================================================
961 #define RADEON_VERBOSE 0
963 #define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring;
965 #define BEGIN_RING( n ) do { \
966 if ( RADEON_VERBOSE ) { \
967 DRM_INFO( "BEGIN_RING( %d ) in %s\n", \
970 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
972 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \
974 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
975 ring = dev_priv->ring.start; \
976 write = dev_priv->ring.tail; \
977 mask = dev_priv->ring.tail_mask; \
980 #define ADVANCE_RING() do { \
981 if ( RADEON_VERBOSE ) { \
982 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
983 write, dev_priv->ring.tail ); \
985 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
987 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
988 ((dev_priv->ring.tail + _nr) & mask), \
991 dev_priv->ring.tail = write; \
994 #define COMMIT_RING() do { \
995 /* Flush writes to ring */ \
996 DRM_MEMORYBARRIER(); \
997 GET_RING_HEAD( dev_priv ); \
998 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
999 /* read from PCI bus to ensure correct posting */ \
1000 RADEON_READ( RADEON_CP_RB_RPTR ); \
1003 #define OUT_RING( x ) do { \
1004 if ( RADEON_VERBOSE ) { \
1005 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
1006 (unsigned int)(x), write ); \
1008 ring[write++] = (x); \
1012 #define OUT_RING_REG( reg, val ) do { \
1013 OUT_RING( CP_PACKET0( reg, 0 ) ); \
1017 #define OUT_RING_TABLE( tab, sz ) do { \
1019 int *_tab = (int *)(tab); \
1021 if (write + _size > mask) { \
1022 int _i = (mask+1) - write; \
1025 *(int *)(ring + write) = *_tab++; \
1032 while (_size > 0) { \
1033 *(ring + write) = *_tab++; \
1040 #endif /* __RADEON_DRV_H__ */