1 /* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
31 #ifndef __RADEON_DRV_H__
32 #define __RADEON_DRV_H__
35 /* General customization:
38 #define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."
40 #define DRIVER_NAME "radeon"
41 #define DRIVER_DESC "ATI Radeon"
42 #define DRIVER_DATE "20080528"
47 * 1.2 - Add vertex2 ioctl (keith)
48 * - Add stencil capability to clear ioctl (gareth, keith)
49 * - Increase MAX_TEXTURE_LEVELS (brian)
50 * 1.3 - Add cmdbuf ioctl (keith)
51 * - Add support for new radeon packets (keith)
52 * - Add getparam ioctl (keith)
53 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
54 * 1.4 - Add scratch registers to get_param ioctl.
55 * 1.5 - Add r200 packets to cmdbuf ioctl
56 * - Add r200 function to init ioctl
57 * - Add 'scalar2' instruction to cmdbuf
58 * 1.6 - Add static GART memory manager
59 * Add irq handler (won't be turned on unless X server knows to)
60 * Add irq ioctls and irq_active getparam.
61 * Add wait command for cmdbuf ioctl
62 * Add GART offset query for getparam
63 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
64 * and R200_PP_CUBIC_OFFSET_F1_[0..5].
65 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
66 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian)
67 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
68 * Add 'GET' queries for starting additional clients on different VT's.
69 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
70 * Add texture rectangle support for r100.
71 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
72 * clients use to tell the DRM where they think the framebuffer is
73 * located in the card's address space
74 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
75 * and GL_EXT_blend_[func|equation]_separate on r200
76 * 1.12- Add R300 CP microcode support - this just loads the CP on r300
77 * (No 3D support yet - just microcode loading).
78 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
79 * - Add hyperz support, add hyperz flags to clear ioctl.
80 * 1.14- Add support for color tiling
81 * - Add R100/R200 surface allocation/free support
82 * 1.15- Add support for texture micro tiling
83 * - Add support for r100 cube maps
84 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear
85 * texture filtering on r200
86 * 1.17- Add initial support for R300 (3D).
87 * 1.18- Add support for GL_ATI_fragment_shader, new packets
88 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces
89 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR
90 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6)
91 * 1.19- Add support for gart table in FB memory and PCIE r300
92 * 1.20- Add support for r300 texrect
93 * 1.21- Add support for card type getparam
94 * 1.22- Add support for texture cache flushes (R300_TX_CNTL)
95 * 1.23- Add new radeon memory map work from benh
96 * 1.24- Add general-purpose packet for manipulating scratch registers (r300)
97 * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL,
99 * 1.26- Add support for variable size PCI(E) gart aperture
100 * 1.27- Add support for IGPGART
101 * 1.28- Add support for VBL on CRTC2
102 * 1.29- R500 3D cmd buffer support
105 #define DRIVER_MAJOR 1
106 #define DRIVER_MINOR 30
107 #define DRIVER_PATCHLEVEL 0
110 * Radeon chip families
154 enum radeon_chip_flags {
155 RADEON_FAMILY_MASK = 0x0000ffffUL,
156 RADEON_FLAGS_MASK = 0xffff0000UL,
157 RADEON_IS_MOBILITY = 0x00010000UL,
158 RADEON_IS_IGP = 0x00020000UL,
159 RADEON_SINGLE_CRTC = 0x00040000UL,
160 RADEON_IS_AGP = 0x00080000UL,
161 RADEON_HAS_HIERZ = 0x00100000UL,
162 RADEON_IS_PCIE = 0x00200000UL,
163 RADEON_NEW_MEMMAP = 0x00400000UL,
164 RADEON_IS_PCI = 0x00800000UL,
165 RADEON_IS_IGPGART = 0x01000000UL,
171 enum radeon_pll_errata {
172 CHIP_ERRATA_R300_CG = 0x00000001,
173 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
174 CHIP_ERRATA_PLL_DELAY = 0x00000004
177 enum radeon_ext_tmds_chip {
183 #if defined(__powerpc__)
184 enum radeon_mac_model {
187 RADEON_MAC_POWERBOOK_EXTERNAL,
188 RADEON_MAC_POWERBOOK_INTERNAL,
189 RADEON_MAC_POWERBOOK_VGA,
190 RADEON_MAC_MINI_EXTERNAL,
191 RADEON_MAC_MINI_INTERNAL,
192 RADEON_MAC_IMAC_G5_ISIGHT
197 #define GET_RING_HEAD(dev_priv) (dev_priv->writeback_works ? \
198 (dev_priv->mm.ring_read_ptr ? readl(dev_priv->mm.ring_read_ptr_map.virtual + 0) : DRM_READ32((dev_priv)->ring_rptr, 0 )) : \
199 RADEON_READ(RADEON_CP_RB_RPTR))
201 #define SET_RING_HEAD(dev_priv,val) (dev_priv->mm.ring_read_ptr ? \
202 writel((val), dev_priv->mm.ring_read_ptr_map.virtual) : \
203 DRM_WRITE32((dev_priv)->ring_rptr, 0, (val)))
205 typedef struct drm_radeon_freelist {
208 struct drm_radeon_freelist *next;
209 struct drm_radeon_freelist *prev;
210 } drm_radeon_freelist_t;
212 typedef struct drm_radeon_ring_buffer {
215 int size; /* Double Words */
216 int size_l2qw; /* log2 Quad Words */
218 int rptr_update; /* Double Words */
219 int rptr_update_l2qw; /* log2 Quad Words */
221 int fetch_size; /* Double Words */
222 int fetch_size_l2ow; /* log2 Oct Words */
229 } drm_radeon_ring_buffer_t;
231 typedef struct drm_radeon_depth_clear_t {
233 u32 rb3d_zstencilcntl;
235 } drm_radeon_depth_clear_t;
237 struct drm_radeon_driver_file_fields {
238 int64_t radeon_fb_delta;
242 struct mem_block *next;
243 struct mem_block *prev;
246 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
249 struct radeon_surface {
256 struct radeon_virt_surface {
261 struct drm_file *file_priv;
264 struct radeon_mm_info {
265 uint64_t vram_offset; // Offset into GPU space
267 uint64_t vram_visible;
272 struct drm_buffer_object *pcie_table;
273 struct drm_bo_kmap_obj pcie_table_map;
275 struct drm_buffer_object *ring;
276 struct drm_bo_kmap_obj ring_map;
278 struct drm_buffer_object *ring_read_ptr;
279 struct drm_bo_kmap_obj ring_read_ptr_map;
282 #include "radeon_mode.h"
284 struct drm_radeon_master_private {
285 drm_local_map_t *sarea;
286 drm_radeon_sarea_t *sarea_priv;
289 typedef struct drm_radeon_private {
291 drm_radeon_ring_buffer_t ring;
297 unsigned long gart_buffers_offset;
302 drm_radeon_freelist_t *head;
303 drm_radeon_freelist_t *tail;
305 volatile u32 *scratch;
312 int freelist_timeouts;
315 int last_frame_reads;
316 int last_clear_reads;
325 unsigned int front_offset;
326 unsigned int front_pitch;
327 unsigned int back_offset;
328 unsigned int back_pitch;
331 unsigned int depth_offset;
332 unsigned int depth_pitch;
334 u32 front_pitch_offset;
335 u32 back_pitch_offset;
336 u32 depth_pitch_offset;
338 drm_radeon_depth_clear_t depth_clear;
340 unsigned long ring_offset;
341 unsigned long ring_rptr_offset;
342 unsigned long buffers_offset;
343 unsigned long gart_textures_offset;
345 drm_local_map_t *cp_ring;
346 drm_local_map_t *ring_rptr;
347 drm_local_map_t *gart_textures;
349 struct mem_block *gart_heap;
350 struct mem_block *fb_heap;
354 wait_queue_head_t swi_queue;
356 uint32_t irq_enable_reg;
358 uint32_t r500_disp_irq_reg;
360 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
361 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
366 unsigned int crtc_last_cnt;
367 unsigned int crtc2_last_cnt;
369 /* starting from here on, data is preserved accross an open */
370 uint32_t flags; /* see radeon_chip_flags */
371 unsigned long fb_aper_offset;
375 struct radeon_mm_info mm;
376 drm_local_map_t *mmio;
378 uint32_t chip_family;
380 unsigned long pcigart_offset;
381 unsigned int pcigart_offset_set;
382 struct drm_ati_pcigart_info gart_info;
384 struct radeon_mode_info mode_info;
386 uint8_t *bios; /* copy of the BIOS image */
388 uint16_t bios_header_start;
394 enum radeon_pll_errata pll_errata;
396 } drm_radeon_private_t;
398 typedef struct drm_radeon_buf_priv {
400 } drm_radeon_buf_priv_t;
402 typedef struct drm_radeon_kcmd_buffer {
406 struct drm_clip_rect __user *boxes;
407 } drm_radeon_kcmd_buffer_t;
409 extern int radeon_no_wb;
410 extern int radeon_dynclks;
411 extern struct drm_ioctl_desc radeon_ioctls[];
412 extern int radeon_max_ioctl;
414 /* Check whether the given hardware address is inside the framebuffer or the
417 static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv,
420 u32 fb_start = dev_priv->fb_location;
421 u32 fb_end = fb_start + dev_priv->fb_size - 1;
422 u32 gart_start = dev_priv->gart_vm_start;
423 u32 gart_end = gart_start + dev_priv->gart_size - 1;
425 return ((off >= fb_start && off <= fb_end) ||
426 (off >= gart_start && off <= gart_end));
430 extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv);
431 extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv);
432 extern int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv);
433 extern int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
434 extern int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv);
435 extern int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv);
436 extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
437 extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv);
438 extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv);
439 extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv);
441 extern void radeon_freelist_reset(struct drm_device * dev);
442 extern struct drm_buf *radeon_freelist_get(struct drm_device * dev);
444 extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
446 extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv);
448 extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv);
449 extern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv);
450 extern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv);
451 extern void radeon_mem_takedown(struct mem_block **heap);
452 extern void radeon_mem_release(struct drm_file *file_priv,
453 struct mem_block *heap);
456 extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv);
457 extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv);
459 extern void radeon_do_release(struct drm_device * dev);
460 extern u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc);
461 extern int radeon_enable_vblank(struct drm_device *dev, int crtc);
462 extern void radeon_disable_vblank(struct drm_device *dev, int crtc);
463 extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
464 extern void radeon_driver_irq_preinstall(struct drm_device * dev);
465 extern int radeon_driver_irq_postinstall(struct drm_device * dev);
466 extern void radeon_driver_irq_uninstall(struct drm_device * dev);
467 extern int radeon_vblank_crtc_get(struct drm_device *dev);
468 extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
470 extern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
471 extern int radeon_driver_unload(struct drm_device *dev);
472 extern int radeon_driver_firstopen(struct drm_device *dev);
473 extern void radeon_driver_preclose(struct drm_device * dev,
474 struct drm_file *file_priv);
475 extern void radeon_driver_postclose(struct drm_device * dev,
476 struct drm_file *file_priv);
477 extern void radeon_driver_lastclose(struct drm_device * dev);
478 extern int radeon_driver_open(struct drm_device * dev,
479 struct drm_file * file_priv);
480 extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
484 extern void r300_init_reg_flags(struct drm_device *dev);
486 extern int r300_do_cp_cmdbuf(struct drm_device *dev,
487 struct drm_file *file_priv,
488 drm_radeon_kcmd_buffer_t *cmdbuf);
490 /* Flags for stats.boxes
492 #define RADEON_BOX_DMA_IDLE 0x1
493 #define RADEON_BOX_RING_FULL 0x2
494 #define RADEON_BOX_FLIP 0x4
495 #define RADEON_BOX_WAIT_IDLE 0x8
496 #define RADEON_BOX_TEXTURE_LOAD 0x10
498 #define R600_CONFIG_MEMSIZE 0x5428
499 #define R600_CONFIG_APER_SIZE 0x5430
500 /* Register definitions, register access macros and drmAddMap constants
501 * for Radeon kernel driver.
504 #include "radeon_reg.h"
506 #define RADEON_AGP_COMMAND 0x0f60
507 #define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
508 # define RADEON_AGP_ENABLE (1<<8)
509 #define RADEON_AUX_SCISSOR_CNTL 0x26f0
510 # define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
511 # define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
512 # define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
513 # define RADEON_SCISSOR_0_ENABLE (1 << 28)
514 # define RADEON_SCISSOR_1_ENABLE (1 << 29)
515 # define RADEON_SCISSOR_2_ENABLE (1 << 30)
517 #define RADEON_BUS_CNTL 0x0030
518 # define RADEON_BUS_MASTER_DIS (1 << 6)
520 #define RADEON_CLOCK_CNTL_DATA 0x000c
521 # define RADEON_PLL_WR_EN (1 << 7)
522 #define RADEON_CLOCK_CNTL_INDEX 0x0008
523 #define RADEON_CONFIG_APER_SIZE 0x0108
524 #define RADEON_CONFIG_MEMSIZE 0x00f8
525 #define RADEON_CRTC_OFFSET 0x0224
526 #define RADEON_CRTC_OFFSET_CNTL 0x0228
527 # define RADEON_CRTC_TILE_EN (1 << 15)
528 # define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
529 #define RADEON_CRTC2_OFFSET 0x0324
530 #define RADEON_CRTC2_OFFSET_CNTL 0x0328
532 #define RADEON_PCIE_INDEX 0x0030
533 #define RADEON_PCIE_DATA 0x0034
534 #define RADEON_PCIE_TX_GART_CNTL 0x10
535 # define RADEON_PCIE_TX_GART_EN (1 << 0)
536 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1)
537 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1)
538 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1)
539 # define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3)
540 # define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3)
541 # define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5)
542 # define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8)
543 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
544 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
545 #define RADEON_PCIE_TX_GART_BASE 0x13
546 #define RADEON_PCIE_TX_GART_START_LO 0x14
547 #define RADEON_PCIE_TX_GART_START_HI 0x15
548 #define RADEON_PCIE_TX_GART_END_LO 0x16
549 #define RADEON_PCIE_TX_GART_END_HI 0x17
551 #define RS480_NB_MC_INDEX 0x168
552 # define RS480_NB_MC_IND_WR_EN (1 << 8)
553 #define RS480_NB_MC_DATA 0x16c
555 #define RS690_MC_INDEX 0x78
556 # define RS690_MC_INDEX_MASK 0x1ff
557 # define RS690_MC_INDEX_WR_EN (1 << 9)
558 # define RS690_MC_INDEX_WR_ACK 0x7f
559 #define RS690_MC_DATA 0x7c
561 /* MC indirect registers */
562 #define RS480_MC_MISC_CNTL 0x18
563 # define RS480_DISABLE_GTW (1 << 1)
564 /* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */
565 # define RS480_GART_INDEX_REG_EN (1 << 12)
566 # define RS690_BLOCK_GFX_D3_EN (1 << 14)
567 #define RS480_K8_FB_LOCATION 0x1e
568 #define RS480_GART_FEATURE_ID 0x2b
569 # define RS480_HANG_EN (1 << 11)
570 # define RS480_TLB_ENABLE (1 << 18)
571 # define RS480_P2P_ENABLE (1 << 19)
572 # define RS480_GTW_LAC_EN (1 << 25)
573 # define RS480_2LEVEL_GART (0 << 30)
574 # define RS480_1LEVEL_GART (1 << 30)
575 # define RS480_PDC_EN (1 << 31)
576 #define RS480_GART_BASE 0x2c
577 #define RS480_GART_CACHE_CNTRL 0x2e
578 # define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */
579 #define RS480_AGP_ADDRESS_SPACE_SIZE 0x38
580 # define RS480_GART_EN (1 << 0)
581 # define RS480_VA_SIZE_32MB (0 << 1)
582 # define RS480_VA_SIZE_64MB (1 << 1)
583 # define RS480_VA_SIZE_128MB (2 << 1)
584 # define RS480_VA_SIZE_256MB (3 << 1)
585 # define RS480_VA_SIZE_512MB (4 << 1)
586 # define RS480_VA_SIZE_1GB (5 << 1)
587 # define RS480_VA_SIZE_2GB (6 << 1)
588 #define RS480_AGP_MODE_CNTL 0x39
589 # define RS480_POST_GART_Q_SIZE (1 << 18)
590 # define RS480_NONGART_SNOOP (1 << 19)
591 # define RS480_AGP_RD_BUF_SIZE (1 << 20)
592 # define RS480_REQ_TYPE_SNOOP_SHIFT 22
593 # define RS480_REQ_TYPE_SNOOP_MASK 0x3
594 # define RS480_REQ_TYPE_SNOOP_DIS (1 << 24)
595 #define RS480_MC_MISC_UMA_CNTL 0x5f
596 #define RS480_MC_MCLK_CNTL 0x7a
597 #define RS480_MC_UMA_DUALCH_CNTL 0x86
599 #define RS690_MC_FB_LOCATION 0x100
600 #define RS690_MC_AGP_LOCATION 0x101
601 #define RS690_MC_AGP_BASE 0x102
602 #define RS690_MC_AGP_BASE_2 0x103
604 #define R520_MC_IND_INDEX 0x70
605 #define R520_MC_IND_WR_EN (1 << 24)
606 #define R520_MC_IND_DATA 0x74
608 #define RADEON_MPP_TB_CONFIG 0x01c0
609 #define RADEON_MEM_CNTL 0x0140
610 #define RADEON_MEM_SDRAM_MODE_REG 0x0158
611 #define RADEON_AGP_BASE_2 0x015c /* r200+ only */
612 #define RS480_AGP_BASE_2 0x0164
613 #define RADEON_AGP_BASE 0x0170
615 /* pipe config regs */
616 #define R400_GB_PIPE_SELECT 0x402c
617 #define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */
618 #define R500_SU_REG_DEST 0x42c8
619 #define R300_GB_TILE_CONFIG 0x4018
620 # define R300_ENABLE_TILING (1 << 0)
621 # define R300_PIPE_COUNT_RV350 (0 << 1)
622 # define R300_PIPE_COUNT_R300 (3 << 1)
623 # define R300_PIPE_COUNT_R420_3P (6 << 1)
624 # define R300_PIPE_COUNT_R420 (7 << 1)
625 # define R300_TILE_SIZE_8 (0 << 4)
626 # define R300_TILE_SIZE_16 (1 << 4)
627 # define R300_TILE_SIZE_32 (2 << 4)
628 # define R300_SUBPIXEL_1_12 (0 << 16)
629 # define R300_SUBPIXEL_1_16 (1 << 16)
630 #define R300_DST_PIPE_CONFIG 0x170c
631 # define R300_PIPE_AUTO_CONFIG (1 << 31)
632 #define R300_RB2D_DSTCACHE_MODE 0x3428
633 # define R300_DC_AUTOFLUSH_ENABLE (1 << 8)
634 # define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17)
636 #define RADEON_RB3D_COLOROFFSET 0x1c40
637 #define RADEON_RB3D_COLORPITCH 0x1c48
639 #define RADEON_SRC_X_Y 0x1590
641 #define RADEON_DP_GUI_MASTER_CNTL 0x146c
642 # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
643 # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
644 # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
645 # define RADEON_GMC_BRUSH_NONE (15 << 4)
646 # define RADEON_GMC_DST_16BPP (4 << 8)
647 # define RADEON_GMC_DST_24BPP (5 << 8)
648 # define RADEON_GMC_DST_32BPP (6 << 8)
649 # define RADEON_GMC_DST_DATATYPE_SHIFT 8
650 # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
651 # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
652 # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
653 # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
654 # define RADEON_GMC_WR_MSK_DIS (1 << 30)
655 # define RADEON_ROP3_S 0x00cc0000
656 # define RADEON_ROP3_P 0x00f00000
657 #define RADEON_DP_WRITE_MASK 0x16cc
658 #define RADEON_SRC_PITCH_OFFSET 0x1428
659 #define RADEON_DST_PITCH_OFFSET 0x142c
660 #define RADEON_DST_PITCH_OFFSET_C 0x1c80
661 # define RADEON_DST_TILE_LINEAR (0 << 30)
662 # define RADEON_DST_TILE_MACRO (1 << 30)
663 # define RADEON_DST_TILE_MICRO (2 << 30)
664 # define RADEON_DST_TILE_BOTH (3 << 30)
666 #define RADEON_SCRATCH_REG0 0x15e0
667 #define RADEON_SCRATCH_REG1 0x15e4
668 #define RADEON_SCRATCH_REG2 0x15e8
669 #define RADEON_SCRATCH_REG3 0x15ec
670 #define RADEON_SCRATCH_REG4 0x15f0
671 #define RADEON_SCRATCH_REG5 0x15f4
672 #define RADEON_SCRATCH_UMSK 0x0770
673 #define RADEON_SCRATCH_ADDR 0x0774
675 #define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
677 #define GET_SCRATCH( x ) (dev_priv->writeback_works ? \
678 (dev_priv->mm.ring_read_ptr ? \
679 readl(dev_priv->mm.ring_read_ptr_map.virtual + RADEON_SCRATCHOFF(0)) : \
680 DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(x))) : \
681 RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x)))
683 #define RADEON_CRTC_CRNT_FRAME 0x0214
684 #define RADEON_CRTC2_CRNT_FRAME 0x0314
686 #define RADEON_CRTC_STATUS 0x005c
687 #define RADEON_CRTC2_STATUS 0x03fc
689 #define RADEON_GEN_INT_CNTL 0x0040
690 # define RADEON_CRTC_VBLANK_MASK (1 << 0)
691 # define RADEON_CRTC2_VBLANK_MASK (1 << 9)
692 # define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
693 # define RADEON_SW_INT_ENABLE (1 << 25)
695 #define RADEON_GEN_INT_STATUS 0x0044
696 # define RADEON_CRTC_VBLANK_STAT (1 << 0)
697 # define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
698 # define RADEON_CRTC2_VBLANK_STAT (1 << 9)
699 # define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)
700 # define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
701 # define RADEON_SW_INT_TEST (1 << 25)
702 # define RADEON_SW_INT_TEST_ACK (1 << 25)
703 # define RADEON_SW_INT_FIRE (1 << 26)
704 # define R500_DISPLAY_INT_STATUS (1 << 0)
706 #define RADEON_HOST_PATH_CNTL 0x0130
707 # define RADEON_HDP_SOFT_RESET (1 << 26)
708 # define RADEON_HDP_APER_CNTL (1 << 23)
710 #define RADEON_NB_TOM 0x15c
712 #define RADEON_ISYNC_CNTL 0x1724
713 # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
714 # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
715 # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
716 # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
717 # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
718 # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
720 #define RADEON_RBBM_GUICNTL 0x172c
721 # define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
722 # define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
723 # define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
724 # define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
726 #define RADEON_MC_AGP_LOCATION 0x014c
727 #define RADEON_MC_FB_LOCATION 0x0148
728 #define RADEON_MCLK_CNTL 0x0012
729 # define RADEON_FORCEON_MCLKA (1 << 16)
730 # define RADEON_FORCEON_MCLKB (1 << 17)
731 # define RADEON_FORCEON_YCLKA (1 << 18)
732 # define RADEON_FORCEON_YCLKB (1 << 19)
733 # define RADEON_FORCEON_MC (1 << 20)
734 # define RADEON_FORCEON_AIC (1 << 21)
736 #define RADEON_PP_BORDER_COLOR_0 0x1d40
737 #define RADEON_PP_BORDER_COLOR_1 0x1d44
738 #define RADEON_PP_BORDER_COLOR_2 0x1d48
739 #define RADEON_PP_CNTL 0x1c38
740 # define RADEON_SCISSOR_ENABLE (1 << 1)
741 #define RADEON_PP_LUM_MATRIX 0x1d00
742 #define RADEON_PP_MISC 0x1c14
743 #define RADEON_PP_ROT_MATRIX_0 0x1d58
744 #define RADEON_PP_TXFILTER_0 0x1c54
745 #define RADEON_PP_TXOFFSET_0 0x1c5c
746 #define RADEON_PP_TXFILTER_1 0x1c6c
747 #define RADEON_PP_TXFILTER_2 0x1c84
749 #define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
750 # define RADEON_RB2D_DC_FLUSH (3 << 0)
751 # define RADEON_RB2D_DC_FREE (3 << 2)
752 # define RADEON_RB2D_DC_FLUSH_ALL 0xf
753 # define RADEON_RB2D_DC_BUSY (1 << 31)
754 #define RADEON_RB3D_CNTL 0x1c3c
755 # define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
756 # define RADEON_PLANE_MASK_ENABLE (1 << 1)
757 # define RADEON_DITHER_ENABLE (1 << 2)
758 # define RADEON_ROUND_ENABLE (1 << 3)
759 # define RADEON_SCALE_DITHER_ENABLE (1 << 4)
760 # define RADEON_DITHER_INIT (1 << 5)
761 # define RADEON_ROP_ENABLE (1 << 6)
762 # define RADEON_STENCIL_ENABLE (1 << 7)
763 # define RADEON_Z_ENABLE (1 << 8)
764 # define RADEON_ZBLOCK16 (1 << 15)
765 #define RADEON_RB3D_DEPTHOFFSET 0x1c24
766 #define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
767 #define RADEON_RB3D_DEPTHPITCH 0x1c28
768 #define RADEON_RB3D_PLANEMASK 0x1d84
769 #define RADEON_RB3D_STENCILREFMASK 0x1d7c
770 #define RADEON_RB3D_ZCACHE_MODE 0x3250
771 #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
772 # define RADEON_RB3D_ZC_FLUSH (1 << 0)
773 # define RADEON_RB3D_ZC_FREE (1 << 2)
774 # define RADEON_RB3D_ZC_FLUSH_ALL 0x5
775 # define RADEON_RB3D_ZC_BUSY (1 << 31)
776 #define R300_ZB_ZCACHE_CTLSTAT 0x4f18
777 # define R300_ZC_FLUSH (1 << 0)
778 # define R300_ZC_FREE (1 << 1)
779 # define R300_ZC_FLUSH_ALL 0x3
780 # define R300_ZC_BUSY (1 << 31)
781 #define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
782 # define R300_RB3D_DC_FINISH (1 << 4)
783 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
784 # define RADEON_Z_TEST_MASK (7 << 4)
785 # define RADEON_Z_TEST_ALWAYS (7 << 4)
786 # define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
787 # define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
788 # define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
789 # define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
790 # define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
791 # define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
792 # define RADEON_FORCE_Z_DIRTY (1 << 29)
793 # define RADEON_Z_WRITE_ENABLE (1 << 30)
794 # define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
795 #define RADEON_RBBM_SOFT_RESET 0x00f0
796 # define RADEON_SOFT_RESET_CP (1 << 0)
797 # define RADEON_SOFT_RESET_HI (1 << 1)
798 # define RADEON_SOFT_RESET_SE (1 << 2)
799 # define RADEON_SOFT_RESET_RE (1 << 3)
800 # define RADEON_SOFT_RESET_PP (1 << 4)
801 # define RADEON_SOFT_RESET_E2 (1 << 5)
802 # define RADEON_SOFT_RESET_RB (1 << 6)
803 # define RADEON_SOFT_RESET_HDP (1 << 7)
805 * 6:0 Available slots in the FIFO
806 * 8 Host Interface active
807 * 9 CP request active
808 * 10 FIFO request active
809 * 11 Host Interface retry active
811 * 13 FIFO retry active
812 * 14 FIFO pipeline busy
813 * 15 Event engine busy
814 * 16 CP command stream busy
816 * 18 2D portion of render backend busy
817 * 20 3D setup engine busy
819 * 27 CBA 2D engine busy
820 * 31 2D engine busy or 3D engine busy or FIFO not empty or CP busy or
821 * command stream queue not empty or Ring Buffer not empty
823 #define RADEON_RBBM_STATUS 0x0e40
824 /* Same as the previous RADEON_RBBM_STATUS; this is a mirror of that register. */
825 /* #define RADEON_RBBM_STATUS 0x1740 */
826 /* bits 6:0 are dword slots available in the cmd fifo */
827 # define RADEON_RBBM_FIFOCNT_MASK 0x007f
828 # define RADEON_HIRQ_ON_RBB (1 << 8)
829 # define RADEON_CPRQ_ON_RBB (1 << 9)
830 # define RADEON_CFRQ_ON_RBB (1 << 10)
831 # define RADEON_HIRQ_IN_RTBUF (1 << 11)
832 # define RADEON_CPRQ_IN_RTBUF (1 << 12)
833 # define RADEON_CFRQ_IN_RTBUF (1 << 13)
834 # define RADEON_PIPE_BUSY (1 << 14)
835 # define RADEON_ENG_EV_BUSY (1 << 15)
836 # define RADEON_CP_CMDSTRM_BUSY (1 << 16)
837 # define RADEON_E2_BUSY (1 << 17)
838 # define RADEON_RB2D_BUSY (1 << 18)
839 # define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */
840 # define RADEON_VAP_BUSY (1 << 20)
841 # define RADEON_RE_BUSY (1 << 21) /* not used on r300 */
842 # define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */
843 # define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */
844 # define RADEON_PB_BUSY (1 << 24) /* not used on r300 */
845 # define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */
846 # define RADEON_GA_BUSY (1 << 26)
847 # define RADEON_CBA2D_BUSY (1 << 27)
848 # define RADEON_RBBM_ACTIVE (1 << 31)
849 #define RADEON_RE_LINE_PATTERN 0x1cd0
850 #define RADEON_RE_MISC 0x26c4
851 #define RADEON_RE_TOP_LEFT 0x26c0
852 #define RADEON_RE_WIDTH_HEIGHT 0x1c44
853 #define RADEON_RE_STIPPLE_ADDR 0x1cc8
854 #define RADEON_RE_STIPPLE_DATA 0x1ccc
856 #define RADEON_SCISSOR_TL_0 0x1cd8
857 #define RADEON_SCISSOR_BR_0 0x1cdc
858 #define RADEON_SCISSOR_TL_1 0x1ce0
859 #define RADEON_SCISSOR_BR_1 0x1ce4
860 #define RADEON_SCISSOR_TL_2 0x1ce8
861 #define RADEON_SCISSOR_BR_2 0x1cec
862 #define RADEON_SE_COORD_FMT 0x1c50
863 #define RADEON_SE_CNTL 0x1c4c
864 # define RADEON_FFACE_CULL_CW (0 << 0)
865 # define RADEON_BFACE_SOLID (3 << 1)
866 # define RADEON_FFACE_SOLID (3 << 3)
867 # define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
868 # define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
869 # define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
870 # define RADEON_ALPHA_SHADE_FLAT (1 << 10)
871 # define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
872 # define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
873 # define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
874 # define RADEON_FOG_SHADE_FLAT (1 << 14)
875 # define RADEON_FOG_SHADE_GOURAUD (2 << 14)
876 # define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
877 # define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
878 # define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
879 # define RADEON_ROUND_MODE_TRUNC (0 << 28)
880 # define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
881 #define RADEON_SE_CNTL_STATUS 0x2140
882 #define RADEON_SE_LINE_WIDTH 0x1db8
883 #define RADEON_SE_VPORT_XSCALE 0x1d98
884 #define RADEON_SE_ZBIAS_FACTOR 0x1db0
885 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
886 #define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
887 #define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
888 # define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
889 # define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
890 #define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
891 #define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
892 # define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
893 #define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
894 #define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
895 #define RADEON_SURFACE_ACCESS_CLR 0x0bfc
896 #define RADEON_SURFACE_CNTL 0x0b00
897 # define RADEON_SURF_TRANSLATION_DIS (1 << 8)
898 # define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
899 # define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
900 # define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
901 # define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
902 # define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
903 # define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
904 # define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
905 # define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
906 #define RADEON_SURFACE0_INFO 0x0b0c
907 # define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
908 # define RADEON_SURF_TILE_MODE_MASK (3 << 16)
909 # define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
910 # define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
911 # define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
912 # define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
913 #define RADEON_SURFACE0_LOWER_BOUND 0x0b04
914 #define RADEON_SURFACE0_UPPER_BOUND 0x0b08
915 # define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0)
916 #define RADEON_SURFACE1_INFO 0x0b1c
917 #define RADEON_SURFACE1_LOWER_BOUND 0x0b14
918 #define RADEON_SURFACE1_UPPER_BOUND 0x0b18
919 #define RADEON_SURFACE2_INFO 0x0b2c
920 #define RADEON_SURFACE2_LOWER_BOUND 0x0b24
921 #define RADEON_SURFACE2_UPPER_BOUND 0x0b28
922 #define RADEON_SURFACE3_INFO 0x0b3c
923 #define RADEON_SURFACE3_LOWER_BOUND 0x0b34
924 #define RADEON_SURFACE3_UPPER_BOUND 0x0b38
925 #define RADEON_SURFACE4_INFO 0x0b4c
926 #define RADEON_SURFACE4_LOWER_BOUND 0x0b44
927 #define RADEON_SURFACE4_UPPER_BOUND 0x0b48
928 #define RADEON_SURFACE5_INFO 0x0b5c
929 #define RADEON_SURFACE5_LOWER_BOUND 0x0b54
930 #define RADEON_SURFACE5_UPPER_BOUND 0x0b58
931 #define RADEON_SURFACE6_INFO 0x0b6c
932 #define RADEON_SURFACE6_LOWER_BOUND 0x0b64
933 #define RADEON_SURFACE6_UPPER_BOUND 0x0b68
934 #define RADEON_SURFACE7_INFO 0x0b7c
935 #define RADEON_SURFACE7_LOWER_BOUND 0x0b74
936 #define RADEON_SURFACE7_UPPER_BOUND 0x0b78
937 #define RADEON_SW_SEMAPHORE 0x013c
939 #define RADEON_WAIT_UNTIL 0x1720
940 # define RADEON_WAIT_CRTC_PFLIP (1 << 0)
941 # define RADEON_WAIT_2D_IDLE (1 << 14)
942 # define RADEON_WAIT_3D_IDLE (1 << 15)
943 # define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
944 # define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
945 # define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
947 #define RADEON_RB3D_ZMASKOFFSET 0x3234
948 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
949 # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
950 # define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
953 #define RADEON_CP_ME_RAM_ADDR 0x07d4
954 #define RADEON_CP_ME_RAM_RADDR 0x07d8
955 #define RADEON_CP_ME_RAM_DATAH 0x07dc
956 #define RADEON_CP_ME_RAM_DATAL 0x07e0
958 #define RADEON_CP_RB_BASE 0x0700
959 #define RADEON_CP_RB_CNTL 0x0704
960 # define RADEON_BUF_SWAP_32BIT (2 << 16)
961 # define RADEON_RB_NO_UPDATE (1 << 27)
962 #define RADEON_CP_RB_RPTR_ADDR 0x070c
963 #define RADEON_CP_RB_RPTR 0x0710
964 #define RADEON_CP_RB_WPTR 0x0714
966 #define RADEON_CP_RB_WPTR_DELAY 0x0718
967 # define RADEON_PRE_WRITE_TIMER_SHIFT 0
968 # define RADEON_PRE_WRITE_LIMIT_SHIFT 23
970 #define RADEON_CP_IB_BASE 0x0738
972 #define RADEON_CP_CSQ_CNTL 0x0740
973 # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
974 # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
975 # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
976 # define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
977 # define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
978 # define RADEON_CSQ_PRIBM_INDBM (4 << 28)
979 # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
981 #define RADEON_AIC_CNTL 0x01d0
982 # define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
983 #define RADEON_AIC_STAT 0x01d4
984 #define RADEON_AIC_PT_BASE 0x01d8
985 #define RADEON_AIC_LO_ADDR 0x01dc
986 #define RADEON_AIC_HI_ADDR 0x01e0
987 #define RADEON_AIC_TLB_ADDR 0x01e4
988 #define RADEON_AIC_TLB_DATA 0x01e8
990 /* CP command packets */
991 #define RADEON_CP_PACKET0 0x00000000
992 # define RADEON_ONE_REG_WR (1 << 15)
993 #define RADEON_CP_PACKET1 0x40000000
994 #define RADEON_CP_PACKET2 0x80000000
995 #define RADEON_CP_PACKET3 0xC0000000
996 # define RADEON_CP_NOP 0x00001000
997 # define RADEON_CP_NEXT_CHAR 0x00001900
998 # define RADEON_CP_PLY_NEXTSCAN 0x00001D00
999 # define RADEON_CP_SET_SCISSORS 0x00001E00
1000 /* GEN_INDX_PRIM is unsupported starting with R300 */
1001 # define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
1002 # define RADEON_WAIT_FOR_IDLE 0x00002600
1003 # define RADEON_3D_DRAW_VBUF 0x00002800
1004 # define RADEON_3D_DRAW_IMMD 0x00002900
1005 # define RADEON_3D_DRAW_INDX 0x00002A00
1006 # define RADEON_CP_LOAD_PALETTE 0x00002C00
1007 # define RADEON_3D_LOAD_VBPNTR 0x00002F00
1008 # define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000
1009 # define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100
1010 # define RADEON_3D_CLEAR_ZMASK 0x00003200
1011 # define RADEON_CP_INDX_BUFFER 0x00003300
1012 # define RADEON_CP_3D_DRAW_VBUF_2 0x00003400
1013 # define RADEON_CP_3D_DRAW_IMMD_2 0x00003500
1014 # define RADEON_CP_3D_DRAW_INDX_2 0x00003600
1015 # define RADEON_3D_CLEAR_HIZ 0x00003700
1016 # define RADEON_CP_3D_CLEAR_CMASK 0x00003802
1017 # define RADEON_CNTL_HOSTDATA_BLT 0x00009400
1018 # define RADEON_CNTL_PAINT_MULTI 0x00009A00
1019 # define RADEON_CNTL_BITBLT_MULTI 0x00009B00
1020 # define RADEON_CNTL_SET_SCISSORS 0xC0001E00
1022 #define RADEON_CP_PACKET_MASK 0xC0000000
1023 #define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
1024 #define RADEON_CP_PACKET0_REG_MASK 0x000007ff
1025 #define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
1026 #define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
1028 #define RADEON_VTX_Z_PRESENT (1 << 31)
1029 #define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
1031 #define RADEON_PRIM_TYPE_NONE (0 << 0)
1032 #define RADEON_PRIM_TYPE_POINT (1 << 0)
1033 #define RADEON_PRIM_TYPE_LINE (2 << 0)
1034 #define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
1035 #define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
1036 #define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
1037 #define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
1038 #define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
1039 #define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
1040 #define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
1041 #define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
1042 #define RADEON_PRIM_TYPE_MASK 0xf
1043 #define RADEON_PRIM_WALK_IND (1 << 4)
1044 #define RADEON_PRIM_WALK_LIST (2 << 4)
1045 #define RADEON_PRIM_WALK_RING (3 << 4)
1046 #define RADEON_COLOR_ORDER_BGRA (0 << 6)
1047 #define RADEON_COLOR_ORDER_RGBA (1 << 6)
1048 #define RADEON_MAOS_ENABLE (1 << 7)
1049 #define RADEON_VTX_FMT_R128_MODE (0 << 8)
1050 #define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
1051 #define RADEON_NUM_VERTICES_SHIFT 16
1053 #define RADEON_COLOR_FORMAT_CI8 2
1055 #define R200_PP_TXCBLEND_0 0x2f00
1056 #define R200_PP_TXCBLEND_1 0x2f10
1057 #define R200_PP_TXCBLEND_2 0x2f20
1058 #define R200_PP_TXCBLEND_3 0x2f30
1059 #define R200_PP_TXCBLEND_4 0x2f40
1060 #define R200_PP_TXCBLEND_5 0x2f50
1061 #define R200_PP_TXCBLEND_6 0x2f60
1062 #define R200_PP_TXCBLEND_7 0x2f70
1063 #define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
1064 #define R200_PP_TFACTOR_0 0x2ee0
1065 #define R200_SE_VTX_FMT_0 0x2088
1066 #define R200_SE_VAP_CNTL 0x2080
1067 #define R200_SE_TCL_MATRIX_SEL_0 0x2230
1068 #define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
1069 #define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
1070 #define R200_PP_TXFILTER_5 0x2ca0
1071 #define R200_PP_TXFILTER_4 0x2c80
1072 #define R200_PP_TXFILTER_3 0x2c60
1073 #define R200_PP_TXFILTER_2 0x2c40
1074 #define R200_PP_TXFILTER_1 0x2c20
1075 #define R200_PP_TXFILTER_0 0x2c00
1076 #define R200_PP_TXOFFSET_5 0x2d78
1077 #define R200_PP_TXOFFSET_4 0x2d60
1078 #define R200_PP_TXOFFSET_3 0x2d48
1079 #define R200_PP_TXOFFSET_2 0x2d30
1080 #define R200_PP_TXOFFSET_1 0x2d18
1081 #define R200_PP_TXOFFSET_0 0x2d00
1083 #define R200_PP_CUBIC_FACES_0 0x2c18
1084 #define R200_PP_CUBIC_FACES_1 0x2c38
1085 #define R200_PP_CUBIC_FACES_2 0x2c58
1086 #define R200_PP_CUBIC_FACES_3 0x2c78
1087 #define R200_PP_CUBIC_FACES_4 0x2c98
1088 #define R200_PP_CUBIC_FACES_5 0x2cb8
1089 #define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
1090 #define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
1091 #define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
1092 #define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
1093 #define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
1094 #define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
1095 #define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
1096 #define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
1097 #define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
1098 #define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
1099 #define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
1100 #define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
1101 #define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
1102 #define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
1103 #define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
1104 #define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
1105 #define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
1106 #define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
1107 #define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
1108 #define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
1109 #define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
1110 #define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
1111 #define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
1112 #define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
1113 #define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
1114 #define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
1115 #define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
1116 #define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
1117 #define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
1118 #define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
1120 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
1121 #define R200_SE_VTE_CNTL 0x20b0
1122 #define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
1123 #define R200_PP_TAM_DEBUG3 0x2d9c
1124 #define R200_PP_CNTL_X 0x2cc4
1125 #define R200_SE_VAP_CNTL_STATUS 0x2140
1126 #define R200_RE_SCISSOR_TL_0 0x1cd8
1127 #define R200_RE_SCISSOR_TL_1 0x1ce0
1128 #define R200_RE_SCISSOR_TL_2 0x1ce8
1129 #define R200_RB3D_DEPTHXY_OFFSET 0x1d60
1130 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
1131 #define R200_SE_VTX_STATE_CNTL 0x2180
1132 #define R200_RE_POINTSIZE 0x2648
1133 #define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
1135 #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
1136 #define RADEON_PP_TEX_SIZE_1 0x1d0c
1137 #define RADEON_PP_TEX_SIZE_2 0x1d14
1139 #define RADEON_PP_CUBIC_FACES_0 0x1d24
1140 #define RADEON_PP_CUBIC_FACES_1 0x1d28
1141 #define RADEON_PP_CUBIC_FACES_2 0x1d2c
1142 #define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
1143 #define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
1144 #define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
1146 #define RADEON_SE_TCL_STATE_FLUSH 0x2284
1148 #define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
1149 #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
1150 #define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
1151 #define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
1152 #define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
1153 #define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
1154 #define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
1155 #define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
1156 #define R200_3D_DRAW_IMMD_2 0xC0003500
1157 #define R200_SE_VTX_FMT_1 0x208c
1158 #define R200_RE_CNTL 0x1c50
1160 #define R200_RB3D_BLENDCOLOR 0x3218
1162 #define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
1164 #define R200_PP_TRI_PERF 0x2cf8
1166 #define R200_PP_AFS_0 0x2f80
1167 #define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */
1169 #define R200_VAP_PVS_CNTL_1 0x22D0
1171 /* MPEG settings from VHA code */
1172 #define RADEON_VHA_SETTO16_1 0x2694
1173 #define RADEON_VHA_SETTO16_2 0x2680
1174 #define RADEON_VHA_SETTO0_1 0x1840
1175 #define RADEON_VHA_FB_OFFSET 0x19e4
1176 #define RADEON_VHA_SETTO1AND70S 0x19d8
1177 #define RADEON_VHA_DST_PITCH 0x1408
1179 // set as reference header
1180 #define RADEON_VHA_BACKFRAME0_OFF_Y 0x1840
1181 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_Y 0x1844
1182 #define RADEON_VHA_BACKFRAME0_OFF_U 0x1848
1183 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_U 0x184c
1184 #define RADOEN_VHA_BACKFRAME0_OFF_V 0x1850
1185 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_V 0x1854
1186 #define RADEON_VHA_FORWFRAME0_OFF_Y 0x1858
1187 #define RADEON_VHA_FORWFRAME1_OFF_PITCH_Y 0x185c
1188 #define RADEON_VHA_FORWFRAME0_OFF_U 0x1860
1189 #define RADEON_VHA_FORWFRAME1_OFF_PITCH_U 0x1864
1190 #define RADEON_VHA_FORWFRAME0_OFF_V 0x1868
1191 #define RADEON_VHA_FORWFRAME0_OFF_PITCH_V 0x1880
1192 #define RADEON_VHA_BACKFRAME0_OFF_Y_2 0x1884
1193 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_Y_2 0x1888
1194 #define RADEON_VHA_BACKFRAME0_OFF_U_2 0x188c
1195 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_U_2 0x1890
1196 #define RADEON_VHA_BACKFRAME0_OFF_V_2 0x1894
1197 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_V_2 0x1898
1199 #define R500_D1CRTC_STATUS 0x609c
1200 #define R500_D2CRTC_STATUS 0x689c
1201 #define R500_CRTC_V_BLANK (1<<0)
1203 #define R500_D1CRTC_FRAME_COUNT 0x60a4
1204 #define R500_D2CRTC_FRAME_COUNT 0x68a4
1206 #define R500_D1MODE_V_COUNTER 0x6530
1207 #define R500_D2MODE_V_COUNTER 0x6d30
1209 #define R500_D1MODE_VBLANK_STATUS 0x6534
1210 #define R500_D2MODE_VBLANK_STATUS 0x6d34
1211 #define R500_VBLANK_OCCURED (1<<0)
1212 #define R500_VBLANK_ACK (1<<4)
1213 #define R500_VBLANK_STAT (1<<12)
1214 #define R500_VBLANK_INT (1<<16)
1216 #define R500_DxMODE_INT_MASK 0x6540
1217 #define R500_D1MODE_INT_MASK (1<<0)
1218 #define R500_D2MODE_INT_MASK (1<<8)
1220 #define R500_DISP_INTERRUPT_STATUS 0x7edc
1221 #define R500_D1_VBLANK_INTERRUPT (1 << 4)
1222 #define R500_D2_VBLANK_INTERRUPT (1 << 5)
1225 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
1227 #define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
1228 #define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
1229 #define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
1230 #define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
1231 #define RADEON_LAST_DISPATCH 1
1233 #define RADEON_MAX_VB_AGE 0x7fffffff
1234 #define RADEON_MAX_VB_VERTS (0xffff)
1236 #define RADEON_RING_HIGH_MARK 128
1238 #define RADEON_PCIGART_TABLE_SIZE (32*1024)
1239 #define RADEON_DEFAULT_RING_SIZE (1024*1024)
1240 #define RADEON_DEFAULT_CP_TIMEOUT 100000 /* usecs */
1242 #define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
1243 #define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
1244 #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
1245 #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
1247 extern int RADEON_READ_PLL(struct drm_radeon_private *dev_priv, int addr);
1248 extern void RADEON_WRITE_PLL(struct drm_radeon_private *dev_priv, int addr, uint32_t data);
1250 #define RADEON_WRITE_PCIE( addr, val ) \
1252 RADEON_WRITE8( RADEON_PCIE_INDEX, \
1254 RADEON_WRITE( RADEON_PCIE_DATA, (val) ); \
1257 #define R500_WRITE_MCIND( addr, val ) \
1259 RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \
1260 RADEON_WRITE(R520_MC_IND_DATA, (val)); \
1261 RADEON_WRITE(R520_MC_IND_INDEX, 0); \
1264 #define RS480_WRITE_MCIND( addr, val ) \
1266 RADEON_WRITE( RS480_NB_MC_INDEX, \
1267 ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \
1268 RADEON_WRITE( RS480_NB_MC_DATA, (val) ); \
1269 RADEON_WRITE( RS480_NB_MC_INDEX, 0xff ); \
1272 #define RS690_WRITE_MCIND( addr, val ) \
1274 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \
1275 RADEON_WRITE(RS690_MC_DATA, val); \
1276 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \
1279 #define IGP_WRITE_MCIND( addr, val ) \
1281 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) \
1282 RS690_WRITE_MCIND( addr, val ); \
1284 RS480_WRITE_MCIND( addr, val ); \
1287 #define CP_PACKET0( reg, n ) \
1288 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
1289 #define CP_PACKET0_TABLE( reg, n ) \
1290 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
1291 #define CP_PACKET1( reg0, reg1 ) \
1292 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
1293 #define CP_PACKET2() \
1295 #define CP_PACKET3( pkt, n ) \
1296 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
1298 /* ================================================================
1299 * Engine control helper macros
1302 #define RADEON_WAIT_UNTIL_2D_IDLE() do { \
1303 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1304 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1305 RADEON_WAIT_HOST_IDLECLEAN) ); \
1308 #define RADEON_WAIT_UNTIL_3D_IDLE() do { \
1309 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1310 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
1311 RADEON_WAIT_HOST_IDLECLEAN) ); \
1314 #define RADEON_WAIT_UNTIL_IDLE() do { \
1315 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1316 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1317 RADEON_WAIT_3D_IDLECLEAN | \
1318 RADEON_WAIT_HOST_IDLECLEAN) ); \
1321 #define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
1322 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1323 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
1326 #define RADEON_FLUSH_CACHE() do { \
1327 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1328 OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \
1329 OUT_RING( RADEON_RB3D_DC_FLUSH ); \
1331 OUT_RING( CP_PACKET0( R300_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \
1332 OUT_RING( RADEON_RB3D_DC_FLUSH ); \
1336 #define RADEON_PURGE_CACHE() do { \
1337 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1338 OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \
1339 OUT_RING( RADEON_RB3D_DC_FLUSH_ALL ); \
1341 OUT_RING( CP_PACKET0( R300_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \
1342 OUT_RING( RADEON_RB3D_DC_FLUSH_ALL ); \
1346 #define RADEON_FLUSH_ZCACHE() do { \
1347 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1348 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
1349 OUT_RING( RADEON_RB3D_ZC_FLUSH ); \
1351 OUT_RING( CP_PACKET0( R300_ZB_ZCACHE_CTLSTAT, 0 ) ); \
1352 OUT_RING( R300_ZC_FLUSH ); \
1356 #define RADEON_PURGE_ZCACHE() do { \
1357 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1358 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
1359 OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \
1361 OUT_RING( CP_PACKET0( R300_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
1362 OUT_RING( R300_ZC_FLUSH_ALL ); \
1366 /* ================================================================
1367 * Misc helper macros
1370 /* Perfbox functionality only.
1372 #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
1374 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
1375 u32 head = GET_RING_HEAD( dev_priv ); \
1376 if (head == dev_priv->ring.tail) \
1377 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
1381 #define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
1383 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv; \
1384 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv; \
1385 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
1386 int __ret = radeon_do_cp_idle( dev_priv ); \
1387 if ( __ret ) return __ret; \
1388 sarea_priv->last_dispatch = 0; \
1389 radeon_freelist_reset( dev ); \
1393 #define RADEON_DISPATCH_AGE( age ) do { \
1394 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
1398 #define RADEON_FRAME_AGE( age ) do { \
1399 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
1403 #define RADEON_CLEAR_AGE( age ) do { \
1404 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
1408 /* ================================================================
1412 #define RADEON_VERBOSE 0
1414 #define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring;
1416 #define BEGIN_RING( n ) do { \
1417 if ( RADEON_VERBOSE ) { \
1418 DRM_INFO( "BEGIN_RING( %d )\n", (n)); \
1420 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
1422 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \
1424 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
1425 ring = dev_priv->ring.start; \
1426 write = dev_priv->ring.tail; \
1427 mask = dev_priv->ring.tail_mask; \
1430 #define ADVANCE_RING() do { \
1431 if ( RADEON_VERBOSE ) { \
1432 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
1433 write, dev_priv->ring.tail ); \
1435 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
1437 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
1438 ((dev_priv->ring.tail + _nr) & mask), \
1441 dev_priv->ring.tail = write; \
1444 #define COMMIT_RING() do { \
1445 /* Flush writes to ring */ \
1446 DRM_MEMORYBARRIER(); \
1447 GET_RING_HEAD( dev_priv ); \
1448 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
1449 /* read from PCI bus to ensure correct posting */ \
1450 RADEON_READ( RADEON_CP_RB_RPTR ); \
1453 #define OUT_RING( x ) do { \
1454 if ( RADEON_VERBOSE ) { \
1455 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
1456 (unsigned int)(x), write ); \
1458 ring[write++] = (x); \
1462 #define OUT_RING_REG( reg, val ) do { \
1463 OUT_RING( CP_PACKET0( reg, 0 ) ); \
1467 #define OUT_RING_TABLE( tab, sz ) do { \
1469 int *_tab = (int *)(tab); \
1471 if (write + _size > mask) { \
1472 int _i = (mask+1) - write; \
1475 *(int *)(ring + write) = *_tab++; \
1482 while (_size > 0) { \
1483 *(ring + write) = *_tab++; \
1490 /* radeon GEM->TTM munger */
1491 struct drm_radeon_gem_object {
1493 struct drm_buffer_object *bo;
1494 struct drm_fence_object *fence;
1495 struct drm_gem_object *obj;
1499 extern int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1500 struct drm_file *file_priv);
1502 extern int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1503 struct drm_file *file_priv);
1505 extern int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1506 struct drm_file *file_priv);
1508 extern int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1509 struct drm_file *file_priv);
1510 extern int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1511 struct drm_file *file_priv);
1513 extern void radeon_fence_handler(struct drm_device *dev);
1514 extern int radeon_fence_emit_sequence(struct drm_device *dev, uint32_t class,
1515 uint32_t flags, uint32_t *sequence,
1516 uint32_t *native_type);
1517 extern void radeon_poke_flush(struct drm_device *dev, uint32_t class);
1518 extern int radeon_fence_has_irq(struct drm_device *dev, uint32_t class, uint32_t flags);
1520 /* radeon_buffer.c */
1521 extern struct drm_ttm_backend *radeon_create_ttm_backend_entry(struct drm_device *dev);
1522 extern int radeon_fence_types(struct drm_buffer_object *bo, uint32_t *class, uint32_t *type);
1523 extern int radeon_invalidate_caches(struct drm_device *dev, uint64_t buffer_flags);
1524 extern int radeon_init_mem_type(struct drm_device * dev, uint32_t type,
1525 struct drm_mem_type_manager * man);
1526 extern int radeon_move(struct drm_buffer_object * bo,
1527 int evict, int no_wait, struct drm_bo_mem_reg * new_mem);
1529 extern void radeon_gart_flush(struct drm_device *dev);
1530 extern uint64_t radeon_evict_flags(struct drm_buffer_object *bo);
1532 #define BREADCRUMB_BITS 31
1533 #define BREADCRUMB_MASK ((1U << BREADCRUMB_BITS) - 1)
1535 /* Breadcrumb - swi irq */
1536 #define READ_BREADCRUMB(dev_priv) RADEON_READ(RADEON_LAST_SWI_REG)
1538 static inline int radeon_update_breadcrumb(struct drm_device *dev)
1540 struct drm_radeon_private *dev_priv = dev->dev_private;
1541 struct drm_radeon_master_private *master_priv;
1543 ++dev_priv->counter;
1544 if (dev_priv->counter > BREADCRUMB_MASK)
1545 dev_priv->counter = 1;
1547 if (dev->primary->master) {
1548 master_priv = dev->primary->master->driver_priv;
1550 if (master_priv->sarea_priv)
1551 master_priv->sarea_priv->last_fence = dev_priv->counter;
1553 return dev_priv->counter;
1556 #define radeon_is_avivo(dev_priv) ((dev_priv->chip_family >= CHIP_RS600))
1558 #define radeon_is_dce3(dev_priv) ((dev_priv->chip_family >= CHIP_RV620))
1560 #define radeon_bios8(dev_priv, v) (dev_priv->bios[v])
1561 #define radeon_bios16(dev_priv, v) (dev_priv->bios[v] | (dev_priv->bios[(v) + 1] << 8))
1562 #define radeon_bios32(dev_priv, v) ((dev_priv->bios[v]) | \
1563 (dev_priv->bios[(v) + 1] << 8) | \
1564 (dev_priv->bios[(v) + 2] << 16) | \
1565 (dev_priv->bios[(v) + 3] << 24))
1567 extern int radeon_emit_irq(struct drm_device * dev);
1569 extern void radeon_gem_free_object(struct drm_gem_object *obj);
1570 extern int radeon_gem_init_object(struct drm_gem_object *obj);
1571 extern int radeon_gem_mm_init(struct drm_device *dev);
1572 extern void radeon_gem_mm_fini(struct drm_device *dev);
1573 extern int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1574 struct drm_file *file_priv);
1575 extern int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1576 struct drm_file *file_priv);
1577 int radeon_gem_object_pin(struct drm_gem_object *obj,
1578 uint32_t alignment);
1579 int radeon_gem_indirect_ioctl(struct drm_device *dev, void *data,
1580 struct drm_file *file_priv);
1581 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1582 struct drm_file *file_priv);
1583 struct drm_gem_object *radeon_gem_object_alloc(struct drm_device *dev, int size, int alignment,
1584 int initial_domain);
1585 int radeon_modeset_init(struct drm_device *dev);
1586 void radeon_modeset_cleanup(struct drm_device *dev);
1587 extern u32 radeon_read_mc_reg(drm_radeon_private_t *dev_priv, int addr);
1588 extern void radeon_write_mc_reg(drm_radeon_private_t *dev_priv, u32 addr, u32 val);
1590 extern void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on);
1591 #define RADEONFB_CONN_LIMIT 4
1593 extern int radeon_master_create(struct drm_device *dev, struct drm_master *master);
1594 extern void radeon_master_destroy(struct drm_device *dev, struct drm_master *master);
1595 extern void radeon_cp_dispatch_flip(struct drm_device * dev, struct drm_master *master);
1596 #endif /* __RADEON_DRV_H__ */