2 * Copyright 2008 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Jerome Glisse <glisse@freedesktop.org>
28 #include "radeon_drm.h"
29 #include "radeon_drv.h"
32 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv)
34 struct drm_radeon_private *radeon = dev->dev_private;
35 struct drm_radeon_cs *cs = data;
36 uint32_t *packets = NULL;
42 /* set command stream id to 0 which is fake id */
44 DRM_COPY_TO_USER(&cs->cs_id, &cs_id, sizeof(uint32_t));
47 DRM_ERROR("called with no initialization\n");
53 /* limit cs to 64K ib */
54 if (cs->dwords > (16 * 1024)) {
57 /* copy cs from userspace maybe we should copy into ib to save
58 * one copy but ib will be mapped wc so not good for cmd checking
59 * somethings worth testing i guess (Jerome)
61 size = cs->dwords * sizeof(uint32_t);
62 packets = drm_alloc(size, DRM_MEM_DRIVER);
63 if (packets == NULL) {
66 if (DRM_COPY_FROM_USER(packets, (void __user *)(unsigned long)cs->packets, size)) {
71 r = radeon->cs.ib_get(dev, &ib, cs->dwords);
76 /* now parse command stream */
77 r = radeon->cs.parse(dev, fpriv, ib, packets, cs->dwords);
82 /* emit cs id sequence */
83 radeon->cs.id_emit(dev, &cs_id);
84 DRM_COPY_TO_USER(&cs->cs_id, &cs_id, sizeof(uint32_t));
86 radeon->cs.ib_free(dev, ib, cs->dwords);
87 drm_free(packets, size, DRM_MEM_DRIVER);
92 static int radeon_nomm_relocate(struct drm_device *dev, struct drm_file *file_priv, uint32_t *reloc, uint32_t *offset)
98 #define RADEON_2D_OFFSET_MASK 0x3fffff
100 static __inline__ int radeon_cs_relocate_offset(struct drm_device *dev, struct drm_file *file_priv,
101 uint32_t *packets, uint32_t offset_dw)
103 drm_radeon_private_t *dev_priv = dev->dev_private;
104 uint32_t hdr = packets[offset_dw];
105 uint32_t reg = (hdr & R300_CP_PACKET0_REG_MASK) << 2;
106 uint32_t val = packets[offset_dw + 1];
107 uint32_t packet3_hdr = packets[offset_dw+2];
108 uint32_t tmp, offset;
111 /* this is too strict we may want to expand the length in the future and have
112 old kernels ignore it. */
113 if (packet3_hdr != (RADEON_CP_PACKET3 | RADEON_CP_NOP | (RELOC_SIZE << 16))) {
114 DRM_ERROR("Packet 3 was %x should have been %x\n", packet3_hdr, RADEON_CP_PACKET3 | RADEON_CP_NOP | (RELOC_SIZE << 16));
119 case RADEON_DST_PITCH_OFFSET:
120 case RADEON_SRC_PITCH_OFFSET:
121 /* pass in the start of the reloc */
122 ret = dev_priv->cs.relocate(dev, file_priv, packets + offset_dw + 2, &offset);
125 tmp = (val & RADEON_2D_OFFSET_MASK) << 10;
126 val &= ~RADEON_2D_OFFSET_MASK;
131 case R300_RB3D_COLOROFFSET0:
132 case R300_RB3D_DEPTHOFFSET:
133 case R300_TX_OFFSET_0:
134 case R300_TX_OFFSET_0+4:
135 offset = packets[offset_dw + 3];
137 ret = dev_priv->cs.relocate(dev, file_priv, packets + offset_dw + 2, &offset);
141 offset &= 0xffffffe0;
149 DRM_ERROR("New offset %x %x %x\n", packets[offset_dw+1], val, offset);
150 packets[offset_dw + 1] = val;
154 static __inline__ int radeon_cs_check_offset(struct drm_device *dev,
155 uint32_t reg, uint32_t val)
160 case RADEON_DST_PITCH_OFFSET:
161 case RADEON_SRC_PITCH_OFFSET:
162 offset = val & ((1 << 22) - 1);
165 case R300_RB3D_COLOROFFSET0:
166 case R300_RB3D_DEPTHOFFSET:
169 case R300_TX_OFFSET_0:
170 case R300_TX_OFFSET_0+4:
171 offset = val & 0xffffffe0;
175 DRM_ERROR("Offset check %x %x\n", reg, offset);
179 int radeon_cs_packet0(struct drm_device *dev, struct drm_file *file_priv,
180 uint32_t *packets, uint32_t offset_dw)
182 drm_radeon_private_t *dev_priv = dev->dev_private;
183 uint32_t hdr = packets[offset_dw];
184 int num_dw = ((hdr & RADEON_CP_PACKET_COUNT_MASK) >> 16) + 2;
186 int reg = (hdr & R300_CP_PACKET0_REG_MASK) << 2;
190 while (count_dw < num_dw) {
191 /* need to have something like the r300 validation here -
192 list of allowed registers */
195 ret = r300_check_range(reg, 1);
198 DRM_ERROR("Illegal register %x\n", reg);
203 flags = r300_get_reg_flags(reg);
204 if (flags == MARK_CHECK_OFFSET) {
206 DRM_ERROR("Cannot relocate inside type stream of reg0 packets\n");
210 ret = radeon_cs_relocate_offset(dev, file_priv, packets, offset_dw);
213 DRM_DEBUG("need to relocate %x %d\n", reg, flags);
214 /* okay it should be followed by a NOP */
215 } else if (flags == MARK_CHECK_SCISSOR) {
216 DRM_DEBUG("need to validate scissor %x %d\n", reg, flags);
218 DRM_DEBUG("illegal register %x %d\n", reg, flags);
229 int radeon_cs_parse(struct drm_device *dev, struct drm_file *file_priv,
230 void *ib, uint32_t *packets, uint32_t dwords)
232 drm_radeon_private_t *dev_priv = dev->dev_private;
234 int size_dw = dwords;
235 /* scan the packet for various things */
239 while (count_dw < size_dw && ret == 0) {
240 int hdr = packets[count_dw];
241 int num_dw = (hdr & RADEON_CP_PACKET_COUNT_MASK) >> 16;
244 switch (hdr & RADEON_CP_PACKET_MASK) {
245 case RADEON_CP_PACKET0:
246 ret = radeon_cs_packet0(dev, file_priv, packets, count_dw);
248 case RADEON_CP_PACKET1:
249 case RADEON_CP_PACKET2:
250 reg = hdr & RADEON_CP_PACKET0_REG_MASK;
251 DRM_DEBUG("Packet 1/2: %d %x\n", num_dw, reg);
254 case RADEON_CP_PACKET3:
258 case RADEON_CNTL_HOSTDATA_BLT:
261 offset = packets[count_dw+2] & ((1 << 22) - 1);
263 DRM_ERROR("Offset check for Packet 3 %x %x\n", reg, offset);
264 /* okay it should be followed by a NOP */
267 case RADEON_CNTL_BITBLT_MULTI:
268 case RADEON_3D_LOAD_VBPNTR: /* load vertex array pointers */
269 case RADEON_CP_INDX_BUFFER:
270 DRM_ERROR("need relocate packet 3 for %x\n", reg);
273 case RADEON_CP_3D_DRAW_IMMD_2: /* triggers drawing using in-packet vertex data */
274 case RADEON_CP_3D_DRAW_VBUF_2: /* triggers drawing of vertex buffers setup elsewhere */
275 case RADEON_CP_3D_DRAW_INDX_2: /* triggers drawing using indices to vertex buffer */
276 case RADEON_WAIT_FOR_IDLE:
280 DRM_ERROR("unknown packet 3 %x\n", reg);
286 count_dw += num_dw+2;
293 /* copy the packet into the IB */
294 memcpy(ib, packets, dwords * sizeof(uint32_t));
296 /* read back last byte to flush WC buffers */
297 rb = readl((ib + (dwords-1) * sizeof(uint32_t)));
302 uint32_t radeon_cs_id_get(struct drm_radeon_private *radeon)
304 /* FIXME: protect with a spinlock */
305 /* FIXME: check if wrap affect last reported wrap & sequence */
306 radeon->cs.id_scnt = (radeon->cs.id_scnt + 1) & 0x00FFFFFF;
307 if (!radeon->cs.id_scnt) {
308 /* increment wrap counter */
309 radeon->cs.id_wcnt += 0x01000000;
310 /* valid sequence counter start at 1 */
311 radeon->cs.id_scnt = 1;
313 return (radeon->cs.id_scnt | radeon->cs.id_wcnt);
316 void r100_cs_id_emit(struct drm_device *dev, uint32_t *id)
318 drm_radeon_private_t *dev_priv = dev->dev_private;
321 /* ISYNC_CNTL should have CPSCRACTH bit set */
322 *id = radeon_cs_id_get(dev_priv);
323 /* emit id in SCRATCH4 (not used yet in old drm) */
325 OUT_RING(CP_PACKET0(RADEON_SCRATCH_REG4, 0));
330 void r300_cs_id_emit(struct drm_device *dev, uint32_t *id)
332 drm_radeon_private_t *dev_priv = dev->dev_private;
335 /* ISYNC_CNTL should not have CPSCRACTH bit set */
336 *id = radeon_cs_id_get(dev_priv);
337 /* emit id in SCRATCH6 */
339 OUT_RING(CP_PACKET0(R300_CP_RESYNC_ADDR, 0));
341 OUT_RING(CP_PACKET0(R300_CP_RESYNC_DATA, 0));
343 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
344 OUT_RING(R300_RB3D_DC_FINISH);
348 uint32_t r100_cs_id_last_get(struct drm_device *dev)
350 drm_radeon_private_t *dev_priv = dev->dev_private;
352 return RADEON_READ(RADEON_SCRATCH_REG4);
355 uint32_t r300_cs_id_last_get(struct drm_device *dev)
357 drm_radeon_private_t *dev_priv = dev->dev_private;
359 return RADEON_READ(RADEON_SCRATCH_REG6);
362 int radeon_cs_init(struct drm_device *dev)
364 drm_radeon_private_t *dev_priv = dev->dev_private;
366 if (dev_priv->chip_family < CHIP_RV280) {
367 dev_priv->cs.id_emit = r100_cs_id_emit;
368 dev_priv->cs.id_last_get = r100_cs_id_last_get;
369 } else if (dev_priv->chip_family < CHIP_R600) {
370 dev_priv->cs.id_emit = r300_cs_id_emit;
371 dev_priv->cs.id_last_get = r300_cs_id_last_get;
374 dev_priv->cs.parse = radeon_cs_parse;
375 /* ib get depends on memory manager or not so memory manager */
376 dev_priv->cs.relocate = radeon_nomm_relocate;