shared-core/radeon_cp.c

   1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
   2 /*
   3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11  * and/or sell copies of the Software, and to permit persons to whom the
  12  * Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the next
  15  * paragraph) shall be included in all copies or substantial portions of the
  16  * Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  21  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  22  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  23  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  24  * DEALINGS IN THE SOFTWARE.
  25  *
  26  * Authors:
  27  *    Kevin E. Martin <martin@valinux.com>
  28  *    Gareth Hughes <gareth@valinux.com>
  29  */
  30
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "radeon_drm.h"
  34 #include "radeon_drv.h"
  35 #include "r300_reg.h"
  36
  37 #define RADEON_FIFO_DEBUG       0
  38
  39 static int radeon_do_cleanup_cp(struct drm_device * dev);
  40
  41 /* CP microcode (from ATI) */
  42 static const u32 R200_cp_microcode[][2] = {
  43         {0x21007000, 0000000000},
  44         {0x20007000, 0000000000},
  45         {0x000000ab, 0x00000004},
  46         {0x000000af, 0x00000004},
  47         {0x66544a49, 0000000000},
  48         {0x49494174, 0000000000},
  49         {0x54517d83, 0000000000},
  50         {0x498d8b64, 0000000000},
  51         {0x49494949, 0000000000},
  52         {0x49da493c, 0000000000},
  53         {0x49989898, 0000000000},
  54         {0xd34949d5, 0000000000},
  55         {0x9dc90e11, 0000000000},
  56         {0xce9b9b9b, 0000000000},
  57         {0x000f0000, 0x00000016},
  58         {0x352e232c, 0000000000},
  59         {0x00000013, 0x00000004},
  60         {0x000f0000, 0x00000016},
  61         {0x352e272c, 0000000000},
  62         {0x000f0001, 0x00000016},
  63         {0x3239362f, 0000000000},
  64         {0x000077ef, 0x00000002},
  65         {0x00061000, 0x00000002},
  66         {0x00000020, 0x0000001a},
  67         {0x00004000, 0x0000001e},
  68         {0x00061000, 0x00000002},
  69         {0x00000020, 0x0000001a},
  70         {0x00004000, 0x0000001e},
  71         {0x00061000, 0x00000002},
  72         {0x00000020, 0x0000001a},
  73         {0x00004000, 0x0000001e},
  74         {0x00000016, 0x00000004},
  75         {0x0003802a, 0x00000002},
  76         {0x040067e0, 0x00000002},
  77         {0x00000016, 0x00000004},
  78         {0x000077e0, 0x00000002},
  79         {0x00065000, 0x00000002},
  80         {0x000037e1, 0x00000002},
  81         {0x040067e1, 0x00000006},
  82         {0x000077e0, 0x00000002},
  83         {0x000077e1, 0x00000002},
  84         {0x000077e1, 0x00000006},
  85         {0xffffffff, 0000000000},
  86         {0x10000000, 0000000000},
  87         {0x0003802a, 0x00000002},
  88         {0x040067e0, 0x00000006},
  89         {0x00007675, 0x00000002},
  90         {0x00007676, 0x00000002},
  91         {0x00007677, 0x00000002},
  92         {0x00007678, 0x00000006},
  93         {0x0003802b, 0x00000002},
  94         {0x04002676, 0x00000002},
  95         {0x00007677, 0x00000002},
  96         {0x00007678, 0x00000006},
  97         {0x0000002e, 0x00000018},
  98         {0x0000002e, 0x00000018},
  99         {0000000000, 0x00000006},
 100         {0x0000002f, 0x00000018},
 101         {0x0000002f, 0x00000018},
 102         {0000000000, 0x00000006},
 103         {0x01605000, 0x00000002},
 104         {0x00065000, 0x00000002},
 105         {0x00098000, 0x00000002},
 106         {0x00061000, 0x00000002},
 107         {0x64c0603d, 0x00000004},
 108         {0x00080000, 0x00000016},
 109         {0000000000, 0000000000},
 110         {0x0400251d, 0x00000002},
 111         {0x00007580, 0x00000002},
 112         {0x00067581, 0x00000002},
 113         {0x04002580, 0x00000002},
 114         {0x00067581, 0x00000002},
 115         {0x00000046, 0x00000004},
 116         {0x00005000, 0000000000},
 117         {0x00061000, 0x00000002},
 118         {0x0000750e, 0x00000002},
 119         {0x00019000, 0x00000002},
 120         {0x00011055, 0x00000014},
 121         {0x00000055, 0x00000012},
 122         {0x0400250f, 0x00000002},
 123         {0x0000504a, 0x00000004},
 124         {0x00007565, 0x00000002},
 125         {0x00007566, 0x00000002},
 126         {0x00000051, 0x00000004},
 127         {0x01e655b4, 0x00000002},
 128         {0x4401b0dc, 0x00000002},
 129         {0x01c110dc, 0x00000002},
 130         {0x2666705d, 0x00000018},
 131         {0x040c2565, 0x00000002},
 132         {0x0000005d, 0x00000018},
 133         {0x04002564, 0x00000002},
 134         {0x00007566, 0x00000002},
 135         {0x00000054, 0x00000004},
 136         {0x00401060, 0x00000008},
 137         {0x00101000, 0x00000002},
 138         {0x000d80ff, 0x00000002},
 139         {0x00800063, 0x00000008},
 140         {0x000f9000, 0x00000002},
 141         {0x000e00ff, 0x00000002},
 142         {0000000000, 0x00000006},
 143         {0x00000080, 0x00000018},
 144         {0x00000054, 0x00000004},
 145         {0x00007576, 0x00000002},
 146         {0x00065000, 0x00000002},
 147         {0x00009000, 0x00000002},
 148         {0x00041000, 0x00000002},
 149         {0x0c00350e, 0x00000002},
 150         {0x00049000, 0x00000002},
 151         {0x00051000, 0x00000002},
 152         {0x01e785f8, 0x00000002},
 153         {0x00200000, 0x00000002},
 154         {0x00600073, 0x0000000c},
 155         {0x00007563, 0x00000002},
 156         {0x006075f0, 0x00000021},
 157         {0x20007068, 0x00000004},
 158         {0x00005068, 0x00000004},
 159         {0x00007576, 0x00000002},
 160         {0x00007577, 0x00000002},
 161         {0x0000750e, 0x00000002},
 162         {0x0000750f, 0x00000002},
 163         {0x00a05000, 0x00000002},
 164         {0x00600076, 0x0000000c},
 165         {0x006075f0, 0x00000021},
 166         {0x000075f8, 0x00000002},
 167         {0x00000076, 0x00000004},
 168         {0x000a750e, 0x00000002},
 169         {0x0020750f, 0x00000002},
 170         {0x00600079, 0x00000004},
 171         {0x00007570, 0x00000002},
 172         {0x00007571, 0x00000002},
 173         {0x00007572, 0x00000006},
 174         {0x00005000, 0x00000002},
 175         {0x00a05000, 0x00000002},
 176         {0x00007568, 0x00000002},
 177         {0x00061000, 0x00000002},
 178         {0x00000084, 0x0000000c},
 179         {0x00058000, 0x00000002},
 180         {0x0c607562, 0x00000002},
 181         {0x00000086, 0x00000004},
 182         {0x00600085, 0x00000004},
 183         {0x400070dd, 0000000000},
 184         {0x000380dd, 0x00000002},
 185         {0x00000093, 0x0000001c},
 186         {0x00065095, 0x00000018},
 187         {0x040025bb, 0x00000002},
 188         {0x00061096, 0x00000018},
 189         {0x040075bc, 0000000000},
 190         {0x000075bb, 0x00000002},
 191         {0x000075bc, 0000000000},
 192         {0x00090000, 0x00000006},
 193         {0x00090000, 0x00000002},
 194         {0x000d8002, 0x00000006},
 195         {0x00005000, 0x00000002},
 196         {0x00007821, 0x00000002},
 197         {0x00007800, 0000000000},
 198         {0x00007821, 0x00000002},
 199         {0x00007800, 0000000000},
 200         {0x01665000, 0x00000002},
 201         {0x000a0000, 0x00000002},
 202         {0x000671cc, 0x00000002},
 203         {0x0286f1cd, 0x00000002},
 204         {0x000000a3, 0x00000010},
 205         {0x21007000, 0000000000},
 206         {0x000000aa, 0x0000001c},
 207         {0x00065000, 0x00000002},
 208         {0x000a0000, 0x00000002},
 209         {0x00061000, 0x00000002},
 210         {0x000b0000, 0x00000002},
 211         {0x38067000, 0x00000002},
 212         {0x000a00a6, 0x00000004},
 213         {0x20007000, 0000000000},
 214         {0x01200000, 0x00000002},
 215         {0x20077000, 0x00000002},
 216         {0x01200000, 0x00000002},
 217         {0x20007000, 0000000000},
 218         {0x00061000, 0x00000002},
 219         {0x0120751b, 0x00000002},
 220         {0x8040750a, 0x00000002},
 221         {0x8040750b, 0x00000002},
 222         {0x00110000, 0x00000002},
 223         {0x000380dd, 0x00000002},
 224         {0x000000bd, 0x0000001c},
 225         {0x00061096, 0x00000018},
 226         {0x844075bd, 0x00000002},
 227         {0x00061095, 0x00000018},
 228         {0x840075bb, 0x00000002},
 229         {0x00061096, 0x00000018},
 230         {0x844075bc, 0x00000002},
 231         {0x000000c0, 0x00000004},
 232         {0x804075bd, 0x00000002},
 233         {0x800075bb, 0x00000002},
 234         {0x804075bc, 0x00000002},
 235         {0x00108000, 0x00000002},
 236         {0x01400000, 0x00000002},
 237         {0x006000c4, 0x0000000c},
 238         {0x20c07000, 0x00000020},
 239         {0x000000c6, 0x00000012},
 240         {0x00800000, 0x00000006},
 241         {0x0080751d, 0x00000006},
 242         {0x000025bb, 0x00000002},
 243         {0x000040c0, 0x00000004},
 244         {0x0000775c, 0x00000002},
 245         {0x00a05000, 0x00000002},
 246         {0x00661000, 0x00000002},
 247         {0x0460275d, 0x00000020},
 248         {0x00004000, 0000000000},
 249         {0x00007999, 0x00000002},
 250         {0x00a05000, 0x00000002},
 251         {0x00661000, 0x00000002},
 252         {0x0460299b, 0x00000020},
 253         {0x00004000, 0000000000},
 254         {0x01e00830, 0x00000002},
 255         {0x21007000, 0000000000},
 256         {0x00005000, 0x00000002},
 257         {0x00038042, 0x00000002},
 258         {0x040025e0, 0x00000002},
 259         {0x000075e1, 0000000000},
 260         {0x00000001, 0000000000},
 261         {0x000380d9, 0x00000002},
 262         {0x04007394, 0000000000},
 263         {0000000000, 0000000000},
 264         {0000000000, 0000000000},
 265         {0000000000, 0000000000},
 266         {0000000000, 0000000000},
 267         {0000000000, 0000000000},
 268         {0000000000, 0000000000},
 269         {0000000000, 0000000000},
 270         {0000000000, 0000000000},
 271         {0000000000, 0000000000},
 272         {0000000000, 0000000000},
 273         {0000000000, 0000000000},
 274         {0000000000, 0000000000},
 275         {0000000000, 0000000000},
 276         {0000000000, 0000000000},
 277         {0000000000, 0000000000},
 278         {0000000000, 0000000000},
 279         {0000000000, 0000000000},
 280         {0000000000, 0000000000},
 281         {0000000000, 0000000000},
 282         {0000000000, 0000000000},
 283         {0000000000, 0000000000},
 284         {0000000000, 0000000000},
 285         {0000000000, 0000000000},
 286         {0000000000, 0000000000},
 287         {0000000000, 0000000000},
 288         {0000000000, 0000000000},
 289         {0000000000, 0000000000},
 290         {0000000000, 0000000000},
 291         {0000000000, 0000000000},
 292         {0000000000, 0000000000},
 293         {0000000000, 0000000000},
 294         {0000000000, 0000000000},
 295         {0000000000, 0000000000},
 296         {0000000000, 0000000000},
 297         {0000000000, 0000000000},
 298         {0000000000, 0000000000},
 299 };
 300
 301 static const u32 radeon_cp_microcode[][2] = {
 302         {0x21007000, 0000000000},
 303         {0x20007000, 0000000000},
 304         {0x000000b4, 0x00000004},
 305         {0x000000b8, 0x00000004},
 306         {0x6f5b4d4c, 0000000000},
 307         {0x4c4c427f, 0000000000},
 308         {0x5b568a92, 0000000000},
 309         {0x4ca09c6d, 0000000000},
 310         {0xad4c4c4c, 0000000000},
 311         {0x4ce1af3d, 0000000000},
 312         {0xd8afafaf, 0000000000},
 313         {0xd64c4cdc, 0000000000},
 314         {0x4cd10d10, 0000000000},
 315         {0x000f0000, 0x00000016},
 316         {0x362f242d, 0000000000},
 317         {0x00000012, 0x00000004},
 318         {0x000f0000, 0x00000016},
 319         {0x362f282d, 0000000000},
 320         {0x000380e7, 0x00000002},
 321         {0x04002c97, 0x00000002},
 322         {0x000f0001, 0x00000016},
 323         {0x333a3730, 0000000000},
 324         {0x000077ef, 0x00000002},
 325         {0x00061000, 0x00000002},
 326         {0x00000021, 0x0000001a},
 327         {0x00004000, 0x0000001e},
 328         {0x00061000, 0x00000002},
 329         {0x00000021, 0x0000001a},
 330         {0x00004000, 0x0000001e},
 331         {0x00061000, 0x00000002},
 332         {0x00000021, 0x0000001a},
 333         {0x00004000, 0x0000001e},
 334         {0x00000017, 0x00000004},
 335         {0x0003802b, 0x00000002},
 336         {0x040067e0, 0x00000002},
 337         {0x00000017, 0x00000004},
 338         {0x000077e0, 0x00000002},
 339         {0x00065000, 0x00000002},
 340         {0x000037e1, 0x00000002},
 341         {0x040067e1, 0x00000006},
 342         {0x000077e0, 0x00000002},
 343         {0x000077e1, 0x00000002},
 344         {0x000077e1, 0x00000006},
 345         {0xffffffff, 0000000000},
 346         {0x10000000, 0000000000},
 347         {0x0003802b, 0x00000002},
 348         {0x040067e0, 0x00000006},
 349         {0x00007675, 0x00000002},
 350         {0x00007676, 0x00000002},
 351         {0x00007677, 0x00000002},
 352         {0x00007678, 0x00000006},
 353         {0x0003802c, 0x00000002},
 354         {0x04002676, 0x00000002},
 355         {0x00007677, 0x00000002},
 356         {0x00007678, 0x00000006},
 357         {0x0000002f, 0x00000018},
 358         {0x0000002f, 0x00000018},
 359         {0000000000, 0x00000006},
 360         {0x00000030, 0x00000018},
 361         {0x00000030, 0x00000018},
 362         {0000000000, 0x00000006},
 363         {0x01605000, 0x00000002},
 364         {0x00065000, 0x00000002},
 365         {0x00098000, 0x00000002},
 366         {0x00061000, 0x00000002},
 367         {0x64c0603e, 0x00000004},
 368         {0x000380e6, 0x00000002},
 369         {0x040025c5, 0x00000002},
 370         {0x00080000, 0x00000016},
 371         {0000000000, 0000000000},
 372         {0x0400251d, 0x00000002},
 373         {0x00007580, 0x00000002},
 374         {0x00067581, 0x00000002},
 375         {0x04002580, 0x00000002},
 376         {0x00067581, 0x00000002},
 377         {0x00000049, 0x00000004},
 378         {0x00005000, 0000000000},
 379         {0x000380e6, 0x00000002},
 380         {0x040025c5, 0x00000002},
 381         {0x00061000, 0x00000002},
 382         {0x0000750e, 0x00000002},
 383         {0x00019000, 0x00000002},
 384         {0x00011055, 0x00000014},
 385         {0x00000055, 0x00000012},
 386         {0x0400250f, 0x00000002},
 387         {0x0000504f, 0x00000004},
 388         {0x000380e6, 0x00000002},
 389         {0x040025c5, 0x00000002},
 390         {0x00007565, 0x00000002},
 391         {0x00007566, 0x00000002},
 392         {0x00000058, 0x00000004},
 393         {0x000380e6, 0x00000002},
 394         {0x040025c5, 0x00000002},
 395         {0x01e655b4, 0x00000002},
 396         {0x4401b0e4, 0x00000002},
 397         {0x01c110e4, 0x00000002},
 398         {0x26667066, 0x00000018},
 399         {0x040c2565, 0x00000002},
 400         {0x00000066, 0x00000018},
 401         {0x04002564, 0x00000002},
 402         {0x00007566, 0x00000002},
 403         {0x0000005d, 0x00000004},
 404         {0x00401069, 0x00000008},
 405         {0x00101000, 0x00000002},
 406         {0x000d80ff, 0x00000002},
 407         {0x0080006c, 0x00000008},
 408         {0x000f9000, 0x00000002},
 409         {0x000e00ff, 0x00000002},
 410         {0000000000, 0x00000006},
 411         {0x0000008f, 0x00000018},
 412         {0x0000005b, 0x00000004},
 413         {0x000380e6, 0x00000002},
 414         {0x040025c5, 0x00000002},
 415         {0x00007576, 0x00000002},
 416         {0x00065000, 0x00000002},
 417         {0x00009000, 0x00000002},
 418         {0x00041000, 0x00000002},
 419         {0x0c00350e, 0x00000002},
 420         {0x00049000, 0x00000002},
 421         {0x00051000, 0x00000002},
 422         {0x01e785f8, 0x00000002},
 423         {0x00200000, 0x00000002},
 424         {0x0060007e, 0x0000000c},
 425         {0x00007563, 0x00000002},
 426         {0x006075f0, 0x00000021},
 427         {0x20007073, 0x00000004},
 428         {0x00005073, 0x00000004},
 429         {0x000380e6, 0x00000002},
 430         {0x040025c5, 0x00000002},
 431         {0x00007576, 0x00000002},
 432         {0x00007577, 0x00000002},
 433         {0x0000750e, 0x00000002},
 434         {0x0000750f, 0x00000002},
 435         {0x00a05000, 0x00000002},
 436         {0x00600083, 0x0000000c},
 437         {0x006075f0, 0x00000021},
 438         {0x000075f8, 0x00000002},
 439         {0x00000083, 0x00000004},
 440         {0x000a750e, 0x00000002},
 441         {0x000380e6, 0x00000002},
 442         {0x040025c5, 0x00000002},
 443         {0x0020750f, 0x00000002},
 444         {0x00600086, 0x00000004},
 445         {0x00007570, 0x00000002},
 446         {0x00007571, 0x00000002},
 447         {0x00007572, 0x00000006},
 448         {0x000380e6, 0x00000002},
 449         {0x040025c5, 0x00000002},
 450         {0x00005000, 0x00000002},
 451         {0x00a05000, 0x00000002},
 452         {0x00007568, 0x00000002},
 453         {0x00061000, 0x00000002},
 454         {0x00000095, 0x0000000c},
 455         {0x00058000, 0x00000002},
 456         {0x0c607562, 0x00000002},
 457         {0x00000097, 0x00000004},
 458         {0x000380e6, 0x00000002},
 459         {0x040025c5, 0x00000002},
 460         {0x00600096, 0x00000004},
 461         {0x400070e5, 0000000000},
 462         {0x000380e6, 0x00000002},
 463         {0x040025c5, 0x00000002},
 464         {0x000380e5, 0x00000002},
 465         {0x000000a8, 0x0000001c},
 466         {0x000650aa, 0x00000018},
 467         {0x040025bb, 0x00000002},
 468         {0x000610ab, 0x00000018},
 469         {0x040075bc, 0000000000},
 470         {0x000075bb, 0x00000002},
 471         {0x000075bc, 0000000000},
 472         {0x00090000, 0x00000006},
 473         {0x00090000, 0x00000002},
 474         {0x000d8002, 0x00000006},
 475         {0x00007832, 0x00000002},
 476         {0x00005000, 0x00000002},
 477         {0x000380e7, 0x00000002},
 478         {0x04002c97, 0x00000002},
 479         {0x00007820, 0x00000002},
 480         {0x00007821, 0x00000002},
 481         {0x00007800, 0000000000},
 482         {0x01200000, 0x00000002},
 483         {0x20077000, 0x00000002},
 484         {0x01200000, 0x00000002},
 485         {0x20007000, 0x00000002},
 486         {0x00061000, 0x00000002},
 487         {0x0120751b, 0x00000002},
 488         {0x8040750a, 0x00000002},
 489         {0x8040750b, 0x00000002},
 490         {0x00110000, 0x00000002},
 491         {0x000380e5, 0x00000002},
 492         {0x000000c6, 0x0000001c},
 493         {0x000610ab, 0x00000018},
 494         {0x844075bd, 0x00000002},
 495         {0x000610aa, 0x00000018},
 496         {0x840075bb, 0x00000002},
 497         {0x000610ab, 0x00000018},
 498         {0x844075bc, 0x00000002},
 499         {0x000000c9, 0x00000004},
 500         {0x804075bd, 0x00000002},
 501         {0x800075bb, 0x00000002},
 502         {0x804075bc, 0x00000002},
 503         {0x00108000, 0x00000002},
 504         {0x01400000, 0x00000002},
 505         {0x006000cd, 0x0000000c},
 506         {0x20c07000, 0x00000020},
 507         {0x000000cf, 0x00000012},
 508         {0x00800000, 0x00000006},
 509         {0x0080751d, 0x00000006},
 510         {0000000000, 0000000000},
 511         {0x0000775c, 0x00000002},
 512         {0x00a05000, 0x00000002},
 513         {0x00661000, 0x00000002},
 514         {0x0460275d, 0x00000020},
 515         {0x00004000, 0000000000},
 516         {0x01e00830, 0x00000002},
 517         {0x21007000, 0000000000},
 518         {0x6464614d, 0000000000},
 519         {0x69687420, 0000000000},
 520         {0x00000073, 0000000000},
 521         {0000000000, 0000000000},
 522         {0x00005000, 0x00000002},
 523         {0x000380d0, 0x00000002},
 524         {0x040025e0, 0x00000002},
 525         {0x000075e1, 0000000000},
 526         {0x00000001, 0000000000},
 527         {0x000380e0, 0x00000002},
 528         {0x04002394, 0x00000002},
 529         {0x00005000, 0000000000},
 530         {0000000000, 0000000000},
 531         {0000000000, 0000000000},
 532         {0x00000008, 0000000000},
 533         {0x00000004, 0000000000},
 534         {0000000000, 0000000000},
 535         {0000000000, 0000000000},
 536         {0000000000, 0000000000},
 537         {0000000000, 0000000000},
 538         {0000000000, 0000000000},
 539         {0000000000, 0000000000},
 540         {0000000000, 0000000000},
 541         {0000000000, 0000000000},
 542         {0000000000, 0000000000},
 543         {0000000000, 0000000000},
 544         {0000000000, 0000000000},
 545         {0000000000, 0000000000},
 546         {0000000000, 0000000000},
 547         {0000000000, 0000000000},
 548         {0000000000, 0000000000},
 549         {0000000000, 0000000000},
 550         {0000000000, 0000000000},
 551         {0000000000, 0000000000},
 552         {0000000000, 0000000000},
 553         {0000000000, 0000000000},
 554         {0000000000, 0000000000},
 555         {0000000000, 0000000000},
 556         {0000000000, 0000000000},
 557         {0000000000, 0000000000},
 558 };
 559
 560 static const u32 R300_cp_microcode[][2] = {
 561         { 0x4200e000, 0000000000 },
 562         { 0x4000e000, 0000000000 },
 563         { 0x000000af, 0x00000008 },
 564         { 0x000000b3, 0x00000008 },
 565         { 0x6c5a504f, 0000000000 },
 566         { 0x4f4f497a, 0000000000 },
 567         { 0x5a578288, 0000000000 },
 568         { 0x4f91906a, 0000000000 },
 569         { 0x4f4f4f4f, 0000000000 },
 570         { 0x4fe24f44, 0000000000 },
 571         { 0x4f9c9c9c, 0000000000 },
 572         { 0xdc4f4fde, 0000000000 },
 573         { 0xa1cd4f4f, 0000000000 },
 574         { 0xd29d9d9d, 0000000000 },
 575         { 0x4f0f9fd7, 0000000000 },
 576         { 0x000ca000, 0x00000004 },
 577         { 0x000d0012, 0x00000038 },
 578         { 0x0000e8b4, 0x00000004 },
 579         { 0x000d0014, 0x00000038 },
 580         { 0x0000e8b6, 0x00000004 },
 581         { 0x000d0016, 0x00000038 },
 582         { 0x0000e854, 0x00000004 },
 583         { 0x000d0018, 0x00000038 },
 584         { 0x0000e855, 0x00000004 },
 585         { 0x000d001a, 0x00000038 },
 586         { 0x0000e856, 0x00000004 },
 587         { 0x000d001c, 0x00000038 },
 588         { 0x0000e857, 0x00000004 },
 589         { 0x000d001e, 0x00000038 },
 590         { 0x0000e824, 0x00000004 },
 591         { 0x000d0020, 0x00000038 },
 592         { 0x0000e825, 0x00000004 },
 593         { 0x000d0022, 0x00000038 },
 594         { 0x0000e830, 0x00000004 },
 595         { 0x000d0024, 0x00000038 },
 596         { 0x0000f0c0, 0x00000004 },
 597         { 0x000d0026, 0x00000038 },
 598         { 0x0000f0c1, 0x00000004 },
 599         { 0x000d0028, 0x00000038 },
 600         { 0x0000f041, 0x00000004 },
 601         { 0x000d002a, 0x00000038 },
 602         { 0x0000f184, 0x00000004 },
 603         { 0x000d002c, 0x00000038 },
 604         { 0x0000f185, 0x00000004 },
 605         { 0x000d002e, 0x00000038 },
 606         { 0x0000f186, 0x00000004 },
 607         { 0x000d0030, 0x00000038 },
 608         { 0x0000f187, 0x00000004 },
 609         { 0x000d0032, 0x00000038 },
 610         { 0x0000f180, 0x00000004 },
 611         { 0x000d0034, 0x00000038 },
 612         { 0x0000f393, 0x00000004 },
 613         { 0x000d0036, 0x00000038 },
 614         { 0x0000f38a, 0x00000004 },
 615         { 0x000d0038, 0x00000038 },
 616         { 0x0000f38e, 0x00000004 },
 617         { 0x0000e821, 0x00000004 },
 618         { 0x0140a000, 0x00000004 },
 619         { 0x00000043, 0x00000018 },
 620         { 0x00cce800, 0x00000004 },
 621         { 0x001b0001, 0x00000004 },
 622         { 0x08004800, 0x00000004 },
 623         { 0x001b0001, 0x00000004 },
 624         { 0x08004800, 0x00000004 },
 625         { 0x001b0001, 0x00000004 },
 626         { 0x08004800, 0x00000004 },
 627         { 0x0000003a, 0x00000008 },
 628         { 0x0000a000, 0000000000 },
 629         { 0x02c0a000, 0x00000004 },
 630         { 0x000ca000, 0x00000004 },
 631         { 0x00130000, 0x00000004 },
 632         { 0x000c2000, 0x00000004 },
 633         { 0xc980c045, 0x00000008 },
 634         { 0x2000451d, 0x00000004 },
 635         { 0x0000e580, 0x00000004 },
 636         { 0x000ce581, 0x00000004 },
 637         { 0x08004580, 0x00000004 },
 638         { 0x000ce581, 0x00000004 },
 639         { 0x0000004c, 0x00000008 },
 640         { 0x0000a000, 0000000000 },
 641         { 0x000c2000, 0x00000004 },
 642         { 0x0000e50e, 0x00000004 },
 643         { 0x00032000, 0x00000004 },
 644         { 0x00022056, 0x00000028 },
 645         { 0x00000056, 0x00000024 },
 646         { 0x0800450f, 0x00000004 },
 647         { 0x0000a050, 0x00000008 },
 648         { 0x0000e565, 0x00000004 },
 649         { 0x0000e566, 0x00000004 },
 650         { 0x00000057, 0x00000008 },
 651         { 0x03cca5b4, 0x00000004 },
 652         { 0x05432000, 0x00000004 },
 653         { 0x00022000, 0x00000004 },
 654         { 0x4ccce063, 0x00000030 },
 655         { 0x08274565, 0x00000004 },
 656         { 0x00000063, 0x00000030 },
 657         { 0x08004564, 0x00000004 },
 658         { 0x0000e566, 0x00000004 },
 659         { 0x0000005a, 0x00000008 },
 660         { 0x00802066, 0x00000010 },
 661         { 0x00202000, 0x00000004 },
 662         { 0x001b00ff, 0x00000004 },
 663         { 0x01000069, 0x00000010 },
 664         { 0x001f2000, 0x00000004 },
 665         { 0x001c00ff, 0x00000004 },
 666         { 0000000000, 0x0000000c },
 667         { 0x00000085, 0x00000030 },
 668         { 0x0000005a, 0x00000008 },
 669         { 0x0000e576, 0x00000004 },
 670         { 0x000ca000, 0x00000004 },
 671         { 0x00012000, 0x00000004 },
 672         { 0x00082000, 0x00000004 },
 673         { 0x1800650e, 0x00000004 },
 674         { 0x00092000, 0x00000004 },
 675         { 0x000a2000, 0x00000004 },
 676         { 0x000f0000, 0x00000004 },
 677         { 0x00400000, 0x00000004 },
 678         { 0x00000079, 0x00000018 },
 679         { 0x0000e563, 0x00000004 },
 680         { 0x00c0e5f9, 0x000000c2 },
 681         { 0x0000006e, 0x00000008 },
 682         { 0x0000a06e, 0x00000008 },
 683         { 0x0000e576, 0x00000004 },
 684         { 0x0000e577, 0x00000004 },
 685         { 0x0000e50e, 0x00000004 },
 686         { 0x0000e50f, 0x00000004 },
 687         { 0x0140a000, 0x00000004 },
 688         { 0x0000007c, 0x00000018 },
 689         { 0x00c0e5f9, 0x000000c2 },
 690         { 0x0000007c, 0x00000008 },
 691         { 0x0014e50e, 0x00000004 },
 692         { 0x0040e50f, 0x00000004 },
 693         { 0x00c0007f, 0x00000008 },
 694         { 0x0000e570, 0x00000004 },
 695         { 0x0000e571, 0x00000004 },
 696         { 0x0000e572, 0x0000000c },
 697         { 0x0000a000, 0x00000004 },
 698         { 0x0140a000, 0x00000004 },
 699         { 0x0000e568, 0x00000004 },
 700         { 0x000c2000, 0x00000004 },
 701         { 0x00000089, 0x00000018 },
 702         { 0x000b0000, 0x00000004 },
 703         { 0x18c0e562, 0x00000004 },
 704         { 0x0000008b, 0x00000008 },
 705         { 0x00c0008a, 0x00000008 },
 706         { 0x000700e4, 0x00000004 },
 707         { 0x00000097, 0x00000038 },
 708         { 0x000ca099, 0x00000030 },
 709         { 0x080045bb, 0x00000004 },
 710         { 0x000c209a, 0x00000030 },
 711         { 0x0800e5bc, 0000000000 },
 712         { 0x0000e5bb, 0x00000004 },
 713         { 0x0000e5bc, 0000000000 },
 714         { 0x00120000, 0x0000000c },
 715         { 0x00120000, 0x00000004 },
 716         { 0x001b0002, 0x0000000c },
 717         { 0x0000a000, 0x00000004 },
 718         { 0x0000e821, 0x00000004 },
 719         { 0x0000e800, 0000000000 },
 720         { 0x0000e821, 0x00000004 },
 721         { 0x0000e82e, 0000000000 },
 722         { 0x02cca000, 0x00000004 },
 723         { 0x00140000, 0x00000004 },
 724         { 0x000ce1cc, 0x00000004 },
 725         { 0x050de1cd, 0x00000004 },
 726         { 0x000000a7, 0x00000020 },
 727         { 0x4200e000, 0000000000 },
 728         { 0x000000ae, 0x00000038 },
 729         { 0x000ca000, 0x00000004 },
 730         { 0x00140000, 0x00000004 },
 731         { 0x000c2000, 0x00000004 },
 732         { 0x00160000, 0x00000004 },
 733         { 0x700ce000, 0x00000004 },
 734         { 0x001400aa, 0x00000008 },
 735         { 0x4000e000, 0000000000 },
 736         { 0x02400000, 0x00000004 },
 737         { 0x400ee000, 0x00000004 },
 738         { 0x02400000, 0x00000004 },
 739         { 0x4000e000, 0000000000 },
 740         { 0x000c2000, 0x00000004 },
 741         { 0x0240e51b, 0x00000004 },
 742         { 0x0080e50a, 0x00000005 },
 743         { 0x0080e50b, 0x00000005 },
 744         { 0x00220000, 0x00000004 },
 745         { 0x000700e4, 0x00000004 },
 746         { 0x000000c1, 0x00000038 },
 747         { 0x000c209a, 0x00000030 },
 748         { 0x0880e5bd, 0x00000005 },
 749         { 0x000c2099, 0x00000030 },
 750         { 0x0800e5bb, 0x00000005 },
 751         { 0x000c209a, 0x00000030 },
 752         { 0x0880e5bc, 0x00000005 },
 753         { 0x000000c4, 0x00000008 },
 754         { 0x0080e5bd, 0x00000005 },
 755         { 0x0000e5bb, 0x00000005 },
 756         { 0x0080e5bc, 0x00000005 },
 757         { 0x00210000, 0x00000004 },
 758         { 0x02800000, 0x00000004 },
 759         { 0x00c000c8, 0x00000018 },
 760         { 0x4180e000, 0x00000040 },
 761         { 0x000000ca, 0x00000024 },
 762         { 0x01000000, 0x0000000c },
 763         { 0x0100e51d, 0x0000000c },
 764         { 0x000045bb, 0x00000004 },
 765         { 0x000080c4, 0x00000008 },
 766         { 0x0000f3ce, 0x00000004 },
 767         { 0x0140a000, 0x00000004 },
 768         { 0x00cc2000, 0x00000004 },
 769         { 0x08c053cf, 0x00000040 },
 770         { 0x00008000, 0000000000 },
 771         { 0x0000f3d2, 0x00000004 },
 772         { 0x0140a000, 0x00000004 },
 773         { 0x00cc2000, 0x00000004 },
 774         { 0x08c053d3, 0x00000040 },
 775         { 0x00008000, 0000000000 },
 776         { 0x0000f39d, 0x00000004 },
 777         { 0x0140a000, 0x00000004 },
 778         { 0x00cc2000, 0x00000004 },
 779         { 0x08c0539e, 0x00000040 },
 780         { 0x00008000, 0000000000 },
 781         { 0x03c00830, 0x00000004 },
 782         { 0x4200e000, 0000000000 },
 783         { 0x0000a000, 0x00000004 },
 784         { 0x200045e0, 0x00000004 },
 785         { 0x0000e5e1, 0000000000 },
 786         { 0x00000001, 0000000000 },
 787         { 0x000700e1, 0x00000004 },
 788         { 0x0800e394, 0000000000 },
 789         { 0000000000, 0000000000 },
 790         { 0000000000, 0000000000 },
 791         { 0000000000, 0000000000 },
 792         { 0000000000, 0000000000 },
 793         { 0000000000, 0000000000 },
 794         { 0000000000, 0000000000 },
 795         { 0000000000, 0000000000 },
 796         { 0000000000, 0000000000 },
 797         { 0000000000, 0000000000 },
 798         { 0000000000, 0000000000 },
 799         { 0000000000, 0000000000 },
 800         { 0000000000, 0000000000 },
 801         { 0000000000, 0000000000 },
 802         { 0000000000, 0000000000 },
 803         { 0000000000, 0000000000 },
 804         { 0000000000, 0000000000 },
 805         { 0000000000, 0000000000 },
 806         { 0000000000, 0000000000 },
 807         { 0000000000, 0000000000 },
 808         { 0000000000, 0000000000 },
 809         { 0000000000, 0000000000 },
 810         { 0000000000, 0000000000 },
 811         { 0000000000, 0000000000 },
 812         { 0000000000, 0000000000 },
 813         { 0000000000, 0000000000 },
 814         { 0000000000, 0000000000 },
 815         { 0000000000, 0000000000 },
 816         { 0000000000, 0000000000 },
 817 };
 818
 819 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
 820 {
 821         drm_radeon_private_t *dev_priv = dev->dev_private;
 822
 823         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
 824         return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 825 }
 826
 827 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
 828 {
 829         RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
 830         return RADEON_READ(RADEON_PCIE_DATA);
 831 }
 832
 833 static u32 RADEON_READ_IGPGART(drm_radeon_private_t *dev_priv, int addr)
 834 {
 835         u32 ret;
 836         RADEON_WRITE(RADEON_IGPGART_INDEX, addr & 0x7f);
 837         ret = RADEON_READ(RADEON_IGPGART_DATA);
 838         RADEON_WRITE(RADEON_IGPGART_INDEX, 0x7f);
 839         return ret;
 840 }
 841
 842 #if RADEON_FIFO_DEBUG
 843 static void radeon_status(drm_radeon_private_t * dev_priv)
 844 {
 845         printk("%s:\n", __FUNCTION__);
 846         printk("RBBM_STATUS = 0x%08x\n",
 847                (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
 848         printk("CP_RB_RTPR = 0x%08x\n",
 849                (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
 850         printk("CP_RB_WTPR = 0x%08x\n",
 851                (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
 852         printk("AIC_CNTL = 0x%08x\n",
 853                (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
 854         printk("AIC_STAT = 0x%08x\n",
 855                (unsigned int)RADEON_READ(RADEON_AIC_STAT));
 856         printk("AIC_PT_BASE = 0x%08x\n",
 857                (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
 858         printk("TLB_ADDR = 0x%08x\n",
 859                (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
 860         printk("TLB_DATA = 0x%08x\n",
 861                (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
 862 }
 863 #endif
 864
 865 /* ================================================================
 866  * Engine, FIFO control
 867  */
 868
 869 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
 870 {
 871         u32 tmp;
 872         int i;
 873
 874         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 875
 876         tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
 877         tmp |= RADEON_RB3D_DC_FLUSH_ALL;
 878         RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
 879
 880         for (i = 0; i < dev_priv->usec_timeout; i++) {
 881                 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
 882                       & RADEON_RB3D_DC_BUSY)) {
 883                         return 0;
 884                 }
 885                 DRM_UDELAY(1);
 886         }
 887
 888 #if RADEON_FIFO_DEBUG
 889         DRM_ERROR("failed!\n");
 890         radeon_status(dev_priv);
 891 #endif
 892         return -EBUSY;
 893 }
 894
 895 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
 896 {
 897         int i;
 898
 899         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 900
 901         for (i = 0; i < dev_priv->usec_timeout; i++) {
 902                 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
 903                              & RADEON_RBBM_FIFOCNT_MASK);
 904                 if (slots >= entries)
 905                         return 0;
 906                 DRM_UDELAY(1);
 907         }
 908
 909 #if RADEON_FIFO_DEBUG
 910         DRM_ERROR("failed!\n");
 911         radeon_status(dev_priv);
 912 #endif
 913         return -EBUSY;
 914 }
 915
 916 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
 917 {
 918         int i, ret;
 919
 920         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 921
 922         ret = radeon_do_wait_for_fifo(dev_priv, 64);
 923         if (ret)
 924                 return ret;
 925
 926         for (i = 0; i < dev_priv->usec_timeout; i++) {
 927                 if (!(RADEON_READ(RADEON_RBBM_STATUS)
 928                       & RADEON_RBBM_ACTIVE)) {
 929                         radeon_do_pixcache_flush(dev_priv);
 930                         return 0;
 931                 }
 932                 DRM_UDELAY(1);
 933         }
 934
 935 #if RADEON_FIFO_DEBUG
 936         DRM_ERROR("failed!\n");
 937         radeon_status(dev_priv);
 938 #endif
 939         return -EBUSY;
 940 }
 941
 942 /* ================================================================
 943  * CP control, initialization
 944  */
 945
 946 /* Load the microcode for the CP */
 947 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
 948 {
 949         int i;
 950         DRM_DEBUG("\n");
 951
 952         radeon_do_wait_for_idle(dev_priv);
 953
 954         RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
 955
 956         if (dev_priv->microcode_version == UCODE_R200) {
 957                 DRM_INFO("Loading R200 Microcode\n");
 958                 for (i = 0; i < 256; i++) {
 959                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 960                                      R200_cp_microcode[i][1]);
 961                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 962                                      R200_cp_microcode[i][0]);
 963                 }
 964         } else if (dev_priv->microcode_version == UCODE_R300) {
 965                 DRM_INFO("Loading R300 Microcode\n");
 966                 for (i = 0; i < 256; i++) {
 967                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 968                                      R300_cp_microcode[i][1]);
 969                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 970                                      R300_cp_microcode[i][0]);
 971                 }
 972         } else {
 973                 for (i = 0; i < 256; i++) {
 974                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 975                                      radeon_cp_microcode[i][1]);
 976                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 977                                      radeon_cp_microcode[i][0]);
 978                 }
 979         }
 980 }
 981
 982 /* Flush any pending commands to the CP.  This should only be used just
 983  * prior to a wait for idle, as it informs the engine that the command
 984  * stream is ending.
 985  */
 986 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
 987 {
 988         DRM_DEBUG("\n");
 989 #if 0
 990         u32 tmp;
 991
 992         tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
 993         RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
 994 #endif
 995 }
 996
 997 /* Wait for the CP to go idle.
 998  */
 999 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
1000 {
1001         RING_LOCALS;
1002         DRM_DEBUG("\n");
1003
1004         BEGIN_RING(6);
1005
1006         RADEON_PURGE_CACHE();
1007         RADEON_PURGE_ZCACHE();
1008         RADEON_WAIT_UNTIL_IDLE();
1009
1010         ADVANCE_RING();
1011         COMMIT_RING();
1012
1013         return radeon_do_wait_for_idle(dev_priv);
1014 }
1015
1016 /* Start the Command Processor.
1017  */
1018 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
1019 {
1020         RING_LOCALS;
1021         DRM_DEBUG("\n");
1022
1023         radeon_do_wait_for_idle(dev_priv);
1024
1025         RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
1026
1027         dev_priv->cp_running = 1;
1028
1029         BEGIN_RING(6);
1030
1031         RADEON_PURGE_CACHE();
1032         RADEON_PURGE_ZCACHE();
1033         RADEON_WAIT_UNTIL_IDLE();
1034
1035         ADVANCE_RING();
1036         COMMIT_RING();
1037 }
1038
1039 /* Reset the Command Processor.  This will not flush any pending
1040  * commands, so you must wait for the CP command stream to complete
1041  * before calling this routine.
1042  */
1043 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
1044 {
1045         u32 cur_read_ptr;
1046         DRM_DEBUG("\n");
1047
1048         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
1049         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
1050         SET_RING_HEAD(dev_priv, cur_read_ptr);
1051         dev_priv->ring.tail = cur_read_ptr;
1052 }
1053
1054 /* Stop the Command Processor.  This will not flush any pending
1055  * commands, so you must flush the command stream and wait for the CP
1056  * to go idle before calling this routine.
1057  */
1058 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
1059 {
1060         DRM_DEBUG("\n");
1061
1062         RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
1063
1064         dev_priv->cp_running = 0;
1065 }
1066
1067 /* Reset the engine.  This will stop the CP if it is running.
1068  */
1069 static int radeon_do_engine_reset(struct drm_device * dev)
1070 {
1071         drm_radeon_private_t *dev_priv = dev->dev_private;
1072         u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
1073         DRM_DEBUG("\n");
1074
1075         radeon_do_pixcache_flush(dev_priv);
1076
1077         clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
1078         mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
1079
1080         RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
1081                                             RADEON_FORCEON_MCLKA |
1082                                             RADEON_FORCEON_MCLKB |
1083                                             RADEON_FORCEON_YCLKA |
1084                                             RADEON_FORCEON_YCLKB |
1085                                             RADEON_FORCEON_MC |
1086                                             RADEON_FORCEON_AIC));
1087
1088         rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
1089
1090         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
1091                                               RADEON_SOFT_RESET_CP |
1092                                               RADEON_SOFT_RESET_HI |
1093                                               RADEON_SOFT_RESET_SE |
1094                                               RADEON_SOFT_RESET_RE |
1095                                               RADEON_SOFT_RESET_PP |
1096                                               RADEON_SOFT_RESET_E2 |
1097                                               RADEON_SOFT_RESET_RB));
1098         RADEON_READ(RADEON_RBBM_SOFT_RESET);
1099         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
1100                                               ~(RADEON_SOFT_RESET_CP |
1101                                                 RADEON_SOFT_RESET_HI |
1102                                                 RADEON_SOFT_RESET_SE |
1103                                                 RADEON_SOFT_RESET_RE |
1104                                                 RADEON_SOFT_RESET_PP |
1105                                                 RADEON_SOFT_RESET_E2 |
1106                                                 RADEON_SOFT_RESET_RB)));
1107         RADEON_READ(RADEON_RBBM_SOFT_RESET);
1108
1109         RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
1110         RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
1111         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
1112
1113         /* Reset the CP ring */
1114         radeon_do_cp_reset(dev_priv);
1115
1116         /* The CP is no longer running after an engine reset */
1117         dev_priv->cp_running = 0;
1118
1119         /* Reset any pending vertex, indirect buffers */
1120         radeon_freelist_reset(dev);
1121
1122         return 0;
1123 }
1124
1125 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
1126                                        drm_radeon_private_t * dev_priv)
1127 {
1128         u32 ring_start, cur_read_ptr;
1129         u32 tmp;
1130
1131         /* Initialize the memory controller. With new memory map, the fb location
1132          * is not changed, it should have been properly initialized already. Part
1133          * of the problem is that the code below is bogus, assuming the GART is
1134          * always appended to the fb which is not necessarily the case
1135          */
1136         if (!dev_priv->new_memmap)
1137                 RADEON_WRITE(RADEON_MC_FB_LOCATION,
1138                              ((dev_priv->gart_vm_start - 1) & 0xffff0000)
1139                              | (dev_priv->fb_location >> 16));
1140
1141 #if __OS_HAS_AGP
1142         if (dev_priv->flags & RADEON_IS_AGP) {
1143                 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);
1144                 RADEON_WRITE(RADEON_MC_AGP_LOCATION,
1145                              (((dev_priv->gart_vm_start - 1 +
1146                                 dev_priv->gart_size) & 0xffff0000) |
1147                               (dev_priv->gart_vm_start >> 16)));
1148
1149                 ring_start = (dev_priv->cp_ring->offset
1150                               - dev->agp->base
1151                               + dev_priv->gart_vm_start);
1152         } else
1153 #endif
1154                 ring_start = (dev_priv->cp_ring->offset
1155                               - (unsigned long)dev->sg->virtual
1156                               + dev_priv->gart_vm_start);
1157
1158         RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
1159
1160         /* Set the write pointer delay */
1161         RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
1162
1163         /* Initialize the ring buffer's read and write pointers */
1164         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
1165         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
1166         SET_RING_HEAD(dev_priv, cur_read_ptr);
1167         dev_priv->ring.tail = cur_read_ptr;
1168
1169 #if __OS_HAS_AGP
1170         if (dev_priv->flags & RADEON_IS_AGP) {
1171                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
1172                              dev_priv->ring_rptr->offset
1173                              - dev->agp->base + dev_priv->gart_vm_start);
1174         } else
1175 #endif
1176         {
1177                 struct drm_sg_mem *entry = dev->sg;
1178                 unsigned long tmp_ofs, page_ofs;
1179
1180                 tmp_ofs = dev_priv->ring_rptr->offset -
1181                                 (unsigned long)dev->sg->virtual;
1182                 page_ofs = tmp_ofs >> PAGE_SHIFT;
1183
1184                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
1185                 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
1186                           (unsigned long)entry->busaddr[page_ofs],
1187                           entry->handle + tmp_ofs);
1188         }
1189
1190         /* Set ring buffer size */
1191 #ifdef __BIG_ENDIAN
1192         RADEON_WRITE(RADEON_CP_RB_CNTL,
1193                      RADEON_BUF_SWAP_32BIT |
1194                      (dev_priv->ring.fetch_size_l2ow << 18) |
1195                      (dev_priv->ring.rptr_update_l2qw << 8) |
1196                      dev_priv->ring.size_l2qw);
1197 #else
1198         RADEON_WRITE(RADEON_CP_RB_CNTL,
1199                      (dev_priv->ring.fetch_size_l2ow << 18) |
1200                      (dev_priv->ring.rptr_update_l2qw << 8) |
1201                      dev_priv->ring.size_l2qw);
1202 #endif
1203
1204         /* Start with assuming that writeback doesn't work */
1205         dev_priv->writeback_works = 0;
1206
1207         /* Initialize the scratch register pointer.  This will cause
1208          * the scratch register values to be written out to memory
1209          * whenever they are updated.
1210          *
1211          * We simply put this behind the ring read pointer, this works
1212          * with PCI GART as well as (whatever kind of) AGP GART
1213          */
1214         RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
1215                      + RADEON_SCRATCH_REG_OFFSET);
1216
1217         dev_priv->scratch = ((__volatile__ u32 *)
1218                              dev_priv->ring_rptr->handle +
1219                              (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
1220
1221         RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
1222
1223         /* Turn on bus mastering */
1224         tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
1225         RADEON_WRITE(RADEON_BUS_CNTL, tmp);
1226
1227         dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
1228         RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
1229
1230         dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
1231         RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
1232                      dev_priv->sarea_priv->last_dispatch);
1233
1234         dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
1235         RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
1236
1237         radeon_do_wait_for_idle(dev_priv);
1238
1239         /* Sync everything up */
1240         RADEON_WRITE(RADEON_ISYNC_CNTL,
1241                      (RADEON_ISYNC_ANY2D_IDLE3D |
1242                       RADEON_ISYNC_ANY3D_IDLE2D |
1243                       RADEON_ISYNC_WAIT_IDLEGUI |
1244                       RADEON_ISYNC_CPSCRATCH_IDLEGUI));
1245
1246 }
1247
1248 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
1249 {
1250         u32 tmp;
1251
1252         /* Writeback doesn't seem to work everywhere, test it here and possibly
1253          * enable it if it appears to work
1254          */
1255         DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
1256         RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
1257
1258         for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
1259                 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
1260                     0xdeadbeef)
1261                         break;
1262                 DRM_UDELAY(1);
1263         }
1264
1265         if (tmp < dev_priv->usec_timeout) {
1266                 dev_priv->writeback_works = 1;
1267                 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
1268         } else {
1269                 dev_priv->writeback_works = 0;
1270                 DRM_INFO("writeback test failed\n");
1271         }
1272         if (radeon_no_wb == 1) {
1273                 dev_priv->writeback_works = 0;
1274                 DRM_INFO("writeback forced off\n");
1275         }
1276
1277         if (!dev_priv->writeback_works) {
1278                 /* Disable writeback to avoid unnecessary bus master transfers */
1279                 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) | RADEON_RB_NO_UPDATE);
1280                 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
1281         }
1282 }
1283
1284 /* Enable or disable IGP GART on the chip */
1285 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
1286 {
1287         u32 temp, tmp;
1288
1289         tmp = RADEON_READ(RADEON_AIC_CNTL);
1290         DRM_DEBUG("setting igpgart AIC CNTL is %08X\n", tmp);
1291         if (on) {
1292                 DRM_DEBUG("programming igpgart %08X %08lX %08X\n",
1293                          dev_priv->gart_vm_start,
1294                          (long)dev_priv->gart_info.bus_addr,
1295                          dev_priv->gart_size);
1296
1297                 RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_18, 0x1000);
1298                 RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, 0x1);
1299                 RADEON_WRITE_IGPGART(RADEON_IGPGART_CTRL, 0x42040800);
1300                 RADEON_WRITE_IGPGART(RADEON_IGPGART_BASE_ADDR,
1301                                      dev_priv->gart_info.bus_addr);
1302
1303                 temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_39);
1304                 RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_39, temp);
1305
1306                 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start);
1307                 dev_priv->gart_size = 32*1024*1024;
1308                 RADEON_WRITE(RADEON_MC_AGP_LOCATION,
1309                              (((dev_priv->gart_vm_start - 1 +
1310                                dev_priv->gart_size) & 0xffff0000) |
1311                              (dev_priv->gart_vm_start >> 16)));
1312
1313                 temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_ENABLE);
1314                 RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, temp);
1315
1316                 RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
1317                 RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x1);
1318                 RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
1319                 RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x0);
1320        }
1321 }
1322
1323 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
1324 {
1325         u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
1326         if (on) {
1327
1328                 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
1329                           dev_priv->gart_vm_start,
1330                           (long)dev_priv->gart_info.bus_addr,
1331                           dev_priv->gart_size);
1332                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
1333                                   dev_priv->gart_vm_start);
1334                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
1335                                   dev_priv->gart_info.bus_addr);
1336                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
1337                                   dev_priv->gart_vm_start);
1338                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
1339                                   dev_priv->gart_vm_start +
1340                                   dev_priv->gart_size - 1);
1341
1342                 RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0);       /* ?? */
1343
1344                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1345                                   RADEON_PCIE_TX_GART_EN);
1346         } else {
1347                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1348                                   tmp & ~RADEON_PCIE_TX_GART_EN);
1349         }
1350 }
1351
1352 /* Enable or disable PCI GART on the chip */
1353 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1354 {
1355         u32 tmp;
1356
1357         if (dev_priv->flags & RADEON_IS_IGPGART) {
1358                 radeon_set_igpgart(dev_priv, on);
1359                 return;
1360         }
1361
1362         if (dev_priv->flags & RADEON_IS_PCIE) {
1363                 radeon_set_pciegart(dev_priv, on);
1364                 return;
1365         }
1366
1367         tmp = RADEON_READ(RADEON_AIC_CNTL);
1368
1369         if (on) {
1370                 RADEON_WRITE(RADEON_AIC_CNTL,
1371                              tmp | RADEON_PCIGART_TRANSLATE_EN);
1372
1373                 /* set PCI GART page-table base address
1374                  */
1375                 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
1376
1377                 /* set address range for PCI address translate
1378                  */
1379                 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1380                 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1381                              + dev_priv->gart_size - 1);
1382
1383                 /* Turn off AGP aperture -- is this required for PCI GART?
1384                  */
1385                 RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0);       /* ?? */
1386                 RADEON_WRITE(RADEON_AGP_COMMAND, 0);    /* clear AGP_COMMAND */
1387         } else {
1388                 RADEON_WRITE(RADEON_AIC_CNTL,
1389                              tmp & ~RADEON_PCIGART_TRANSLATE_EN);
1390         }
1391 }
1392
1393 static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
1394 {
1395         drm_radeon_private_t *dev_priv = dev->dev_private;
1396
1397         DRM_DEBUG("\n");
1398
1399         /* if we require new memory map but we don't have it fail */
1400         if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1401                 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1402                 radeon_do_cleanup_cp(dev);
1403                 return -EINVAL;
1404         }
1405
1406         if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP))
1407         {
1408                 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1409                 dev_priv->flags &= ~RADEON_IS_AGP;
1410         }
1411         else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1412                  && !init->is_pci)
1413         {
1414                 DRM_DEBUG("Restoring AGP flag\n");
1415                 dev_priv->flags |= RADEON_IS_AGP;
1416         }
1417
1418         if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
1419                 DRM_ERROR("PCI GART memory not allocated!\n");
1420                 radeon_do_cleanup_cp(dev);
1421                 return -EINVAL;
1422         }
1423
1424         dev_priv->usec_timeout = init->usec_timeout;
1425         if (dev_priv->usec_timeout < 1 ||
1426             dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1427                 DRM_DEBUG("TIMEOUT problem!\n");
1428                 radeon_do_cleanup_cp(dev);
1429                 return -EINVAL;
1430         }
1431
1432         /* Enable vblank on CRTC1 for older X servers
1433          */
1434         dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1435
1436         switch(init->func) {
1437         case RADEON_INIT_R200_CP:
1438                 dev_priv->microcode_version = UCODE_R200;
1439                 break;
1440         case RADEON_INIT_R300_CP:
1441                 dev_priv->microcode_version = UCODE_R300;
1442                 break;
1443         default:
1444                 dev_priv->microcode_version = UCODE_R100;
1445         }
1446
1447         dev_priv->do_boxes = 0;
1448         dev_priv->cp_mode = init->cp_mode;
1449
1450         /* We don't support anything other than bus-mastering ring mode,
1451          * but the ring can be in either AGP or PCI space for the ring
1452          * read pointer.
1453          */
1454         if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1455             (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1456                 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1457                 radeon_do_cleanup_cp(dev);
1458                 return -EINVAL;
1459         }
1460
1461         switch (init->fb_bpp) {
1462         case 16:
1463                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1464                 break;
1465         case 32:
1466         default:
1467                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1468                 break;
1469         }
1470         dev_priv->front_offset = init->front_offset;
1471         dev_priv->front_pitch = init->front_pitch;
1472         dev_priv->back_offset = init->back_offset;
1473         dev_priv->back_pitch = init->back_pitch;
1474
1475         switch (init->depth_bpp) {
1476         case 16:
1477                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1478                 break;
1479         case 32:
1480         default:
1481                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1482                 break;
1483         }
1484         dev_priv->depth_offset = init->depth_offset;
1485         dev_priv->depth_pitch = init->depth_pitch;
1486
1487         /* Hardware state for depth clears.  Remove this if/when we no
1488          * longer clear the depth buffer with a 3D rectangle.  Hard-code
1489          * all values to prevent unwanted 3D state from slipping through
1490          * and screwing with the clear operation.
1491          */
1492         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1493                                            (dev_priv->color_fmt << 10) |
1494                                            (dev_priv->microcode_version ==
1495                                             UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1496
1497         dev_priv->depth_clear.rb3d_zstencilcntl =
1498             (dev_priv->depth_fmt |
1499              RADEON_Z_TEST_ALWAYS |
1500              RADEON_STENCIL_TEST_ALWAYS |
1501              RADEON_STENCIL_S_FAIL_REPLACE |
1502              RADEON_STENCIL_ZPASS_REPLACE |
1503              RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1504
1505         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1506                                          RADEON_BFACE_SOLID |
1507                                          RADEON_FFACE_SOLID |
1508                                          RADEON_FLAT_SHADE_VTX_LAST |
1509                                          RADEON_DIFFUSE_SHADE_FLAT |
1510                                          RADEON_ALPHA_SHADE_FLAT |
1511                                          RADEON_SPECULAR_SHADE_FLAT |
1512                                          RADEON_FOG_SHADE_FLAT |
1513                                          RADEON_VTX_PIX_CENTER_OGL |
1514                                          RADEON_ROUND_MODE_TRUNC |
1515                                          RADEON_ROUND_PREC_8TH_PIX);
1516
1517
1518         dev_priv->ring_offset = init->ring_offset;
1519         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1520         dev_priv->buffers_offset = init->buffers_offset;
1521         dev_priv->gart_textures_offset = init->gart_textures_offset;
1522
1523         dev_priv->sarea = drm_getsarea(dev);
1524         if (!dev_priv->sarea) {
1525                 DRM_ERROR("could not find sarea!\n");
1526                 radeon_do_cleanup_cp(dev);
1527                 return -EINVAL;
1528         }
1529
1530         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1531         if (!dev_priv->cp_ring) {
1532                 DRM_ERROR("could not find cp ring region!\n");
1533                 radeon_do_cleanup_cp(dev);
1534                 return -EINVAL;
1535         }
1536         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1537         if (!dev_priv->ring_rptr) {
1538                 DRM_ERROR("could not find ring read pointer!\n");
1539                 radeon_do_cleanup_cp(dev);
1540                 return -EINVAL;
1541         }
1542         dev->agp_buffer_token = init->buffers_offset;
1543         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1544         if (!dev->agp_buffer_map) {
1545                 DRM_ERROR("could not find dma buffer region!\n");
1546                 radeon_do_cleanup_cp(dev);
1547                 return -EINVAL;
1548         }
1549
1550         if (init->gart_textures_offset) {
1551                 dev_priv->gart_textures =
1552                     drm_core_findmap(dev, init->gart_textures_offset);
1553                 if (!dev_priv->gart_textures) {
1554                         DRM_ERROR("could not find GART texture region!\n");
1555                         radeon_do_cleanup_cp(dev);
1556                         return -EINVAL;
1557                 }
1558         }
1559
1560         dev_priv->sarea_priv =
1561             (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
1562                                     init->sarea_priv_offset);
1563
1564 #if __OS_HAS_AGP
1565         if (dev_priv->flags & RADEON_IS_AGP) {
1566                 drm_core_ioremap(dev_priv->cp_ring, dev);
1567                 drm_core_ioremap(dev_priv->ring_rptr, dev);
1568                 drm_core_ioremap(dev->agp_buffer_map, dev);
1569                 if (!dev_priv->cp_ring->handle ||
1570                     !dev_priv->ring_rptr->handle ||
1571                     !dev->agp_buffer_map->handle) {
1572                         DRM_ERROR("could not find ioremap agp regions!\n");
1573                         radeon_do_cleanup_cp(dev);
1574                         return -EINVAL;
1575                 }
1576         } else
1577 #endif
1578         {
1579                 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1580                 dev_priv->ring_rptr->handle =
1581                     (void *)dev_priv->ring_rptr->offset;
1582                 dev->agp_buffer_map->handle =
1583                     (void *)dev->agp_buffer_map->offset;
1584
1585                 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1586                           dev_priv->cp_ring->handle);
1587                 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1588                           dev_priv->ring_rptr->handle);
1589                 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1590                           dev->agp_buffer_map->handle);
1591         }
1592
1593         dev_priv->fb_location = (RADEON_READ(RADEON_MC_FB_LOCATION)
1594                                  & 0xffff) << 16;
1595         dev_priv->fb_size =
1596                 ((RADEON_READ(RADEON_MC_FB_LOCATION) & 0xffff0000u) + 0x10000)
1597                 - dev_priv->fb_location;
1598
1599         dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1600                                         ((dev_priv->front_offset
1601                                           + dev_priv->fb_location) >> 10));
1602
1603         dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1604                                        ((dev_priv->back_offset
1605                                          + dev_priv->fb_location) >> 10));
1606
1607         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1608                                         ((dev_priv->depth_offset
1609                                           + dev_priv->fb_location) >> 10));
1610
1611         dev_priv->gart_size = init->gart_size;
1612
1613         /* New let's set the memory map ... */
1614         if (dev_priv->new_memmap) {
1615                 u32 base = 0;
1616
1617                 DRM_INFO("Setting GART location based on new memory map\n");
1618
1619                 /* If using AGP, try to locate the AGP aperture at the same
1620                  * location in the card and on the bus, though we have to
1621                  * align it down.
1622                  */
1623 #if __OS_HAS_AGP
1624                 if (dev_priv->flags & RADEON_IS_AGP) {
1625                         base = dev->agp->base;
1626                         /* Check if valid */
1627                         if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1628                             base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1629                                 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1630                                          dev->agp->base);
1631                                 base = 0;
1632                         }
1633                 }
1634 #endif
1635                 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1636                 if (base == 0) {
1637                         base = dev_priv->fb_location + dev_priv->fb_size;
1638                         if (base < dev_priv->fb_location ||
1639                             ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1640                                 base = dev_priv->fb_location
1641                                         - dev_priv->gart_size;
1642                 }
1643                 dev_priv->gart_vm_start = base & 0xffc00000u;
1644                 if (dev_priv->gart_vm_start != base)
1645                         DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1646                                  base, dev_priv->gart_vm_start);
1647         } else {
1648                 DRM_INFO("Setting GART location based on old memory map\n");
1649                 dev_priv->gart_vm_start = dev_priv->fb_location +
1650                         RADEON_READ(RADEON_CONFIG_APER_SIZE);
1651         }
1652
1653 #if __OS_HAS_AGP
1654         if (dev_priv->flags & RADEON_IS_AGP)
1655                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1656                                                  - dev->agp->base
1657                                                  + dev_priv->gart_vm_start);
1658         else
1659 #endif
1660                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1661                                         - (unsigned long)dev->sg->virtual
1662                                         + dev_priv->gart_vm_start);
1663
1664         DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1665         DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1666         DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1667                   dev_priv->gart_buffers_offset);
1668
1669         dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1670         dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1671                               + init->ring_size / sizeof(u32));
1672         dev_priv->ring.size = init->ring_size;
1673         dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1674
1675         dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1676         dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1677
1678         dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1679         dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1680
1681         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1682
1683         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1684
1685 #if __OS_HAS_AGP
1686         if (dev_priv->flags & RADEON_IS_AGP) {
1687                 /* Turn off PCI GART */
1688                 radeon_set_pcigart(dev_priv, 0);
1689         } else
1690 #endif
1691         {
1692                 /* if we have an offset set from userspace */
1693                 if (dev_priv->pcigart_offset_set) {
1694                         dev_priv->gart_info.bus_addr =
1695                             dev_priv->pcigart_offset + dev_priv->fb_location;
1696                         dev_priv->gart_info.mapping.offset =
1697                             dev_priv->gart_info.bus_addr;
1698                         dev_priv->gart_info.mapping.size =
1699                             dev_priv->gart_info.table_size;
1700
1701                         drm_core_ioremap(&dev_priv->gart_info.mapping, dev);
1702                         dev_priv->gart_info.addr =
1703                             dev_priv->gart_info.mapping.handle;
1704
1705                         if (dev_priv->flags & RADEON_IS_PCIE)
1706                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1707                         else
1708                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1709                         dev_priv->gart_info.gart_table_location =
1710                             DRM_ATI_GART_FB;
1711
1712                         DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1713                                   dev_priv->gart_info.addr,
1714                                   dev_priv->pcigart_offset);
1715                 } else {
1716                         if (dev_priv->flags & RADEON_IS_IGPGART)
1717                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1718                         else
1719                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1720                         dev_priv->gart_info.gart_table_location =
1721                             DRM_ATI_GART_MAIN;
1722                         dev_priv->gart_info.addr = NULL;
1723                         dev_priv->gart_info.bus_addr = 0;
1724                         if (dev_priv->flags & RADEON_IS_PCIE) {
1725                                 DRM_ERROR
1726                                     ("Cannot use PCI Express without GART in FB memory\n");
1727                                 radeon_do_cleanup_cp(dev);
1728                                 return -EINVAL;
1729                         }
1730                 }
1731
1732                 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
1733                         DRM_ERROR("failed to init PCI GART!\n");
1734                         radeon_do_cleanup_cp(dev);
1735                         return -ENOMEM;
1736                 }
1737
1738                 /* Turn on PCI GART */
1739                 radeon_set_pcigart(dev_priv, 1);
1740         }
1741
1742         radeon_cp_load_microcode(dev_priv);
1743         radeon_cp_init_ring_buffer(dev, dev_priv);
1744
1745         dev_priv->last_buf = 0;
1746
1747         radeon_do_engine_reset(dev);
1748         radeon_test_writeback(dev_priv);
1749
1750         return 0;
1751 }
1752
1753 static int radeon_do_cleanup_cp(struct drm_device * dev)
1754 {
1755         drm_radeon_private_t *dev_priv = dev->dev_private;
1756         DRM_DEBUG("\n");
1757
1758         /* Make sure interrupts are disabled here because the uninstall ioctl
1759          * may not have been called from userspace and after dev_private
1760          * is freed, it's too late.
1761          */
1762         if (dev->irq_enabled)
1763                 drm_irq_uninstall(dev);
1764
1765 #if __OS_HAS_AGP
1766         if (dev_priv->flags & RADEON_IS_AGP) {
1767                 if (dev_priv->cp_ring != NULL) {
1768                         drm_core_ioremapfree(dev_priv->cp_ring, dev);
1769                         dev_priv->cp_ring = NULL;
1770                 }
1771                 if (dev_priv->ring_rptr != NULL) {
1772                         drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1773                         dev_priv->ring_rptr = NULL;
1774                 }
1775                 if (dev->agp_buffer_map != NULL) {
1776                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
1777                         dev->agp_buffer_map = NULL;
1778                 }
1779         } else
1780 #endif
1781         {
1782
1783                 if (dev_priv->gart_info.bus_addr) {
1784                         /* Turn off PCI GART */
1785                         radeon_set_pcigart(dev_priv, 0);
1786                         if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1787                                 DRM_ERROR("failed to cleanup PCI GART!\n");
1788                 }
1789
1790                 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1791                 {
1792                         drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1793                         dev_priv->gart_info.addr = 0;
1794                 }
1795         }
1796         /* only clear to the start of flags */
1797         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1798
1799         return 0;
1800 }
1801
1802 /* This code will reinit the Radeon CP hardware after a resume from disc.
1803  * AFAIK, it would be very difficult to pickle the state at suspend time, so
1804  * here we make sure that all Radeon hardware initialisation is re-done without
1805  * affecting running applications.
1806  *
1807  * Charl P. Botha <http://cpbotha.net>
1808  */
1809 static int radeon_do_resume_cp(struct drm_device * dev)
1810 {
1811         drm_radeon_private_t *dev_priv = dev->dev_private;
1812
1813         if (!dev_priv) {
1814                 DRM_ERROR("Called with no initialization\n");
1815                 return -EINVAL;
1816         }
1817
1818         DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1819
1820 #if __OS_HAS_AGP
1821         if (dev_priv->flags & RADEON_IS_AGP) {
1822                 /* Turn off PCI GART */
1823                 radeon_set_pcigart(dev_priv, 0);
1824         } else
1825 #endif
1826         {
1827                 /* Turn on PCI GART */
1828                 radeon_set_pcigart(dev_priv, 1);
1829         }
1830
1831         radeon_cp_load_microcode(dev_priv);
1832         radeon_cp_init_ring_buffer(dev, dev_priv);
1833
1834         radeon_do_engine_reset(dev);
1835
1836         DRM_DEBUG("radeon_do_resume_cp() complete\n");
1837
1838         return 0;
1839 }
1840
1841 int radeon_cp_init(DRM_IOCTL_ARGS)
1842 {
1843         DRM_DEVICE;
1844         drm_radeon_init_t init;
1845
1846         LOCK_TEST_WITH_RETURN(dev, filp);
1847
1848         DRM_COPY_FROM_USER_IOCTL(init, (drm_radeon_init_t __user *) data,
1849                                  sizeof(init));
1850
1851         if (init.func == RADEON_INIT_R300_CP)
1852                 r300_init_reg_flags();
1853
1854         switch (init.func) {
1855         case RADEON_INIT_CP:
1856         case RADEON_INIT_R200_CP:
1857         case RADEON_INIT_R300_CP:
1858                 return radeon_do_init_cp(dev, &init);
1859         case RADEON_CLEANUP_CP:
1860                 return radeon_do_cleanup_cp(dev);
1861         }
1862
1863         return -EINVAL;
1864 }
1865
1866 int radeon_cp_start(DRM_IOCTL_ARGS)
1867 {
1868         DRM_DEVICE;
1869         drm_radeon_private_t *dev_priv = dev->dev_private;
1870         DRM_DEBUG("\n");
1871
1872         LOCK_TEST_WITH_RETURN(dev, filp);
1873
1874         if (dev_priv->cp_running) {
1875                 DRM_DEBUG("%s while CP running\n", __FUNCTION__);
1876                 return 0;
1877         }
1878         if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1879                 DRM_DEBUG("%s called with bogus CP mode (%d)\n",
1880                           __FUNCTION__, dev_priv->cp_mode);
1881                 return 0;
1882         }
1883
1884         radeon_do_cp_start(dev_priv);
1885
1886         return 0;
1887 }
1888
1889 /* Stop the CP.  The engine must have been idled before calling this
1890  * routine.
1891  */
1892 int radeon_cp_stop(DRM_IOCTL_ARGS)
1893 {
1894         DRM_DEVICE;
1895         drm_radeon_private_t *dev_priv = dev->dev_private;
1896         drm_radeon_cp_stop_t stop;
1897         int ret;
1898         DRM_DEBUG("\n");
1899
1900         LOCK_TEST_WITH_RETURN(dev, filp);
1901
1902         DRM_COPY_FROM_USER_IOCTL(stop, (drm_radeon_cp_stop_t __user *) data,
1903                                  sizeof(stop));
1904
1905         if (!dev_priv->cp_running)
1906                 return 0;
1907
1908         /* Flush any pending CP commands.  This ensures any outstanding
1909          * commands are exectuted by the engine before we turn it off.
1910          */
1911         if (stop.flush) {
1912                 radeon_do_cp_flush(dev_priv);
1913         }
1914
1915         /* If we fail to make the engine go idle, we return an error
1916          * code so that the DRM ioctl wrapper can try again.
1917          */
1918         if (stop.idle) {
1919                 ret = radeon_do_cp_idle(dev_priv);
1920                 if (ret)
1921                         return ret;
1922         }
1923
1924         /* Finally, we can turn off the CP.  If the engine isn't idle,
1925          * we will get some dropped triangles as they won't be fully
1926          * rendered before the CP is shut down.
1927          */
1928         radeon_do_cp_stop(dev_priv);
1929
1930         /* Reset the engine */
1931         radeon_do_engine_reset(dev);
1932
1933         return 0;
1934 }
1935
1936 void radeon_do_release(struct drm_device * dev)
1937 {
1938         drm_radeon_private_t *dev_priv = dev->dev_private;
1939         int i, ret;
1940
1941         if (dev_priv) {
1942                 if (dev_priv->cp_running) {
1943                         /* Stop the cp */
1944                         while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1945                                 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1946 #ifdef __linux__
1947                                 schedule();
1948 #else
1949 #if defined(__FreeBSD__) && __FreeBSD_version > 500000
1950                                 msleep(&ret, &dev->dev_lock, PZERO, "rdnrel",
1951                                        1);
1952 #else
1953                                 tsleep(&ret, PZERO, "rdnrel", 1);
1954 #endif
1955 #endif
1956                         }
1957                         radeon_do_cp_stop(dev_priv);
1958                         radeon_do_engine_reset(dev);
1959                 }
1960
1961                 /* Disable *all* interrupts */
1962                 if (dev_priv->mmio)     /* remove this after permanent addmaps */
1963                         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1964
1965                 if (dev_priv->mmio) {   /* remove all surfaces */
1966                         for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1967                                 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1968                                 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1969                                              16 * i, 0);
1970                                 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1971                                              16 * i, 0);
1972                         }
1973                 }
1974
1975                 /* Free memory heap structures */
1976                 radeon_mem_takedown(&(dev_priv->gart_heap));
1977                 radeon_mem_takedown(&(dev_priv->fb_heap));
1978
1979                 /* deallocate kernel resources */
1980                 radeon_do_cleanup_cp(dev);
1981         }
1982 }
1983
1984 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1985  */
1986 int radeon_cp_reset(DRM_IOCTL_ARGS)
1987 {
1988         DRM_DEVICE;
1989         drm_radeon_private_t *dev_priv = dev->dev_private;
1990         DRM_DEBUG("\n");
1991
1992         LOCK_TEST_WITH_RETURN(dev, filp);
1993
1994         if (!dev_priv) {
1995                 DRM_DEBUG("%s called before init done\n", __FUNCTION__);
1996                 return -EINVAL;
1997         }
1998
1999         radeon_do_cp_reset(dev_priv);
2000
2001         /* The CP is no longer running after an engine reset */
2002         dev_priv->cp_running = 0;
2003
2004         return 0;
2005 }
2006
2007 int radeon_cp_idle(DRM_IOCTL_ARGS)
2008 {
2009         DRM_DEVICE;
2010         drm_radeon_private_t *dev_priv = dev->dev_private;
2011         DRM_DEBUG("\n");
2012
2013         LOCK_TEST_WITH_RETURN(dev, filp);
2014
2015         return radeon_do_cp_idle(dev_priv);
2016 }
2017
2018 /* Added by Charl P. Botha to call radeon_do_resume_cp().
2019  */
2020 int radeon_cp_resume(DRM_IOCTL_ARGS)
2021 {
2022         DRM_DEVICE;
2023
2024         return radeon_do_resume_cp(dev);
2025 }
2026
2027 int radeon_engine_reset(DRM_IOCTL_ARGS)
2028 {
2029         DRM_DEVICE;
2030         DRM_DEBUG("\n");
2031
2032         LOCK_TEST_WITH_RETURN(dev, filp);
2033
2034         return radeon_do_engine_reset(dev);
2035 }
2036
2037 /* ================================================================
2038  * Fullscreen mode
2039  */
2040
2041 /* KW: Deprecated to say the least:
2042  */
2043 int radeon_fullscreen(DRM_IOCTL_ARGS)
2044 {
2045         return 0;
2046 }
2047
2048 /* ================================================================
2049  * Freelist management
2050  */
2051
2052 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
2053  *   bufs until freelist code is used.  Note this hides a problem with
2054  *   the scratch register * (used to keep track of last buffer
2055  *   completed) being written to before * the last buffer has actually
2056  *   completed rendering.
2057  *
2058  * KW:  It's also a good way to find free buffers quickly.
2059  *
2060  * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
2061  * sleep.  However, bugs in older versions of radeon_accel.c mean that
2062  * we essentially have to do this, else old clients will break.
2063  *
2064  * However, it does leave open a potential deadlock where all the
2065  * buffers are held by other clients, which can't release them because
2066  * they can't get the lock.
2067  */
2068
2069 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
2070 {
2071         struct drm_device_dma *dma = dev->dma;
2072         drm_radeon_private_t *dev_priv = dev->dev_private;
2073         drm_radeon_buf_priv_t *buf_priv;
2074         struct drm_buf *buf;
2075         int i, t;
2076         int start;
2077
2078         if (++dev_priv->last_buf >= dma->buf_count)
2079                 dev_priv->last_buf = 0;
2080
2081         start = dev_priv->last_buf;
2082
2083         for (t = 0; t < dev_priv->usec_timeout; t++) {
2084                 u32 done_age = GET_SCRATCH(1);
2085                 DRM_DEBUG("done_age = %d\n", done_age);
2086                 for (i = start; i < dma->buf_count; i++) {
2087                         buf = dma->buflist[i];
2088                         buf_priv = buf->dev_private;
2089                         if (buf->filp == 0 || (buf->pending &&
2090                                                buf_priv->age <= done_age)) {
2091                                 dev_priv->stats.requested_bufs++;
2092                                 buf->pending = 0;
2093                                 return buf;
2094                         }
2095                         start = 0;
2096                 }
2097
2098                 if (t) {
2099                         DRM_UDELAY(1);
2100                         dev_priv->stats.freelist_loops++;
2101                 }
2102         }
2103
2104         DRM_DEBUG("returning NULL!\n");
2105         return NULL;
2106 }
2107
2108 #if 0
2109 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
2110 {
2111         struct drm_device_dma *dma = dev->dma;
2112         drm_radeon_private_t *dev_priv = dev->dev_private;
2113         drm_radeon_buf_priv_t *buf_priv;
2114         struct drm_buf *buf;
2115         int i, t;
2116         int start;
2117         u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
2118
2119         if (++dev_priv->last_buf >= dma->buf_count)
2120                 dev_priv->last_buf = 0;
2121
2122         start = dev_priv->last_buf;
2123         dev_priv->stats.freelist_loops++;
2124
2125         for (t = 0; t < 2; t++) {
2126                 for (i = start; i < dma->buf_count; i++) {
2127                         buf = dma->buflist[i];
2128                         buf_priv = buf->dev_private;
2129                         if (buf->filp == 0 || (buf->pending &&
2130                                                buf_priv->age <= done_age)) {
2131                                 dev_priv->stats.requested_bufs++;
2132                                 buf->pending = 0;
2133                                 return buf;
2134                         }
2135                 }
2136                 start = 0;
2137         }
2138
2139         return NULL;
2140 }
2141 #endif
2142
2143 void radeon_freelist_reset(struct drm_device * dev)
2144 {
2145         struct drm_device_dma *dma = dev->dma;
2146         drm_radeon_private_t *dev_priv = dev->dev_private;
2147         int i;
2148
2149         dev_priv->last_buf = 0;
2150         for (i = 0; i < dma->buf_count; i++) {
2151                 struct drm_buf *buf = dma->buflist[i];
2152                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
2153                 buf_priv->age = 0;
2154         }
2155 }
2156
2157 /* ================================================================
2158  * CP command submission
2159  */
2160
2161 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
2162 {
2163         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
2164         int i;
2165         u32 last_head = GET_RING_HEAD(dev_priv);
2166
2167         for (i = 0; i < dev_priv->usec_timeout; i++) {
2168                 u32 head = GET_RING_HEAD(dev_priv);
2169
2170                 ring->space = (head - ring->tail) * sizeof(u32);
2171                 if (ring->space <= 0)
2172                         ring->space += ring->size;
2173                 if (ring->space > n)
2174                         return 0;
2175
2176                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
2177
2178                 if (head != last_head)
2179                         i = 0;
2180                 last_head = head;
2181
2182                 DRM_UDELAY(1);
2183         }
2184
2185         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
2186 #if RADEON_FIFO_DEBUG
2187         radeon_status(dev_priv);
2188         DRM_ERROR("failed!\n");
2189 #endif
2190         return -EBUSY;
2191 }
2192
2193 static int radeon_cp_get_buffers(DRMFILE filp, struct drm_device * dev,
2194                                  struct drm_dma * d)
2195 {
2196         int i;
2197         struct drm_buf *buf;
2198
2199         for (i = d->granted_count; i < d->request_count; i++) {
2200                 buf = radeon_freelist_get(dev);
2201                 if (!buf)
2202                         return -EBUSY;  /* NOTE: broken client */
2203
2204                 buf->filp = filp;
2205
2206                 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
2207                                      sizeof(buf->idx)))
2208                         return -EFAULT;
2209                 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
2210                                      sizeof(buf->total)))
2211                         return -EFAULT;
2212
2213                 d->granted_count++;
2214         }
2215         return 0;
2216 }
2217
2218 int radeon_cp_buffers(DRM_IOCTL_ARGS)
2219 {
2220         DRM_DEVICE;
2221         struct drm_device_dma *dma = dev->dma;
2222         int ret = 0;
2223         struct drm_dma __user *argp = (void __user *)data;
2224         struct drm_dma d;
2225
2226         LOCK_TEST_WITH_RETURN(dev, filp);
2227
2228         DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d));
2229
2230         /* Please don't send us buffers.
2231          */
2232         if (d.send_count != 0) {
2233                 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
2234                           DRM_CURRENTPID, d.send_count);
2235                 return -EINVAL;
2236         }
2237
2238         /* We'll send you buffers.
2239          */
2240         if (d.request_count < 0 || d.request_count > dma->buf_count) {
2241                 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
2242                           DRM_CURRENTPID, d.request_count, dma->buf_count);
2243                 return -EINVAL;
2244         }
2245
2246         d.granted_count = 0;
2247
2248         if (d.request_count) {
2249                 ret = radeon_cp_get_buffers(filp, dev, &d);
2250         }
2251
2252         DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d));
2253
2254         return ret;
2255 }
2256
2257 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
2258 {
2259         drm_radeon_private_t *dev_priv;
2260         int ret = 0;
2261
2262         dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
2263         if (dev_priv == NULL)
2264                 return -ENOMEM;
2265
2266         memset(dev_priv, 0, sizeof(drm_radeon_private_t));
2267         dev->dev_private = (void *)dev_priv;
2268         dev_priv->flags = flags;
2269
2270         switch (flags & RADEON_FAMILY_MASK) {
2271         case CHIP_R100:
2272         case CHIP_RV200:
2273         case CHIP_R200:
2274         case CHIP_R300:
2275         case CHIP_R350:
2276         case CHIP_R420:
2277         case CHIP_RV410:
2278                 dev_priv->flags |= RADEON_HAS_HIERZ;
2279                 break;
2280         default:
2281                 /* all other chips have no hierarchical z buffer */
2282                 break;
2283         }
2284
2285         if (drm_device_is_agp(dev))
2286                 dev_priv->flags |= RADEON_IS_AGP;
2287         else if (drm_device_is_pcie(dev))
2288                 dev_priv->flags |= RADEON_IS_PCIE;
2289         else
2290                 dev_priv->flags |= RADEON_IS_PCI;
2291
2292         DRM_DEBUG("%s card detected\n",
2293                   ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
2294         return ret;
2295 }
2296
2297 /* Create mappings for registers and framebuffer so userland doesn't necessarily
2298  * have to find them.
2299  */
2300 int radeon_driver_firstopen(struct drm_device *dev)
2301 {
2302         int ret;
2303         drm_local_map_t *map;
2304         drm_radeon_private_t *dev_priv = dev->dev_private;
2305
2306         dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
2307
2308         ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
2309                          drm_get_resource_len(dev, 2), _DRM_REGISTERS,
2310                          _DRM_READ_ONLY, &dev_priv->mmio);
2311         if (ret != 0)
2312                 return ret;
2313
2314         ret = drm_addmap(dev, drm_get_resource_start(dev, 0),
2315                          drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
2316                          _DRM_WRITE_COMBINING, &map);
2317         if (ret != 0)
2318                 return ret;
2319
2320         return 0;
2321 }
2322
2323 int radeon_driver_unload(struct drm_device *dev)
2324 {
2325         drm_radeon_private_t *dev_priv = dev->dev_private;
2326
2327         DRM_DEBUG("\n");
2328         drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
2329
2330         dev->dev_private = NULL;
2331         return 0;
2332 }