shared-core/radeon_cp.c

   1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
   2 /*
   3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11  * and/or sell copies of the Software, and to permit persons to whom the
  12  * Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the next
  15  * paragraph) shall be included in all copies or substantial portions of the
  16  * Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  21  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  22  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  23  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  24  * DEALINGS IN THE SOFTWARE.
  25  *
  26  * Authors:
  27  *    Kevin E. Martin <martin@valinux.com>
  28  *    Gareth Hughes <gareth@valinux.com>
  29  */
  30
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "radeon_drm.h"
  34 #include "radeon_drv.h"
  35 #include "r300_reg.h"
  36
  37 #define RADEON_FIFO_DEBUG       0
  38
  39 static int radeon_do_cleanup_cp(drm_device_t * dev);
  40
  41 /* CP microcode (from ATI) */
  42 static const u32 R200_cp_microcode[][2] = {
  43         {0x21007000, 0000000000},
  44         {0x20007000, 0000000000},
  45         {0x000000ab, 0x00000004},
  46         {0x000000af, 0x00000004},
  47         {0x66544a49, 0000000000},
  48         {0x49494174, 0000000000},
  49         {0x54517d83, 0000000000},
  50         {0x498d8b64, 0000000000},
  51         {0x49494949, 0000000000},
  52         {0x49da493c, 0000000000},
  53         {0x49989898, 0000000000},
  54         {0xd34949d5, 0000000000},
  55         {0x9dc90e11, 0000000000},
  56         {0xce9b9b9b, 0000000000},
  57         {0x000f0000, 0x00000016},
  58         {0x352e232c, 0000000000},
  59         {0x00000013, 0x00000004},
  60         {0x000f0000, 0x00000016},
  61         {0x352e272c, 0000000000},
  62         {0x000f0001, 0x00000016},
  63         {0x3239362f, 0000000000},
  64         {0x000077ef, 0x00000002},
  65         {0x00061000, 0x00000002},
  66         {0x00000020, 0x0000001a},
  67         {0x00004000, 0x0000001e},
  68         {0x00061000, 0x00000002},
  69         {0x00000020, 0x0000001a},
  70         {0x00004000, 0x0000001e},
  71         {0x00061000, 0x00000002},
  72         {0x00000020, 0x0000001a},
  73         {0x00004000, 0x0000001e},
  74         {0x00000016, 0x00000004},
  75         {0x0003802a, 0x00000002},
  76         {0x040067e0, 0x00000002},
  77         {0x00000016, 0x00000004},
  78         {0x000077e0, 0x00000002},
  79         {0x00065000, 0x00000002},
  80         {0x000037e1, 0x00000002},
  81         {0x040067e1, 0x00000006},
  82         {0x000077e0, 0x00000002},
  83         {0x000077e1, 0x00000002},
  84         {0x000077e1, 0x00000006},
  85         {0xffffffff, 0000000000},
  86         {0x10000000, 0000000000},
  87         {0x0003802a, 0x00000002},
  88         {0x040067e0, 0x00000006},
  89         {0x00007675, 0x00000002},
  90         {0x00007676, 0x00000002},
  91         {0x00007677, 0x00000002},
  92         {0x00007678, 0x00000006},
  93         {0x0003802b, 0x00000002},
  94         {0x04002676, 0x00000002},
  95         {0x00007677, 0x00000002},
  96         {0x00007678, 0x00000006},
  97         {0x0000002e, 0x00000018},
  98         {0x0000002e, 0x00000018},
  99         {0000000000, 0x00000006},
 100         {0x0000002f, 0x00000018},
 101         {0x0000002f, 0x00000018},
 102         {0000000000, 0x00000006},
 103         {0x01605000, 0x00000002},
 104         {0x00065000, 0x00000002},
 105         {0x00098000, 0x00000002},
 106         {0x00061000, 0x00000002},
 107         {0x64c0603d, 0x00000004},
 108         {0x00080000, 0x00000016},
 109         {0000000000, 0000000000},
 110         {0x0400251d, 0x00000002},
 111         {0x00007580, 0x00000002},
 112         {0x00067581, 0x00000002},
 113         {0x04002580, 0x00000002},
 114         {0x00067581, 0x00000002},
 115         {0x00000046, 0x00000004},
 116         {0x00005000, 0000000000},
 117         {0x00061000, 0x00000002},
 118         {0x0000750e, 0x00000002},
 119         {0x00019000, 0x00000002},
 120         {0x00011055, 0x00000014},
 121         {0x00000055, 0x00000012},
 122         {0x0400250f, 0x00000002},
 123         {0x0000504a, 0x00000004},
 124         {0x00007565, 0x00000002},
 125         {0x00007566, 0x00000002},
 126         {0x00000051, 0x00000004},
 127         {0x01e655b4, 0x00000002},
 128         {0x4401b0dc, 0x00000002},
 129         {0x01c110dc, 0x00000002},
 130         {0x2666705d, 0x00000018},
 131         {0x040c2565, 0x00000002},
 132         {0x0000005d, 0x00000018},
 133         {0x04002564, 0x00000002},
 134         {0x00007566, 0x00000002},
 135         {0x00000054, 0x00000004},
 136         {0x00401060, 0x00000008},
 137         {0x00101000, 0x00000002},
 138         {0x000d80ff, 0x00000002},
 139         {0x00800063, 0x00000008},
 140         {0x000f9000, 0x00000002},
 141         {0x000e00ff, 0x00000002},
 142         {0000000000, 0x00000006},
 143         {0x00000080, 0x00000018},
 144         {0x00000054, 0x00000004},
 145         {0x00007576, 0x00000002},
 146         {0x00065000, 0x00000002},
 147         {0x00009000, 0x00000002},
 148         {0x00041000, 0x00000002},
 149         {0x0c00350e, 0x00000002},
 150         {0x00049000, 0x00000002},
 151         {0x00051000, 0x00000002},
 152         {0x01e785f8, 0x00000002},
 153         {0x00200000, 0x00000002},
 154         {0x00600073, 0x0000000c},
 155         {0x00007563, 0x00000002},
 156         {0x006075f0, 0x00000021},
 157         {0x20007068, 0x00000004},
 158         {0x00005068, 0x00000004},
 159         {0x00007576, 0x00000002},
 160         {0x00007577, 0x00000002},
 161         {0x0000750e, 0x00000002},
 162         {0x0000750f, 0x00000002},
 163         {0x00a05000, 0x00000002},
 164         {0x00600076, 0x0000000c},
 165         {0x006075f0, 0x00000021},
 166         {0x000075f8, 0x00000002},
 167         {0x00000076, 0x00000004},
 168         {0x000a750e, 0x00000002},
 169         {0x0020750f, 0x00000002},
 170         {0x00600079, 0x00000004},
 171         {0x00007570, 0x00000002},
 172         {0x00007571, 0x00000002},
 173         {0x00007572, 0x00000006},
 174         {0x00005000, 0x00000002},
 175         {0x00a05000, 0x00000002},
 176         {0x00007568, 0x00000002},
 177         {0x00061000, 0x00000002},
 178         {0x00000084, 0x0000000c},
 179         {0x00058000, 0x00000002},
 180         {0x0c607562, 0x00000002},
 181         {0x00000086, 0x00000004},
 182         {0x00600085, 0x00000004},
 183         {0x400070dd, 0000000000},
 184         {0x000380dd, 0x00000002},
 185         {0x00000093, 0x0000001c},
 186         {0x00065095, 0x00000018},
 187         {0x040025bb, 0x00000002},
 188         {0x00061096, 0x00000018},
 189         {0x040075bc, 0000000000},
 190         {0x000075bb, 0x00000002},
 191         {0x000075bc, 0000000000},
 192         {0x00090000, 0x00000006},
 193         {0x00090000, 0x00000002},
 194         {0x000d8002, 0x00000006},
 195         {0x00005000, 0x00000002},
 196         {0x00007821, 0x00000002},
 197         {0x00007800, 0000000000},
 198         {0x00007821, 0x00000002},
 199         {0x00007800, 0000000000},
 200         {0x01665000, 0x00000002},
 201         {0x000a0000, 0x00000002},
 202         {0x000671cc, 0x00000002},
 203         {0x0286f1cd, 0x00000002},
 204         {0x000000a3, 0x00000010},
 205         {0x21007000, 0000000000},
 206         {0x000000aa, 0x0000001c},
 207         {0x00065000, 0x00000002},
 208         {0x000a0000, 0x00000002},
 209         {0x00061000, 0x00000002},
 210         {0x000b0000, 0x00000002},
 211         {0x38067000, 0x00000002},
 212         {0x000a00a6, 0x00000004},
 213         {0x20007000, 0000000000},
 214         {0x01200000, 0x00000002},
 215         {0x20077000, 0x00000002},
 216         {0x01200000, 0x00000002},
 217         {0x20007000, 0000000000},
 218         {0x00061000, 0x00000002},
 219         {0x0120751b, 0x00000002},
 220         {0x8040750a, 0x00000002},
 221         {0x8040750b, 0x00000002},
 222         {0x00110000, 0x00000002},
 223         {0x000380dd, 0x00000002},
 224         {0x000000bd, 0x0000001c},
 225         {0x00061096, 0x00000018},
 226         {0x844075bd, 0x00000002},
 227         {0x00061095, 0x00000018},
 228         {0x840075bb, 0x00000002},
 229         {0x00061096, 0x00000018},
 230         {0x844075bc, 0x00000002},
 231         {0x000000c0, 0x00000004},
 232         {0x804075bd, 0x00000002},
 233         {0x800075bb, 0x00000002},
 234         {0x804075bc, 0x00000002},
 235         {0x00108000, 0x00000002},
 236         {0x01400000, 0x00000002},
 237         {0x006000c4, 0x0000000c},
 238         {0x20c07000, 0x00000020},
 239         {0x000000c6, 0x00000012},
 240         {0x00800000, 0x00000006},
 241         {0x0080751d, 0x00000006},
 242         {0x000025bb, 0x00000002},
 243         {0x000040c0, 0x00000004},
 244         {0x0000775c, 0x00000002},
 245         {0x00a05000, 0x00000002},
 246         {0x00661000, 0x00000002},
 247         {0x0460275d, 0x00000020},
 248         {0x00004000, 0000000000},
 249         {0x00007999, 0x00000002},
 250         {0x00a05000, 0x00000002},
 251         {0x00661000, 0x00000002},
 252         {0x0460299b, 0x00000020},
 253         {0x00004000, 0000000000},
 254         {0x01e00830, 0x00000002},
 255         {0x21007000, 0000000000},
 256         {0x00005000, 0x00000002},
 257         {0x00038042, 0x00000002},
 258         {0x040025e0, 0x00000002},
 259         {0x000075e1, 0000000000},
 260         {0x00000001, 0000000000},
 261         {0x000380d9, 0x00000002},
 262         {0x04007394, 0000000000},
 263         {0000000000, 0000000000},
 264         {0000000000, 0000000000},
 265         {0000000000, 0000000000},
 266         {0000000000, 0000000000},
 267         {0000000000, 0000000000},
 268         {0000000000, 0000000000},
 269         {0000000000, 0000000000},
 270         {0000000000, 0000000000},
 271         {0000000000, 0000000000},
 272         {0000000000, 0000000000},
 273         {0000000000, 0000000000},
 274         {0000000000, 0000000000},
 275         {0000000000, 0000000000},
 276         {0000000000, 0000000000},
 277         {0000000000, 0000000000},
 278         {0000000000, 0000000000},
 279         {0000000000, 0000000000},
 280         {0000000000, 0000000000},
 281         {0000000000, 0000000000},
 282         {0000000000, 0000000000},
 283         {0000000000, 0000000000},
 284         {0000000000, 0000000000},
 285         {0000000000, 0000000000},
 286         {0000000000, 0000000000},
 287         {0000000000, 0000000000},
 288         {0000000000, 0000000000},
 289         {0000000000, 0000000000},
 290         {0000000000, 0000000000},
 291         {0000000000, 0000000000},
 292         {0000000000, 0000000000},
 293         {0000000000, 0000000000},
 294         {0000000000, 0000000000},
 295         {0000000000, 0000000000},
 296         {0000000000, 0000000000},
 297         {0000000000, 0000000000},
 298         {0000000000, 0000000000},
 299 };
 300
 301 static const u32 radeon_cp_microcode[][2] = {
 302         {0x21007000, 0000000000},
 303         {0x20007000, 0000000000},
 304         {0x000000b4, 0x00000004},
 305         {0x000000b8, 0x00000004},
 306         {0x6f5b4d4c, 0000000000},
 307         {0x4c4c427f, 0000000000},
 308         {0x5b568a92, 0000000000},
 309         {0x4ca09c6d, 0000000000},
 310         {0xad4c4c4c, 0000000000},
 311         {0x4ce1af3d, 0000000000},
 312         {0xd8afafaf, 0000000000},
 313         {0xd64c4cdc, 0000000000},
 314         {0x4cd10d10, 0000000000},
 315         {0x000f0000, 0x00000016},
 316         {0x362f242d, 0000000000},
 317         {0x00000012, 0x00000004},
 318         {0x000f0000, 0x00000016},
 319         {0x362f282d, 0000000000},
 320         {0x000380e7, 0x00000002},
 321         {0x04002c97, 0x00000002},
 322         {0x000f0001, 0x00000016},
 323         {0x333a3730, 0000000000},
 324         {0x000077ef, 0x00000002},
 325         {0x00061000, 0x00000002},
 326         {0x00000021, 0x0000001a},
 327         {0x00004000, 0x0000001e},
 328         {0x00061000, 0x00000002},
 329         {0x00000021, 0x0000001a},
 330         {0x00004000, 0x0000001e},
 331         {0x00061000, 0x00000002},
 332         {0x00000021, 0x0000001a},
 333         {0x00004000, 0x0000001e},
 334         {0x00000017, 0x00000004},
 335         {0x0003802b, 0x00000002},
 336         {0x040067e0, 0x00000002},
 337         {0x00000017, 0x00000004},
 338         {0x000077e0, 0x00000002},
 339         {0x00065000, 0x00000002},
 340         {0x000037e1, 0x00000002},
 341         {0x040067e1, 0x00000006},
 342         {0x000077e0, 0x00000002},
 343         {0x000077e1, 0x00000002},
 344         {0x000077e1, 0x00000006},
 345         {0xffffffff, 0000000000},
 346         {0x10000000, 0000000000},
 347         {0x0003802b, 0x00000002},
 348         {0x040067e0, 0x00000006},
 349         {0x00007675, 0x00000002},
 350         {0x00007676, 0x00000002},
 351         {0x00007677, 0x00000002},
 352         {0x00007678, 0x00000006},
 353         {0x0003802c, 0x00000002},
 354         {0x04002676, 0x00000002},
 355         {0x00007677, 0x00000002},
 356         {0x00007678, 0x00000006},
 357         {0x0000002f, 0x00000018},
 358         {0x0000002f, 0x00000018},
 359         {0000000000, 0x00000006},
 360         {0x00000030, 0x00000018},
 361         {0x00000030, 0x00000018},
 362         {0000000000, 0x00000006},
 363         {0x01605000, 0x00000002},
 364         {0x00065000, 0x00000002},
 365         {0x00098000, 0x00000002},
 366         {0x00061000, 0x00000002},
 367         {0x64c0603e, 0x00000004},
 368         {0x000380e6, 0x00000002},
 369         {0x040025c5, 0x00000002},
 370         {0x00080000, 0x00000016},
 371         {0000000000, 0000000000},
 372         {0x0400251d, 0x00000002},
 373         {0x00007580, 0x00000002},
 374         {0x00067581, 0x00000002},
 375         {0x04002580, 0x00000002},
 376         {0x00067581, 0x00000002},
 377         {0x00000049, 0x00000004},
 378         {0x00005000, 0000000000},
 379         {0x000380e6, 0x00000002},
 380         {0x040025c5, 0x00000002},
 381         {0x00061000, 0x00000002},
 382         {0x0000750e, 0x00000002},
 383         {0x00019000, 0x00000002},
 384         {0x00011055, 0x00000014},
 385         {0x00000055, 0x00000012},
 386         {0x0400250f, 0x00000002},
 387         {0x0000504f, 0x00000004},
 388         {0x000380e6, 0x00000002},
 389         {0x040025c5, 0x00000002},
 390         {0x00007565, 0x00000002},
 391         {0x00007566, 0x00000002},
 392         {0x00000058, 0x00000004},
 393         {0x000380e6, 0x00000002},
 394         {0x040025c5, 0x00000002},
 395         {0x01e655b4, 0x00000002},
 396         {0x4401b0e4, 0x00000002},
 397         {0x01c110e4, 0x00000002},
 398         {0x26667066, 0x00000018},
 399         {0x040c2565, 0x00000002},
 400         {0x00000066, 0x00000018},
 401         {0x04002564, 0x00000002},
 402         {0x00007566, 0x00000002},
 403         {0x0000005d, 0x00000004},
 404         {0x00401069, 0x00000008},
 405         {0x00101000, 0x00000002},
 406         {0x000d80ff, 0x00000002},
 407         {0x0080006c, 0x00000008},
 408         {0x000f9000, 0x00000002},
 409         {0x000e00ff, 0x00000002},
 410         {0000000000, 0x00000006},
 411         {0x0000008f, 0x00000018},
 412         {0x0000005b, 0x00000004},
 413         {0x000380e6, 0x00000002},
 414         {0x040025c5, 0x00000002},
 415         {0x00007576, 0x00000002},
 416         {0x00065000, 0x00000002},
 417         {0x00009000, 0x00000002},
 418         {0x00041000, 0x00000002},
 419         {0x0c00350e, 0x00000002},
 420         {0x00049000, 0x00000002},
 421         {0x00051000, 0x00000002},
 422         {0x01e785f8, 0x00000002},
 423         {0x00200000, 0x00000002},
 424         {0x0060007e, 0x0000000c},
 425         {0x00007563, 0x00000002},
 426         {0x006075f0, 0x00000021},
 427         {0x20007073, 0x00000004},
 428         {0x00005073, 0x00000004},
 429         {0x000380e6, 0x00000002},
 430         {0x040025c5, 0x00000002},
 431         {0x00007576, 0x00000002},
 432         {0x00007577, 0x00000002},
 433         {0x0000750e, 0x00000002},
 434         {0x0000750f, 0x00000002},
 435         {0x00a05000, 0x00000002},
 436         {0x00600083, 0x0000000c},
 437         {0x006075f0, 0x00000021},
 438         {0x000075f8, 0x00000002},
 439         {0x00000083, 0x00000004},
 440         {0x000a750e, 0x00000002},
 441         {0x000380e6, 0x00000002},
 442         {0x040025c5, 0x00000002},
 443         {0x0020750f, 0x00000002},
 444         {0x00600086, 0x00000004},
 445         {0x00007570, 0x00000002},
 446         {0x00007571, 0x00000002},
 447         {0x00007572, 0x00000006},
 448         {0x000380e6, 0x00000002},
 449         {0x040025c5, 0x00000002},
 450         {0x00005000, 0x00000002},
 451         {0x00a05000, 0x00000002},
 452         {0x00007568, 0x00000002},
 453         {0x00061000, 0x00000002},
 454         {0x00000095, 0x0000000c},
 455         {0x00058000, 0x00000002},
 456         {0x0c607562, 0x00000002},
 457         {0x00000097, 0x00000004},
 458         {0x000380e6, 0x00000002},
 459         {0x040025c5, 0x00000002},
 460         {0x00600096, 0x00000004},
 461         {0x400070e5, 0000000000},
 462         {0x000380e6, 0x00000002},
 463         {0x040025c5, 0x00000002},
 464         {0x000380e5, 0x00000002},
 465         {0x000000a8, 0x0000001c},
 466         {0x000650aa, 0x00000018},
 467         {0x040025bb, 0x00000002},
 468         {0x000610ab, 0x00000018},
 469         {0x040075bc, 0000000000},
 470         {0x000075bb, 0x00000002},
 471         {0x000075bc, 0000000000},
 472         {0x00090000, 0x00000006},
 473         {0x00090000, 0x00000002},
 474         {0x000d8002, 0x00000006},
 475         {0x00007832, 0x00000002},
 476         {0x00005000, 0x00000002},
 477         {0x000380e7, 0x00000002},
 478         {0x04002c97, 0x00000002},
 479         {0x00007820, 0x00000002},
 480         {0x00007821, 0x00000002},
 481         {0x00007800, 0000000000},
 482         {0x01200000, 0x00000002},
 483         {0x20077000, 0x00000002},
 484         {0x01200000, 0x00000002},
 485         {0x20007000, 0x00000002},
 486         {0x00061000, 0x00000002},
 487         {0x0120751b, 0x00000002},
 488         {0x8040750a, 0x00000002},
 489         {0x8040750b, 0x00000002},
 490         {0x00110000, 0x00000002},
 491         {0x000380e5, 0x00000002},
 492         {0x000000c6, 0x0000001c},
 493         {0x000610ab, 0x00000018},
 494         {0x844075bd, 0x00000002},
 495         {0x000610aa, 0x00000018},
 496         {0x840075bb, 0x00000002},
 497         {0x000610ab, 0x00000018},
 498         {0x844075bc, 0x00000002},
 499         {0x000000c9, 0x00000004},
 500         {0x804075bd, 0x00000002},
 501         {0x800075bb, 0x00000002},
 502         {0x804075bc, 0x00000002},
 503         {0x00108000, 0x00000002},
 504         {0x01400000, 0x00000002},
 505         {0x006000cd, 0x0000000c},
 506         {0x20c07000, 0x00000020},
 507         {0x000000cf, 0x00000012},
 508         {0x00800000, 0x00000006},
 509         {0x0080751d, 0x00000006},
 510         {0000000000, 0000000000},
 511         {0x0000775c, 0x00000002},
 512         {0x00a05000, 0x00000002},
 513         {0x00661000, 0x00000002},
 514         {0x0460275d, 0x00000020},
 515         {0x00004000, 0000000000},
 516         {0x01e00830, 0x00000002},
 517         {0x21007000, 0000000000},
 518         {0x6464614d, 0000000000},
 519         {0x69687420, 0000000000},
 520         {0x00000073, 0000000000},
 521         {0000000000, 0000000000},
 522         {0x00005000, 0x00000002},
 523         {0x000380d0, 0x00000002},
 524         {0x040025e0, 0x00000002},
 525         {0x000075e1, 0000000000},
 526         {0x00000001, 0000000000},
 527         {0x000380e0, 0x00000002},
 528         {0x04002394, 0x00000002},
 529         {0x00005000, 0000000000},
 530         {0000000000, 0000000000},
 531         {0000000000, 0000000000},
 532         {0x00000008, 0000000000},
 533         {0x00000004, 0000000000},
 534         {0000000000, 0000000000},
 535         {0000000000, 0000000000},
 536         {0000000000, 0000000000},
 537         {0000000000, 0000000000},
 538         {0000000000, 0000000000},
 539         {0000000000, 0000000000},
 540         {0000000000, 0000000000},
 541         {0000000000, 0000000000},
 542         {0000000000, 0000000000},
 543         {0000000000, 0000000000},
 544         {0000000000, 0000000000},
 545         {0000000000, 0000000000},
 546         {0000000000, 0000000000},
 547         {0000000000, 0000000000},
 548         {0000000000, 0000000000},
 549         {0000000000, 0000000000},
 550         {0000000000, 0000000000},
 551         {0000000000, 0000000000},
 552         {0000000000, 0000000000},
 553         {0000000000, 0000000000},
 554         {0000000000, 0000000000},
 555         {0000000000, 0000000000},
 556         {0000000000, 0000000000},
 557         {0000000000, 0000000000},
 558 };
 559
 560 static const u32 R300_cp_microcode[][2] = {
 561         { 0x4200e000, 0000000000 },
 562         { 0x4000e000, 0000000000 },
 563         { 0x000000af, 0x00000008 },
 564         { 0x000000b3, 0x00000008 },
 565         { 0x6c5a504f, 0000000000 },
 566         { 0x4f4f497a, 0000000000 },
 567         { 0x5a578288, 0000000000 },
 568         { 0x4f91906a, 0000000000 },
 569         { 0x4f4f4f4f, 0000000000 },
 570         { 0x4fe24f44, 0000000000 },
 571         { 0x4f9c9c9c, 0000000000 },
 572         { 0xdc4f4fde, 0000000000 },
 573         { 0xa1cd4f4f, 0000000000 },
 574         { 0xd29d9d9d, 0000000000 },
 575         { 0x4f0f9fd7, 0000000000 },
 576         { 0x000ca000, 0x00000004 },
 577         { 0x000d0012, 0x00000038 },
 578         { 0x0000e8b4, 0x00000004 },
 579         { 0x000d0014, 0x00000038 },
 580         { 0x0000e8b6, 0x00000004 },
 581         { 0x000d0016, 0x00000038 },
 582         { 0x0000e854, 0x00000004 },
 583         { 0x000d0018, 0x00000038 },
 584         { 0x0000e855, 0x00000004 },
 585         { 0x000d001a, 0x00000038 },
 586         { 0x0000e856, 0x00000004 },
 587         { 0x000d001c, 0x00000038 },
 588         { 0x0000e857, 0x00000004 },
 589         { 0x000d001e, 0x00000038 },
 590         { 0x0000e824, 0x00000004 },
 591         { 0x000d0020, 0x00000038 },
 592         { 0x0000e825, 0x00000004 },
 593         { 0x000d0022, 0x00000038 },
 594         { 0x0000e830, 0x00000004 },
 595         { 0x000d0024, 0x00000038 },
 596         { 0x0000f0c0, 0x00000004 },
 597         { 0x000d0026, 0x00000038 },
 598         { 0x0000f0c1, 0x00000004 },
 599         { 0x000d0028, 0x00000038 },
 600         { 0x0000f041, 0x00000004 },
 601         { 0x000d002a, 0x00000038 },
 602         { 0x0000f184, 0x00000004 },
 603         { 0x000d002c, 0x00000038 },
 604         { 0x0000f185, 0x00000004 },
 605         { 0x000d002e, 0x00000038 },
 606         { 0x0000f186, 0x00000004 },
 607         { 0x000d0030, 0x00000038 },
 608         { 0x0000f187, 0x00000004 },
 609         { 0x000d0032, 0x00000038 },
 610         { 0x0000f180, 0x00000004 },
 611         { 0x000d0034, 0x00000038 },
 612         { 0x0000f393, 0x00000004 },
 613         { 0x000d0036, 0x00000038 },
 614         { 0x0000f38a, 0x00000004 },
 615         { 0x000d0038, 0x00000038 },
 616         { 0x0000f38e, 0x00000004 },
 617         { 0x0000e821, 0x00000004 },
 618         { 0x0140a000, 0x00000004 },
 619         { 0x00000043, 0x00000018 },
 620         { 0x00cce800, 0x00000004 },
 621         { 0x001b0001, 0x00000004 },
 622         { 0x08004800, 0x00000004 },
 623         { 0x001b0001, 0x00000004 },
 624         { 0x08004800, 0x00000004 },
 625         { 0x001b0001, 0x00000004 },
 626         { 0x08004800, 0x00000004 },
 627         { 0x0000003a, 0x00000008 },
 628         { 0x0000a000, 0000000000 },
 629         { 0x02c0a000, 0x00000004 },
 630         { 0x000ca000, 0x00000004 },
 631         { 0x00130000, 0x00000004 },
 632         { 0x000c2000, 0x00000004 },
 633         { 0xc980c045, 0x00000008 },
 634         { 0x2000451d, 0x00000004 },
 635         { 0x0000e580, 0x00000004 },
 636         { 0x000ce581, 0x00000004 },
 637         { 0x08004580, 0x00000004 },
 638         { 0x000ce581, 0x00000004 },
 639         { 0x0000004c, 0x00000008 },
 640         { 0x0000a000, 0000000000 },
 641         { 0x000c2000, 0x00000004 },
 642         { 0x0000e50e, 0x00000004 },
 643         { 0x00032000, 0x00000004 },
 644         { 0x00022056, 0x00000028 },
 645         { 0x00000056, 0x00000024 },
 646         { 0x0800450f, 0x00000004 },
 647         { 0x0000a050, 0x00000008 },
 648         { 0x0000e565, 0x00000004 },
 649         { 0x0000e566, 0x00000004 },
 650         { 0x00000057, 0x00000008 },
 651         { 0x03cca5b4, 0x00000004 },
 652         { 0x05432000, 0x00000004 },
 653         { 0x00022000, 0x00000004 },
 654         { 0x4ccce063, 0x00000030 },
 655         { 0x08274565, 0x00000004 },
 656         { 0x00000063, 0x00000030 },
 657         { 0x08004564, 0x00000004 },
 658         { 0x0000e566, 0x00000004 },
 659         { 0x0000005a, 0x00000008 },
 660         { 0x00802066, 0x00000010 },
 661         { 0x00202000, 0x00000004 },
 662         { 0x001b00ff, 0x00000004 },
 663         { 0x01000069, 0x00000010 },
 664         { 0x001f2000, 0x00000004 },
 665         { 0x001c00ff, 0x00000004 },
 666         { 0000000000, 0x0000000c },
 667         { 0x00000085, 0x00000030 },
 668         { 0x0000005a, 0x00000008 },
 669         { 0x0000e576, 0x00000004 },
 670         { 0x000ca000, 0x00000004 },
 671         { 0x00012000, 0x00000004 },
 672         { 0x00082000, 0x00000004 },
 673         { 0x1800650e, 0x00000004 },
 674         { 0x00092000, 0x00000004 },
 675         { 0x000a2000, 0x00000004 },
 676         { 0x000f0000, 0x00000004 },
 677         { 0x00400000, 0x00000004 },
 678         { 0x00000079, 0x00000018 },
 679         { 0x0000e563, 0x00000004 },
 680         { 0x00c0e5f9, 0x000000c2 },
 681         { 0x0000006e, 0x00000008 },
 682         { 0x0000a06e, 0x00000008 },
 683         { 0x0000e576, 0x00000004 },
 684         { 0x0000e577, 0x00000004 },
 685         { 0x0000e50e, 0x00000004 },
 686         { 0x0000e50f, 0x00000004 },
 687         { 0x0140a000, 0x00000004 },
 688         { 0x0000007c, 0x00000018 },
 689         { 0x00c0e5f9, 0x000000c2 },
 690         { 0x0000007c, 0x00000008 },
 691         { 0x0014e50e, 0x00000004 },
 692         { 0x0040e50f, 0x00000004 },
 693         { 0x00c0007f, 0x00000008 },
 694         { 0x0000e570, 0x00000004 },
 695         { 0x0000e571, 0x00000004 },
 696         { 0x0000e572, 0x0000000c },
 697         { 0x0000a000, 0x00000004 },
 698         { 0x0140a000, 0x00000004 },
 699         { 0x0000e568, 0x00000004 },
 700         { 0x000c2000, 0x00000004 },
 701         { 0x00000089, 0x00000018 },
 702         { 0x000b0000, 0x00000004 },
 703         { 0x18c0e562, 0x00000004 },
 704         { 0x0000008b, 0x00000008 },
 705         { 0x00c0008a, 0x00000008 },
 706         { 0x000700e4, 0x00000004 },
 707         { 0x00000097, 0x00000038 },
 708         { 0x000ca099, 0x00000030 },
 709         { 0x080045bb, 0x00000004 },
 710         { 0x000c209a, 0x00000030 },
 711         { 0x0800e5bc, 0000000000 },
 712         { 0x0000e5bb, 0x00000004 },
 713         { 0x0000e5bc, 0000000000 },
 714         { 0x00120000, 0x0000000c },
 715         { 0x00120000, 0x00000004 },
 716         { 0x001b0002, 0x0000000c },
 717         { 0x0000a000, 0x00000004 },
 718         { 0x0000e821, 0x00000004 },
 719         { 0x0000e800, 0000000000 },
 720         { 0x0000e821, 0x00000004 },
 721         { 0x0000e82e, 0000000000 },
 722         { 0x02cca000, 0x00000004 },
 723         { 0x00140000, 0x00000004 },
 724         { 0x000ce1cc, 0x00000004 },
 725         { 0x050de1cd, 0x00000004 },
 726         { 0x000000a7, 0x00000020 },
 727         { 0x4200e000, 0000000000 },
 728         { 0x000000ae, 0x00000038 },
 729         { 0x000ca000, 0x00000004 },
 730         { 0x00140000, 0x00000004 },
 731         { 0x000c2000, 0x00000004 },
 732         { 0x00160000, 0x00000004 },
 733         { 0x700ce000, 0x00000004 },
 734         { 0x001400aa, 0x00000008 },
 735         { 0x4000e000, 0000000000 },
 736         { 0x02400000, 0x00000004 },
 737         { 0x400ee000, 0x00000004 },
 738         { 0x02400000, 0x00000004 },
 739         { 0x4000e000, 0000000000 },
 740         { 0x000c2000, 0x00000004 },
 741         { 0x0240e51b, 0x00000004 },
 742         { 0x0080e50a, 0x00000005 },
 743         { 0x0080e50b, 0x00000005 },
 744         { 0x00220000, 0x00000004 },
 745         { 0x000700e4, 0x00000004 },
 746         { 0x000000c1, 0x00000038 },
 747         { 0x000c209a, 0x00000030 },
 748         { 0x0880e5bd, 0x00000005 },
 749         { 0x000c2099, 0x00000030 },
 750         { 0x0800e5bb, 0x00000005 },
 751         { 0x000c209a, 0x00000030 },
 752         { 0x0880e5bc, 0x00000005 },
 753         { 0x000000c4, 0x00000008 },
 754         { 0x0080e5bd, 0x00000005 },
 755         { 0x0000e5bb, 0x00000005 },
 756         { 0x0080e5bc, 0x00000005 },
 757         { 0x00210000, 0x00000004 },
 758         { 0x02800000, 0x00000004 },
 759         { 0x00c000c8, 0x00000018 },
 760         { 0x4180e000, 0x00000040 },
 761         { 0x000000ca, 0x00000024 },
 762         { 0x01000000, 0x0000000c },
 763         { 0x0100e51d, 0x0000000c },
 764         { 0x000045bb, 0x00000004 },
 765         { 0x000080c4, 0x00000008 },
 766         { 0x0000f3ce, 0x00000004 },
 767         { 0x0140a000, 0x00000004 },
 768         { 0x00cc2000, 0x00000004 },
 769         { 0x08c053cf, 0x00000040 },
 770         { 0x00008000, 0000000000 },
 771         { 0x0000f3d2, 0x00000004 },
 772         { 0x0140a000, 0x00000004 },
 773         { 0x00cc2000, 0x00000004 },
 774         { 0x08c053d3, 0x00000040 },
 775         { 0x00008000, 0000000000 },
 776         { 0x0000f39d, 0x00000004 },
 777         { 0x0140a000, 0x00000004 },
 778         { 0x00cc2000, 0x00000004 },
 779         { 0x08c0539e, 0x00000040 },
 780         { 0x00008000, 0000000000 },
 781         { 0x03c00830, 0x00000004 },
 782         { 0x4200e000, 0000000000 },
 783         { 0x0000a000, 0x00000004 },
 784         { 0x200045e0, 0x00000004 },
 785         { 0x0000e5e1, 0000000000 },
 786         { 0x00000001, 0000000000 },
 787         { 0x000700e1, 0x00000004 },
 788         { 0x0800e394, 0000000000 },
 789         { 0000000000, 0000000000 },
 790         { 0000000000, 0000000000 },
 791         { 0000000000, 0000000000 },
 792         { 0000000000, 0000000000 },
 793         { 0000000000, 0000000000 },
 794         { 0000000000, 0000000000 },
 795         { 0000000000, 0000000000 },
 796         { 0000000000, 0000000000 },
 797         { 0000000000, 0000000000 },
 798         { 0000000000, 0000000000 },
 799         { 0000000000, 0000000000 },
 800         { 0000000000, 0000000000 },
 801         { 0000000000, 0000000000 },
 802         { 0000000000, 0000000000 },
 803         { 0000000000, 0000000000 },
 804         { 0000000000, 0000000000 },
 805         { 0000000000, 0000000000 },
 806         { 0000000000, 0000000000 },
 807         { 0000000000, 0000000000 },
 808         { 0000000000, 0000000000 },
 809         { 0000000000, 0000000000 },
 810         { 0000000000, 0000000000 },
 811         { 0000000000, 0000000000 },
 812         { 0000000000, 0000000000 },
 813         { 0000000000, 0000000000 },
 814         { 0000000000, 0000000000 },
 815         { 0000000000, 0000000000 },
 816         { 0000000000, 0000000000 },
 817 };
 818
 819 static int RADEON_READ_PLL(drm_device_t * dev, int addr)
 820 {
 821         drm_radeon_private_t *dev_priv = dev->dev_private;
 822
 823         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
 824         return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 825 }
 826
 827 static int RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
 828 {
 829         RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
 830         return RADEON_READ(RADEON_PCIE_DATA);
 831 }
 832
 833 #if RADEON_FIFO_DEBUG
 834 static void radeon_status(drm_radeon_private_t * dev_priv)
 835 {
 836         printk("%s:\n", __FUNCTION__);
 837         printk("RBBM_STATUS = 0x%08x\n",
 838                (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
 839         printk("CP_RB_RTPR = 0x%08x\n",
 840                (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
 841         printk("CP_RB_WTPR = 0x%08x\n",
 842                (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
 843         printk("AIC_CNTL = 0x%08x\n",
 844                (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
 845         printk("AIC_STAT = 0x%08x\n",
 846                (unsigned int)RADEON_READ(RADEON_AIC_STAT));
 847         printk("AIC_PT_BASE = 0x%08x\n",
 848                (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
 849         printk("TLB_ADDR = 0x%08x\n",
 850                (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
 851         printk("TLB_DATA = 0x%08x\n",
 852                (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
 853 }
 854 #endif
 855
 856 /* ================================================================
 857  * Engine, FIFO control
 858  */
 859
 860 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
 861 {
 862         u32 tmp;
 863         int i;
 864
 865         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 866
 867         tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
 868         tmp |= RADEON_RB3D_DC_FLUSH_ALL;
 869         RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
 870
 871         for (i = 0; i < dev_priv->usec_timeout; i++) {
 872                 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
 873                       & RADEON_RB3D_DC_BUSY)) {
 874                         return 0;
 875                 }
 876                 DRM_UDELAY(1);
 877         }
 878
 879 #if RADEON_FIFO_DEBUG
 880         DRM_ERROR("failed!\n");
 881         radeon_status(dev_priv);
 882 #endif
 883         return DRM_ERR(EBUSY);
 884 }
 885
 886 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
 887 {
 888         int i;
 889
 890         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 891
 892         for (i = 0; i < dev_priv->usec_timeout; i++) {
 893                 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
 894                              & RADEON_RBBM_FIFOCNT_MASK);
 895                 if (slots >= entries)
 896                         return 0;
 897                 DRM_UDELAY(1);
 898         }
 899
 900 #if RADEON_FIFO_DEBUG
 901         DRM_ERROR("failed!\n");
 902         radeon_status(dev_priv);
 903 #endif
 904         return DRM_ERR(EBUSY);
 905 }
 906
 907 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
 908 {
 909         int i, ret;
 910
 911         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 912
 913         ret = radeon_do_wait_for_fifo(dev_priv, 64);
 914         if (ret)
 915                 return ret;
 916
 917         for (i = 0; i < dev_priv->usec_timeout; i++) {
 918                 if (!(RADEON_READ(RADEON_RBBM_STATUS)
 919                       & RADEON_RBBM_ACTIVE)) {
 920                         radeon_do_pixcache_flush(dev_priv);
 921                         return 0;
 922                 }
 923                 DRM_UDELAY(1);
 924         }
 925
 926 #if RADEON_FIFO_DEBUG
 927         DRM_ERROR("failed!\n");
 928         radeon_status(dev_priv);
 929 #endif
 930         return DRM_ERR(EBUSY);
 931 }
 932
 933 /* ================================================================
 934  * CP control, initialization
 935  */
 936
 937 /* Load the microcode for the CP */
 938 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
 939 {
 940         int i;
 941         DRM_DEBUG("\n");
 942
 943         radeon_do_wait_for_idle(dev_priv);
 944
 945         RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
 946
 947         if (dev_priv->microcode_version == UCODE_R200) {
 948                 DRM_INFO("Loading R200 Microcode\n");
 949                 for (i = 0; i < 256; i++) {
 950                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 951                                      R200_cp_microcode[i][1]);
 952                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 953                                      R200_cp_microcode[i][0]);
 954                 }
 955         } else if (dev_priv->microcode_version == UCODE_R300) {
 956                 DRM_INFO("Loading R300 Microcode\n");
 957                 for (i = 0; i < 256; i++) {
 958                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 959                                      R300_cp_microcode[i][1]);
 960                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 961                                      R300_cp_microcode[i][0]);
 962                 }
 963         } else {
 964                 for (i = 0; i < 256; i++) {
 965                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 966                                      radeon_cp_microcode[i][1]);
 967                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 968                                      radeon_cp_microcode[i][0]);
 969                 }
 970         }
 971 }
 972
 973 /* Flush any pending commands to the CP.  This should only be used just
 974  * prior to a wait for idle, as it informs the engine that the command
 975  * stream is ending.
 976  */
 977 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
 978 {
 979         DRM_DEBUG("\n");
 980 #if 0
 981         u32 tmp;
 982
 983         tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
 984         RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
 985 #endif
 986 }
 987
 988 /* Wait for the CP to go idle.
 989  */
 990 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
 991 {
 992         RING_LOCALS;
 993         DRM_DEBUG("\n");
 994
 995         BEGIN_RING(6);
 996
 997         RADEON_PURGE_CACHE();
 998         RADEON_PURGE_ZCACHE();
 999         RADEON_WAIT_UNTIL_IDLE();
1000
1001         ADVANCE_RING();
1002         COMMIT_RING();
1003
1004         return radeon_do_wait_for_idle(dev_priv);
1005 }
1006
1007 /* Start the Command Processor.
1008  */
1009 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
1010 {
1011         RING_LOCALS;
1012         DRM_DEBUG("\n");
1013
1014         radeon_do_wait_for_idle(dev_priv);
1015
1016         RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
1017
1018         dev_priv->cp_running = 1;
1019
1020         BEGIN_RING(6);
1021
1022         RADEON_PURGE_CACHE();
1023         RADEON_PURGE_ZCACHE();
1024         RADEON_WAIT_UNTIL_IDLE();
1025
1026         ADVANCE_RING();
1027         COMMIT_RING();
1028 }
1029
1030 /* Reset the Command Processor.  This will not flush any pending
1031  * commands, so you must wait for the CP command stream to complete
1032  * before calling this routine.
1033  */
1034 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
1035 {
1036         u32 cur_read_ptr;
1037         DRM_DEBUG("\n");
1038
1039         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
1040         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
1041         SET_RING_HEAD(dev_priv, cur_read_ptr);
1042         dev_priv->ring.tail = cur_read_ptr;
1043 }
1044
1045 /* Stop the Command Processor.  This will not flush any pending
1046  * commands, so you must flush the command stream and wait for the CP
1047  * to go idle before calling this routine.
1048  */
1049 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
1050 {
1051         DRM_DEBUG("\n");
1052
1053         RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
1054
1055         dev_priv->cp_running = 0;
1056 }
1057
1058 /* Reset the engine.  This will stop the CP if it is running.
1059  */
1060 static int radeon_do_engine_reset(drm_device_t * dev)
1061 {
1062         drm_radeon_private_t *dev_priv = dev->dev_private;
1063         u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
1064         DRM_DEBUG("\n");
1065
1066         radeon_do_pixcache_flush(dev_priv);
1067
1068         clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
1069         mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
1070
1071         RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
1072                                             RADEON_FORCEON_MCLKA |
1073                                             RADEON_FORCEON_MCLKB |
1074                                             RADEON_FORCEON_YCLKA |
1075                                             RADEON_FORCEON_YCLKB |
1076                                             RADEON_FORCEON_MC |
1077                                             RADEON_FORCEON_AIC));
1078
1079         rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
1080
1081         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
1082                                               RADEON_SOFT_RESET_CP |
1083                                               RADEON_SOFT_RESET_HI |
1084                                               RADEON_SOFT_RESET_SE |
1085                                               RADEON_SOFT_RESET_RE |
1086                                               RADEON_SOFT_RESET_PP |
1087                                               RADEON_SOFT_RESET_E2 |
1088                                               RADEON_SOFT_RESET_RB));
1089         RADEON_READ(RADEON_RBBM_SOFT_RESET);
1090         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
1091                                               ~(RADEON_SOFT_RESET_CP |
1092                                                 RADEON_SOFT_RESET_HI |
1093                                                 RADEON_SOFT_RESET_SE |
1094                                                 RADEON_SOFT_RESET_RE |
1095                                                 RADEON_SOFT_RESET_PP |
1096                                                 RADEON_SOFT_RESET_E2 |
1097                                                 RADEON_SOFT_RESET_RB)));
1098         RADEON_READ(RADEON_RBBM_SOFT_RESET);
1099
1100         RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
1101         RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
1102         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
1103
1104         /* Reset the CP ring */
1105         radeon_do_cp_reset(dev_priv);
1106
1107         /* The CP is no longer running after an engine reset */
1108         dev_priv->cp_running = 0;
1109
1110         /* Reset any pending vertex, indirect buffers */
1111         radeon_freelist_reset(dev);
1112
1113         return 0;
1114 }
1115
1116 static void radeon_cp_init_ring_buffer(drm_device_t * dev,
1117                                        drm_radeon_private_t * dev_priv)
1118 {
1119         u32 ring_start, cur_read_ptr;
1120         u32 tmp;
1121
1122         /* Initialize the memory controller. With new memory map, the fb location
1123          * is not changed, it should have been properly initialized already. Part
1124          * of the problem is that the code below is bogus, assuming the GART is
1125          * always appended to the fb which is not necessarily the case
1126          */
1127         if (!dev_priv->new_memmap)
1128                 RADEON_WRITE(RADEON_MC_FB_LOCATION,
1129                              ((dev_priv->gart_vm_start - 1) & 0xffff0000)
1130                              | (dev_priv->fb_location >> 16));
1131
1132 #if __OS_HAS_AGP
1133         if (dev_priv->flags & RADEON_IS_AGP) {
1134                 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);
1135                 RADEON_WRITE(RADEON_MC_AGP_LOCATION,
1136                              (((dev_priv->gart_vm_start - 1 +
1137                                 dev_priv->gart_size) & 0xffff0000) |
1138                               (dev_priv->gart_vm_start >> 16)));
1139
1140                 ring_start = (dev_priv->cp_ring->offset
1141                               - dev->agp->base
1142                               + dev_priv->gart_vm_start);
1143         } else
1144 #endif
1145                 ring_start = (dev_priv->cp_ring->offset
1146                               - (unsigned long)dev->sg->virtual
1147                               + dev_priv->gart_vm_start);
1148
1149         RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
1150
1151         /* Set the write pointer delay */
1152         RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
1153
1154         /* Initialize the ring buffer's read and write pointers */
1155         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
1156         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
1157         SET_RING_HEAD(dev_priv, cur_read_ptr);
1158         dev_priv->ring.tail = cur_read_ptr;
1159
1160 #if __OS_HAS_AGP
1161         if (dev_priv->flags & RADEON_IS_AGP) {
1162                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
1163                              dev_priv->ring_rptr->offset
1164                              - dev->agp->base + dev_priv->gart_vm_start);
1165         } else
1166 #endif
1167         {
1168                 drm_sg_mem_t *entry = dev->sg;
1169                 unsigned long tmp_ofs, page_ofs;
1170
1171                 tmp_ofs = dev_priv->ring_rptr->offset -
1172                                 (unsigned long)dev->sg->virtual;
1173                 page_ofs = tmp_ofs >> PAGE_SHIFT;
1174
1175                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
1176                 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
1177                           (unsigned long)entry->busaddr[page_ofs],
1178                           entry->handle + tmp_ofs);
1179         }
1180
1181         /* Set ring buffer size */
1182 #ifdef __BIG_ENDIAN
1183         RADEON_WRITE(RADEON_CP_RB_CNTL,
1184                      dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT);
1185 #else
1186         RADEON_WRITE(RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw);
1187 #endif
1188
1189         /* Start with assuming that writeback doesn't work */
1190         dev_priv->writeback_works = 0;
1191
1192         /* Initialize the scratch register pointer.  This will cause
1193          * the scratch register values to be written out to memory
1194          * whenever they are updated.
1195          *
1196          * We simply put this behind the ring read pointer, this works
1197          * with PCI GART as well as (whatever kind of) AGP GART
1198          */
1199         RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
1200                      + RADEON_SCRATCH_REG_OFFSET);
1201
1202         dev_priv->scratch = ((__volatile__ u32 *)
1203                              dev_priv->ring_rptr->handle +
1204                              (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
1205
1206         RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
1207
1208         /* Turn on bus mastering */
1209         tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
1210         RADEON_WRITE(RADEON_BUS_CNTL, tmp);
1211
1212         dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
1213         RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
1214
1215         dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
1216         RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
1217                      dev_priv->sarea_priv->last_dispatch);
1218
1219         dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
1220         RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
1221
1222         radeon_do_wait_for_idle(dev_priv);
1223
1224         /* Sync everything up */
1225         RADEON_WRITE(RADEON_ISYNC_CNTL,
1226                      (RADEON_ISYNC_ANY2D_IDLE3D |
1227                       RADEON_ISYNC_ANY3D_IDLE2D |
1228                       RADEON_ISYNC_WAIT_IDLEGUI |
1229                       RADEON_ISYNC_CPSCRATCH_IDLEGUI));
1230
1231 }
1232
1233 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
1234 {
1235         u32 tmp;
1236
1237         /* Writeback doesn't seem to work everywhere, test it here and possibly
1238          * enable it if it appears to work
1239          */
1240         DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
1241         RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
1242
1243         for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
1244                 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
1245                     0xdeadbeef)
1246                         break;
1247                 DRM_UDELAY(1);
1248         }
1249
1250         if (tmp < dev_priv->usec_timeout) {
1251                 dev_priv->writeback_works = 1;
1252                 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
1253         } else {
1254                 dev_priv->writeback_works = 0;
1255                 DRM_INFO("writeback test failed\n");
1256         }
1257         if (radeon_no_wb == 1) {
1258                 dev_priv->writeback_works = 0;
1259                 DRM_INFO("writeback forced off\n");
1260         }
1261
1262         if (!dev_priv->writeback_works) {
1263                 /* Disable writeback to avoid unnecessary bus master transfers */
1264                 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) | RADEON_RB_NO_UPDATE);
1265                 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
1266         }
1267 }
1268
1269 /* Enable or disable PCI-E GART on the chip */
1270 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
1271 {
1272         u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
1273         if (on) {
1274
1275                 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
1276                           dev_priv->gart_vm_start,
1277                           (long)dev_priv->gart_info.bus_addr,
1278                           dev_priv->gart_size);
1279                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
1280                                   dev_priv->gart_vm_start);
1281                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
1282                                   dev_priv->gart_info.bus_addr);
1283                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
1284                                   dev_priv->gart_vm_start);
1285                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
1286                                   dev_priv->gart_vm_start +
1287                                   dev_priv->gart_size - 1);
1288
1289                 RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0);       /* ?? */
1290
1291                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1292                                   RADEON_PCIE_TX_GART_EN);
1293         } else {
1294                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1295                                   tmp & ~RADEON_PCIE_TX_GART_EN);
1296         }
1297 }
1298
1299 /* Enable or disable PCI GART on the chip */
1300 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1301 {
1302         u32 tmp;
1303
1304         if (dev_priv->flags & RADEON_IS_PCIE) {
1305                 radeon_set_pciegart(dev_priv, on);
1306                 return;
1307         }
1308
1309         tmp = RADEON_READ(RADEON_AIC_CNTL);
1310
1311         if (on) {
1312                 RADEON_WRITE(RADEON_AIC_CNTL,
1313                              tmp | RADEON_PCIGART_TRANSLATE_EN);
1314
1315                 /* set PCI GART page-table base address
1316                  */
1317                 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
1318
1319                 /* set address range for PCI address translate
1320                  */
1321                 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1322                 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1323                              + dev_priv->gart_size - 1);
1324
1325                 /* Turn off AGP aperture -- is this required for PCI GART?
1326                  */
1327                 RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0);       /* ?? */
1328                 RADEON_WRITE(RADEON_AGP_COMMAND, 0);    /* clear AGP_COMMAND */
1329         } else {
1330                 RADEON_WRITE(RADEON_AIC_CNTL,
1331                              tmp & ~RADEON_PCIGART_TRANSLATE_EN);
1332         }
1333 }
1334
1335 static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
1336 {
1337         drm_radeon_private_t *dev_priv = dev->dev_private;
1338
1339         DRM_DEBUG("\n");
1340
1341         /* if we require new memory map but we don't have it fail */
1342         if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap)
1343         {
1344                 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1345                 radeon_do_cleanup_cp(dev);
1346                 return DRM_ERR(EINVAL);
1347         }
1348
1349         if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP))
1350         {
1351                 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1352                 dev_priv->flags &= ~RADEON_IS_AGP;
1353         }
1354         else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1355                  && !init->is_pci)
1356         {
1357                 DRM_DEBUG("Restoring AGP flag\n");
1358                 dev_priv->flags |= RADEON_IS_AGP;
1359         }
1360
1361         if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
1362                 DRM_ERROR("PCI GART memory not allocated!\n");
1363                 radeon_do_cleanup_cp(dev);
1364                 return DRM_ERR(EINVAL);
1365         }
1366
1367         dev_priv->usec_timeout = init->usec_timeout;
1368         if (dev_priv->usec_timeout < 1 ||
1369             dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1370                 DRM_DEBUG("TIMEOUT problem!\n");
1371                 radeon_do_cleanup_cp(dev);
1372                 return DRM_ERR(EINVAL);
1373         }
1374
1375         switch(init->func) {
1376         case RADEON_INIT_R200_CP:
1377                 dev_priv->microcode_version = UCODE_R200;
1378                 break;
1379         case RADEON_INIT_R300_CP:
1380                 dev_priv->microcode_version = UCODE_R300;
1381                 break;
1382         default:
1383                 dev_priv->microcode_version = UCODE_R100;
1384         }
1385
1386         dev_priv->do_boxes = 0;
1387         dev_priv->cp_mode = init->cp_mode;
1388
1389         /* We don't support anything other than bus-mastering ring mode,
1390          * but the ring can be in either AGP or PCI space for the ring
1391          * read pointer.
1392          */
1393         if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1394             (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1395                 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1396                 radeon_do_cleanup_cp(dev);
1397                 return DRM_ERR(EINVAL);
1398         }
1399
1400         switch (init->fb_bpp) {
1401         case 16:
1402                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1403                 break;
1404         case 32:
1405         default:
1406                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1407                 break;
1408         }
1409         dev_priv->front_offset = init->front_offset;
1410         dev_priv->front_pitch = init->front_pitch;
1411         dev_priv->back_offset = init->back_offset;
1412         dev_priv->back_pitch = init->back_pitch;
1413
1414         switch (init->depth_bpp) {
1415         case 16:
1416                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1417                 break;
1418         case 32:
1419         default:
1420                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1421                 break;
1422         }
1423         dev_priv->depth_offset = init->depth_offset;
1424         dev_priv->depth_pitch = init->depth_pitch;
1425
1426         /* Hardware state for depth clears.  Remove this if/when we no
1427          * longer clear the depth buffer with a 3D rectangle.  Hard-code
1428          * all values to prevent unwanted 3D state from slipping through
1429          * and screwing with the clear operation.
1430          */
1431         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1432                                            (dev_priv->color_fmt << 10) |
1433                                            (dev_priv->microcode_version ==
1434                                             UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1435
1436         dev_priv->depth_clear.rb3d_zstencilcntl =
1437             (dev_priv->depth_fmt |
1438              RADEON_Z_TEST_ALWAYS |
1439              RADEON_STENCIL_TEST_ALWAYS |
1440              RADEON_STENCIL_S_FAIL_REPLACE |
1441              RADEON_STENCIL_ZPASS_REPLACE |
1442              RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1443
1444         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1445                                          RADEON_BFACE_SOLID |
1446                                          RADEON_FFACE_SOLID |
1447                                          RADEON_FLAT_SHADE_VTX_LAST |
1448                                          RADEON_DIFFUSE_SHADE_FLAT |
1449                                          RADEON_ALPHA_SHADE_FLAT |
1450                                          RADEON_SPECULAR_SHADE_FLAT |
1451                                          RADEON_FOG_SHADE_FLAT |
1452                                          RADEON_VTX_PIX_CENTER_OGL |
1453                                          RADEON_ROUND_MODE_TRUNC |
1454                                          RADEON_ROUND_PREC_8TH_PIX);
1455
1456         DRM_GETSAREA();
1457
1458         dev_priv->ring_offset = init->ring_offset;
1459         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1460         dev_priv->buffers_offset = init->buffers_offset;
1461         dev_priv->gart_textures_offset = init->gart_textures_offset;
1462
1463         if (!dev_priv->sarea) {
1464                 DRM_ERROR("could not find sarea!\n");
1465                 radeon_do_cleanup_cp(dev);
1466                 return DRM_ERR(EINVAL);
1467         }
1468
1469         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1470         if (!dev_priv->cp_ring) {
1471                 DRM_ERROR("could not find cp ring region!\n");
1472                 radeon_do_cleanup_cp(dev);
1473                 return DRM_ERR(EINVAL);
1474         }
1475         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1476         if (!dev_priv->ring_rptr) {
1477                 DRM_ERROR("could not find ring read pointer!\n");
1478                 radeon_do_cleanup_cp(dev);
1479                 return DRM_ERR(EINVAL);
1480         }
1481         dev->agp_buffer_token = init->buffers_offset;
1482         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1483         if (!dev->agp_buffer_map) {
1484                 DRM_ERROR("could not find dma buffer region!\n");
1485                 radeon_do_cleanup_cp(dev);
1486                 return DRM_ERR(EINVAL);
1487         }
1488
1489         if (init->gart_textures_offset) {
1490                 dev_priv->gart_textures =
1491                     drm_core_findmap(dev, init->gart_textures_offset);
1492                 if (!dev_priv->gart_textures) {
1493                         DRM_ERROR("could not find GART texture region!\n");
1494                         radeon_do_cleanup_cp(dev);
1495                         return DRM_ERR(EINVAL);
1496                 }
1497         }
1498
1499         dev_priv->sarea_priv =
1500             (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
1501                                     init->sarea_priv_offset);
1502
1503 #if __OS_HAS_AGP
1504         if (dev_priv->flags & RADEON_IS_AGP) {
1505                 drm_core_ioremap(dev_priv->cp_ring, dev);
1506                 drm_core_ioremap(dev_priv->ring_rptr, dev);
1507                 drm_core_ioremap(dev->agp_buffer_map, dev);
1508                 if (!dev_priv->cp_ring->handle ||
1509                     !dev_priv->ring_rptr->handle ||
1510                     !dev->agp_buffer_map->handle) {
1511                         DRM_ERROR("could not find ioremap agp regions!\n");
1512                         radeon_do_cleanup_cp(dev);
1513                         return DRM_ERR(EINVAL);
1514                 }
1515         } else
1516 #endif
1517         {
1518                 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1519                 dev_priv->ring_rptr->handle =
1520                     (void *)dev_priv->ring_rptr->offset;
1521                 dev->agp_buffer_map->handle =
1522                     (void *)dev->agp_buffer_map->offset;
1523
1524                 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1525                           dev_priv->cp_ring->handle);
1526                 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1527                           dev_priv->ring_rptr->handle);
1528                 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1529                           dev->agp_buffer_map->handle);
1530         }
1531
1532         dev_priv->fb_location = (RADEON_READ(RADEON_MC_FB_LOCATION)
1533                                  & 0xffff) << 16;
1534         dev_priv->fb_size =
1535                 ((RADEON_READ(RADEON_MC_FB_LOCATION) & 0xffff0000u) + 0x10000)
1536                 - dev_priv->fb_location;
1537
1538         dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1539                                         ((dev_priv->front_offset
1540                                           + dev_priv->fb_location) >> 10));
1541
1542         dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1543                                        ((dev_priv->back_offset
1544                                          + dev_priv->fb_location) >> 10));
1545
1546         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1547                                         ((dev_priv->depth_offset
1548                                           + dev_priv->fb_location) >> 10));
1549
1550         dev_priv->gart_size = init->gart_size;
1551
1552         /* New let's set the memory map ... */
1553         if (dev_priv->new_memmap) {
1554                 u32 base = 0;
1555
1556                 DRM_INFO("Setting GART location based on new memory map\n");
1557
1558                 /* If using AGP, try to locate the AGP aperture at the same
1559                  * location in the card and on the bus, though we have to
1560                  * align it down.
1561                  */
1562 #if __OS_HAS_AGP
1563                 if (dev_priv->flags & RADEON_IS_AGP) {
1564                         base = dev->agp->base;
1565                         /* Check if valid */
1566                         if ((base + dev_priv->gart_size) > dev_priv->fb_location &&
1567                             base < (dev_priv->fb_location + dev_priv->fb_size)) {
1568                                 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1569                                          dev->agp->base);
1570                                 base = 0;
1571                         }
1572                 }
1573 #endif
1574                 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1575                 if (base == 0) {
1576                         base = dev_priv->fb_location + dev_priv->fb_size;
1577                         if (((base + dev_priv->gart_size) & 0xfffffffful)
1578                             < base)
1579                                 base = dev_priv->fb_location
1580                                         - dev_priv->gart_size;
1581                 }
1582                 dev_priv->gart_vm_start = base & 0xffc00000u;
1583                 if (dev_priv->gart_vm_start != base)
1584                         DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1585                                  base, dev_priv->gart_vm_start);
1586         } else {
1587                 DRM_INFO("Setting GART location based on old memory map\n");
1588                 dev_priv->gart_vm_start = dev_priv->fb_location +
1589                         RADEON_READ(RADEON_CONFIG_APER_SIZE);
1590         }
1591
1592 #if __OS_HAS_AGP
1593         if (dev_priv->flags & RADEON_IS_AGP)
1594                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1595                                                  - dev->agp->base
1596                                                  + dev_priv->gart_vm_start);
1597         else
1598 #endif
1599                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1600                                         - (unsigned long)dev->sg->virtual
1601                                         + dev_priv->gart_vm_start);
1602
1603         DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1604         DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1605         DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1606                   dev_priv->gart_buffers_offset);
1607
1608         dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1609         dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1610                               + init->ring_size / sizeof(u32));
1611         dev_priv->ring.size = init->ring_size;
1612         dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1613
1614         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1615
1616         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1617
1618 #if __OS_HAS_AGP
1619         if (dev_priv->flags & RADEON_IS_AGP) {
1620                 /* Turn off PCI GART */
1621                 radeon_set_pcigart(dev_priv, 0);
1622         } else
1623 #endif
1624         {
1625                 /* if we have an offset set from userspace */
1626                 if (dev_priv->pcigart_offset) {
1627                         dev_priv->gart_info.bus_addr =
1628                             dev_priv->pcigart_offset + dev_priv->fb_location;
1629                         dev_priv->gart_info.mapping.offset =
1630                             dev_priv->gart_info.bus_addr;
1631                         dev_priv->gart_info.mapping.size =
1632                             RADEON_PCIGART_TABLE_SIZE;
1633
1634                         drm_core_ioremap(&dev_priv->gart_info.mapping, dev);
1635                         dev_priv->gart_info.addr =
1636                             dev_priv->gart_info.mapping.handle;
1637
1638                         dev_priv->gart_info.is_pcie =
1639                             !!(dev_priv->flags & RADEON_IS_PCIE);
1640                         dev_priv->gart_info.gart_table_location =
1641                             DRM_ATI_GART_FB;
1642
1643                         DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1644                                   dev_priv->gart_info.addr,
1645                                   dev_priv->pcigart_offset);
1646                 } else {
1647                         dev_priv->gart_info.gart_table_location =
1648                             DRM_ATI_GART_MAIN;
1649                         dev_priv->gart_info.addr = NULL;
1650                         dev_priv->gart_info.bus_addr = 0;
1651                         if (dev_priv->flags & RADEON_IS_PCIE) {
1652                                 DRM_ERROR
1653                                     ("Cannot use PCI Express without GART in FB memory\n");
1654                                 radeon_do_cleanup_cp(dev);
1655                                 return DRM_ERR(EINVAL);
1656                         }
1657                 }
1658
1659                 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
1660                         DRM_ERROR("failed to init PCI GART!\n");
1661                         radeon_do_cleanup_cp(dev);
1662                         return DRM_ERR(ENOMEM);
1663                 }
1664
1665                 /* Turn on PCI GART */
1666                 radeon_set_pcigart(dev_priv, 1);
1667         }
1668
1669         radeon_cp_load_microcode(dev_priv);
1670         radeon_cp_init_ring_buffer(dev, dev_priv);
1671
1672         dev_priv->last_buf = 0;
1673
1674         radeon_do_engine_reset(dev);
1675         radeon_test_writeback(dev_priv);
1676
1677         return 0;
1678 }
1679
1680 static int radeon_do_cleanup_cp(drm_device_t * dev)
1681 {
1682         drm_radeon_private_t *dev_priv = dev->dev_private;
1683         DRM_DEBUG("\n");
1684
1685         /* Make sure interrupts are disabled here because the uninstall ioctl
1686          * may not have been called from userspace and after dev_private
1687          * is freed, it's too late.
1688          */
1689         if (dev->irq_enabled)
1690                 drm_irq_uninstall(dev);
1691
1692 #if __OS_HAS_AGP
1693         if (dev_priv->flags & RADEON_IS_AGP) {
1694                 if (dev_priv->cp_ring != NULL) {
1695                         drm_core_ioremapfree(dev_priv->cp_ring, dev);
1696                         dev_priv->cp_ring = NULL;
1697                 }
1698                 if (dev_priv->ring_rptr != NULL) {
1699                         drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1700                         dev_priv->ring_rptr = NULL;
1701                 }
1702                 if (dev->agp_buffer_map != NULL) {
1703                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
1704                         dev->agp_buffer_map = NULL;
1705                 }
1706         } else
1707 #endif
1708         {
1709
1710                 if (dev_priv->gart_info.bus_addr) {
1711                         /* Turn off PCI GART */
1712                         radeon_set_pcigart(dev_priv, 0);
1713                         if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1714                                 DRM_ERROR("failed to cleanup PCI GART!\n");
1715                 }
1716
1717                 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1718                 {
1719                         drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1720                         dev_priv->gart_info.addr = 0;
1721                 }
1722         }
1723         /* only clear to the start of flags */
1724         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1725
1726         return 0;
1727 }
1728
1729 /* This code will reinit the Radeon CP hardware after a resume from disc.
1730  * AFAIK, it would be very difficult to pickle the state at suspend time, so
1731  * here we make sure that all Radeon hardware initialisation is re-done without
1732  * affecting running applications.
1733  *
1734  * Charl P. Botha <http://cpbotha.net>
1735  */
1736 static int radeon_do_resume_cp(drm_device_t * dev)
1737 {
1738         drm_radeon_private_t *dev_priv = dev->dev_private;
1739
1740         if (!dev_priv) {
1741                 DRM_ERROR("Called with no initialization\n");
1742                 return DRM_ERR(EINVAL);
1743         }
1744
1745         DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1746
1747 #if __OS_HAS_AGP
1748         if (dev_priv->flags & RADEON_IS_AGP) {
1749                 /* Turn off PCI GART */
1750                 radeon_set_pcigart(dev_priv, 0);
1751         } else
1752 #endif
1753         {
1754                 /* Turn on PCI GART */
1755                 radeon_set_pcigart(dev_priv, 1);
1756         }
1757
1758         radeon_cp_load_microcode(dev_priv);
1759         radeon_cp_init_ring_buffer(dev, dev_priv);
1760
1761         radeon_do_engine_reset(dev);
1762
1763         DRM_DEBUG("radeon_do_resume_cp() complete\n");
1764
1765         return 0;
1766 }
1767
1768 int radeon_cp_init(DRM_IOCTL_ARGS)
1769 {
1770         DRM_DEVICE;
1771         drm_radeon_init_t init;
1772
1773         LOCK_TEST_WITH_RETURN(dev, filp);
1774
1775         DRM_COPY_FROM_USER_IOCTL(init, (drm_radeon_init_t __user *) data,
1776                                  sizeof(init));
1777
1778         if (init.func == RADEON_INIT_R300_CP)
1779                 r300_init_reg_flags();
1780
1781         switch (init.func) {
1782         case RADEON_INIT_CP:
1783         case RADEON_INIT_R200_CP:
1784         case RADEON_INIT_R300_CP:
1785                 return radeon_do_init_cp(dev, &init);
1786         case RADEON_CLEANUP_CP:
1787                 return radeon_do_cleanup_cp(dev);
1788         }
1789
1790         return DRM_ERR(EINVAL);
1791 }
1792
1793 int radeon_cp_start(DRM_IOCTL_ARGS)
1794 {
1795         DRM_DEVICE;
1796         drm_radeon_private_t *dev_priv = dev->dev_private;
1797         DRM_DEBUG("\n");
1798
1799         LOCK_TEST_WITH_RETURN(dev, filp);
1800
1801         if (dev_priv->cp_running) {
1802                 DRM_DEBUG("%s while CP running\n", __FUNCTION__);
1803                 return 0;
1804         }
1805         if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1806                 DRM_DEBUG("%s called with bogus CP mode (%d)\n",
1807                           __FUNCTION__, dev_priv->cp_mode);
1808                 return 0;
1809         }
1810
1811         radeon_do_cp_start(dev_priv);
1812
1813         return 0;
1814 }
1815
1816 /* Stop the CP.  The engine must have been idled before calling this
1817  * routine.
1818  */
1819 int radeon_cp_stop(DRM_IOCTL_ARGS)
1820 {
1821         DRM_DEVICE;
1822         drm_radeon_private_t *dev_priv = dev->dev_private;
1823         drm_radeon_cp_stop_t stop;
1824         int ret;
1825         DRM_DEBUG("\n");
1826
1827         LOCK_TEST_WITH_RETURN(dev, filp);
1828
1829         DRM_COPY_FROM_USER_IOCTL(stop, (drm_radeon_cp_stop_t __user *) data,
1830                                  sizeof(stop));
1831
1832         if (!dev_priv->cp_running)
1833                 return 0;
1834
1835         /* Flush any pending CP commands.  This ensures any outstanding
1836          * commands are exectuted by the engine before we turn it off.
1837          */
1838         if (stop.flush) {
1839                 radeon_do_cp_flush(dev_priv);
1840         }
1841
1842         /* If we fail to make the engine go idle, we return an error
1843          * code so that the DRM ioctl wrapper can try again.
1844          */
1845         if (stop.idle) {
1846                 ret = radeon_do_cp_idle(dev_priv);
1847                 if (ret)
1848                         return ret;
1849         }
1850
1851         /* Finally, we can turn off the CP.  If the engine isn't idle,
1852          * we will get some dropped triangles as they won't be fully
1853          * rendered before the CP is shut down.
1854          */
1855         radeon_do_cp_stop(dev_priv);
1856
1857         /* Reset the engine */
1858         radeon_do_engine_reset(dev);
1859
1860         return 0;
1861 }
1862
1863 void radeon_do_release(drm_device_t * dev)
1864 {
1865         drm_radeon_private_t *dev_priv = dev->dev_private;
1866         int i, ret;
1867
1868         if (dev_priv) {
1869                 if (dev_priv->cp_running) {
1870                         /* Stop the cp */
1871                         while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1872                                 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1873 #ifdef __linux__
1874                                 schedule();
1875 #else
1876 #if defined(__FreeBSD__) && __FreeBSD_version > 500000
1877                                 msleep(&ret, &dev->dev_lock, PZERO, "rdnrel",
1878                                        1);
1879 #else
1880                                 tsleep(&ret, PZERO, "rdnrel", 1);
1881 #endif
1882 #endif
1883                         }
1884                         radeon_do_cp_stop(dev_priv);
1885                         radeon_do_engine_reset(dev);
1886                 }
1887
1888                 /* Disable *all* interrupts */
1889                 if (dev_priv->mmio)     /* remove this after permanent addmaps */
1890                         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1891
1892                 if (dev_priv->mmio) {   /* remove all surfaces */
1893                         for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1894                                 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1895                                 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1896                                              16 * i, 0);
1897                                 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1898                                              16 * i, 0);
1899                         }
1900                 }
1901
1902                 /* Free memory heap structures */
1903                 radeon_mem_takedown(&(dev_priv->gart_heap));
1904                 radeon_mem_takedown(&(dev_priv->fb_heap));
1905
1906                 /* deallocate kernel resources */
1907                 radeon_do_cleanup_cp(dev);
1908         }
1909 }
1910
1911 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1912  */
1913 int radeon_cp_reset(DRM_IOCTL_ARGS)
1914 {
1915         DRM_DEVICE;
1916         drm_radeon_private_t *dev_priv = dev->dev_private;
1917         DRM_DEBUG("\n");
1918
1919         LOCK_TEST_WITH_RETURN(dev, filp);
1920
1921         if (!dev_priv) {
1922                 DRM_DEBUG("%s called before init done\n", __FUNCTION__);
1923                 return DRM_ERR(EINVAL);
1924         }
1925
1926         radeon_do_cp_reset(dev_priv);
1927
1928         /* The CP is no longer running after an engine reset */
1929         dev_priv->cp_running = 0;
1930
1931         return 0;
1932 }
1933
1934 int radeon_cp_idle(DRM_IOCTL_ARGS)
1935 {
1936         DRM_DEVICE;
1937         drm_radeon_private_t *dev_priv = dev->dev_private;
1938         DRM_DEBUG("\n");
1939
1940         LOCK_TEST_WITH_RETURN(dev, filp);
1941
1942         return radeon_do_cp_idle(dev_priv);
1943 }
1944
1945 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1946  */
1947 int radeon_cp_resume(DRM_IOCTL_ARGS)
1948 {
1949         DRM_DEVICE;
1950
1951         return radeon_do_resume_cp(dev);
1952 }
1953
1954 int radeon_engine_reset(DRM_IOCTL_ARGS)
1955 {
1956         DRM_DEVICE;
1957         DRM_DEBUG("\n");
1958
1959         LOCK_TEST_WITH_RETURN(dev, filp);
1960
1961         return radeon_do_engine_reset(dev);
1962 }
1963
1964 /* ================================================================
1965  * Fullscreen mode
1966  */
1967
1968 /* KW: Deprecated to say the least:
1969  */
1970 int radeon_fullscreen(DRM_IOCTL_ARGS)
1971 {
1972         return 0;
1973 }
1974
1975 /* ================================================================
1976  * Freelist management
1977  */
1978
1979 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1980  *   bufs until freelist code is used.  Note this hides a problem with
1981  *   the scratch register * (used to keep track of last buffer
1982  *   completed) being written to before * the last buffer has actually
1983  *   completed rendering.
1984  *
1985  * KW:  It's also a good way to find free buffers quickly.
1986  *
1987  * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1988  * sleep.  However, bugs in older versions of radeon_accel.c mean that
1989  * we essentially have to do this, else old clients will break.
1990  *
1991  * However, it does leave open a potential deadlock where all the
1992  * buffers are held by other clients, which can't release them because
1993  * they can't get the lock.
1994  */
1995
1996 drm_buf_t *radeon_freelist_get(drm_device_t * dev)
1997 {
1998         drm_device_dma_t *dma = dev->dma;
1999         drm_radeon_private_t *dev_priv = dev->dev_private;
2000         drm_radeon_buf_priv_t *buf_priv;
2001         drm_buf_t *buf;
2002         int i, t;
2003         int start;
2004
2005         if (++dev_priv->last_buf >= dma->buf_count)
2006                 dev_priv->last_buf = 0;
2007
2008         start = dev_priv->last_buf;
2009
2010         for (t = 0; t < dev_priv->usec_timeout; t++) {
2011                 u32 done_age = GET_SCRATCH(1);
2012                 DRM_DEBUG("done_age = %d\n", done_age);
2013                 for (i = start; i < dma->buf_count; i++) {
2014                         buf = dma->buflist[i];
2015                         buf_priv = buf->dev_private;
2016                         if (buf->filp == 0 || (buf->pending &&
2017                                                buf_priv->age <= done_age)) {
2018                                 dev_priv->stats.requested_bufs++;
2019                                 buf->pending = 0;
2020                                 return buf;
2021                         }
2022                         start = 0;
2023                 }
2024
2025                 if (t) {
2026                         DRM_UDELAY(1);
2027                         dev_priv->stats.freelist_loops++;
2028                 }
2029         }
2030
2031         DRM_DEBUG("returning NULL!\n");
2032         return NULL;
2033 }
2034
2035 #if 0
2036 drm_buf_t *radeon_freelist_get(drm_device_t * dev)
2037 {
2038         drm_device_dma_t *dma = dev->dma;
2039         drm_radeon_private_t *dev_priv = dev->dev_private;
2040         drm_radeon_buf_priv_t *buf_priv;
2041         drm_buf_t *buf;
2042         int i, t;
2043         int start;
2044         u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
2045
2046         if (++dev_priv->last_buf >= dma->buf_count)
2047                 dev_priv->last_buf = 0;
2048
2049         start = dev_priv->last_buf;
2050         dev_priv->stats.freelist_loops++;
2051
2052         for (t = 0; t < 2; t++) {
2053                 for (i = start; i < dma->buf_count; i++) {
2054                         buf = dma->buflist[i];
2055                         buf_priv = buf->dev_private;
2056                         if (buf->filp == 0 || (buf->pending &&
2057                                                buf_priv->age <= done_age)) {
2058                                 dev_priv->stats.requested_bufs++;
2059                                 buf->pending = 0;
2060                                 return buf;
2061                         }
2062                 }
2063                 start = 0;
2064         }
2065
2066         return NULL;
2067 }
2068 #endif
2069
2070 void radeon_freelist_reset(drm_device_t * dev)
2071 {
2072         drm_device_dma_t *dma = dev->dma;
2073         drm_radeon_private_t *dev_priv = dev->dev_private;
2074         int i;
2075
2076         dev_priv->last_buf = 0;
2077         for (i = 0; i < dma->buf_count; i++) {
2078                 drm_buf_t *buf = dma->buflist[i];
2079                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
2080                 buf_priv->age = 0;
2081         }
2082 }
2083
2084 /* ================================================================
2085  * CP command submission
2086  */
2087
2088 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
2089 {
2090         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
2091         int i;
2092         u32 last_head = GET_RING_HEAD(dev_priv);
2093
2094         for (i = 0; i < dev_priv->usec_timeout; i++) {
2095                 u32 head = GET_RING_HEAD(dev_priv);
2096
2097                 ring->space = (head - ring->tail) * sizeof(u32);
2098                 if (ring->space <= 0)
2099                         ring->space += ring->size;
2100                 if (ring->space > n)
2101                         return 0;
2102
2103                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
2104
2105                 if (head != last_head)
2106                         i = 0;
2107                 last_head = head;
2108
2109                 DRM_UDELAY(1);
2110         }
2111
2112         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
2113 #if RADEON_FIFO_DEBUG
2114         radeon_status(dev_priv);
2115         DRM_ERROR("failed!\n");
2116 #endif
2117         return DRM_ERR(EBUSY);
2118 }
2119
2120 static int radeon_cp_get_buffers(DRMFILE filp, drm_device_t * dev,
2121                                  drm_dma_t * d)
2122 {
2123         int i;
2124         drm_buf_t *buf;
2125
2126         for (i = d->granted_count; i < d->request_count; i++) {
2127                 buf = radeon_freelist_get(dev);
2128                 if (!buf)
2129                         return DRM_ERR(EBUSY);  /* NOTE: broken client */
2130
2131                 buf->filp = filp;
2132
2133                 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
2134                                      sizeof(buf->idx)))
2135                         return DRM_ERR(EFAULT);
2136                 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
2137                                      sizeof(buf->total)))
2138                         return DRM_ERR(EFAULT);
2139
2140                 d->granted_count++;
2141         }
2142         return 0;
2143 }
2144
2145 int radeon_cp_buffers(DRM_IOCTL_ARGS)
2146 {
2147         DRM_DEVICE;
2148         drm_device_dma_t *dma = dev->dma;
2149         int ret = 0;
2150         drm_dma_t __user *argp = (void __user *)data;
2151         drm_dma_t d;
2152
2153         LOCK_TEST_WITH_RETURN(dev, filp);
2154
2155         DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d));
2156
2157         /* Please don't send us buffers.
2158          */
2159         if (d.send_count != 0) {
2160                 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
2161                           DRM_CURRENTPID, d.send_count);
2162                 return DRM_ERR(EINVAL);
2163         }
2164
2165         /* We'll send you buffers.
2166          */
2167         if (d.request_count < 0 || d.request_count > dma->buf_count) {
2168                 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
2169                           DRM_CURRENTPID, d.request_count, dma->buf_count);
2170                 return DRM_ERR(EINVAL);
2171         }
2172
2173         d.granted_count = 0;
2174
2175         if (d.request_count) {
2176                 ret = radeon_cp_get_buffers(filp, dev, &d);
2177         }
2178
2179         DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d));
2180
2181         return ret;
2182 }
2183
2184 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
2185 {
2186         drm_radeon_private_t *dev_priv;
2187         int ret = 0;
2188
2189         dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
2190         if (dev_priv == NULL)
2191                 return DRM_ERR(ENOMEM);
2192
2193         memset(dev_priv, 0, sizeof(drm_radeon_private_t));
2194         dev->dev_private = (void *)dev_priv;
2195         dev_priv->flags = flags;
2196
2197         switch (flags & RADEON_FAMILY_MASK) {
2198         case CHIP_R100:
2199         case CHIP_RV200:
2200         case CHIP_R200:
2201         case CHIP_R300:
2202         case CHIP_R350:
2203         case CHIP_R420:
2204         case CHIP_RV410:
2205                 dev_priv->flags |= RADEON_HAS_HIERZ;
2206                 break;
2207         default:
2208                 /* all other chips have no hierarchical z buffer */
2209                 break;
2210         }
2211
2212         if (drm_device_is_agp(dev))
2213                 dev_priv->flags |= RADEON_IS_AGP;
2214         else if (drm_device_is_pcie(dev))
2215                 dev_priv->flags |= RADEON_IS_PCIE;
2216         else
2217                 dev_priv->flags |= RADEON_IS_PCI;
2218
2219         DRM_DEBUG("%s card detected\n",
2220                   ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
2221         return ret;
2222 }
2223
2224 /* Create mappings for registers and framebuffer so userland doesn't necessarily
2225  * have to find them.
2226  */
2227 int radeon_driver_firstopen(struct drm_device *dev)
2228 {
2229         int ret;
2230         drm_local_map_t *map;
2231         drm_radeon_private_t *dev_priv = dev->dev_private;
2232
2233         ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
2234                          drm_get_resource_len(dev, 2), _DRM_REGISTERS,
2235                          _DRM_READ_ONLY, &dev_priv->mmio);
2236         if (ret != 0)
2237                 return ret;
2238
2239         ret = drm_addmap(dev, drm_get_resource_start(dev, 0),
2240                          drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
2241                          _DRM_WRITE_COMBINING, &map);
2242         if (ret != 0)
2243                 return ret;
2244
2245         return 0;
2246 }
2247
2248 int radeon_driver_unload(struct drm_device *dev)
2249 {
2250         drm_radeon_private_t *dev_priv = dev->dev_private;
2251
2252         DRM_DEBUG("\n");
2253         drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
2254
2255         dev->dev_private = NULL;
2256         return 0;
2257 }