1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*-
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
33 #include "radeon_drm.h"
34 #include "radeon_drv.h"
36 #define RADEON_FIFO_DEBUG 0
38 static int radeon_do_cleanup_cp(drm_device_t * dev);
40 /* CP microcode (from ATI) */
41 static u32 R200_cp_microcode[][2] = {
42 {0x21007000, 0000000000},
43 {0x20007000, 0000000000},
44 {0x000000ab, 0x00000004},
45 {0x000000af, 0x00000004},
46 {0x66544a49, 0000000000},
47 {0x49494174, 0000000000},
48 {0x54517d83, 0000000000},
49 {0x498d8b64, 0000000000},
50 {0x49494949, 0000000000},
51 {0x49da493c, 0000000000},
52 {0x49989898, 0000000000},
53 {0xd34949d5, 0000000000},
54 {0x9dc90e11, 0000000000},
55 {0xce9b9b9b, 0000000000},
56 {0x000f0000, 0x00000016},
57 {0x352e232c, 0000000000},
58 {0x00000013, 0x00000004},
59 {0x000f0000, 0x00000016},
60 {0x352e272c, 0000000000},
61 {0x000f0001, 0x00000016},
62 {0x3239362f, 0000000000},
63 {0x000077ef, 0x00000002},
64 {0x00061000, 0x00000002},
65 {0x00000020, 0x0000001a},
66 {0x00004000, 0x0000001e},
67 {0x00061000, 0x00000002},
68 {0x00000020, 0x0000001a},
69 {0x00004000, 0x0000001e},
70 {0x00061000, 0x00000002},
71 {0x00000020, 0x0000001a},
72 {0x00004000, 0x0000001e},
73 {0x00000016, 0x00000004},
74 {0x0003802a, 0x00000002},
75 {0x040067e0, 0x00000002},
76 {0x00000016, 0x00000004},
77 {0x000077e0, 0x00000002},
78 {0x00065000, 0x00000002},
79 {0x000037e1, 0x00000002},
80 {0x040067e1, 0x00000006},
81 {0x000077e0, 0x00000002},
82 {0x000077e1, 0x00000002},
83 {0x000077e1, 0x00000006},
84 {0xffffffff, 0000000000},
85 {0x10000000, 0000000000},
86 {0x0003802a, 0x00000002},
87 {0x040067e0, 0x00000006},
88 {0x00007675, 0x00000002},
89 {0x00007676, 0x00000002},
90 {0x00007677, 0x00000002},
91 {0x00007678, 0x00000006},
92 {0x0003802b, 0x00000002},
93 {0x04002676, 0x00000002},
94 {0x00007677, 0x00000002},
95 {0x00007678, 0x00000006},
96 {0x0000002e, 0x00000018},
97 {0x0000002e, 0x00000018},
98 {0000000000, 0x00000006},
99 {0x0000002f, 0x00000018},
100 {0x0000002f, 0x00000018},
101 {0000000000, 0x00000006},
102 {0x01605000, 0x00000002},
103 {0x00065000, 0x00000002},
104 {0x00098000, 0x00000002},
105 {0x00061000, 0x00000002},
106 {0x64c0603d, 0x00000004},
107 {0x00080000, 0x00000016},
108 {0000000000, 0000000000},
109 {0x0400251d, 0x00000002},
110 {0x00007580, 0x00000002},
111 {0x00067581, 0x00000002},
112 {0x04002580, 0x00000002},
113 {0x00067581, 0x00000002},
114 {0x00000046, 0x00000004},
115 {0x00005000, 0000000000},
116 {0x00061000, 0x00000002},
117 {0x0000750e, 0x00000002},
118 {0x00019000, 0x00000002},
119 {0x00011055, 0x00000014},
120 {0x00000055, 0x00000012},
121 {0x0400250f, 0x00000002},
122 {0x0000504a, 0x00000004},
123 {0x00007565, 0x00000002},
124 {0x00007566, 0x00000002},
125 {0x00000051, 0x00000004},
126 {0x01e655b4, 0x00000002},
127 {0x4401b0dc, 0x00000002},
128 {0x01c110dc, 0x00000002},
129 {0x2666705d, 0x00000018},
130 {0x040c2565, 0x00000002},
131 {0x0000005d, 0x00000018},
132 {0x04002564, 0x00000002},
133 {0x00007566, 0x00000002},
134 {0x00000054, 0x00000004},
135 {0x00401060, 0x00000008},
136 {0x00101000, 0x00000002},
137 {0x000d80ff, 0x00000002},
138 {0x00800063, 0x00000008},
139 {0x000f9000, 0x00000002},
140 {0x000e00ff, 0x00000002},
141 {0000000000, 0x00000006},
142 {0x00000080, 0x00000018},
143 {0x00000054, 0x00000004},
144 {0x00007576, 0x00000002},
145 {0x00065000, 0x00000002},
146 {0x00009000, 0x00000002},
147 {0x00041000, 0x00000002},
148 {0x0c00350e, 0x00000002},
149 {0x00049000, 0x00000002},
150 {0x00051000, 0x00000002},
151 {0x01e785f8, 0x00000002},
152 {0x00200000, 0x00000002},
153 {0x00600073, 0x0000000c},
154 {0x00007563, 0x00000002},
155 {0x006075f0, 0x00000021},
156 {0x20007068, 0x00000004},
157 {0x00005068, 0x00000004},
158 {0x00007576, 0x00000002},
159 {0x00007577, 0x00000002},
160 {0x0000750e, 0x00000002},
161 {0x0000750f, 0x00000002},
162 {0x00a05000, 0x00000002},
163 {0x00600076, 0x0000000c},
164 {0x006075f0, 0x00000021},
165 {0x000075f8, 0x00000002},
166 {0x00000076, 0x00000004},
167 {0x000a750e, 0x00000002},
168 {0x0020750f, 0x00000002},
169 {0x00600079, 0x00000004},
170 {0x00007570, 0x00000002},
171 {0x00007571, 0x00000002},
172 {0x00007572, 0x00000006},
173 {0x00005000, 0x00000002},
174 {0x00a05000, 0x00000002},
175 {0x00007568, 0x00000002},
176 {0x00061000, 0x00000002},
177 {0x00000084, 0x0000000c},
178 {0x00058000, 0x00000002},
179 {0x0c607562, 0x00000002},
180 {0x00000086, 0x00000004},
181 {0x00600085, 0x00000004},
182 {0x400070dd, 0000000000},
183 {0x000380dd, 0x00000002},
184 {0x00000093, 0x0000001c},
185 {0x00065095, 0x00000018},
186 {0x040025bb, 0x00000002},
187 {0x00061096, 0x00000018},
188 {0x040075bc, 0000000000},
189 {0x000075bb, 0x00000002},
190 {0x000075bc, 0000000000},
191 {0x00090000, 0x00000006},
192 {0x00090000, 0x00000002},
193 {0x000d8002, 0x00000006},
194 {0x00005000, 0x00000002},
195 {0x00007821, 0x00000002},
196 {0x00007800, 0000000000},
197 {0x00007821, 0x00000002},
198 {0x00007800, 0000000000},
199 {0x01665000, 0x00000002},
200 {0x000a0000, 0x00000002},
201 {0x000671cc, 0x00000002},
202 {0x0286f1cd, 0x00000002},
203 {0x000000a3, 0x00000010},
204 {0x21007000, 0000000000},
205 {0x000000aa, 0x0000001c},
206 {0x00065000, 0x00000002},
207 {0x000a0000, 0x00000002},
208 {0x00061000, 0x00000002},
209 {0x000b0000, 0x00000002},
210 {0x38067000, 0x00000002},
211 {0x000a00a6, 0x00000004},
212 {0x20007000, 0000000000},
213 {0x01200000, 0x00000002},
214 {0x20077000, 0x00000002},
215 {0x01200000, 0x00000002},
216 {0x20007000, 0000000000},
217 {0x00061000, 0x00000002},
218 {0x0120751b, 0x00000002},
219 {0x8040750a, 0x00000002},
220 {0x8040750b, 0x00000002},
221 {0x00110000, 0x00000002},
222 {0x000380dd, 0x00000002},
223 {0x000000bd, 0x0000001c},
224 {0x00061096, 0x00000018},
225 {0x844075bd, 0x00000002},
226 {0x00061095, 0x00000018},
227 {0x840075bb, 0x00000002},
228 {0x00061096, 0x00000018},
229 {0x844075bc, 0x00000002},
230 {0x000000c0, 0x00000004},
231 {0x804075bd, 0x00000002},
232 {0x800075bb, 0x00000002},
233 {0x804075bc, 0x00000002},
234 {0x00108000, 0x00000002},
235 {0x01400000, 0x00000002},
236 {0x006000c4, 0x0000000c},
237 {0x20c07000, 0x00000020},
238 {0x000000c6, 0x00000012},
239 {0x00800000, 0x00000006},
240 {0x0080751d, 0x00000006},
241 {0x000025bb, 0x00000002},
242 {0x000040c0, 0x00000004},
243 {0x0000775c, 0x00000002},
244 {0x00a05000, 0x00000002},
245 {0x00661000, 0x00000002},
246 {0x0460275d, 0x00000020},
247 {0x00004000, 0000000000},
248 {0x00007999, 0x00000002},
249 {0x00a05000, 0x00000002},
250 {0x00661000, 0x00000002},
251 {0x0460299b, 0x00000020},
252 {0x00004000, 0000000000},
253 {0x01e00830, 0x00000002},
254 {0x21007000, 0000000000},
255 {0x00005000, 0x00000002},
256 {0x00038042, 0x00000002},
257 {0x040025e0, 0x00000002},
258 {0x000075e1, 0000000000},
259 {0x00000001, 0000000000},
260 {0x000380d9, 0x00000002},
261 {0x04007394, 0000000000},
262 {0000000000, 0000000000},
263 {0000000000, 0000000000},
264 {0000000000, 0000000000},
265 {0000000000, 0000000000},
266 {0000000000, 0000000000},
267 {0000000000, 0000000000},
268 {0000000000, 0000000000},
269 {0000000000, 0000000000},
270 {0000000000, 0000000000},
271 {0000000000, 0000000000},
272 {0000000000, 0000000000},
273 {0000000000, 0000000000},
274 {0000000000, 0000000000},
275 {0000000000, 0000000000},
276 {0000000000, 0000000000},
277 {0000000000, 0000000000},
278 {0000000000, 0000000000},
279 {0000000000, 0000000000},
280 {0000000000, 0000000000},
281 {0000000000, 0000000000},
282 {0000000000, 0000000000},
283 {0000000000, 0000000000},
284 {0000000000, 0000000000},
285 {0000000000, 0000000000},
286 {0000000000, 0000000000},
287 {0000000000, 0000000000},
288 {0000000000, 0000000000},
289 {0000000000, 0000000000},
290 {0000000000, 0000000000},
291 {0000000000, 0000000000},
292 {0000000000, 0000000000},
293 {0000000000, 0000000000},
294 {0000000000, 0000000000},
295 {0000000000, 0000000000},
296 {0000000000, 0000000000},
297 {0000000000, 0000000000},
300 static u32 radeon_cp_microcode[][2] = {
301 {0x21007000, 0000000000},
302 {0x20007000, 0000000000},
303 {0x000000b4, 0x00000004},
304 {0x000000b8, 0x00000004},
305 {0x6f5b4d4c, 0000000000},
306 {0x4c4c427f, 0000000000},
307 {0x5b568a92, 0000000000},
308 {0x4ca09c6d, 0000000000},
309 {0xad4c4c4c, 0000000000},
310 {0x4ce1af3d, 0000000000},
311 {0xd8afafaf, 0000000000},
312 {0xd64c4cdc, 0000000000},
313 {0x4cd10d10, 0000000000},
314 {0x000f0000, 0x00000016},
315 {0x362f242d, 0000000000},
316 {0x00000012, 0x00000004},
317 {0x000f0000, 0x00000016},
318 {0x362f282d, 0000000000},
319 {0x000380e7, 0x00000002},
320 {0x04002c97, 0x00000002},
321 {0x000f0001, 0x00000016},
322 {0x333a3730, 0000000000},
323 {0x000077ef, 0x00000002},
324 {0x00061000, 0x00000002},
325 {0x00000021, 0x0000001a},
326 {0x00004000, 0x0000001e},
327 {0x00061000, 0x00000002},
328 {0x00000021, 0x0000001a},
329 {0x00004000, 0x0000001e},
330 {0x00061000, 0x00000002},
331 {0x00000021, 0x0000001a},
332 {0x00004000, 0x0000001e},
333 {0x00000017, 0x00000004},
334 {0x0003802b, 0x00000002},
335 {0x040067e0, 0x00000002},
336 {0x00000017, 0x00000004},
337 {0x000077e0, 0x00000002},
338 {0x00065000, 0x00000002},
339 {0x000037e1, 0x00000002},
340 {0x040067e1, 0x00000006},
341 {0x000077e0, 0x00000002},
342 {0x000077e1, 0x00000002},
343 {0x000077e1, 0x00000006},
344 {0xffffffff, 0000000000},
345 {0x10000000, 0000000000},
346 {0x0003802b, 0x00000002},
347 {0x040067e0, 0x00000006},
348 {0x00007675, 0x00000002},
349 {0x00007676, 0x00000002},
350 {0x00007677, 0x00000002},
351 {0x00007678, 0x00000006},
352 {0x0003802c, 0x00000002},
353 {0x04002676, 0x00000002},
354 {0x00007677, 0x00000002},
355 {0x00007678, 0x00000006},
356 {0x0000002f, 0x00000018},
357 {0x0000002f, 0x00000018},
358 {0000000000, 0x00000006},
359 {0x00000030, 0x00000018},
360 {0x00000030, 0x00000018},
361 {0000000000, 0x00000006},
362 {0x01605000, 0x00000002},
363 {0x00065000, 0x00000002},
364 {0x00098000, 0x00000002},
365 {0x00061000, 0x00000002},
366 {0x64c0603e, 0x00000004},
367 {0x000380e6, 0x00000002},
368 {0x040025c5, 0x00000002},
369 {0x00080000, 0x00000016},
370 {0000000000, 0000000000},
371 {0x0400251d, 0x00000002},
372 {0x00007580, 0x00000002},
373 {0x00067581, 0x00000002},
374 {0x04002580, 0x00000002},
375 {0x00067581, 0x00000002},
376 {0x00000049, 0x00000004},
377 {0x00005000, 0000000000},
378 {0x000380e6, 0x00000002},
379 {0x040025c5, 0x00000002},
380 {0x00061000, 0x00000002},
381 {0x0000750e, 0x00000002},
382 {0x00019000, 0x00000002},
383 {0x00011055, 0x00000014},
384 {0x00000055, 0x00000012},
385 {0x0400250f, 0x00000002},
386 {0x0000504f, 0x00000004},
387 {0x000380e6, 0x00000002},
388 {0x040025c5, 0x00000002},
389 {0x00007565, 0x00000002},
390 {0x00007566, 0x00000002},
391 {0x00000058, 0x00000004},
392 {0x000380e6, 0x00000002},
393 {0x040025c5, 0x00000002},
394 {0x01e655b4, 0x00000002},
395 {0x4401b0e4, 0x00000002},
396 {0x01c110e4, 0x00000002},
397 {0x26667066, 0x00000018},
398 {0x040c2565, 0x00000002},
399 {0x00000066, 0x00000018},
400 {0x04002564, 0x00000002},
401 {0x00007566, 0x00000002},
402 {0x0000005d, 0x00000004},
403 {0x00401069, 0x00000008},
404 {0x00101000, 0x00000002},
405 {0x000d80ff, 0x00000002},
406 {0x0080006c, 0x00000008},
407 {0x000f9000, 0x00000002},
408 {0x000e00ff, 0x00000002},
409 {0000000000, 0x00000006},
410 {0x0000008f, 0x00000018},
411 {0x0000005b, 0x00000004},
412 {0x000380e6, 0x00000002},
413 {0x040025c5, 0x00000002},
414 {0x00007576, 0x00000002},
415 {0x00065000, 0x00000002},
416 {0x00009000, 0x00000002},
417 {0x00041000, 0x00000002},
418 {0x0c00350e, 0x00000002},
419 {0x00049000, 0x00000002},
420 {0x00051000, 0x00000002},
421 {0x01e785f8, 0x00000002},
422 {0x00200000, 0x00000002},
423 {0x0060007e, 0x0000000c},
424 {0x00007563, 0x00000002},
425 {0x006075f0, 0x00000021},
426 {0x20007073, 0x00000004},
427 {0x00005073, 0x00000004},
428 {0x000380e6, 0x00000002},
429 {0x040025c5, 0x00000002},
430 {0x00007576, 0x00000002},
431 {0x00007577, 0x00000002},
432 {0x0000750e, 0x00000002},
433 {0x0000750f, 0x00000002},
434 {0x00a05000, 0x00000002},
435 {0x00600083, 0x0000000c},
436 {0x006075f0, 0x00000021},
437 {0x000075f8, 0x00000002},
438 {0x00000083, 0x00000004},
439 {0x000a750e, 0x00000002},
440 {0x000380e6, 0x00000002},
441 {0x040025c5, 0x00000002},
442 {0x0020750f, 0x00000002},
443 {0x00600086, 0x00000004},
444 {0x00007570, 0x00000002},
445 {0x00007571, 0x00000002},
446 {0x00007572, 0x00000006},
447 {0x000380e6, 0x00000002},
448 {0x040025c5, 0x00000002},
449 {0x00005000, 0x00000002},
450 {0x00a05000, 0x00000002},
451 {0x00007568, 0x00000002},
452 {0x00061000, 0x00000002},
453 {0x00000095, 0x0000000c},
454 {0x00058000, 0x00000002},
455 {0x0c607562, 0x00000002},
456 {0x00000097, 0x00000004},
457 {0x000380e6, 0x00000002},
458 {0x040025c5, 0x00000002},
459 {0x00600096, 0x00000004},
460 {0x400070e5, 0000000000},
461 {0x000380e6, 0x00000002},
462 {0x040025c5, 0x00000002},
463 {0x000380e5, 0x00000002},
464 {0x000000a8, 0x0000001c},
465 {0x000650aa, 0x00000018},
466 {0x040025bb, 0x00000002},
467 {0x000610ab, 0x00000018},
468 {0x040075bc, 0000000000},
469 {0x000075bb, 0x00000002},
470 {0x000075bc, 0000000000},
471 {0x00090000, 0x00000006},
472 {0x00090000, 0x00000002},
473 {0x000d8002, 0x00000006},
474 {0x00007832, 0x00000002},
475 {0x00005000, 0x00000002},
476 {0x000380e7, 0x00000002},
477 {0x04002c97, 0x00000002},
478 {0x00007820, 0x00000002},
479 {0x00007821, 0x00000002},
480 {0x00007800, 0000000000},
481 {0x01200000, 0x00000002},
482 {0x20077000, 0x00000002},
483 {0x01200000, 0x00000002},
484 {0x20007000, 0x00000002},
485 {0x00061000, 0x00000002},
486 {0x0120751b, 0x00000002},
487 {0x8040750a, 0x00000002},
488 {0x8040750b, 0x00000002},
489 {0x00110000, 0x00000002},
490 {0x000380e5, 0x00000002},
491 {0x000000c6, 0x0000001c},
492 {0x000610ab, 0x00000018},
493 {0x844075bd, 0x00000002},
494 {0x000610aa, 0x00000018},
495 {0x840075bb, 0x00000002},
496 {0x000610ab, 0x00000018},
497 {0x844075bc, 0x00000002},
498 {0x000000c9, 0x00000004},
499 {0x804075bd, 0x00000002},
500 {0x800075bb, 0x00000002},
501 {0x804075bc, 0x00000002},
502 {0x00108000, 0x00000002},
503 {0x01400000, 0x00000002},
504 {0x006000cd, 0x0000000c},
505 {0x20c07000, 0x00000020},
506 {0x000000cf, 0x00000012},
507 {0x00800000, 0x00000006},
508 {0x0080751d, 0x00000006},
509 {0000000000, 0000000000},
510 {0x0000775c, 0x00000002},
511 {0x00a05000, 0x00000002},
512 {0x00661000, 0x00000002},
513 {0x0460275d, 0x00000020},
514 {0x00004000, 0000000000},
515 {0x01e00830, 0x00000002},
516 {0x21007000, 0000000000},
517 {0x6464614d, 0000000000},
518 {0x69687420, 0000000000},
519 {0x00000073, 0000000000},
520 {0000000000, 0000000000},
521 {0x00005000, 0x00000002},
522 {0x000380d0, 0x00000002},
523 {0x040025e0, 0x00000002},
524 {0x000075e1, 0000000000},
525 {0x00000001, 0000000000},
526 {0x000380e0, 0x00000002},
527 {0x04002394, 0x00000002},
528 {0x00005000, 0000000000},
529 {0000000000, 0000000000},
530 {0000000000, 0000000000},
531 {0x00000008, 0000000000},
532 {0x00000004, 0000000000},
533 {0000000000, 0000000000},
534 {0000000000, 0000000000},
535 {0000000000, 0000000000},
536 {0000000000, 0000000000},
537 {0000000000, 0000000000},
538 {0000000000, 0000000000},
539 {0000000000, 0000000000},
540 {0000000000, 0000000000},
541 {0000000000, 0000000000},
542 {0000000000, 0000000000},
543 {0000000000, 0000000000},
544 {0000000000, 0000000000},
545 {0000000000, 0000000000},
546 {0000000000, 0000000000},
547 {0000000000, 0000000000},
548 {0000000000, 0000000000},
549 {0000000000, 0000000000},
550 {0000000000, 0000000000},
551 {0000000000, 0000000000},
552 {0000000000, 0000000000},
553 {0000000000, 0000000000},
554 {0000000000, 0000000000},
555 {0000000000, 0000000000},
556 {0000000000, 0000000000},
559 static u32 R300_cp_microcode[][2] = {
560 { 0x4200e000, 0000000000 },
561 { 0x4000e000, 0000000000 },
562 { 0x000000af, 0x00000008 },
563 { 0x000000b3, 0x00000008 },
564 { 0x6c5a504f, 0000000000 },
565 { 0x4f4f497a, 0000000000 },
566 { 0x5a578288, 0000000000 },
567 { 0x4f91906a, 0000000000 },
568 { 0x4f4f4f4f, 0000000000 },
569 { 0x4fe24f44, 0000000000 },
570 { 0x4f9c9c9c, 0000000000 },
571 { 0xdc4f4fde, 0000000000 },
572 { 0xa1cd4f4f, 0000000000 },
573 { 0xd29d9d9d, 0000000000 },
574 { 0x4f0f9fd7, 0000000000 },
575 { 0x000ca000, 0x00000004 },
576 { 0x000d0012, 0x00000038 },
577 { 0x0000e8b4, 0x00000004 },
578 { 0x000d0014, 0x00000038 },
579 { 0x0000e8b6, 0x00000004 },
580 { 0x000d0016, 0x00000038 },
581 { 0x0000e854, 0x00000004 },
582 { 0x000d0018, 0x00000038 },
583 { 0x0000e855, 0x00000004 },
584 { 0x000d001a, 0x00000038 },
585 { 0x0000e856, 0x00000004 },
586 { 0x000d001c, 0x00000038 },
587 { 0x0000e857, 0x00000004 },
588 { 0x000d001e, 0x00000038 },
589 { 0x0000e824, 0x00000004 },
590 { 0x000d0020, 0x00000038 },
591 { 0x0000e825, 0x00000004 },
592 { 0x000d0022, 0x00000038 },
593 { 0x0000e830, 0x00000004 },
594 { 0x000d0024, 0x00000038 },
595 { 0x0000f0c0, 0x00000004 },
596 { 0x000d0026, 0x00000038 },
597 { 0x0000f0c1, 0x00000004 },
598 { 0x000d0028, 0x00000038 },
599 { 0x0000f041, 0x00000004 },
600 { 0x000d002a, 0x00000038 },
601 { 0x0000f184, 0x00000004 },
602 { 0x000d002c, 0x00000038 },
603 { 0x0000f185, 0x00000004 },
604 { 0x000d002e, 0x00000038 },
605 { 0x0000f186, 0x00000004 },
606 { 0x000d0030, 0x00000038 },
607 { 0x0000f187, 0x00000004 },
608 { 0x000d0032, 0x00000038 },
609 { 0x0000f180, 0x00000004 },
610 { 0x000d0034, 0x00000038 },
611 { 0x0000f393, 0x00000004 },
612 { 0x000d0036, 0x00000038 },
613 { 0x0000f38a, 0x00000004 },
614 { 0x000d0038, 0x00000038 },
615 { 0x0000f38e, 0x00000004 },
616 { 0x0000e821, 0x00000004 },
617 { 0x0140a000, 0x00000004 },
618 { 0x00000043, 0x00000018 },
619 { 0x00cce800, 0x00000004 },
620 { 0x001b0001, 0x00000004 },
621 { 0x08004800, 0x00000004 },
622 { 0x001b0001, 0x00000004 },
623 { 0x08004800, 0x00000004 },
624 { 0x001b0001, 0x00000004 },
625 { 0x08004800, 0x00000004 },
626 { 0x0000003a, 0x00000008 },
627 { 0x0000a000, 0000000000 },
628 { 0x02c0a000, 0x00000004 },
629 { 0x000ca000, 0x00000004 },
630 { 0x00130000, 0x00000004 },
631 { 0x000c2000, 0x00000004 },
632 { 0xc980c045, 0x00000008 },
633 { 0x2000451d, 0x00000004 },
634 { 0x0000e580, 0x00000004 },
635 { 0x000ce581, 0x00000004 },
636 { 0x08004580, 0x00000004 },
637 { 0x000ce581, 0x00000004 },
638 { 0x0000004c, 0x00000008 },
639 { 0x0000a000, 0000000000 },
640 { 0x000c2000, 0x00000004 },
641 { 0x0000e50e, 0x00000004 },
642 { 0x00032000, 0x00000004 },
643 { 0x00022056, 0x00000028 },
644 { 0x00000056, 0x00000024 },
645 { 0x0800450f, 0x00000004 },
646 { 0x0000a050, 0x00000008 },
647 { 0x0000e565, 0x00000004 },
648 { 0x0000e566, 0x00000004 },
649 { 0x00000057, 0x00000008 },
650 { 0x03cca5b4, 0x00000004 },
651 { 0x05432000, 0x00000004 },
652 { 0x00022000, 0x00000004 },
653 { 0x4ccce063, 0x00000030 },
654 { 0x08274565, 0x00000004 },
655 { 0x00000063, 0x00000030 },
656 { 0x08004564, 0x00000004 },
657 { 0x0000e566, 0x00000004 },
658 { 0x0000005a, 0x00000008 },
659 { 0x00802066, 0x00000010 },
660 { 0x00202000, 0x00000004 },
661 { 0x001b00ff, 0x00000004 },
662 { 0x01000069, 0x00000010 },
663 { 0x001f2000, 0x00000004 },
664 { 0x001c00ff, 0x00000004 },
665 { 0000000000, 0x0000000c },
666 { 0x00000085, 0x00000030 },
667 { 0x0000005a, 0x00000008 },
668 { 0x0000e576, 0x00000004 },
669 { 0x000ca000, 0x00000004 },
670 { 0x00012000, 0x00000004 },
671 { 0x00082000, 0x00000004 },
672 { 0x1800650e, 0x00000004 },
673 { 0x00092000, 0x00000004 },
674 { 0x000a2000, 0x00000004 },
675 { 0x000f0000, 0x00000004 },
676 { 0x00400000, 0x00000004 },
677 { 0x00000079, 0x00000018 },
678 { 0x0000e563, 0x00000004 },
679 { 0x00c0e5f9, 0x000000c2 },
680 { 0x0000006e, 0x00000008 },
681 { 0x0000a06e, 0x00000008 },
682 { 0x0000e576, 0x00000004 },
683 { 0x0000e577, 0x00000004 },
684 { 0x0000e50e, 0x00000004 },
685 { 0x0000e50f, 0x00000004 },
686 { 0x0140a000, 0x00000004 },
687 { 0x0000007c, 0x00000018 },
688 { 0x00c0e5f9, 0x000000c2 },
689 { 0x0000007c, 0x00000008 },
690 { 0x0014e50e, 0x00000004 },
691 { 0x0040e50f, 0x00000004 },
692 { 0x00c0007f, 0x00000008 },
693 { 0x0000e570, 0x00000004 },
694 { 0x0000e571, 0x00000004 },
695 { 0x0000e572, 0x0000000c },
696 { 0x0000a000, 0x00000004 },
697 { 0x0140a000, 0x00000004 },
698 { 0x0000e568, 0x00000004 },
699 { 0x000c2000, 0x00000004 },
700 { 0x00000089, 0x00000018 },
701 { 0x000b0000, 0x00000004 },
702 { 0x18c0e562, 0x00000004 },
703 { 0x0000008b, 0x00000008 },
704 { 0x00c0008a, 0x00000008 },
705 { 0x000700e4, 0x00000004 },
706 { 0x00000097, 0x00000038 },
707 { 0x000ca099, 0x00000030 },
708 { 0x080045bb, 0x00000004 },
709 { 0x000c209a, 0x00000030 },
710 { 0x0800e5bc, 0000000000 },
711 { 0x0000e5bb, 0x00000004 },
712 { 0x0000e5bc, 0000000000 },
713 { 0x00120000, 0x0000000c },
714 { 0x00120000, 0x00000004 },
715 { 0x001b0002, 0x0000000c },
716 { 0x0000a000, 0x00000004 },
717 { 0x0000e821, 0x00000004 },
718 { 0x0000e800, 0000000000 },
719 { 0x0000e821, 0x00000004 },
720 { 0x0000e82e, 0000000000 },
721 { 0x02cca000, 0x00000004 },
722 { 0x00140000, 0x00000004 },
723 { 0x000ce1cc, 0x00000004 },
724 { 0x050de1cd, 0x00000004 },
725 { 0x000000a7, 0x00000020 },
726 { 0x4200e000, 0000000000 },
727 { 0x000000ae, 0x00000038 },
728 { 0x000ca000, 0x00000004 },
729 { 0x00140000, 0x00000004 },
730 { 0x000c2000, 0x00000004 },
731 { 0x00160000, 0x00000004 },
732 { 0x700ce000, 0x00000004 },
733 { 0x001400aa, 0x00000008 },
734 { 0x4000e000, 0000000000 },
735 { 0x02400000, 0x00000004 },
736 { 0x400ee000, 0x00000004 },
737 { 0x02400000, 0x00000004 },
738 { 0x4000e000, 0000000000 },
739 { 0x000c2000, 0x00000004 },
740 { 0x0240e51b, 0x00000004 },
741 { 0x0080e50a, 0x00000005 },
742 { 0x0080e50b, 0x00000005 },
743 { 0x00220000, 0x00000004 },
744 { 0x000700e4, 0x00000004 },
745 { 0x000000c1, 0x00000038 },
746 { 0x000c209a, 0x00000030 },
747 { 0x0880e5bd, 0x00000005 },
748 { 0x000c2099, 0x00000030 },
749 { 0x0800e5bb, 0x00000005 },
750 { 0x000c209a, 0x00000030 },
751 { 0x0880e5bc, 0x00000005 },
752 { 0x000000c4, 0x00000008 },
753 { 0x0080e5bd, 0x00000005 },
754 { 0x0000e5bb, 0x00000005 },
755 { 0x0080e5bc, 0x00000005 },
756 { 0x00210000, 0x00000004 },
757 { 0x02800000, 0x00000004 },
758 { 0x00c000c8, 0x00000018 },
759 { 0x4180e000, 0x00000040 },
760 { 0x000000ca, 0x00000024 },
761 { 0x01000000, 0x0000000c },
762 { 0x0100e51d, 0x0000000c },
763 { 0x000045bb, 0x00000004 },
764 { 0x000080c4, 0x00000008 },
765 { 0x0000f3ce, 0x00000004 },
766 { 0x0140a000, 0x00000004 },
767 { 0x00cc2000, 0x00000004 },
768 { 0x08c053cf, 0x00000040 },
769 { 0x00008000, 0000000000 },
770 { 0x0000f3d2, 0x00000004 },
771 { 0x0140a000, 0x00000004 },
772 { 0x00cc2000, 0x00000004 },
773 { 0x08c053d3, 0x00000040 },
774 { 0x00008000, 0000000000 },
775 { 0x0000f39d, 0x00000004 },
776 { 0x0140a000, 0x00000004 },
777 { 0x00cc2000, 0x00000004 },
778 { 0x08c0539e, 0x00000040 },
779 { 0x00008000, 0000000000 },
780 { 0x03c00830, 0x00000004 },
781 { 0x4200e000, 0000000000 },
782 { 0x0000a000, 0x00000004 },
783 { 0x200045e0, 0x00000004 },
784 { 0x0000e5e1, 0000000000 },
785 { 0x00000001, 0000000000 },
786 { 0x000700e1, 0x00000004 },
787 { 0x0800e394, 0000000000 },
788 { 0000000000, 0000000000 },
789 { 0000000000, 0000000000 },
790 { 0000000000, 0000000000 },
791 { 0000000000, 0000000000 },
792 { 0000000000, 0000000000 },
793 { 0000000000, 0000000000 },
794 { 0000000000, 0000000000 },
795 { 0000000000, 0000000000 },
796 { 0000000000, 0000000000 },
797 { 0000000000, 0000000000 },
798 { 0000000000, 0000000000 },
799 { 0000000000, 0000000000 },
800 { 0000000000, 0000000000 },
801 { 0000000000, 0000000000 },
802 { 0000000000, 0000000000 },
803 { 0000000000, 0000000000 },
804 { 0000000000, 0000000000 },
805 { 0000000000, 0000000000 },
806 { 0000000000, 0000000000 },
807 { 0000000000, 0000000000 },
808 { 0000000000, 0000000000 },
809 { 0000000000, 0000000000 },
810 { 0000000000, 0000000000 },
811 { 0000000000, 0000000000 },
812 { 0000000000, 0000000000 },
813 { 0000000000, 0000000000 },
814 { 0000000000, 0000000000 },
815 { 0000000000, 0000000000 },
818 static int RADEON_READ_PLL(drm_device_t * dev, int addr)
820 drm_radeon_private_t *dev_priv = dev->dev_private;
822 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
823 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
826 #if RADEON_FIFO_DEBUG
827 static void radeon_status(drm_radeon_private_t * dev_priv)
829 printk("%s:\n", __FUNCTION__);
830 printk("RBBM_STATUS = 0x%08x\n",
831 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
832 printk("CP_RB_RTPR = 0x%08x\n",
833 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
834 printk("CP_RB_WTPR = 0x%08x\n",
835 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
836 printk("AIC_CNTL = 0x%08x\n",
837 (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
838 printk("AIC_STAT = 0x%08x\n",
839 (unsigned int)RADEON_READ(RADEON_AIC_STAT));
840 printk("AIC_PT_BASE = 0x%08x\n",
841 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
842 printk("TLB_ADDR = 0x%08x\n",
843 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
844 printk("TLB_DATA = 0x%08x\n",
845 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
849 /* ================================================================
850 * Engine, FIFO control
853 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
858 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
860 tmp = RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT);
861 tmp |= RADEON_RB2D_DC_FLUSH_ALL;
862 RADEON_WRITE(RADEON_RB2D_DSTCACHE_CTLSTAT, tmp);
864 for (i = 0; i < dev_priv->usec_timeout; i++) {
865 if (!(RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT)
866 & RADEON_RB2D_DC_BUSY)) {
872 #if RADEON_FIFO_DEBUG
873 DRM_ERROR("failed!\n");
874 radeon_status(dev_priv);
876 return DRM_ERR(EBUSY);
879 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
883 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
885 for (i = 0; i < dev_priv->usec_timeout; i++) {
886 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
887 & RADEON_RBBM_FIFOCNT_MASK);
888 if (slots >= entries)
893 #if RADEON_FIFO_DEBUG
894 DRM_ERROR("failed!\n");
895 radeon_status(dev_priv);
897 return DRM_ERR(EBUSY);
900 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
904 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
906 ret = radeon_do_wait_for_fifo(dev_priv, 64);
910 for (i = 0; i < dev_priv->usec_timeout; i++) {
911 if (!(RADEON_READ(RADEON_RBBM_STATUS)
912 & RADEON_RBBM_ACTIVE)) {
913 radeon_do_pixcache_flush(dev_priv);
919 #if RADEON_FIFO_DEBUG
920 DRM_ERROR("failed!\n");
921 radeon_status(dev_priv);
923 return DRM_ERR(EBUSY);
926 /* ================================================================
927 * CP control, initialization
930 /* Load the microcode for the CP */
931 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
936 radeon_do_wait_for_idle(dev_priv);
938 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
940 if (dev_priv->microcode_version==UCODE_R200) {
941 DRM_INFO("Loading R200 Microcode\n");
942 for (i = 0; i < 256; i++) {
943 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
944 R200_cp_microcode[i][1]);
945 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
946 R200_cp_microcode[i][0]);
948 } else if (dev_priv->microcode_version==UCODE_R300) {
949 DRM_INFO("Loading R300 Microcode\n");
950 for ( i = 0 ; i < 256 ; i++ ) {
951 RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
952 R300_cp_microcode[i][1] );
953 RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
954 R300_cp_microcode[i][0] );
957 for (i = 0; i < 256; i++) {
958 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
959 radeon_cp_microcode[i][1]);
960 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
961 radeon_cp_microcode[i][0]);
966 /* Flush any pending commands to the CP. This should only be used just
967 * prior to a wait for idle, as it informs the engine that the command
970 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
976 tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
977 RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
981 /* Wait for the CP to go idle.
983 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
990 RADEON_PURGE_CACHE();
991 RADEON_PURGE_ZCACHE();
992 RADEON_WAIT_UNTIL_IDLE();
997 return radeon_do_wait_for_idle(dev_priv);
1000 /* Start the Command Processor.
1002 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
1007 radeon_do_wait_for_idle(dev_priv);
1009 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
1011 dev_priv->cp_running = 1;
1015 RADEON_PURGE_CACHE();
1016 RADEON_PURGE_ZCACHE();
1017 RADEON_WAIT_UNTIL_IDLE();
1023 /* Reset the Command Processor. This will not flush any pending
1024 * commands, so you must wait for the CP command stream to complete
1025 * before calling this routine.
1027 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
1032 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
1033 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
1034 SET_RING_HEAD(dev_priv, cur_read_ptr);
1035 dev_priv->ring.tail = cur_read_ptr;
1038 /* Stop the Command Processor. This will not flush any pending
1039 * commands, so you must flush the command stream and wait for the CP
1040 * to go idle before calling this routine.
1042 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
1046 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
1048 dev_priv->cp_running = 0;
1051 /* Reset the engine. This will stop the CP if it is running.
1053 static int radeon_do_engine_reset(drm_device_t * dev)
1055 drm_radeon_private_t *dev_priv = dev->dev_private;
1056 u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
1059 radeon_do_pixcache_flush(dev_priv);
1061 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
1062 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
1064 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
1065 RADEON_FORCEON_MCLKA |
1066 RADEON_FORCEON_MCLKB |
1067 RADEON_FORCEON_YCLKA |
1068 RADEON_FORCEON_YCLKB |
1070 RADEON_FORCEON_AIC));
1072 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
1074 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
1075 RADEON_SOFT_RESET_CP |
1076 RADEON_SOFT_RESET_HI |
1077 RADEON_SOFT_RESET_SE |
1078 RADEON_SOFT_RESET_RE |
1079 RADEON_SOFT_RESET_PP |
1080 RADEON_SOFT_RESET_E2 |
1081 RADEON_SOFT_RESET_RB));
1082 RADEON_READ(RADEON_RBBM_SOFT_RESET);
1083 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
1084 ~(RADEON_SOFT_RESET_CP |
1085 RADEON_SOFT_RESET_HI |
1086 RADEON_SOFT_RESET_SE |
1087 RADEON_SOFT_RESET_RE |
1088 RADEON_SOFT_RESET_PP |
1089 RADEON_SOFT_RESET_E2 |
1090 RADEON_SOFT_RESET_RB)));
1091 RADEON_READ(RADEON_RBBM_SOFT_RESET);
1093 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
1094 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
1095 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
1097 /* Reset the CP ring */
1098 radeon_do_cp_reset(dev_priv);
1100 /* The CP is no longer running after an engine reset */
1101 dev_priv->cp_running = 0;
1103 /* Reset any pending vertex, indirect buffers */
1104 radeon_freelist_reset(dev);
1109 static void radeon_cp_init_ring_buffer(drm_device_t * dev,
1110 drm_radeon_private_t * dev_priv)
1112 u32 ring_start, cur_read_ptr;
1115 /* Initialize the memory controller */
1116 RADEON_WRITE(RADEON_MC_FB_LOCATION,
1117 ((dev_priv->gart_vm_start - 1) & 0xffff0000)
1118 | (dev_priv->fb_location >> 16));
1121 if (dev_priv->flags & CHIP_IS_AGP) {
1122 RADEON_WRITE(RADEON_MC_AGP_LOCATION,
1123 (((dev_priv->gart_vm_start - 1 +
1124 dev_priv->gart_size) & 0xffff0000) |
1125 (dev_priv->gart_vm_start >> 16)));
1127 ring_start = (dev_priv->cp_ring->offset
1128 - dev->agp->base + dev_priv->gart_vm_start);
1131 ring_start = (dev_priv->cp_ring->offset
1132 - dev->sg->handle + dev_priv->gart_vm_start);
1134 RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
1136 /* Set the write pointer delay */
1137 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
1139 /* Initialize the ring buffer's read and write pointers */
1140 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
1141 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
1142 SET_RING_HEAD(dev_priv, cur_read_ptr);
1143 dev_priv->ring.tail = cur_read_ptr;
1146 if (dev_priv->flags & CHIP_IS_AGP) {
1147 /* set RADEON_AGP_BASE here instead of relying on X from user space */
1148 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);
1149 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
1150 dev_priv->ring_rptr->offset
1151 - dev->agp->base + dev_priv->gart_vm_start);
1155 drm_sg_mem_t *entry = dev->sg;
1156 unsigned long tmp_ofs, page_ofs;
1158 tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle;
1159 page_ofs = tmp_ofs >> PAGE_SHIFT;
1161 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
1162 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
1163 (unsigned long)entry->busaddr[page_ofs],
1164 entry->handle + tmp_ofs);
1167 /* Initialize the scratch register pointer. This will cause
1168 * the scratch register values to be written out to memory
1169 * whenever they are updated.
1171 * We simply put this behind the ring read pointer, this works
1172 * with PCI GART as well as (whatever kind of) AGP GART
1174 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
1175 + RADEON_SCRATCH_REG_OFFSET);
1177 dev_priv->scratch = ((__volatile__ u32 *)
1178 dev_priv->ring_rptr->handle +
1179 (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
1181 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
1183 /* Writeback doesn't seem to work everywhere, test it first */
1184 DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
1185 RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
1187 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
1188 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
1194 if (tmp < dev_priv->usec_timeout) {
1195 dev_priv->writeback_works = 1;
1196 DRM_DEBUG("writeback test succeeded, tmp=%d\n", tmp);
1198 dev_priv->writeback_works = 0;
1199 DRM_DEBUG("writeback test failed\n");
1202 dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
1203 RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
1205 dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
1206 RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
1207 dev_priv->sarea_priv->last_dispatch);
1209 dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
1210 RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
1212 /* Set ring buffer size */
1214 RADEON_WRITE(RADEON_CP_RB_CNTL,
1215 dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT);
1217 RADEON_WRITE(RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw);
1220 radeon_do_wait_for_idle(dev_priv);
1222 /* Turn on bus mastering */
1223 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
1224 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
1226 /* Sync everything up */
1227 RADEON_WRITE(RADEON_ISYNC_CNTL,
1228 (RADEON_ISYNC_ANY2D_IDLE3D |
1229 RADEON_ISYNC_ANY3D_IDLE2D |
1230 RADEON_ISYNC_WAIT_IDLEGUI |
1231 RADEON_ISYNC_CPSCRATCH_IDLEGUI));
1234 /* Enable or disable PCI GART on the chip */
1235 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1237 u32 tmp = RADEON_READ(RADEON_AIC_CNTL);
1240 RADEON_WRITE(RADEON_AIC_CNTL,
1241 tmp | RADEON_PCIGART_TRANSLATE_EN);
1243 /* set PCI GART page-table base address
1245 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart);
1247 /* set address range for PCI address translate
1249 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1250 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1251 + dev_priv->gart_size - 1);
1253 /* Turn off AGP aperture -- is this required for PCI GART?
1255 RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0); /* ?? */
1256 RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
1258 RADEON_WRITE(RADEON_AIC_CNTL,
1259 tmp & ~RADEON_PCIGART_TRANSLATE_EN);
1263 static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
1265 drm_radeon_private_t *dev_priv = dev->dev_private;
1268 if ((!(dev_priv->flags & CHIP_IS_AGP)) && !dev->sg) {
1269 DRM_ERROR("PCI GART memory not allocated!\n");
1270 radeon_do_cleanup_cp(dev);
1271 return DRM_ERR(EINVAL);
1274 dev_priv->usec_timeout = init->usec_timeout;
1275 if (dev_priv->usec_timeout < 1 ||
1276 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1277 DRM_DEBUG("TIMEOUT problem!\n");
1278 radeon_do_cleanup_cp(dev);
1279 return DRM_ERR(EINVAL);
1282 switch(init->func) {
1283 case RADEON_INIT_R200_CP:
1284 dev_priv->microcode_version=UCODE_R200;
1286 case RADEON_INIT_R300_CP:
1287 dev_priv->microcode_version=UCODE_R300;
1290 dev_priv->microcode_version=UCODE_R100;
1294 dev_priv->do_boxes = 0;
1295 dev_priv->cp_mode = init->cp_mode;
1297 /* We don't support anything other than bus-mastering ring mode,
1298 * but the ring can be in either AGP or PCI space for the ring
1301 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1302 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1303 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1304 radeon_do_cleanup_cp(dev);
1305 return DRM_ERR(EINVAL);
1308 switch (init->fb_bpp) {
1310 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1314 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1317 dev_priv->front_offset = init->front_offset;
1318 dev_priv->front_pitch = init->front_pitch;
1319 dev_priv->back_offset = init->back_offset;
1320 dev_priv->back_pitch = init->back_pitch;
1322 switch (init->depth_bpp) {
1324 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1328 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1331 dev_priv->depth_offset = init->depth_offset;
1332 dev_priv->depth_pitch = init->depth_pitch;
1334 /* Hardware state for depth clears. Remove this if/when we no
1335 * longer clear the depth buffer with a 3D rectangle. Hard-code
1336 * all values to prevent unwanted 3D state from slipping through
1337 * and screwing with the clear operation.
1339 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1340 (dev_priv->color_fmt << 10) |
1341 (dev_priv->microcode_version == UCODE_R100 ?
1342 RADEON_ZBLOCK16 : 0));
1344 dev_priv->depth_clear.rb3d_zstencilcntl =
1345 (dev_priv->depth_fmt |
1346 RADEON_Z_TEST_ALWAYS |
1347 RADEON_STENCIL_TEST_ALWAYS |
1348 RADEON_STENCIL_S_FAIL_REPLACE |
1349 RADEON_STENCIL_ZPASS_REPLACE |
1350 RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1352 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1353 RADEON_BFACE_SOLID |
1354 RADEON_FFACE_SOLID |
1355 RADEON_FLAT_SHADE_VTX_LAST |
1356 RADEON_DIFFUSE_SHADE_FLAT |
1357 RADEON_ALPHA_SHADE_FLAT |
1358 RADEON_SPECULAR_SHADE_FLAT |
1359 RADEON_FOG_SHADE_FLAT |
1360 RADEON_VTX_PIX_CENTER_OGL |
1361 RADEON_ROUND_MODE_TRUNC |
1362 RADEON_ROUND_PREC_8TH_PIX);
1366 dev_priv->fb_offset = init->fb_offset;
1367 dev_priv->mmio_offset = init->mmio_offset;
1368 dev_priv->ring_offset = init->ring_offset;
1369 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1370 dev_priv->buffers_offset = init->buffers_offset;
1371 dev_priv->gart_textures_offset = init->gart_textures_offset;
1373 if (!dev_priv->sarea) {
1374 DRM_ERROR("could not find sarea!\n");
1375 radeon_do_cleanup_cp(dev);
1376 return DRM_ERR(EINVAL);
1379 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
1380 if (!dev_priv->mmio) {
1381 DRM_ERROR("could not find mmio region!\n");
1382 radeon_do_cleanup_cp(dev);
1383 return DRM_ERR(EINVAL);
1385 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1386 if (!dev_priv->cp_ring) {
1387 DRM_ERROR("could not find cp ring region!\n");
1388 radeon_do_cleanup_cp(dev);
1389 return DRM_ERR(EINVAL);
1391 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1392 if (!dev_priv->ring_rptr) {
1393 DRM_ERROR("could not find ring read pointer!\n");
1394 radeon_do_cleanup_cp(dev);
1395 return DRM_ERR(EINVAL);
1397 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1398 if (!dev->agp_buffer_map) {
1399 DRM_ERROR("could not find dma buffer region!\n");
1400 radeon_do_cleanup_cp(dev);
1401 return DRM_ERR(EINVAL);
1404 if (init->gart_textures_offset) {
1405 dev_priv->gart_textures =
1406 drm_core_findmap(dev, init->gart_textures_offset);
1407 if (!dev_priv->gart_textures) {
1408 DRM_ERROR("could not find GART texture region!\n");
1409 radeon_do_cleanup_cp(dev);
1410 return DRM_ERR(EINVAL);
1414 dev_priv->sarea_priv =
1415 (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
1416 init->sarea_priv_offset);
1419 if (dev_priv->flags & CHIP_IS_AGP) {
1420 drm_core_ioremap(dev_priv->cp_ring, dev);
1421 drm_core_ioremap(dev_priv->ring_rptr, dev);
1422 drm_core_ioremap(dev->agp_buffer_map, dev);
1423 if (!dev_priv->cp_ring->handle ||
1424 !dev_priv->ring_rptr->handle ||
1425 !dev->agp_buffer_map->handle) {
1426 DRM_ERROR("could not find ioremap agp regions!\n");
1427 radeon_do_cleanup_cp(dev);
1428 return DRM_ERR(EINVAL);
1433 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1434 dev_priv->ring_rptr->handle =
1435 (void *)dev_priv->ring_rptr->offset;
1436 dev->agp_buffer_map->handle =
1437 (void *)dev->agp_buffer_map->offset;
1439 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1440 dev_priv->cp_ring->handle);
1441 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1442 dev_priv->ring_rptr->handle);
1443 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1444 dev->agp_buffer_map->handle);
1447 dev_priv->fb_location = (RADEON_READ(RADEON_MC_FB_LOCATION)
1450 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1451 ((dev_priv->front_offset
1452 + dev_priv->fb_location) >> 10));
1454 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1455 ((dev_priv->back_offset
1456 + dev_priv->fb_location) >> 10));
1458 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1459 ((dev_priv->depth_offset
1460 + dev_priv->fb_location) >> 10));
1462 dev_priv->gart_size = init->gart_size;
1463 dev_priv->gart_vm_start = dev_priv->fb_location
1464 + RADEON_READ(RADEON_CONFIG_APER_SIZE);
1467 if (dev_priv->flags & CHIP_IS_AGP)
1468 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1470 + dev_priv->gart_vm_start);
1473 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1475 + dev_priv->gart_vm_start);
1477 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1478 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1479 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1480 dev_priv->gart_buffers_offset);
1482 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1483 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1484 + init->ring_size / sizeof(u32));
1485 dev_priv->ring.size = init->ring_size;
1486 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1488 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1490 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1493 if (dev_priv->flags & CHIP_IS_AGP) {
1494 /* Turn off PCI GART */
1495 radeon_set_pcigart(dev_priv, 0);
1499 if (!drm_ati_pcigart_init(dev, &dev_priv->phys_pci_gart,
1500 &dev_priv->bus_pci_gart)) {
1501 DRM_ERROR("failed to init PCI GART!\n");
1502 radeon_do_cleanup_cp(dev);
1503 return DRM_ERR(ENOMEM);
1506 /* Turn on PCI GART */
1507 radeon_set_pcigart(dev_priv, 1);
1510 radeon_cp_load_microcode(dev_priv);
1511 radeon_cp_init_ring_buffer(dev, dev_priv);
1513 dev_priv->last_buf = 0;
1515 radeon_do_engine_reset(dev);
1520 static int radeon_do_cleanup_cp(drm_device_t * dev)
1522 drm_radeon_private_t *dev_priv = dev->dev_private;
1525 /* Make sure interrupts are disabled here because the uninstall ioctl
1526 * may not have been called from userspace and after dev_private
1527 * is freed, it's too late.
1529 if (dev->irq_enabled)
1530 drm_irq_uninstall(dev);
1533 if (dev_priv->flags & CHIP_IS_AGP) {
1534 if (dev_priv->cp_ring != NULL) {
1535 drm_core_ioremapfree(dev_priv->cp_ring, dev);
1536 dev_priv->cp_ring = NULL;
1538 if (dev_priv->ring_rptr != NULL) {
1539 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1540 dev_priv->ring_rptr = NULL;
1542 if (dev->agp_buffer_map != NULL) {
1543 drm_core_ioremapfree(dev->agp_buffer_map, dev);
1544 dev->agp_buffer_map = NULL;
1549 if (!drm_ati_pcigart_cleanup(dev,
1550 dev_priv->phys_pci_gart,
1551 dev_priv->bus_pci_gart))
1552 DRM_ERROR("failed to cleanup PCI GART!\n");
1554 /* only clear to the start of flags */
1555 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1560 /* This code will reinit the Radeon CP hardware after a resume from disc.
1561 * AFAIK, it would be very difficult to pickle the state at suspend time, so
1562 * here we make sure that all Radeon hardware initialisation is re-done without
1563 * affecting running applications.
1565 * Charl P. Botha <http://cpbotha.net>
1567 static int radeon_do_resume_cp(drm_device_t * dev)
1569 drm_radeon_private_t *dev_priv = dev->dev_private;
1572 DRM_ERROR("Called with no initialization\n");
1573 return DRM_ERR(EINVAL);
1576 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1579 if (dev_priv->flags & CHIP_IS_AGP) {
1580 /* Turn off PCI GART */
1581 radeon_set_pcigart(dev_priv, 0);
1585 /* Turn on PCI GART */
1586 radeon_set_pcigart(dev_priv, 1);
1589 radeon_cp_load_microcode(dev_priv);
1590 radeon_cp_init_ring_buffer(dev, dev_priv);
1592 radeon_do_engine_reset(dev);
1594 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1599 int radeon_cp_init(DRM_IOCTL_ARGS)
1602 drm_radeon_init_t init;
1604 LOCK_TEST_WITH_RETURN(dev, filp);
1606 DRM_COPY_FROM_USER_IOCTL(init, (drm_radeon_init_t __user *) data,
1609 switch (init.func) {
1610 case RADEON_INIT_CP:
1611 case RADEON_INIT_R200_CP:
1612 case RADEON_INIT_R300_CP:
1613 return radeon_do_init_cp(dev, &init);
1614 case RADEON_CLEANUP_CP:
1615 return radeon_do_cleanup_cp(dev);
1618 return DRM_ERR(EINVAL);
1621 int radeon_cp_start(DRM_IOCTL_ARGS)
1624 drm_radeon_private_t *dev_priv = dev->dev_private;
1627 LOCK_TEST_WITH_RETURN(dev, filp);
1629 if (dev_priv->cp_running) {
1630 DRM_DEBUG("%s while CP running\n", __FUNCTION__);
1633 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1634 DRM_DEBUG("%s called with bogus CP mode (%d)\n",
1635 __FUNCTION__, dev_priv->cp_mode);
1639 radeon_do_cp_start(dev_priv);
1644 /* Stop the CP. The engine must have been idled before calling this
1647 int radeon_cp_stop(DRM_IOCTL_ARGS)
1650 drm_radeon_private_t *dev_priv = dev->dev_private;
1651 drm_radeon_cp_stop_t stop;
1655 LOCK_TEST_WITH_RETURN(dev, filp);
1657 DRM_COPY_FROM_USER_IOCTL(stop, (drm_radeon_cp_stop_t __user *) data,
1660 if (!dev_priv->cp_running)
1663 /* Flush any pending CP commands. This ensures any outstanding
1664 * commands are exectuted by the engine before we turn it off.
1667 radeon_do_cp_flush(dev_priv);
1670 /* If we fail to make the engine go idle, we return an error
1671 * code so that the DRM ioctl wrapper can try again.
1674 ret = radeon_do_cp_idle(dev_priv);
1679 /* Finally, we can turn off the CP. If the engine isn't idle,
1680 * we will get some dropped triangles as they won't be fully
1681 * rendered before the CP is shut down.
1683 radeon_do_cp_stop(dev_priv);
1685 /* Reset the engine */
1686 radeon_do_engine_reset(dev);
1691 void radeon_do_release(drm_device_t * dev)
1693 drm_radeon_private_t *dev_priv = dev->dev_private;
1698 if (dev_priv->cp_running) {
1700 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1701 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1705 #if defined(__FreeBSD__) && __FreeBSD_version > 500000
1706 msleep(&ret, &dev->dev_lock, PZERO, "rdnrel",
1709 tsleep(&ret, PZERO, "rdnrel", 1);
1713 radeon_do_cp_stop(dev_priv);
1714 radeon_do_engine_reset(dev);
1717 /* Disable *all* interrupts */
1718 if (dev_priv->mmio) /* remove this after permanent addmaps */
1719 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1721 if (dev_priv->mmio) {/* remove all surfaces */
1722 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1723 RADEON_WRITE(RADEON_SURFACE0_INFO + 16*i, 0);
1724 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16*i, 0);
1725 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16*i, 0);
1729 /* Free memory heap structures */
1730 radeon_mem_takedown(&(dev_priv->gart_heap));
1731 radeon_mem_takedown(&(dev_priv->fb_heap));
1733 /* deallocate kernel resources */
1734 radeon_do_cleanup_cp(dev);
1738 /* Just reset the CP ring. Called as part of an X Server engine reset.
1740 int radeon_cp_reset(DRM_IOCTL_ARGS)
1743 drm_radeon_private_t *dev_priv = dev->dev_private;
1746 LOCK_TEST_WITH_RETURN(dev, filp);
1749 DRM_DEBUG("%s called before init done\n", __FUNCTION__);
1750 return DRM_ERR(EINVAL);
1753 radeon_do_cp_reset(dev_priv);
1755 /* The CP is no longer running after an engine reset */
1756 dev_priv->cp_running = 0;
1761 int radeon_cp_idle(DRM_IOCTL_ARGS)
1764 drm_radeon_private_t *dev_priv = dev->dev_private;
1767 LOCK_TEST_WITH_RETURN(dev, filp);
1769 return radeon_do_cp_idle(dev_priv);
1772 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1774 int radeon_cp_resume(DRM_IOCTL_ARGS)
1778 return radeon_do_resume_cp(dev);
1781 int radeon_engine_reset(DRM_IOCTL_ARGS)
1786 LOCK_TEST_WITH_RETURN(dev, filp);
1788 return radeon_do_engine_reset(dev);
1791 /* ================================================================
1795 /* KW: Deprecated to say the least:
1797 int radeon_fullscreen(DRM_IOCTL_ARGS)
1802 /* ================================================================
1803 * Freelist management
1806 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1807 * bufs until freelist code is used. Note this hides a problem with
1808 * the scratch register * (used to keep track of last buffer
1809 * completed) being written to before * the last buffer has actually
1810 * completed rendering.
1812 * KW: It's also a good way to find free buffers quickly.
1814 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1815 * sleep. However, bugs in older versions of radeon_accel.c mean that
1816 * we essentially have to do this, else old clients will break.
1818 * However, it does leave open a potential deadlock where all the
1819 * buffers are held by other clients, which can't release them because
1820 * they can't get the lock.
1823 drm_buf_t *radeon_freelist_get(drm_device_t * dev)
1825 drm_device_dma_t *dma = dev->dma;
1826 drm_radeon_private_t *dev_priv = dev->dev_private;
1827 drm_radeon_buf_priv_t *buf_priv;
1832 if (++dev_priv->last_buf >= dma->buf_count)
1833 dev_priv->last_buf = 0;
1835 start = dev_priv->last_buf;
1837 for (t = 0; t < dev_priv->usec_timeout; t++) {
1838 u32 done_age = GET_SCRATCH(1);
1839 DRM_DEBUG("done_age = %d\n", done_age);
1840 for (i = start; i < dma->buf_count; i++) {
1841 buf = dma->buflist[i];
1842 buf_priv = buf->dev_private;
1843 if (buf->filp == 0 || (buf->pending &&
1844 buf_priv->age <= done_age)) {
1845 dev_priv->stats.requested_bufs++;
1854 dev_priv->stats.freelist_loops++;
1858 DRM_DEBUG("returning NULL!\n");
1863 drm_buf_t *radeon_freelist_get(drm_device_t * dev)
1865 drm_device_dma_t *dma = dev->dma;
1866 drm_radeon_private_t *dev_priv = dev->dev_private;
1867 drm_radeon_buf_priv_t *buf_priv;
1871 u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1873 if (++dev_priv->last_buf >= dma->buf_count)
1874 dev_priv->last_buf = 0;
1876 start = dev_priv->last_buf;
1877 dev_priv->stats.freelist_loops++;
1879 for (t = 0; t < 2; t++) {
1880 for (i = start; i < dma->buf_count; i++) {
1881 buf = dma->buflist[i];
1882 buf_priv = buf->dev_private;
1883 if (buf->filp == 0 || (buf->pending &&
1884 buf_priv->age <= done_age)) {
1885 dev_priv->stats.requested_bufs++;
1897 void radeon_freelist_reset(drm_device_t * dev)
1899 drm_device_dma_t *dma = dev->dma;
1900 drm_radeon_private_t *dev_priv = dev->dev_private;
1903 dev_priv->last_buf = 0;
1904 for (i = 0; i < dma->buf_count; i++) {
1905 drm_buf_t *buf = dma->buflist[i];
1906 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1911 /* ================================================================
1912 * CP command submission
1915 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1917 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1919 u32 last_head = GET_RING_HEAD(dev_priv);
1921 for (i = 0; i < dev_priv->usec_timeout; i++) {
1922 u32 head = GET_RING_HEAD(dev_priv);
1924 ring->space = (head - ring->tail) * sizeof(u32);
1925 if (ring->space <= 0)
1926 ring->space += ring->size;
1927 if (ring->space > n)
1930 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1932 if (head != last_head)
1939 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1940 #if RADEON_FIFO_DEBUG
1941 radeon_status(dev_priv);
1942 DRM_ERROR("failed!\n");
1944 return DRM_ERR(EBUSY);
1947 static int radeon_cp_get_buffers(DRMFILE filp, drm_device_t * dev,
1953 for (i = d->granted_count; i < d->request_count; i++) {
1954 buf = radeon_freelist_get(dev);
1956 return DRM_ERR(EBUSY); /* NOTE: broken client */
1960 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1962 return DRM_ERR(EFAULT);
1963 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
1964 sizeof(buf->total)))
1965 return DRM_ERR(EFAULT);
1972 int radeon_cp_buffers(DRM_IOCTL_ARGS)
1975 drm_device_dma_t *dma = dev->dma;
1977 drm_dma_t __user *argp = (void __user *)data;
1980 LOCK_TEST_WITH_RETURN(dev, filp);
1982 DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d));
1984 /* Please don't send us buffers.
1986 if (d.send_count != 0) {
1987 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1988 DRM_CURRENTPID, d.send_count);
1989 return DRM_ERR(EINVAL);
1992 /* We'll send you buffers.
1994 if (d.request_count < 0 || d.request_count > dma->buf_count) {
1995 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1996 DRM_CURRENTPID, d.request_count, dma->buf_count);
1997 return DRM_ERR(EINVAL);
2000 d.granted_count = 0;
2002 if (d.request_count) {
2003 ret = radeon_cp_get_buffers(filp, dev, &d);
2006 DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d));
2011 /* Always create a map record for MMIO and FB memory, done from DRIVER_POSTINIT */
2012 int radeon_preinit(struct drm_device *dev, unsigned long flags)
2014 drm_radeon_private_t *dev_priv;
2017 dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
2018 if (dev_priv == NULL)
2019 return DRM_ERR(ENOMEM);
2021 memset(dev_priv, 0, sizeof(drm_radeon_private_t));
2022 dev->dev_private = (void *)dev_priv;
2023 dev_priv->flags = flags;
2025 switch (flags & CHIP_FAMILY_MASK) {
2030 dev_priv->flags |= CHIP_HAS_HIERZ;
2033 /* all other chips have no hierarchical z buffer */
2037 if (drm_device_is_agp(dev))
2038 dev_priv->flags |= CHIP_IS_AGP;
2040 DRM_DEBUG("%s card detected\n",
2041 ((dev_priv->flags & CHIP_IS_AGP) ? "AGP" : "PCI"));
2046 int radeon_presetup(struct drm_device *dev)
2049 drm_local_map_t *map;
2050 drm_radeon_private_t *dev_priv = dev->dev_private;
2052 ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
2053 drm_get_resource_len(dev, 2), _DRM_REGISTERS,
2054 _DRM_READ_ONLY, &dev_priv->mmio);
2058 ret = drm_addmap(dev, drm_get_resource_start(dev, 0),
2059 drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
2060 _DRM_WRITE_COMBINING, &map);
2067 int radeon_postcleanup(struct drm_device *dev)
2069 drm_radeon_private_t *dev_priv = dev->dev_private;
2072 drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
2074 dev->dev_private = NULL;