shared-core/radeon_cp.c

   1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*-
   2  *
   3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11  * and/or sell copies of the Software, and to permit persons to whom the
  12  * Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the next
  15  * paragraph) shall be included in all copies or substantial portions of the
  16  * Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  21  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  22  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  23  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  24  * DEALINGS IN THE SOFTWARE.
  25  *
  26  * Authors:
  27  *    Kevin E. Martin <martin@valinux.com>
  28  *    Gareth Hughes <gareth@valinux.com>
  29  */
  30
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "radeon_drm.h"
  34 #include "radeon_drv.h"
  35
  36 #define RADEON_FIFO_DEBUG       0
  37
  38 /* CP microcode (from ATI) */
  39 static u32 R200_cp_microcode[][2] = {
  40         {0x21007000, 0000000000},
  41         {0x20007000, 0000000000},
  42         {0x000000ab, 0x00000004},
  43         {0x000000af, 0x00000004},
  44         {0x66544a49, 0000000000},
  45         {0x49494174, 0000000000},
  46         {0x54517d83, 0000000000},
  47         {0x498d8b64, 0000000000},
  48         {0x49494949, 0000000000},
  49         {0x49da493c, 0000000000},
  50         {0x49989898, 0000000000},
  51         {0xd34949d5, 0000000000},
  52         {0x9dc90e11, 0000000000},
  53         {0xce9b9b9b, 0000000000},
  54         {0x000f0000, 0x00000016},
  55         {0x352e232c, 0000000000},
  56         {0x00000013, 0x00000004},
  57         {0x000f0000, 0x00000016},
  58         {0x352e272c, 0000000000},
  59         {0x000f0001, 0x00000016},
  60         {0x3239362f, 0000000000},
  61         {0x000077ef, 0x00000002},
  62         {0x00061000, 0x00000002},
  63         {0x00000020, 0x0000001a},
  64         {0x00004000, 0x0000001e},
  65         {0x00061000, 0x00000002},
  66         {0x00000020, 0x0000001a},
  67         {0x00004000, 0x0000001e},
  68         {0x00061000, 0x00000002},
  69         {0x00000020, 0x0000001a},
  70         {0x00004000, 0x0000001e},
  71         {0x00000016, 0x00000004},
  72         {0x0003802a, 0x00000002},
  73         {0x040067e0, 0x00000002},
  74         {0x00000016, 0x00000004},
  75         {0x000077e0, 0x00000002},
  76         {0x00065000, 0x00000002},
  77         {0x000037e1, 0x00000002},
  78         {0x040067e1, 0x00000006},
  79         {0x000077e0, 0x00000002},
  80         {0x000077e1, 0x00000002},
  81         {0x000077e1, 0x00000006},
  82         {0xffffffff, 0000000000},
  83         {0x10000000, 0000000000},
  84         {0x0003802a, 0x00000002},
  85         {0x040067e0, 0x00000006},
  86         {0x00007675, 0x00000002},
  87         {0x00007676, 0x00000002},
  88         {0x00007677, 0x00000002},
  89         {0x00007678, 0x00000006},
  90         {0x0003802b, 0x00000002},
  91         {0x04002676, 0x00000002},
  92         {0x00007677, 0x00000002},
  93         {0x00007678, 0x00000006},
  94         {0x0000002e, 0x00000018},
  95         {0x0000002e, 0x00000018},
  96         {0000000000, 0x00000006},
  97         {0x0000002f, 0x00000018},
  98         {0x0000002f, 0x00000018},
  99         {0000000000, 0x00000006},
 100         {0x01605000, 0x00000002},
 101         {0x00065000, 0x00000002},
 102         {0x00098000, 0x00000002},
 103         {0x00061000, 0x00000002},
 104         {0x64c0603d, 0x00000004},
 105         {0x00080000, 0x00000016},
 106         {0000000000, 0000000000},
 107         {0x0400251d, 0x00000002},
 108         {0x00007580, 0x00000002},
 109         {0x00067581, 0x00000002},
 110         {0x04002580, 0x00000002},
 111         {0x00067581, 0x00000002},
 112         {0x00000046, 0x00000004},
 113         {0x00005000, 0000000000},
 114         {0x00061000, 0x00000002},
 115         {0x0000750e, 0x00000002},
 116         {0x00019000, 0x00000002},
 117         {0x00011055, 0x00000014},
 118         {0x00000055, 0x00000012},
 119         {0x0400250f, 0x00000002},
 120         {0x0000504a, 0x00000004},
 121         {0x00007565, 0x00000002},
 122         {0x00007566, 0x00000002},
 123         {0x00000051, 0x00000004},
 124         {0x01e655b4, 0x00000002},
 125         {0x4401b0dc, 0x00000002},
 126         {0x01c110dc, 0x00000002},
 127         {0x2666705d, 0x00000018},
 128         {0x040c2565, 0x00000002},
 129         {0x0000005d, 0x00000018},
 130         {0x04002564, 0x00000002},
 131         {0x00007566, 0x00000002},
 132         {0x00000054, 0x00000004},
 133         {0x00401060, 0x00000008},
 134         {0x00101000, 0x00000002},
 135         {0x000d80ff, 0x00000002},
 136         {0x00800063, 0x00000008},
 137         {0x000f9000, 0x00000002},
 138         {0x000e00ff, 0x00000002},
 139         {0000000000, 0x00000006},
 140         {0x00000080, 0x00000018},
 141         {0x00000054, 0x00000004},
 142         {0x00007576, 0x00000002},
 143         {0x00065000, 0x00000002},
 144         {0x00009000, 0x00000002},
 145         {0x00041000, 0x00000002},
 146         {0x0c00350e, 0x00000002},
 147         {0x00049000, 0x00000002},
 148         {0x00051000, 0x00000002},
 149         {0x01e785f8, 0x00000002},
 150         {0x00200000, 0x00000002},
 151         {0x00600073, 0x0000000c},
 152         {0x00007563, 0x00000002},
 153         {0x006075f0, 0x00000021},
 154         {0x20007068, 0x00000004},
 155         {0x00005068, 0x00000004},
 156         {0x00007576, 0x00000002},
 157         {0x00007577, 0x00000002},
 158         {0x0000750e, 0x00000002},
 159         {0x0000750f, 0x00000002},
 160         {0x00a05000, 0x00000002},
 161         {0x00600076, 0x0000000c},
 162         {0x006075f0, 0x00000021},
 163         {0x000075f8, 0x00000002},
 164         {0x00000076, 0x00000004},
 165         {0x000a750e, 0x00000002},
 166         {0x0020750f, 0x00000002},
 167         {0x00600079, 0x00000004},
 168         {0x00007570, 0x00000002},
 169         {0x00007571, 0x00000002},
 170         {0x00007572, 0x00000006},
 171         {0x00005000, 0x00000002},
 172         {0x00a05000, 0x00000002},
 173         {0x00007568, 0x00000002},
 174         {0x00061000, 0x00000002},
 175         {0x00000084, 0x0000000c},
 176         {0x00058000, 0x00000002},
 177         {0x0c607562, 0x00000002},
 178         {0x00000086, 0x00000004},
 179         {0x00600085, 0x00000004},
 180         {0x400070dd, 0000000000},
 181         {0x000380dd, 0x00000002},
 182         {0x00000093, 0x0000001c},
 183         {0x00065095, 0x00000018},
 184         {0x040025bb, 0x00000002},
 185         {0x00061096, 0x00000018},
 186         {0x040075bc, 0000000000},
 187         {0x000075bb, 0x00000002},
 188         {0x000075bc, 0000000000},
 189         {0x00090000, 0x00000006},
 190         {0x00090000, 0x00000002},
 191         {0x000d8002, 0x00000006},
 192         {0x00005000, 0x00000002},
 193         {0x00007821, 0x00000002},
 194         {0x00007800, 0000000000},
 195         {0x00007821, 0x00000002},
 196         {0x00007800, 0000000000},
 197         {0x01665000, 0x00000002},
 198         {0x000a0000, 0x00000002},
 199         {0x000671cc, 0x00000002},
 200         {0x0286f1cd, 0x00000002},
 201         {0x000000a3, 0x00000010},
 202         {0x21007000, 0000000000},
 203         {0x000000aa, 0x0000001c},
 204         {0x00065000, 0x00000002},
 205         {0x000a0000, 0x00000002},
 206         {0x00061000, 0x00000002},
 207         {0x000b0000, 0x00000002},
 208         {0x38067000, 0x00000002},
 209         {0x000a00a6, 0x00000004},
 210         {0x20007000, 0000000000},
 211         {0x01200000, 0x00000002},
 212         {0x20077000, 0x00000002},
 213         {0x01200000, 0x00000002},
 214         {0x20007000, 0000000000},
 215         {0x00061000, 0x00000002},
 216         {0x0120751b, 0x00000002},
 217         {0x8040750a, 0x00000002},
 218         {0x8040750b, 0x00000002},
 219         {0x00110000, 0x00000002},
 220         {0x000380dd, 0x00000002},
 221         {0x000000bd, 0x0000001c},
 222         {0x00061096, 0x00000018},
 223         {0x844075bd, 0x00000002},
 224         {0x00061095, 0x00000018},
 225         {0x840075bb, 0x00000002},
 226         {0x00061096, 0x00000018},
 227         {0x844075bc, 0x00000002},
 228         {0x000000c0, 0x00000004},
 229         {0x804075bd, 0x00000002},
 230         {0x800075bb, 0x00000002},
 231         {0x804075bc, 0x00000002},
 232         {0x00108000, 0x00000002},
 233         {0x01400000, 0x00000002},
 234         {0x006000c4, 0x0000000c},
 235         {0x20c07000, 0x00000020},
 236         {0x000000c6, 0x00000012},
 237         {0x00800000, 0x00000006},
 238         {0x0080751d, 0x00000006},
 239         {0x000025bb, 0x00000002},
 240         {0x000040c0, 0x00000004},
 241         {0x0000775c, 0x00000002},
 242         {0x00a05000, 0x00000002},
 243         {0x00661000, 0x00000002},
 244         {0x0460275d, 0x00000020},
 245         {0x00004000, 0000000000},
 246         {0x00007999, 0x00000002},
 247         {0x00a05000, 0x00000002},
 248         {0x00661000, 0x00000002},
 249         {0x0460299b, 0x00000020},
 250         {0x00004000, 0000000000},
 251         {0x01e00830, 0x00000002},
 252         {0x21007000, 0000000000},
 253         {0x00005000, 0x00000002},
 254         {0x00038042, 0x00000002},
 255         {0x040025e0, 0x00000002},
 256         {0x000075e1, 0000000000},
 257         {0x00000001, 0000000000},
 258         {0x000380d9, 0x00000002},
 259         {0x04007394, 0000000000},
 260         {0000000000, 0000000000},
 261         {0000000000, 0000000000},
 262         {0000000000, 0000000000},
 263         {0000000000, 0000000000},
 264         {0000000000, 0000000000},
 265         {0000000000, 0000000000},
 266         {0000000000, 0000000000},
 267         {0000000000, 0000000000},
 268         {0000000000, 0000000000},
 269         {0000000000, 0000000000},
 270         {0000000000, 0000000000},
 271         {0000000000, 0000000000},
 272         {0000000000, 0000000000},
 273         {0000000000, 0000000000},
 274         {0000000000, 0000000000},
 275         {0000000000, 0000000000},
 276         {0000000000, 0000000000},
 277         {0000000000, 0000000000},
 278         {0000000000, 0000000000},
 279         {0000000000, 0000000000},
 280         {0000000000, 0000000000},
 281         {0000000000, 0000000000},
 282         {0000000000, 0000000000},
 283         {0000000000, 0000000000},
 284         {0000000000, 0000000000},
 285         {0000000000, 0000000000},
 286         {0000000000, 0000000000},
 287         {0000000000, 0000000000},
 288         {0000000000, 0000000000},
 289         {0000000000, 0000000000},
 290         {0000000000, 0000000000},
 291         {0000000000, 0000000000},
 292         {0000000000, 0000000000},
 293         {0000000000, 0000000000},
 294         {0000000000, 0000000000},
 295         {0000000000, 0000000000},
 296 };
 297
 298 static u32 radeon_cp_microcode[][2] = {
 299         {0x21007000, 0000000000},
 300         {0x20007000, 0000000000},
 301         {0x000000b4, 0x00000004},
 302         {0x000000b8, 0x00000004},
 303         {0x6f5b4d4c, 0000000000},
 304         {0x4c4c427f, 0000000000},
 305         {0x5b568a92, 0000000000},
 306         {0x4ca09c6d, 0000000000},
 307         {0xad4c4c4c, 0000000000},
 308         {0x4ce1af3d, 0000000000},
 309         {0xd8afafaf, 0000000000},
 310         {0xd64c4cdc, 0000000000},
 311         {0x4cd10d10, 0000000000},
 312         {0x000f0000, 0x00000016},
 313         {0x362f242d, 0000000000},
 314         {0x00000012, 0x00000004},
 315         {0x000f0000, 0x00000016},
 316         {0x362f282d, 0000000000},
 317         {0x000380e7, 0x00000002},
 318         {0x04002c97, 0x00000002},
 319         {0x000f0001, 0x00000016},
 320         {0x333a3730, 0000000000},
 321         {0x000077ef, 0x00000002},
 322         {0x00061000, 0x00000002},
 323         {0x00000021, 0x0000001a},
 324         {0x00004000, 0x0000001e},
 325         {0x00061000, 0x00000002},
 326         {0x00000021, 0x0000001a},
 327         {0x00004000, 0x0000001e},
 328         {0x00061000, 0x00000002},
 329         {0x00000021, 0x0000001a},
 330         {0x00004000, 0x0000001e},
 331         {0x00000017, 0x00000004},
 332         {0x0003802b, 0x00000002},
 333         {0x040067e0, 0x00000002},
 334         {0x00000017, 0x00000004},
 335         {0x000077e0, 0x00000002},
 336         {0x00065000, 0x00000002},
 337         {0x000037e1, 0x00000002},
 338         {0x040067e1, 0x00000006},
 339         {0x000077e0, 0x00000002},
 340         {0x000077e1, 0x00000002},
 341         {0x000077e1, 0x00000006},
 342         {0xffffffff, 0000000000},
 343         {0x10000000, 0000000000},
 344         {0x0003802b, 0x00000002},
 345         {0x040067e0, 0x00000006},
 346         {0x00007675, 0x00000002},
 347         {0x00007676, 0x00000002},
 348         {0x00007677, 0x00000002},
 349         {0x00007678, 0x00000006},
 350         {0x0003802c, 0x00000002},
 351         {0x04002676, 0x00000002},
 352         {0x00007677, 0x00000002},
 353         {0x00007678, 0x00000006},
 354         {0x0000002f, 0x00000018},
 355         {0x0000002f, 0x00000018},
 356         {0000000000, 0x00000006},
 357         {0x00000030, 0x00000018},
 358         {0x00000030, 0x00000018},
 359         {0000000000, 0x00000006},
 360         {0x01605000, 0x00000002},
 361         {0x00065000, 0x00000002},
 362         {0x00098000, 0x00000002},
 363         {0x00061000, 0x00000002},
 364         {0x64c0603e, 0x00000004},
 365         {0x000380e6, 0x00000002},
 366         {0x040025c5, 0x00000002},
 367         {0x00080000, 0x00000016},
 368         {0000000000, 0000000000},
 369         {0x0400251d, 0x00000002},
 370         {0x00007580, 0x00000002},
 371         {0x00067581, 0x00000002},
 372         {0x04002580, 0x00000002},
 373         {0x00067581, 0x00000002},
 374         {0x00000049, 0x00000004},
 375         {0x00005000, 0000000000},
 376         {0x000380e6, 0x00000002},
 377         {0x040025c5, 0x00000002},
 378         {0x00061000, 0x00000002},
 379         {0x0000750e, 0x00000002},
 380         {0x00019000, 0x00000002},
 381         {0x00011055, 0x00000014},
 382         {0x00000055, 0x00000012},
 383         {0x0400250f, 0x00000002},
 384         {0x0000504f, 0x00000004},
 385         {0x000380e6, 0x00000002},
 386         {0x040025c5, 0x00000002},
 387         {0x00007565, 0x00000002},
 388         {0x00007566, 0x00000002},
 389         {0x00000058, 0x00000004},
 390         {0x000380e6, 0x00000002},
 391         {0x040025c5, 0x00000002},
 392         {0x01e655b4, 0x00000002},
 393         {0x4401b0e4, 0x00000002},
 394         {0x01c110e4, 0x00000002},
 395         {0x26667066, 0x00000018},
 396         {0x040c2565, 0x00000002},
 397         {0x00000066, 0x00000018},
 398         {0x04002564, 0x00000002},
 399         {0x00007566, 0x00000002},
 400         {0x0000005d, 0x00000004},
 401         {0x00401069, 0x00000008},
 402         {0x00101000, 0x00000002},
 403         {0x000d80ff, 0x00000002},
 404         {0x0080006c, 0x00000008},
 405         {0x000f9000, 0x00000002},
 406         {0x000e00ff, 0x00000002},
 407         {0000000000, 0x00000006},
 408         {0x0000008f, 0x00000018},
 409         {0x0000005b, 0x00000004},
 410         {0x000380e6, 0x00000002},
 411         {0x040025c5, 0x00000002},
 412         {0x00007576, 0x00000002},
 413         {0x00065000, 0x00000002},
 414         {0x00009000, 0x00000002},
 415         {0x00041000, 0x00000002},
 416         {0x0c00350e, 0x00000002},
 417         {0x00049000, 0x00000002},
 418         {0x00051000, 0x00000002},
 419         {0x01e785f8, 0x00000002},
 420         {0x00200000, 0x00000002},
 421         {0x0060007e, 0x0000000c},
 422         {0x00007563, 0x00000002},
 423         {0x006075f0, 0x00000021},
 424         {0x20007073, 0x00000004},
 425         {0x00005073, 0x00000004},
 426         {0x000380e6, 0x00000002},
 427         {0x040025c5, 0x00000002},
 428         {0x00007576, 0x00000002},
 429         {0x00007577, 0x00000002},
 430         {0x0000750e, 0x00000002},
 431         {0x0000750f, 0x00000002},
 432         {0x00a05000, 0x00000002},
 433         {0x00600083, 0x0000000c},
 434         {0x006075f0, 0x00000021},
 435         {0x000075f8, 0x00000002},
 436         {0x00000083, 0x00000004},
 437         {0x000a750e, 0x00000002},
 438         {0x000380e6, 0x00000002},
 439         {0x040025c5, 0x00000002},
 440         {0x0020750f, 0x00000002},
 441         {0x00600086, 0x00000004},
 442         {0x00007570, 0x00000002},
 443         {0x00007571, 0x00000002},
 444         {0x00007572, 0x00000006},
 445         {0x000380e6, 0x00000002},
 446         {0x040025c5, 0x00000002},
 447         {0x00005000, 0x00000002},
 448         {0x00a05000, 0x00000002},
 449         {0x00007568, 0x00000002},
 450         {0x00061000, 0x00000002},
 451         {0x00000095, 0x0000000c},
 452         {0x00058000, 0x00000002},
 453         {0x0c607562, 0x00000002},
 454         {0x00000097, 0x00000004},
 455         {0x000380e6, 0x00000002},
 456         {0x040025c5, 0x00000002},
 457         {0x00600096, 0x00000004},
 458         {0x400070e5, 0000000000},
 459         {0x000380e6, 0x00000002},
 460         {0x040025c5, 0x00000002},
 461         {0x000380e5, 0x00000002},
 462         {0x000000a8, 0x0000001c},
 463         {0x000650aa, 0x00000018},
 464         {0x040025bb, 0x00000002},
 465         {0x000610ab, 0x00000018},
 466         {0x040075bc, 0000000000},
 467         {0x000075bb, 0x00000002},
 468         {0x000075bc, 0000000000},
 469         {0x00090000, 0x00000006},
 470         {0x00090000, 0x00000002},
 471         {0x000d8002, 0x00000006},
 472         {0x00007832, 0x00000002},
 473         {0x00005000, 0x00000002},
 474         {0x000380e7, 0x00000002},
 475         {0x04002c97, 0x00000002},
 476         {0x00007820, 0x00000002},
 477         {0x00007821, 0x00000002},
 478         {0x00007800, 0000000000},
 479         {0x01200000, 0x00000002},
 480         {0x20077000, 0x00000002},
 481         {0x01200000, 0x00000002},
 482         {0x20007000, 0x00000002},
 483         {0x00061000, 0x00000002},
 484         {0x0120751b, 0x00000002},
 485         {0x8040750a, 0x00000002},
 486         {0x8040750b, 0x00000002},
 487         {0x00110000, 0x00000002},
 488         {0x000380e5, 0x00000002},
 489         {0x000000c6, 0x0000001c},
 490         {0x000610ab, 0x00000018},
 491         {0x844075bd, 0x00000002},
 492         {0x000610aa, 0x00000018},
 493         {0x840075bb, 0x00000002},
 494         {0x000610ab, 0x00000018},
 495         {0x844075bc, 0x00000002},
 496         {0x000000c9, 0x00000004},
 497         {0x804075bd, 0x00000002},
 498         {0x800075bb, 0x00000002},
 499         {0x804075bc, 0x00000002},
 500         {0x00108000, 0x00000002},
 501         {0x01400000, 0x00000002},
 502         {0x006000cd, 0x0000000c},
 503         {0x20c07000, 0x00000020},
 504         {0x000000cf, 0x00000012},
 505         {0x00800000, 0x00000006},
 506         {0x0080751d, 0x00000006},
 507         {0000000000, 0000000000},
 508         {0x0000775c, 0x00000002},
 509         {0x00a05000, 0x00000002},
 510         {0x00661000, 0x00000002},
 511         {0x0460275d, 0x00000020},
 512         {0x00004000, 0000000000},
 513         {0x01e00830, 0x00000002},
 514         {0x21007000, 0000000000},
 515         {0x6464614d, 0000000000},
 516         {0x69687420, 0000000000},
 517         {0x00000073, 0000000000},
 518         {0000000000, 0000000000},
 519         {0x00005000, 0x00000002},
 520         {0x000380d0, 0x00000002},
 521         {0x040025e0, 0x00000002},
 522         {0x000075e1, 0000000000},
 523         {0x00000001, 0000000000},
 524         {0x000380e0, 0x00000002},
 525         {0x04002394, 0x00000002},
 526         {0x00005000, 0000000000},
 527         {0000000000, 0000000000},
 528         {0000000000, 0000000000},
 529         {0x00000008, 0000000000},
 530         {0x00000004, 0000000000},
 531         {0000000000, 0000000000},
 532         {0000000000, 0000000000},
 533         {0000000000, 0000000000},
 534         {0000000000, 0000000000},
 535         {0000000000, 0000000000},
 536         {0000000000, 0000000000},
 537         {0000000000, 0000000000},
 538         {0000000000, 0000000000},
 539         {0000000000, 0000000000},
 540         {0000000000, 0000000000},
 541         {0000000000, 0000000000},
 542         {0000000000, 0000000000},
 543         {0000000000, 0000000000},
 544         {0000000000, 0000000000},
 545         {0000000000, 0000000000},
 546         {0000000000, 0000000000},
 547         {0000000000, 0000000000},
 548         {0000000000, 0000000000},
 549         {0000000000, 0000000000},
 550         {0000000000, 0000000000},
 551         {0000000000, 0000000000},
 552         {0000000000, 0000000000},
 553         {0000000000, 0000000000},
 554         {0000000000, 0000000000},
 555 };
 556
 557 static u32 R300_cp_microcode[][2] = {
 558         { 0x4200e000, 0000000000 },
 559         { 0x4000e000, 0000000000 },
 560         { 0x000000af, 0x00000008 },
 561         { 0x000000b3, 0x00000008 },
 562         { 0x6c5a504f, 0000000000 },
 563         { 0x4f4f497a, 0000000000 },
 564         { 0x5a578288, 0000000000 },
 565         { 0x4f91906a, 0000000000 },
 566         { 0x4f4f4f4f, 0000000000 },
 567         { 0x4fe24f44, 0000000000 },
 568         { 0x4f9c9c9c, 0000000000 },
 569         { 0xdc4f4fde, 0000000000 },
 570         { 0xa1cd4f4f, 0000000000 },
 571         { 0xd29d9d9d, 0000000000 },
 572         { 0x4f0f9fd7, 0000000000 },
 573         { 0x000ca000, 0x00000004 },
 574         { 0x000d0012, 0x00000038 },
 575         { 0x0000e8b4, 0x00000004 },
 576         { 0x000d0014, 0x00000038 },
 577         { 0x0000e8b6, 0x00000004 },
 578         { 0x000d0016, 0x00000038 },
 579         { 0x0000e854, 0x00000004 },
 580         { 0x000d0018, 0x00000038 },
 581         { 0x0000e855, 0x00000004 },
 582         { 0x000d001a, 0x00000038 },
 583         { 0x0000e856, 0x00000004 },
 584         { 0x000d001c, 0x00000038 },
 585         { 0x0000e857, 0x00000004 },
 586         { 0x000d001e, 0x00000038 },
 587         { 0x0000e824, 0x00000004 },
 588         { 0x000d0020, 0x00000038 },
 589         { 0x0000e825, 0x00000004 },
 590         { 0x000d0022, 0x00000038 },
 591         { 0x0000e830, 0x00000004 },
 592         { 0x000d0024, 0x00000038 },
 593         { 0x0000f0c0, 0x00000004 },
 594         { 0x000d0026, 0x00000038 },
 595         { 0x0000f0c1, 0x00000004 },
 596         { 0x000d0028, 0x00000038 },
 597         { 0x0000f041, 0x00000004 },
 598         { 0x000d002a, 0x00000038 },
 599         { 0x0000f184, 0x00000004 },
 600         { 0x000d002c, 0x00000038 },
 601         { 0x0000f185, 0x00000004 },
 602         { 0x000d002e, 0x00000038 },
 603         { 0x0000f186, 0x00000004 },
 604         { 0x000d0030, 0x00000038 },
 605         { 0x0000f187, 0x00000004 },
 606         { 0x000d0032, 0x00000038 },
 607         { 0x0000f180, 0x00000004 },
 608         { 0x000d0034, 0x00000038 },
 609         { 0x0000f393, 0x00000004 },
 610         { 0x000d0036, 0x00000038 },
 611         { 0x0000f38a, 0x00000004 },
 612         { 0x000d0038, 0x00000038 },
 613         { 0x0000f38e, 0x00000004 },
 614         { 0x0000e821, 0x00000004 },
 615         { 0x0140a000, 0x00000004 },
 616         { 0x00000043, 0x00000018 },
 617         { 0x00cce800, 0x00000004 },
 618         { 0x001b0001, 0x00000004 },
 619         { 0x08004800, 0x00000004 },
 620         { 0x001b0001, 0x00000004 },
 621         { 0x08004800, 0x00000004 },
 622         { 0x001b0001, 0x00000004 },
 623         { 0x08004800, 0x00000004 },
 624         { 0x0000003a, 0x00000008 },
 625         { 0x0000a000, 0000000000 },
 626         { 0x02c0a000, 0x00000004 },
 627         { 0x000ca000, 0x00000004 },
 628         { 0x00130000, 0x00000004 },
 629         { 0x000c2000, 0x00000004 },
 630         { 0xc980c045, 0x00000008 },
 631         { 0x2000451d, 0x00000004 },
 632         { 0x0000e580, 0x00000004 },
 633         { 0x000ce581, 0x00000004 },
 634         { 0x08004580, 0x00000004 },
 635         { 0x000ce581, 0x00000004 },
 636         { 0x0000004c, 0x00000008 },
 637         { 0x0000a000, 0000000000 },
 638         { 0x000c2000, 0x00000004 },
 639         { 0x0000e50e, 0x00000004 },
 640         { 0x00032000, 0x00000004 },
 641         { 0x00022056, 0x00000028 },
 642         { 0x00000056, 0x00000024 },
 643         { 0x0800450f, 0x00000004 },
 644         { 0x0000a050, 0x00000008 },
 645         { 0x0000e565, 0x00000004 },
 646         { 0x0000e566, 0x00000004 },
 647         { 0x00000057, 0x00000008 },
 648         { 0x03cca5b4, 0x00000004 },
 649         { 0x05432000, 0x00000004 },
 650         { 0x00022000, 0x00000004 },
 651         { 0x4ccce063, 0x00000030 },
 652         { 0x08274565, 0x00000004 },
 653         { 0x00000063, 0x00000030 },
 654         { 0x08004564, 0x00000004 },
 655         { 0x0000e566, 0x00000004 },
 656         { 0x0000005a, 0x00000008 },
 657         { 0x00802066, 0x00000010 },
 658         { 0x00202000, 0x00000004 },
 659         { 0x001b00ff, 0x00000004 },
 660         { 0x01000069, 0x00000010 },
 661         { 0x001f2000, 0x00000004 },
 662         { 0x001c00ff, 0x00000004 },
 663         { 0000000000, 0x0000000c },
 664         { 0x00000085, 0x00000030 },
 665         { 0x0000005a, 0x00000008 },
 666         { 0x0000e576, 0x00000004 },
 667         { 0x000ca000, 0x00000004 },
 668         { 0x00012000, 0x00000004 },
 669         { 0x00082000, 0x00000004 },
 670         { 0x1800650e, 0x00000004 },
 671         { 0x00092000, 0x00000004 },
 672         { 0x000a2000, 0x00000004 },
 673         { 0x000f0000, 0x00000004 },
 674         { 0x00400000, 0x00000004 },
 675         { 0x00000079, 0x00000018 },
 676         { 0x0000e563, 0x00000004 },
 677         { 0x00c0e5f9, 0x000000c2 },
 678         { 0x0000006e, 0x00000008 },
 679         { 0x0000a06e, 0x00000008 },
 680         { 0x0000e576, 0x00000004 },
 681         { 0x0000e577, 0x00000004 },
 682         { 0x0000e50e, 0x00000004 },
 683         { 0x0000e50f, 0x00000004 },
 684         { 0x0140a000, 0x00000004 },
 685         { 0x0000007c, 0x00000018 },
 686         { 0x00c0e5f9, 0x000000c2 },
 687         { 0x0000007c, 0x00000008 },
 688         { 0x0014e50e, 0x00000004 },
 689         { 0x0040e50f, 0x00000004 },
 690         { 0x00c0007f, 0x00000008 },
 691         { 0x0000e570, 0x00000004 },
 692         { 0x0000e571, 0x00000004 },
 693         { 0x0000e572, 0x0000000c },
 694         { 0x0000a000, 0x00000004 },
 695         { 0x0140a000, 0x00000004 },
 696         { 0x0000e568, 0x00000004 },
 697         { 0x000c2000, 0x00000004 },
 698         { 0x00000089, 0x00000018 },
 699         { 0x000b0000, 0x00000004 },
 700         { 0x18c0e562, 0x00000004 },
 701         { 0x0000008b, 0x00000008 },
 702         { 0x00c0008a, 0x00000008 },
 703         { 0x000700e4, 0x00000004 },
 704         { 0x00000097, 0x00000038 },
 705         { 0x000ca099, 0x00000030 },
 706         { 0x080045bb, 0x00000004 },
 707         { 0x000c209a, 0x00000030 },
 708         { 0x0800e5bc, 0000000000 },
 709         { 0x0000e5bb, 0x00000004 },
 710         { 0x0000e5bc, 0000000000 },
 711         { 0x00120000, 0x0000000c },
 712         { 0x00120000, 0x00000004 },
 713         { 0x001b0002, 0x0000000c },
 714         { 0x0000a000, 0x00000004 },
 715         { 0x0000e821, 0x00000004 },
 716         { 0x0000e800, 0000000000 },
 717         { 0x0000e821, 0x00000004 },
 718         { 0x0000e82e, 0000000000 },
 719         { 0x02cca000, 0x00000004 },
 720         { 0x00140000, 0x00000004 },
 721         { 0x000ce1cc, 0x00000004 },
 722         { 0x050de1cd, 0x00000004 },
 723         { 0x000000a7, 0x00000020 },
 724         { 0x4200e000, 0000000000 },
 725         { 0x000000ae, 0x00000038 },
 726         { 0x000ca000, 0x00000004 },
 727         { 0x00140000, 0x00000004 },
 728         { 0x000c2000, 0x00000004 },
 729         { 0x00160000, 0x00000004 },
 730         { 0x700ce000, 0x00000004 },
 731         { 0x001400aa, 0x00000008 },
 732         { 0x4000e000, 0000000000 },
 733         { 0x02400000, 0x00000004 },
 734         { 0x400ee000, 0x00000004 },
 735         { 0x02400000, 0x00000004 },
 736         { 0x4000e000, 0000000000 },
 737         { 0x000c2000, 0x00000004 },
 738         { 0x0240e51b, 0x00000004 },
 739         { 0x0080e50a, 0x00000005 },
 740         { 0x0080e50b, 0x00000005 },
 741         { 0x00220000, 0x00000004 },
 742         { 0x000700e4, 0x00000004 },
 743         { 0x000000c1, 0x00000038 },
 744         { 0x000c209a, 0x00000030 },
 745         { 0x0880e5bd, 0x00000005 },
 746         { 0x000c2099, 0x00000030 },
 747         { 0x0800e5bb, 0x00000005 },
 748         { 0x000c209a, 0x00000030 },
 749         { 0x0880e5bc, 0x00000005 },
 750         { 0x000000c4, 0x00000008 },
 751         { 0x0080e5bd, 0x00000005 },
 752         { 0x0000e5bb, 0x00000005 },
 753         { 0x0080e5bc, 0x00000005 },
 754         { 0x00210000, 0x00000004 },
 755         { 0x02800000, 0x00000004 },
 756         { 0x00c000c8, 0x00000018 },
 757         { 0x4180e000, 0x00000040 },
 758         { 0x000000ca, 0x00000024 },
 759         { 0x01000000, 0x0000000c },
 760         { 0x0100e51d, 0x0000000c },
 761         { 0x000045bb, 0x00000004 },
 762         { 0x000080c4, 0x00000008 },
 763         { 0x0000f3ce, 0x00000004 },
 764         { 0x0140a000, 0x00000004 },
 765         { 0x00cc2000, 0x00000004 },
 766         { 0x08c053cf, 0x00000040 },
 767         { 0x00008000, 0000000000 },
 768         { 0x0000f3d2, 0x00000004 },
 769         { 0x0140a000, 0x00000004 },
 770         { 0x00cc2000, 0x00000004 },
 771         { 0x08c053d3, 0x00000040 },
 772         { 0x00008000, 0000000000 },
 773         { 0x0000f39d, 0x00000004 },
 774         { 0x0140a000, 0x00000004 },
 775         { 0x00cc2000, 0x00000004 },
 776         { 0x08c0539e, 0x00000040 },
 777         { 0x00008000, 0000000000 },
 778         { 0x03c00830, 0x00000004 },
 779         { 0x4200e000, 0000000000 },
 780         { 0x0000a000, 0x00000004 },
 781         { 0x200045e0, 0x00000004 },
 782         { 0x0000e5e1, 0000000000 },
 783         { 0x00000001, 0000000000 },
 784         { 0x000700e1, 0x00000004 },
 785         { 0x0800e394, 0000000000 },
 786         { 0000000000, 0000000000 },
 787         { 0000000000, 0000000000 },
 788         { 0000000000, 0000000000 },
 789         { 0000000000, 0000000000 },
 790         { 0000000000, 0000000000 },
 791         { 0000000000, 0000000000 },
 792         { 0000000000, 0000000000 },
 793         { 0000000000, 0000000000 },
 794         { 0000000000, 0000000000 },
 795         { 0000000000, 0000000000 },
 796         { 0000000000, 0000000000 },
 797         { 0000000000, 0000000000 },
 798         { 0000000000, 0000000000 },
 799         { 0000000000, 0000000000 },
 800         { 0000000000, 0000000000 },
 801         { 0000000000, 0000000000 },
 802         { 0000000000, 0000000000 },
 803         { 0000000000, 0000000000 },
 804         { 0000000000, 0000000000 },
 805         { 0000000000, 0000000000 },
 806         { 0000000000, 0000000000 },
 807         { 0000000000, 0000000000 },
 808         { 0000000000, 0000000000 },
 809         { 0000000000, 0000000000 },
 810         { 0000000000, 0000000000 },
 811         { 0000000000, 0000000000 },
 812         { 0000000000, 0000000000 },
 813         { 0000000000, 0000000000 },
 814 };
 815
 816 int RADEON_READ_PLL(drm_device_t * dev, int addr)
 817 {
 818         drm_radeon_private_t *dev_priv = dev->dev_private;
 819
 820         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
 821         return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 822 }
 823
 824 #if RADEON_FIFO_DEBUG
 825 static void radeon_status(drm_radeon_private_t * dev_priv)
 826 {
 827         printk("%s:\n", __FUNCTION__);
 828         printk("RBBM_STATUS = 0x%08x\n",
 829                (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
 830         printk("CP_RB_RTPR = 0x%08x\n",
 831                (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
 832         printk("CP_RB_WTPR = 0x%08x\n",
 833                (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
 834         printk("AIC_CNTL = 0x%08x\n",
 835                (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
 836         printk("AIC_STAT = 0x%08x\n",
 837                (unsigned int)RADEON_READ(RADEON_AIC_STAT));
 838         printk("AIC_PT_BASE = 0x%08x\n",
 839                (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
 840         printk("TLB_ADDR = 0x%08x\n",
 841                (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
 842         printk("TLB_DATA = 0x%08x\n",
 843                (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
 844 }
 845 #endif
 846
 847 /* ================================================================
 848  * Engine, FIFO control
 849  */
 850
 851 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
 852 {
 853         u32 tmp;
 854         int i;
 855
 856         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 857
 858         tmp = RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT);
 859         tmp |= RADEON_RB2D_DC_FLUSH_ALL;
 860         RADEON_WRITE(RADEON_RB2D_DSTCACHE_CTLSTAT, tmp);
 861
 862         for (i = 0; i < dev_priv->usec_timeout; i++) {
 863                 if (!(RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT)
 864                       & RADEON_RB2D_DC_BUSY)) {
 865                         return 0;
 866                 }
 867                 DRM_UDELAY(1);
 868         }
 869
 870 #if RADEON_FIFO_DEBUG
 871         DRM_ERROR("failed!\n");
 872         radeon_status(dev_priv);
 873 #endif
 874         return DRM_ERR(EBUSY);
 875 }
 876
 877 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
 878 {
 879         int i;
 880
 881         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 882
 883         for (i = 0; i < dev_priv->usec_timeout; i++) {
 884                 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
 885                              & RADEON_RBBM_FIFOCNT_MASK);
 886                 if (slots >= entries)
 887                         return 0;
 888                 DRM_UDELAY(1);
 889         }
 890
 891 #if RADEON_FIFO_DEBUG
 892         DRM_ERROR("failed!\n");
 893         radeon_status(dev_priv);
 894 #endif
 895         return DRM_ERR(EBUSY);
 896 }
 897
 898 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
 899 {
 900         int i, ret;
 901
 902         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 903
 904         ret = radeon_do_wait_for_fifo(dev_priv, 64);
 905         if (ret)
 906                 return ret;
 907
 908         for (i = 0; i < dev_priv->usec_timeout; i++) {
 909                 if (!(RADEON_READ(RADEON_RBBM_STATUS)
 910                       & RADEON_RBBM_ACTIVE)) {
 911                         radeon_do_pixcache_flush(dev_priv);
 912                         return 0;
 913                 }
 914                 DRM_UDELAY(1);
 915         }
 916
 917 #if RADEON_FIFO_DEBUG
 918         DRM_ERROR("failed!\n");
 919         radeon_status(dev_priv);
 920 #endif
 921         return DRM_ERR(EBUSY);
 922 }
 923
 924 /* ================================================================
 925  * CP control, initialization
 926  */
 927
 928 /* Load the microcode for the CP */
 929 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
 930 {
 931         int i;
 932         DRM_DEBUG("\n");
 933
 934         radeon_do_wait_for_idle(dev_priv);
 935
 936         RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
 937
 938         if (dev_priv->microcode_version==UCODE_R200) {
 939                 DRM_INFO("Loading R200 Microcode\n");
 940                 for (i = 0; i < 256; i++) {
 941                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 942                                      R200_cp_microcode[i][1]);
 943                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 944                                      R200_cp_microcode[i][0]);
 945                 }
 946         } else if (dev_priv->microcode_version==UCODE_R300) {
 947                 DRM_INFO("Loading R300 Microcode\n");
 948                 for ( i = 0 ; i < 256 ; i++ ) {
 949                         RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
 950                                       R300_cp_microcode[i][1] );
 951                         RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
 952                                       R300_cp_microcode[i][0] );
 953                 }
 954         } else {
 955                 for (i = 0; i < 256; i++) {
 956                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 957                                      radeon_cp_microcode[i][1]);
 958                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 959                                      radeon_cp_microcode[i][0]);
 960                 }
 961         }
 962 }
 963
 964 /* Flush any pending commands to the CP.  This should only be used just
 965  * prior to a wait for idle, as it informs the engine that the command
 966  * stream is ending.
 967  */
 968 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
 969 {
 970         DRM_DEBUG("\n");
 971 #if 0
 972         u32 tmp;
 973
 974         tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
 975         RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
 976 #endif
 977 }
 978
 979 /* Wait for the CP to go idle.
 980  */
 981 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
 982 {
 983         RING_LOCALS;
 984         DRM_DEBUG("\n");
 985
 986         BEGIN_RING(6);
 987
 988         RADEON_PURGE_CACHE();
 989         RADEON_PURGE_ZCACHE();
 990         RADEON_WAIT_UNTIL_IDLE();
 991
 992         ADVANCE_RING();
 993         COMMIT_RING();
 994
 995         return radeon_do_wait_for_idle(dev_priv);
 996 }
 997
 998 /* Start the Command Processor.
 999  */
1000 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
1001 {
1002         RING_LOCALS;
1003         DRM_DEBUG("\n");
1004
1005         radeon_do_wait_for_idle(dev_priv);
1006
1007         RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
1008
1009         dev_priv->cp_running = 1;
1010
1011         BEGIN_RING(6);
1012
1013         RADEON_PURGE_CACHE();
1014         RADEON_PURGE_ZCACHE();
1015         RADEON_WAIT_UNTIL_IDLE();
1016
1017         ADVANCE_RING();
1018         COMMIT_RING();
1019 }
1020
1021 /* Reset the Command Processor.  This will not flush any pending
1022  * commands, so you must wait for the CP command stream to complete
1023  * before calling this routine.
1024  */
1025 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
1026 {
1027         u32 cur_read_ptr;
1028         DRM_DEBUG("\n");
1029
1030         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
1031         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
1032         SET_RING_HEAD(dev_priv, cur_read_ptr);
1033         dev_priv->ring.tail = cur_read_ptr;
1034 }
1035
1036 /* Stop the Command Processor.  This will not flush any pending
1037  * commands, so you must flush the command stream and wait for the CP
1038  * to go idle before calling this routine.
1039  */
1040 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
1041 {
1042         DRM_DEBUG("\n");
1043
1044         RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
1045
1046         dev_priv->cp_running = 0;
1047 }
1048
1049 /* Reset the engine.  This will stop the CP if it is running.
1050  */
1051 static int radeon_do_engine_reset(drm_device_t * dev)
1052 {
1053         drm_radeon_private_t *dev_priv = dev->dev_private;
1054         u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
1055         DRM_DEBUG("\n");
1056
1057         radeon_do_pixcache_flush(dev_priv);
1058
1059         clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
1060         mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
1061
1062         RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
1063                                             RADEON_FORCEON_MCLKA |
1064                                             RADEON_FORCEON_MCLKB |
1065                                             RADEON_FORCEON_YCLKA |
1066                                             RADEON_FORCEON_YCLKB |
1067                                             RADEON_FORCEON_MC |
1068                                             RADEON_FORCEON_AIC));
1069
1070         rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
1071
1072         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
1073                                               RADEON_SOFT_RESET_CP |
1074                                               RADEON_SOFT_RESET_HI |
1075                                               RADEON_SOFT_RESET_SE |
1076                                               RADEON_SOFT_RESET_RE |
1077                                               RADEON_SOFT_RESET_PP |
1078                                               RADEON_SOFT_RESET_E2 |
1079                                               RADEON_SOFT_RESET_RB));
1080         RADEON_READ(RADEON_RBBM_SOFT_RESET);
1081         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
1082                                               ~(RADEON_SOFT_RESET_CP |
1083                                                 RADEON_SOFT_RESET_HI |
1084                                                 RADEON_SOFT_RESET_SE |
1085                                                 RADEON_SOFT_RESET_RE |
1086                                                 RADEON_SOFT_RESET_PP |
1087                                                 RADEON_SOFT_RESET_E2 |
1088                                                 RADEON_SOFT_RESET_RB)));
1089         RADEON_READ(RADEON_RBBM_SOFT_RESET);
1090
1091         RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
1092         RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
1093         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
1094
1095         /* Reset the CP ring */
1096         radeon_do_cp_reset(dev_priv);
1097
1098         /* The CP is no longer running after an engine reset */
1099         dev_priv->cp_running = 0;
1100
1101         /* Reset any pending vertex, indirect buffers */
1102         radeon_freelist_reset(dev);
1103
1104         return 0;
1105 }
1106
1107 static void radeon_cp_init_ring_buffer(drm_device_t * dev,
1108                                        drm_radeon_private_t * dev_priv)
1109 {
1110         u32 ring_start, cur_read_ptr;
1111         u32 tmp;
1112
1113         /* Initialize the memory controller */
1114         RADEON_WRITE(RADEON_MC_FB_LOCATION,
1115                      ((dev_priv->gart_vm_start - 1) & 0xffff0000)
1116                      | (dev_priv->fb_location >> 16));
1117
1118 #if __OS_HAS_AGP
1119         if (dev_priv->flags & CHIP_IS_AGP) {
1120                 RADEON_WRITE(RADEON_MC_AGP_LOCATION,
1121                              (((dev_priv->gart_vm_start - 1 +
1122                                 dev_priv->gart_size) & 0xffff0000) |
1123                               (dev_priv->gart_vm_start >> 16)));
1124
1125                 ring_start = (dev_priv->cp_ring->offset
1126                               - dev->agp->base + dev_priv->gart_vm_start);
1127         } else
1128 #endif
1129                 ring_start = (dev_priv->cp_ring->offset
1130                               - dev->sg->handle + dev_priv->gart_vm_start);
1131
1132         RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
1133
1134         /* Set the write pointer delay */
1135         RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
1136
1137         /* Initialize the ring buffer's read and write pointers */
1138         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
1139         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
1140         SET_RING_HEAD(dev_priv, cur_read_ptr);
1141         dev_priv->ring.tail = cur_read_ptr;
1142
1143 #if __OS_HAS_AGP
1144         if (dev_priv->flags & CHIP_IS_AGP) {
1145                 /* set RADEON_AGP_BASE here instead of relying on X from user space */
1146                 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);
1147                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
1148                              dev_priv->ring_rptr->offset
1149                              - dev->agp->base + dev_priv->gart_vm_start);
1150         } else
1151 #endif
1152         {
1153                 drm_sg_mem_t *entry = dev->sg;
1154                 unsigned long tmp_ofs, page_ofs;
1155
1156                 tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle;
1157                 page_ofs = tmp_ofs >> PAGE_SHIFT;
1158
1159                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
1160                 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
1161                           (unsigned long)entry->busaddr[page_ofs],
1162                           entry->handle + tmp_ofs);
1163         }
1164
1165         /* Initialize the scratch register pointer.  This will cause
1166          * the scratch register values to be written out to memory
1167          * whenever they are updated.
1168          *
1169          * We simply put this behind the ring read pointer, this works
1170          * with PCI GART as well as (whatever kind of) AGP GART
1171          */
1172         RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
1173                      + RADEON_SCRATCH_REG_OFFSET);
1174
1175         dev_priv->scratch = ((__volatile__ u32 *)
1176                              dev_priv->ring_rptr->handle +
1177                              (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
1178
1179         RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
1180
1181         /* Writeback doesn't seem to work everywhere, test it first */
1182         DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
1183         RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
1184
1185         for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
1186                 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
1187                     0xdeadbeef)
1188                         break;
1189                 DRM_UDELAY(1);
1190         }
1191
1192         if (tmp < dev_priv->usec_timeout) {
1193                 dev_priv->writeback_works = 1;
1194                 DRM_DEBUG("writeback test succeeded, tmp=%d\n", tmp);
1195         } else {
1196                 dev_priv->writeback_works = 0;
1197                 DRM_DEBUG("writeback test failed\n");
1198         }
1199
1200         dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
1201         RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
1202
1203         dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
1204         RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
1205                      dev_priv->sarea_priv->last_dispatch);
1206
1207         dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
1208         RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
1209
1210         /* Set ring buffer size */
1211 #ifdef __BIG_ENDIAN
1212         RADEON_WRITE(RADEON_CP_RB_CNTL,
1213                      dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT);
1214 #else
1215         RADEON_WRITE(RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw);
1216 #endif
1217
1218         radeon_do_wait_for_idle(dev_priv);
1219
1220         /* Turn on bus mastering */
1221         tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
1222         RADEON_WRITE(RADEON_BUS_CNTL, tmp);
1223
1224         /* Sync everything up */
1225         RADEON_WRITE(RADEON_ISYNC_CNTL,
1226                      (RADEON_ISYNC_ANY2D_IDLE3D |
1227                       RADEON_ISYNC_ANY3D_IDLE2D |
1228                       RADEON_ISYNC_WAIT_IDLEGUI |
1229                       RADEON_ISYNC_CPSCRATCH_IDLEGUI));
1230 }
1231
1232 /* Enable or disable PCI GART on the chip */
1233 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1234 {
1235         u32 tmp = RADEON_READ(RADEON_AIC_CNTL);
1236
1237         if (on) {
1238                 RADEON_WRITE(RADEON_AIC_CNTL,
1239                              tmp | RADEON_PCIGART_TRANSLATE_EN);
1240
1241                 /* set PCI GART page-table base address
1242                  */
1243                 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart);
1244
1245                 /* set address range for PCI address translate
1246                  */
1247                 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1248                 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1249                              + dev_priv->gart_size - 1);
1250
1251                 /* Turn off AGP aperture -- is this required for PCI GART?
1252                  */
1253                 RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0);       /* ?? */
1254                 RADEON_WRITE(RADEON_AGP_COMMAND, 0);    /* clear AGP_COMMAND */
1255         } else {
1256                 RADEON_WRITE(RADEON_AIC_CNTL,
1257                              tmp & ~RADEON_PCIGART_TRANSLATE_EN);
1258         }
1259 }
1260
1261 static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
1262 {
1263         drm_radeon_private_t *dev_priv = dev->dev_private;
1264         DRM_DEBUG("\n");
1265
1266         if ((!(dev_priv->flags & CHIP_IS_AGP)) && !dev->sg) {
1267                 DRM_ERROR("PCI GART memory not allocated!\n");
1268                 radeon_do_cleanup_cp(dev);
1269                 return DRM_ERR(EINVAL);
1270         }
1271
1272         dev_priv->usec_timeout = init->usec_timeout;
1273         if (dev_priv->usec_timeout < 1 ||
1274             dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1275                 DRM_DEBUG("TIMEOUT problem!\n");
1276                 radeon_do_cleanup_cp(dev);
1277                 return DRM_ERR(EINVAL);
1278         }
1279
1280         switch(init->func) {
1281         case RADEON_INIT_R200_CP:
1282                 dev_priv->microcode_version=UCODE_R200;
1283                 break;
1284         case RADEON_INIT_R300_CP:
1285                 dev_priv->microcode_version=UCODE_R300;
1286                 break;
1287         default:
1288                 dev_priv->microcode_version=UCODE_R100;
1289                 break;
1290         }
1291
1292         dev_priv->do_boxes = 0;
1293         dev_priv->cp_mode = init->cp_mode;
1294
1295         /* We don't support anything other than bus-mastering ring mode,
1296          * but the ring can be in either AGP or PCI space for the ring
1297          * read pointer.
1298          */
1299         if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1300             (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1301                 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1302                 radeon_do_cleanup_cp(dev);
1303                 return DRM_ERR(EINVAL);
1304         }
1305
1306         switch (init->fb_bpp) {
1307         case 16:
1308                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1309                 break;
1310         case 32:
1311         default:
1312                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1313                 break;
1314         }
1315         dev_priv->front_offset = init->front_offset;
1316         dev_priv->front_pitch = init->front_pitch;
1317         dev_priv->back_offset = init->back_offset;
1318         dev_priv->back_pitch = init->back_pitch;
1319
1320         switch (init->depth_bpp) {
1321         case 16:
1322                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1323                 break;
1324         case 32:
1325         default:
1326                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1327                 break;
1328         }
1329         dev_priv->depth_offset = init->depth_offset;
1330         dev_priv->depth_pitch = init->depth_pitch;
1331
1332         /* Hardware state for depth clears.  Remove this if/when we no
1333          * longer clear the depth buffer with a 3D rectangle.  Hard-code
1334          * all values to prevent unwanted 3D state from slipping through
1335          * and screwing with the clear operation.
1336          */
1337         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1338                                            (dev_priv->color_fmt << 10) |
1339                                            (dev_priv->microcode_version == UCODE_R100 ?
1340                                                 RADEON_ZBLOCK16 : 0));
1341
1342         dev_priv->depth_clear.rb3d_zstencilcntl =
1343             (dev_priv->depth_fmt |
1344              RADEON_Z_TEST_ALWAYS |
1345              RADEON_STENCIL_TEST_ALWAYS |
1346              RADEON_STENCIL_S_FAIL_REPLACE |
1347              RADEON_STENCIL_ZPASS_REPLACE |
1348              RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1349
1350         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1351                                          RADEON_BFACE_SOLID |
1352                                          RADEON_FFACE_SOLID |
1353                                          RADEON_FLAT_SHADE_VTX_LAST |
1354                                          RADEON_DIFFUSE_SHADE_FLAT |
1355                                          RADEON_ALPHA_SHADE_FLAT |
1356                                          RADEON_SPECULAR_SHADE_FLAT |
1357                                          RADEON_FOG_SHADE_FLAT |
1358                                          RADEON_VTX_PIX_CENTER_OGL |
1359                                          RADEON_ROUND_MODE_TRUNC |
1360                                          RADEON_ROUND_PREC_8TH_PIX);
1361
1362         DRM_GETSAREA();
1363
1364         dev_priv->fb_offset = init->fb_offset;
1365         dev_priv->mmio_offset = init->mmio_offset;
1366         dev_priv->ring_offset = init->ring_offset;
1367         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1368         dev_priv->buffers_offset = init->buffers_offset;
1369         dev_priv->gart_textures_offset = init->gart_textures_offset;
1370
1371         if (!dev_priv->sarea) {
1372                 DRM_ERROR("could not find sarea!\n");
1373                 radeon_do_cleanup_cp(dev);
1374                 return DRM_ERR(EINVAL);
1375         }
1376
1377         dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
1378         if (!dev_priv->mmio) {
1379                 DRM_ERROR("could not find mmio region!\n");
1380                 radeon_do_cleanup_cp(dev);
1381                 return DRM_ERR(EINVAL);
1382         }
1383         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1384         if (!dev_priv->cp_ring) {
1385                 DRM_ERROR("could not find cp ring region!\n");
1386                 radeon_do_cleanup_cp(dev);
1387                 return DRM_ERR(EINVAL);
1388         }
1389         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1390         if (!dev_priv->ring_rptr) {
1391                 DRM_ERROR("could not find ring read pointer!\n");
1392                 radeon_do_cleanup_cp(dev);
1393                 return DRM_ERR(EINVAL);
1394         }
1395         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1396         if (!dev->agp_buffer_map) {
1397                 DRM_ERROR("could not find dma buffer region!\n");
1398                 radeon_do_cleanup_cp(dev);
1399                 return DRM_ERR(EINVAL);
1400         }
1401
1402         if (init->gart_textures_offset) {
1403                 dev_priv->gart_textures =
1404                     drm_core_findmap(dev, init->gart_textures_offset);
1405                 if (!dev_priv->gart_textures) {
1406                         DRM_ERROR("could not find GART texture region!\n");
1407                         radeon_do_cleanup_cp(dev);
1408                         return DRM_ERR(EINVAL);
1409                 }
1410         }
1411
1412         dev_priv->sarea_priv =
1413             (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
1414                                     init->sarea_priv_offset);
1415
1416 #if __OS_HAS_AGP
1417         if (dev_priv->flags & CHIP_IS_AGP) {
1418                 drm_core_ioremap(dev_priv->cp_ring, dev);
1419                 drm_core_ioremap(dev_priv->ring_rptr, dev);
1420                 drm_core_ioremap(dev->agp_buffer_map, dev);
1421                 if (!dev_priv->cp_ring->handle ||
1422                     !dev_priv->ring_rptr->handle ||
1423                     !dev->agp_buffer_map->handle) {
1424                         DRM_ERROR("could not find ioremap agp regions!\n");
1425                         radeon_do_cleanup_cp(dev);
1426                         return DRM_ERR(EINVAL);
1427                 }
1428         } else
1429 #endif
1430         {
1431                 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1432                 dev_priv->ring_rptr->handle =
1433                     (void *)dev_priv->ring_rptr->offset;
1434                 dev->agp_buffer_map->handle =
1435                     (void *)dev->agp_buffer_map->offset;
1436
1437                 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1438                           dev_priv->cp_ring->handle);
1439                 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1440                           dev_priv->ring_rptr->handle);
1441                 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1442                           dev->agp_buffer_map->handle);
1443         }
1444
1445         dev_priv->fb_location = (RADEON_READ(RADEON_MC_FB_LOCATION)
1446                                  & 0xffff) << 16;
1447
1448         dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1449                                         ((dev_priv->front_offset
1450                                           + dev_priv->fb_location) >> 10));
1451
1452         dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1453                                        ((dev_priv->back_offset
1454                                          + dev_priv->fb_location) >> 10));
1455
1456         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1457                                         ((dev_priv->depth_offset
1458                                           + dev_priv->fb_location) >> 10));
1459
1460         dev_priv->gart_size = init->gart_size;
1461         dev_priv->gart_vm_start = dev_priv->fb_location
1462             + RADEON_READ(RADEON_CONFIG_APER_SIZE);
1463
1464 #if __OS_HAS_AGP
1465         if (dev_priv->flags & CHIP_IS_AGP)
1466                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1467                                                  - dev->agp->base
1468                                                  + dev_priv->gart_vm_start);
1469         else
1470 #endif
1471                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1472                                                  - dev->sg->handle
1473                                                  + dev_priv->gart_vm_start);
1474
1475         DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1476         DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1477         DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1478                   dev_priv->gart_buffers_offset);
1479
1480         dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1481         dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1482                               + init->ring_size / sizeof(u32));
1483         dev_priv->ring.size = init->ring_size;
1484         dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1485
1486         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1487
1488         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1489
1490 #if __OS_HAS_AGP
1491         if (dev_priv->flags & CHIP_IS_AGP) {
1492                 /* Turn off PCI GART */
1493                 radeon_set_pcigart(dev_priv, 0);
1494         } else
1495 #endif
1496         {
1497                 if (!drm_ati_pcigart_init(dev, &dev_priv->phys_pci_gart,
1498                                           &dev_priv->bus_pci_gart)) {
1499                         DRM_ERROR("failed to init PCI GART!\n");
1500                         radeon_do_cleanup_cp(dev);
1501                         return DRM_ERR(ENOMEM);
1502                 }
1503
1504                 /* Turn on PCI GART */
1505                 radeon_set_pcigart(dev_priv, 1);
1506         }
1507
1508         radeon_cp_load_microcode(dev_priv);
1509         radeon_cp_init_ring_buffer(dev, dev_priv);
1510
1511         dev_priv->last_buf = 0;
1512
1513         radeon_do_engine_reset(dev);
1514
1515         return 0;
1516 }
1517
1518 int radeon_do_cleanup_cp(drm_device_t * dev)
1519 {
1520         drm_radeon_private_t *dev_priv = dev->dev_private;
1521         DRM_DEBUG("\n");
1522
1523         /* Make sure interrupts are disabled here because the uninstall ioctl
1524          * may not have been called from userspace and after dev_private
1525          * is freed, it's too late.
1526          */
1527         if (dev->irq_enabled)
1528                 drm_irq_uninstall(dev);
1529
1530 #if __OS_HAS_AGP
1531         if (dev_priv->flags & CHIP_IS_AGP) {
1532                 if (dev_priv->cp_ring != NULL) {
1533                         drm_core_ioremapfree(dev_priv->cp_ring, dev);
1534                         dev_priv->cp_ring = NULL;
1535                 }
1536                 if (dev_priv->ring_rptr != NULL) {
1537                         drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1538                         dev_priv->ring_rptr = NULL;
1539                 }
1540                 if (dev->agp_buffer_map != NULL) {
1541                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
1542                         dev->agp_buffer_map = NULL;
1543                 }
1544         } else
1545 #endif
1546         {
1547                 if (!drm_ati_pcigart_cleanup(dev,
1548                                              dev_priv->phys_pci_gart,
1549                                              dev_priv->bus_pci_gart))
1550                         DRM_ERROR("failed to cleanup PCI GART!\n");
1551         }
1552         /* only clear to the start of flags */
1553         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1554
1555         return 0;
1556 }
1557
1558 /* This code will reinit the Radeon CP hardware after a resume from disc.
1559  * AFAIK, it would be very difficult to pickle the state at suspend time, so
1560  * here we make sure that all Radeon hardware initialisation is re-done without
1561  * affecting running applications.
1562  *
1563  * Charl P. Botha <http://cpbotha.net>
1564  */
1565 static int radeon_do_resume_cp(drm_device_t * dev)
1566 {
1567         drm_radeon_private_t *dev_priv = dev->dev_private;
1568
1569         if (!dev_priv) {
1570                 DRM_ERROR("Called with no initialization\n");
1571                 return DRM_ERR(EINVAL);
1572         }
1573
1574         DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1575
1576 #if __OS_HAS_AGP
1577         if (dev_priv->flags & CHIP_IS_AGP) {
1578                 /* Turn off PCI GART */
1579                 radeon_set_pcigart(dev_priv, 0);
1580         } else
1581 #endif
1582         {
1583                 /* Turn on PCI GART */
1584                 radeon_set_pcigart(dev_priv, 1);
1585         }
1586
1587         radeon_cp_load_microcode(dev_priv);
1588         radeon_cp_init_ring_buffer(dev, dev_priv);
1589
1590         radeon_do_engine_reset(dev);
1591
1592         DRM_DEBUG("radeon_do_resume_cp() complete\n");
1593
1594         return 0;
1595 }
1596
1597 int radeon_cp_init(DRM_IOCTL_ARGS)
1598 {
1599         DRM_DEVICE;
1600         drm_radeon_init_t init;
1601
1602         LOCK_TEST_WITH_RETURN(dev, filp);
1603
1604         DRM_COPY_FROM_USER_IOCTL(init, (drm_radeon_init_t __user *) data,
1605                                  sizeof(init));
1606
1607         switch (init.func) {
1608         case RADEON_INIT_CP:
1609         case RADEON_INIT_R200_CP:
1610         case RADEON_INIT_R300_CP:
1611                 return radeon_do_init_cp(dev, &init);
1612         case RADEON_CLEANUP_CP:
1613                 return radeon_do_cleanup_cp(dev);
1614         }
1615
1616         return DRM_ERR(EINVAL);
1617 }
1618
1619 int radeon_cp_start(DRM_IOCTL_ARGS)
1620 {
1621         DRM_DEVICE;
1622         drm_radeon_private_t *dev_priv = dev->dev_private;
1623         DRM_DEBUG("\n");
1624
1625         LOCK_TEST_WITH_RETURN(dev, filp);
1626
1627         if (dev_priv->cp_running) {
1628                 DRM_DEBUG("%s while CP running\n", __FUNCTION__);
1629                 return 0;
1630         }
1631         if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1632                 DRM_DEBUG("%s called with bogus CP mode (%d)\n",
1633                           __FUNCTION__, dev_priv->cp_mode);
1634                 return 0;
1635         }
1636
1637         radeon_do_cp_start(dev_priv);
1638
1639         return 0;
1640 }
1641
1642 /* Stop the CP.  The engine must have been idled before calling this
1643  * routine.
1644  */
1645 int radeon_cp_stop(DRM_IOCTL_ARGS)
1646 {
1647         DRM_DEVICE;
1648         drm_radeon_private_t *dev_priv = dev->dev_private;
1649         drm_radeon_cp_stop_t stop;
1650         int ret;
1651         DRM_DEBUG("\n");
1652
1653         LOCK_TEST_WITH_RETURN(dev, filp);
1654
1655         DRM_COPY_FROM_USER_IOCTL(stop, (drm_radeon_cp_stop_t __user *) data,
1656                                  sizeof(stop));
1657
1658         if (!dev_priv->cp_running)
1659                 return 0;
1660
1661         /* Flush any pending CP commands.  This ensures any outstanding
1662          * commands are exectuted by the engine before we turn it off.
1663          */
1664         if (stop.flush) {
1665                 radeon_do_cp_flush(dev_priv);
1666         }
1667
1668         /* If we fail to make the engine go idle, we return an error
1669          * code so that the DRM ioctl wrapper can try again.
1670          */
1671         if (stop.idle) {
1672                 ret = radeon_do_cp_idle(dev_priv);
1673                 if (ret)
1674                         return ret;
1675         }
1676
1677         /* Finally, we can turn off the CP.  If the engine isn't idle,
1678          * we will get some dropped triangles as they won't be fully
1679          * rendered before the CP is shut down.
1680          */
1681         radeon_do_cp_stop(dev_priv);
1682
1683         /* Reset the engine */
1684         radeon_do_engine_reset(dev);
1685
1686         return 0;
1687 }
1688
1689 void radeon_do_release(drm_device_t * dev)
1690 {
1691         drm_radeon_private_t *dev_priv = dev->dev_private;
1692         int i, ret;
1693
1694         if (dev_priv) {
1695
1696                 if (dev_priv->cp_running) {
1697                         /* Stop the cp */
1698                         while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1699                                 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1700 #ifdef __linux__
1701                                 schedule();
1702 #else
1703                                 tsleep(&ret, PZERO, "rdnrel", 1);
1704 #endif
1705                         }
1706                         radeon_do_cp_stop(dev_priv);
1707                         radeon_do_engine_reset(dev);
1708                 }
1709
1710                 /* Disable *all* interrupts */
1711                 if (dev_priv->mmio)     /* remove this after permanent addmaps */
1712                         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1713
1714                 if (dev_priv->mmio) {/* remove all surfaces */
1715                         for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1716                                 RADEON_WRITE(RADEON_SURFACE0_INFO + 16*i, 0);
1717                                 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16*i, 0);
1718                                 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16*i, 0);
1719                         }
1720                 }
1721
1722                 /* Free memory heap structures */
1723                 radeon_mem_takedown(&(dev_priv->gart_heap));
1724                 radeon_mem_takedown(&(dev_priv->fb_heap));
1725
1726                 /* deallocate kernel resources */
1727                 radeon_do_cleanup_cp(dev);
1728         }
1729 }
1730
1731 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1732  */
1733 int radeon_cp_reset(DRM_IOCTL_ARGS)
1734 {
1735         DRM_DEVICE;
1736         drm_radeon_private_t *dev_priv = dev->dev_private;
1737         DRM_DEBUG("\n");
1738
1739         LOCK_TEST_WITH_RETURN(dev, filp);
1740
1741         if (!dev_priv) {
1742                 DRM_DEBUG("%s called before init done\n", __FUNCTION__);
1743                 return DRM_ERR(EINVAL);
1744         }
1745
1746         radeon_do_cp_reset(dev_priv);
1747
1748         /* The CP is no longer running after an engine reset */
1749         dev_priv->cp_running = 0;
1750
1751         return 0;
1752 }
1753
1754 int radeon_cp_idle(DRM_IOCTL_ARGS)
1755 {
1756         DRM_DEVICE;
1757         drm_radeon_private_t *dev_priv = dev->dev_private;
1758         DRM_DEBUG("\n");
1759
1760         LOCK_TEST_WITH_RETURN(dev, filp);
1761
1762         return radeon_do_cp_idle(dev_priv);
1763 }
1764
1765 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1766  */
1767 int radeon_cp_resume(DRM_IOCTL_ARGS)
1768 {
1769         DRM_DEVICE;
1770
1771         return radeon_do_resume_cp(dev);
1772 }
1773
1774 int radeon_engine_reset(DRM_IOCTL_ARGS)
1775 {
1776         DRM_DEVICE;
1777         DRM_DEBUG("\n");
1778
1779         LOCK_TEST_WITH_RETURN(dev, filp);
1780
1781         return radeon_do_engine_reset(dev);
1782 }
1783
1784 /* ================================================================
1785  * Fullscreen mode
1786  */
1787
1788 /* KW: Deprecated to say the least:
1789  */
1790 int radeon_fullscreen(DRM_IOCTL_ARGS)
1791 {
1792         return 0;
1793 }
1794
1795 /* ================================================================
1796  * Freelist management
1797  */
1798
1799 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1800  *   bufs until freelist code is used.  Note this hides a problem with
1801  *   the scratch register * (used to keep track of last buffer
1802  *   completed) being written to before * the last buffer has actually
1803  *   completed rendering.
1804  *
1805  * KW:  It's also a good way to find free buffers quickly.
1806  *
1807  * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1808  * sleep.  However, bugs in older versions of radeon_accel.c mean that
1809  * we essentially have to do this, else old clients will break.
1810  *
1811  * However, it does leave open a potential deadlock where all the
1812  * buffers are held by other clients, which can't release them because
1813  * they can't get the lock.
1814  */
1815
1816 drm_buf_t *radeon_freelist_get(drm_device_t * dev)
1817 {
1818         drm_device_dma_t *dma = dev->dma;
1819         drm_radeon_private_t *dev_priv = dev->dev_private;
1820         drm_radeon_buf_priv_t *buf_priv;
1821         drm_buf_t *buf;
1822         int i, t;
1823         int start;
1824
1825         if (++dev_priv->last_buf >= dma->buf_count)
1826                 dev_priv->last_buf = 0;
1827
1828         start = dev_priv->last_buf;
1829
1830         for (t = 0; t < dev_priv->usec_timeout; t++) {
1831                 u32 done_age = GET_SCRATCH(1);
1832                 DRM_DEBUG("done_age = %d\n", done_age);
1833                 for (i = start; i < dma->buf_count; i++) {
1834                         buf = dma->buflist[i];
1835                         buf_priv = buf->dev_private;
1836                         if (buf->filp == 0 || (buf->pending &&
1837                                                buf_priv->age <= done_age)) {
1838                                 dev_priv->stats.requested_bufs++;
1839                                 buf->pending = 0;
1840                                 return buf;
1841                         }
1842                         start = 0;
1843                 }
1844
1845                 if (t) {
1846                         DRM_UDELAY(1);
1847                         dev_priv->stats.freelist_loops++;
1848                 }
1849         }
1850
1851         DRM_DEBUG("returning NULL!\n");
1852         return NULL;
1853 }
1854
1855 #if 0
1856 drm_buf_t *radeon_freelist_get(drm_device_t * dev)
1857 {
1858         drm_device_dma_t *dma = dev->dma;
1859         drm_radeon_private_t *dev_priv = dev->dev_private;
1860         drm_radeon_buf_priv_t *buf_priv;
1861         drm_buf_t *buf;
1862         int i, t;
1863         int start;
1864         u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1865
1866         if (++dev_priv->last_buf >= dma->buf_count)
1867                 dev_priv->last_buf = 0;
1868
1869         start = dev_priv->last_buf;
1870         dev_priv->stats.freelist_loops++;
1871
1872         for (t = 0; t < 2; t++) {
1873                 for (i = start; i < dma->buf_count; i++) {
1874                         buf = dma->buflist[i];
1875                         buf_priv = buf->dev_private;
1876                         if (buf->filp == 0 || (buf->pending &&
1877                                                buf_priv->age <= done_age)) {
1878                                 dev_priv->stats.requested_bufs++;
1879                                 buf->pending = 0;
1880                                 return buf;
1881                         }
1882                 }
1883                 start = 0;
1884         }
1885
1886         return NULL;
1887 }
1888 #endif
1889
1890 void radeon_freelist_reset(drm_device_t * dev)
1891 {
1892         drm_device_dma_t *dma = dev->dma;
1893         drm_radeon_private_t *dev_priv = dev->dev_private;
1894         int i;
1895
1896         dev_priv->last_buf = 0;
1897         for (i = 0; i < dma->buf_count; i++) {
1898                 drm_buf_t *buf = dma->buflist[i];
1899                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1900                 buf_priv->age = 0;
1901         }
1902 }
1903
1904 /* ================================================================
1905  * CP command submission
1906  */
1907
1908 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1909 {
1910         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1911         int i;
1912         u32 last_head = GET_RING_HEAD(dev_priv);
1913
1914         for (i = 0; i < dev_priv->usec_timeout; i++) {
1915                 u32 head = GET_RING_HEAD(dev_priv);
1916
1917                 ring->space = (head - ring->tail) * sizeof(u32);
1918                 if (ring->space <= 0)
1919                         ring->space += ring->size;
1920                 if (ring->space > n)
1921                         return 0;
1922
1923                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1924
1925                 if (head != last_head)
1926                         i = 0;
1927                 last_head = head;
1928
1929                 DRM_UDELAY(1);
1930         }
1931
1932         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1933 #if RADEON_FIFO_DEBUG
1934         radeon_status(dev_priv);
1935         DRM_ERROR("failed!\n");
1936 #endif
1937         return DRM_ERR(EBUSY);
1938 }
1939
1940 static int radeon_cp_get_buffers(DRMFILE filp, drm_device_t * dev,
1941                                  drm_dma_t * d)
1942 {
1943         int i;
1944         drm_buf_t *buf;
1945
1946         for (i = d->granted_count; i < d->request_count; i++) {
1947                 buf = radeon_freelist_get(dev);
1948                 if (!buf)
1949                         return DRM_ERR(EBUSY);  /* NOTE: broken client */
1950
1951                 buf->filp = filp;
1952
1953                 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1954                                      sizeof(buf->idx)))
1955                         return DRM_ERR(EFAULT);
1956                 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
1957                                      sizeof(buf->total)))
1958                         return DRM_ERR(EFAULT);
1959
1960                 d->granted_count++;
1961         }
1962         return 0;
1963 }
1964
1965 int radeon_cp_buffers(DRM_IOCTL_ARGS)
1966 {
1967         DRM_DEVICE;
1968         drm_device_dma_t *dma = dev->dma;
1969         int ret = 0;
1970         drm_dma_t __user *argp = (void __user *)data;
1971         drm_dma_t d;
1972
1973         LOCK_TEST_WITH_RETURN(dev, filp);
1974
1975         DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d));
1976
1977         /* Please don't send us buffers.
1978          */
1979         if (d.send_count != 0) {
1980                 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1981                           DRM_CURRENTPID, d.send_count);
1982                 return DRM_ERR(EINVAL);
1983         }
1984
1985         /* We'll send you buffers.
1986          */
1987         if (d.request_count < 0 || d.request_count > dma->buf_count) {
1988                 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1989                           DRM_CURRENTPID, d.request_count, dma->buf_count);
1990                 return DRM_ERR(EINVAL);
1991         }
1992
1993         d.granted_count = 0;
1994
1995         if (d.request_count) {
1996                 ret = radeon_cp_get_buffers(filp, dev, &d);
1997         }
1998
1999         DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d));
2000
2001         return ret;
2002 }
2003
2004 /* Always create a map record for MMIO and FB memory, done from DRIVER_POSTINIT */
2005 int radeon_preinit(struct drm_device *dev, unsigned long flags)
2006 {
2007         u32 save, temp;
2008         drm_radeon_private_t *dev_priv;
2009         int ret = 0;
2010
2011         dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
2012         if (dev_priv == NULL)
2013                 return DRM_ERR(ENOMEM);
2014
2015         memset(dev_priv, 0, sizeof(drm_radeon_private_t));
2016         dev->dev_private = (void *)dev_priv;
2017         dev_priv->flags = flags;
2018
2019         switch (flags & CHIP_FAMILY_MASK) {
2020         case CHIP_R100:
2021         case CHIP_RV200:
2022         case CHIP_R200:
2023         case CHIP_R300:
2024                 dev_priv->flags |= CHIP_HAS_HIERZ;
2025                 break;
2026         default:
2027         /* all other chips have no hierarchical z buffer */
2028                 break;
2029         }
2030
2031 #ifdef __linux__
2032         /* registers */
2033         if ((ret = drm_initmap(dev, pci_resource_start(dev->pdev, 2),
2034                                pci_resource_len(dev->pdev, 2), _DRM_REGISTERS,
2035                                0)))
2036                 return ret;
2037
2038         /* framebuffer */
2039         if ((ret = drm_initmap(dev, pci_resource_start(dev->pdev, 0),
2040                                pci_resource_len(dev->pdev, 0),
2041                                _DRM_FRAME_BUFFER, _DRM_WRITE_COMBINING)))
2042                 return ret;
2043
2044         /* There are signatures in BIOS and PCI-SSID for a PCI card, but they are not very reliable.
2045            Following detection method works for all cards tested so far.
2046            Note, checking AGP_ENABLE bit after drmAgpEnable call can also give the correct result.
2047            However, calling drmAgpEnable on a PCI card can cause some strange lockup when the server
2048            restarts next time.
2049          */
2050         pci_read_config_dword(dev->pdev, RADEON_AGP_COMMAND_PCI_CONFIG, &save);
2051         pci_write_config_dword(dev->pdev, RADEON_AGP_COMMAND_PCI_CONFIG,
2052                                save | RADEON_AGP_ENABLE);
2053         pci_read_config_dword(dev->pdev, RADEON_AGP_COMMAND_PCI_CONFIG, &temp);
2054         pci_write_config_dword(dev->pdev, RADEON_AGP_COMMAND_PCI_CONFIG, save);
2055         if (temp & RADEON_AGP_ENABLE)
2056                 dev_priv->flags |= CHIP_IS_AGP;
2057 #else
2058         if (drm_device_is_agp(dev))
2059                 dev_priv->flags & CHIP_IS_AGP;
2060 #endif
2061         DRM_DEBUG("%s card detected\n",
2062                   ((dev_priv->flags & CHIP_IS_AGP) ? "AGP" : "PCI"));
2063
2064 #if defined(__linux__)
2065         /* Check if we need a reset */
2066         if (!
2067             (dev_priv->mmio =
2068              drm_core_findmap(dev, pci_resource_start(dev->pdev, 2))))
2069                 return DRM_ERR(ENOMEM);
2070
2071         ret = radeon_create_i2c_busses(dev);
2072 #endif
2073         return ret;
2074 }
2075
2076 int radeon_postcleanup(struct drm_device *dev)
2077 {
2078         drm_radeon_private_t *dev_priv = dev->dev_private;
2079
2080         DRM_DEBUG("\n");
2081 #if defined(__linux__)
2082         radeon_delete_i2c_busses(dev);
2083 #endif
2084         drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
2085
2086         dev->dev_private = NULL;
2087         return 0;
2088 }