1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*-
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
34 #include "radeon_drm.h"
35 #include "radeon_drv.h"
37 #define RADEON_FIFO_DEBUG 0
39 /* CP microcode (from ATI) */
40 static u32 R200_cp_microcode[][2] = {
41 { 0x21007000, 0000000000 },
42 { 0x20007000, 0000000000 },
43 { 0x000000ab, 0x00000004 },
44 { 0x000000af, 0x00000004 },
45 { 0x66544a49, 0000000000 },
46 { 0x49494174, 0000000000 },
47 { 0x54517d83, 0000000000 },
48 { 0x498d8b64, 0000000000 },
49 { 0x49494949, 0000000000 },
50 { 0x49da493c, 0000000000 },
51 { 0x49989898, 0000000000 },
52 { 0xd34949d5, 0000000000 },
53 { 0x9dc90e11, 0000000000 },
54 { 0xce9b9b9b, 0000000000 },
55 { 0x000f0000, 0x00000016 },
56 { 0x352e232c, 0000000000 },
57 { 0x00000013, 0x00000004 },
58 { 0x000f0000, 0x00000016 },
59 { 0x352e272c, 0000000000 },
60 { 0x000f0001, 0x00000016 },
61 { 0x3239362f, 0000000000 },
62 { 0x000077ef, 0x00000002 },
63 { 0x00061000, 0x00000002 },
64 { 0x00000020, 0x0000001a },
65 { 0x00004000, 0x0000001e },
66 { 0x00061000, 0x00000002 },
67 { 0x00000020, 0x0000001a },
68 { 0x00004000, 0x0000001e },
69 { 0x00061000, 0x00000002 },
70 { 0x00000020, 0x0000001a },
71 { 0x00004000, 0x0000001e },
72 { 0x00000016, 0x00000004 },
73 { 0x0003802a, 0x00000002 },
74 { 0x040067e0, 0x00000002 },
75 { 0x00000016, 0x00000004 },
76 { 0x000077e0, 0x00000002 },
77 { 0x00065000, 0x00000002 },
78 { 0x000037e1, 0x00000002 },
79 { 0x040067e1, 0x00000006 },
80 { 0x000077e0, 0x00000002 },
81 { 0x000077e1, 0x00000002 },
82 { 0x000077e1, 0x00000006 },
83 { 0xffffffff, 0000000000 },
84 { 0x10000000, 0000000000 },
85 { 0x0003802a, 0x00000002 },
86 { 0x040067e0, 0x00000006 },
87 { 0x00007675, 0x00000002 },
88 { 0x00007676, 0x00000002 },
89 { 0x00007677, 0x00000002 },
90 { 0x00007678, 0x00000006 },
91 { 0x0003802b, 0x00000002 },
92 { 0x04002676, 0x00000002 },
93 { 0x00007677, 0x00000002 },
94 { 0x00007678, 0x00000006 },
95 { 0x0000002e, 0x00000018 },
96 { 0x0000002e, 0x00000018 },
97 { 0000000000, 0x00000006 },
98 { 0x0000002f, 0x00000018 },
99 { 0x0000002f, 0x00000018 },
100 { 0000000000, 0x00000006 },
101 { 0x01605000, 0x00000002 },
102 { 0x00065000, 0x00000002 },
103 { 0x00098000, 0x00000002 },
104 { 0x00061000, 0x00000002 },
105 { 0x64c0603d, 0x00000004 },
106 { 0x00080000, 0x00000016 },
107 { 0000000000, 0000000000 },
108 { 0x0400251d, 0x00000002 },
109 { 0x00007580, 0x00000002 },
110 { 0x00067581, 0x00000002 },
111 { 0x04002580, 0x00000002 },
112 { 0x00067581, 0x00000002 },
113 { 0x00000046, 0x00000004 },
114 { 0x00005000, 0000000000 },
115 { 0x00061000, 0x00000002 },
116 { 0x0000750e, 0x00000002 },
117 { 0x00019000, 0x00000002 },
118 { 0x00011055, 0x00000014 },
119 { 0x00000055, 0x00000012 },
120 { 0x0400250f, 0x00000002 },
121 { 0x0000504a, 0x00000004 },
122 { 0x00007565, 0x00000002 },
123 { 0x00007566, 0x00000002 },
124 { 0x00000051, 0x00000004 },
125 { 0x01e655b4, 0x00000002 },
126 { 0x4401b0dc, 0x00000002 },
127 { 0x01c110dc, 0x00000002 },
128 { 0x2666705d, 0x00000018 },
129 { 0x040c2565, 0x00000002 },
130 { 0x0000005d, 0x00000018 },
131 { 0x04002564, 0x00000002 },
132 { 0x00007566, 0x00000002 },
133 { 0x00000054, 0x00000004 },
134 { 0x00401060, 0x00000008 },
135 { 0x00101000, 0x00000002 },
136 { 0x000d80ff, 0x00000002 },
137 { 0x00800063, 0x00000008 },
138 { 0x000f9000, 0x00000002 },
139 { 0x000e00ff, 0x00000002 },
140 { 0000000000, 0x00000006 },
141 { 0x00000080, 0x00000018 },
142 { 0x00000054, 0x00000004 },
143 { 0x00007576, 0x00000002 },
144 { 0x00065000, 0x00000002 },
145 { 0x00009000, 0x00000002 },
146 { 0x00041000, 0x00000002 },
147 { 0x0c00350e, 0x00000002 },
148 { 0x00049000, 0x00000002 },
149 { 0x00051000, 0x00000002 },
150 { 0x01e785f8, 0x00000002 },
151 { 0x00200000, 0x00000002 },
152 { 0x00600073, 0x0000000c },
153 { 0x00007563, 0x00000002 },
154 { 0x006075f0, 0x00000021 },
155 { 0x20007068, 0x00000004 },
156 { 0x00005068, 0x00000004 },
157 { 0x00007576, 0x00000002 },
158 { 0x00007577, 0x00000002 },
159 { 0x0000750e, 0x00000002 },
160 { 0x0000750f, 0x00000002 },
161 { 0x00a05000, 0x00000002 },
162 { 0x00600076, 0x0000000c },
163 { 0x006075f0, 0x00000021 },
164 { 0x000075f8, 0x00000002 },
165 { 0x00000076, 0x00000004 },
166 { 0x000a750e, 0x00000002 },
167 { 0x0020750f, 0x00000002 },
168 { 0x00600079, 0x00000004 },
169 { 0x00007570, 0x00000002 },
170 { 0x00007571, 0x00000002 },
171 { 0x00007572, 0x00000006 },
172 { 0x00005000, 0x00000002 },
173 { 0x00a05000, 0x00000002 },
174 { 0x00007568, 0x00000002 },
175 { 0x00061000, 0x00000002 },
176 { 0x00000084, 0x0000000c },
177 { 0x00058000, 0x00000002 },
178 { 0x0c607562, 0x00000002 },
179 { 0x00000086, 0x00000004 },
180 { 0x00600085, 0x00000004 },
181 { 0x400070dd, 0000000000 },
182 { 0x000380dd, 0x00000002 },
183 { 0x00000093, 0x0000001c },
184 { 0x00065095, 0x00000018 },
185 { 0x040025bb, 0x00000002 },
186 { 0x00061096, 0x00000018 },
187 { 0x040075bc, 0000000000 },
188 { 0x000075bb, 0x00000002 },
189 { 0x000075bc, 0000000000 },
190 { 0x00090000, 0x00000006 },
191 { 0x00090000, 0x00000002 },
192 { 0x000d8002, 0x00000006 },
193 { 0x00005000, 0x00000002 },
194 { 0x00007821, 0x00000002 },
195 { 0x00007800, 0000000000 },
196 { 0x00007821, 0x00000002 },
197 { 0x00007800, 0000000000 },
198 { 0x01665000, 0x00000002 },
199 { 0x000a0000, 0x00000002 },
200 { 0x000671cc, 0x00000002 },
201 { 0x0286f1cd, 0x00000002 },
202 { 0x000000a3, 0x00000010 },
203 { 0x21007000, 0000000000 },
204 { 0x000000aa, 0x0000001c },
205 { 0x00065000, 0x00000002 },
206 { 0x000a0000, 0x00000002 },
207 { 0x00061000, 0x00000002 },
208 { 0x000b0000, 0x00000002 },
209 { 0x38067000, 0x00000002 },
210 { 0x000a00a6, 0x00000004 },
211 { 0x20007000, 0000000000 },
212 { 0x01200000, 0x00000002 },
213 { 0x20077000, 0x00000002 },
214 { 0x01200000, 0x00000002 },
215 { 0x20007000, 0000000000 },
216 { 0x00061000, 0x00000002 },
217 { 0x0120751b, 0x00000002 },
218 { 0x8040750a, 0x00000002 },
219 { 0x8040750b, 0x00000002 },
220 { 0x00110000, 0x00000002 },
221 { 0x000380dd, 0x00000002 },
222 { 0x000000bd, 0x0000001c },
223 { 0x00061096, 0x00000018 },
224 { 0x844075bd, 0x00000002 },
225 { 0x00061095, 0x00000018 },
226 { 0x840075bb, 0x00000002 },
227 { 0x00061096, 0x00000018 },
228 { 0x844075bc, 0x00000002 },
229 { 0x000000c0, 0x00000004 },
230 { 0x804075bd, 0x00000002 },
231 { 0x800075bb, 0x00000002 },
232 { 0x804075bc, 0x00000002 },
233 { 0x00108000, 0x00000002 },
234 { 0x01400000, 0x00000002 },
235 { 0x006000c4, 0x0000000c },
236 { 0x20c07000, 0x00000020 },
237 { 0x000000c6, 0x00000012 },
238 { 0x00800000, 0x00000006 },
239 { 0x0080751d, 0x00000006 },
240 { 0x000025bb, 0x00000002 },
241 { 0x000040c0, 0x00000004 },
242 { 0x0000775c, 0x00000002 },
243 { 0x00a05000, 0x00000002 },
244 { 0x00661000, 0x00000002 },
245 { 0x0460275d, 0x00000020 },
246 { 0x00004000, 0000000000 },
247 { 0x00007999, 0x00000002 },
248 { 0x00a05000, 0x00000002 },
249 { 0x00661000, 0x00000002 },
250 { 0x0460299b, 0x00000020 },
251 { 0x00004000, 0000000000 },
252 { 0x01e00830, 0x00000002 },
253 { 0x21007000, 0000000000 },
254 { 0x00005000, 0x00000002 },
255 { 0x00038042, 0x00000002 },
256 { 0x040025e0, 0x00000002 },
257 { 0x000075e1, 0000000000 },
258 { 0x00000001, 0000000000 },
259 { 0x000380d9, 0x00000002 },
260 { 0x04007394, 0000000000 },
261 { 0000000000, 0000000000 },
262 { 0000000000, 0000000000 },
263 { 0000000000, 0000000000 },
264 { 0000000000, 0000000000 },
265 { 0000000000, 0000000000 },
266 { 0000000000, 0000000000 },
267 { 0000000000, 0000000000 },
268 { 0000000000, 0000000000 },
269 { 0000000000, 0000000000 },
270 { 0000000000, 0000000000 },
271 { 0000000000, 0000000000 },
272 { 0000000000, 0000000000 },
273 { 0000000000, 0000000000 },
274 { 0000000000, 0000000000 },
275 { 0000000000, 0000000000 },
276 { 0000000000, 0000000000 },
277 { 0000000000, 0000000000 },
278 { 0000000000, 0000000000 },
279 { 0000000000, 0000000000 },
280 { 0000000000, 0000000000 },
281 { 0000000000, 0000000000 },
282 { 0000000000, 0000000000 },
283 { 0000000000, 0000000000 },
284 { 0000000000, 0000000000 },
285 { 0000000000, 0000000000 },
286 { 0000000000, 0000000000 },
287 { 0000000000, 0000000000 },
288 { 0000000000, 0000000000 },
289 { 0000000000, 0000000000 },
290 { 0000000000, 0000000000 },
291 { 0000000000, 0000000000 },
292 { 0000000000, 0000000000 },
293 { 0000000000, 0000000000 },
294 { 0000000000, 0000000000 },
295 { 0000000000, 0000000000 },
296 { 0000000000, 0000000000 },
300 static u32 radeon_cp_microcode[][2] = {
301 { 0x21007000, 0000000000 },
302 { 0x20007000, 0000000000 },
303 { 0x000000b4, 0x00000004 },
304 { 0x000000b8, 0x00000004 },
305 { 0x6f5b4d4c, 0000000000 },
306 { 0x4c4c427f, 0000000000 },
307 { 0x5b568a92, 0000000000 },
308 { 0x4ca09c6d, 0000000000 },
309 { 0xad4c4c4c, 0000000000 },
310 { 0x4ce1af3d, 0000000000 },
311 { 0xd8afafaf, 0000000000 },
312 { 0xd64c4cdc, 0000000000 },
313 { 0x4cd10d10, 0000000000 },
314 { 0x000f0000, 0x00000016 },
315 { 0x362f242d, 0000000000 },
316 { 0x00000012, 0x00000004 },
317 { 0x000f0000, 0x00000016 },
318 { 0x362f282d, 0000000000 },
319 { 0x000380e7, 0x00000002 },
320 { 0x04002c97, 0x00000002 },
321 { 0x000f0001, 0x00000016 },
322 { 0x333a3730, 0000000000 },
323 { 0x000077ef, 0x00000002 },
324 { 0x00061000, 0x00000002 },
325 { 0x00000021, 0x0000001a },
326 { 0x00004000, 0x0000001e },
327 { 0x00061000, 0x00000002 },
328 { 0x00000021, 0x0000001a },
329 { 0x00004000, 0x0000001e },
330 { 0x00061000, 0x00000002 },
331 { 0x00000021, 0x0000001a },
332 { 0x00004000, 0x0000001e },
333 { 0x00000017, 0x00000004 },
334 { 0x0003802b, 0x00000002 },
335 { 0x040067e0, 0x00000002 },
336 { 0x00000017, 0x00000004 },
337 { 0x000077e0, 0x00000002 },
338 { 0x00065000, 0x00000002 },
339 { 0x000037e1, 0x00000002 },
340 { 0x040067e1, 0x00000006 },
341 { 0x000077e0, 0x00000002 },
342 { 0x000077e1, 0x00000002 },
343 { 0x000077e1, 0x00000006 },
344 { 0xffffffff, 0000000000 },
345 { 0x10000000, 0000000000 },
346 { 0x0003802b, 0x00000002 },
347 { 0x040067e0, 0x00000006 },
348 { 0x00007675, 0x00000002 },
349 { 0x00007676, 0x00000002 },
350 { 0x00007677, 0x00000002 },
351 { 0x00007678, 0x00000006 },
352 { 0x0003802c, 0x00000002 },
353 { 0x04002676, 0x00000002 },
354 { 0x00007677, 0x00000002 },
355 { 0x00007678, 0x00000006 },
356 { 0x0000002f, 0x00000018 },
357 { 0x0000002f, 0x00000018 },
358 { 0000000000, 0x00000006 },
359 { 0x00000030, 0x00000018 },
360 { 0x00000030, 0x00000018 },
361 { 0000000000, 0x00000006 },
362 { 0x01605000, 0x00000002 },
363 { 0x00065000, 0x00000002 },
364 { 0x00098000, 0x00000002 },
365 { 0x00061000, 0x00000002 },
366 { 0x64c0603e, 0x00000004 },
367 { 0x000380e6, 0x00000002 },
368 { 0x040025c5, 0x00000002 },
369 { 0x00080000, 0x00000016 },
370 { 0000000000, 0000000000 },
371 { 0x0400251d, 0x00000002 },
372 { 0x00007580, 0x00000002 },
373 { 0x00067581, 0x00000002 },
374 { 0x04002580, 0x00000002 },
375 { 0x00067581, 0x00000002 },
376 { 0x00000049, 0x00000004 },
377 { 0x00005000, 0000000000 },
378 { 0x000380e6, 0x00000002 },
379 { 0x040025c5, 0x00000002 },
380 { 0x00061000, 0x00000002 },
381 { 0x0000750e, 0x00000002 },
382 { 0x00019000, 0x00000002 },
383 { 0x00011055, 0x00000014 },
384 { 0x00000055, 0x00000012 },
385 { 0x0400250f, 0x00000002 },
386 { 0x0000504f, 0x00000004 },
387 { 0x000380e6, 0x00000002 },
388 { 0x040025c5, 0x00000002 },
389 { 0x00007565, 0x00000002 },
390 { 0x00007566, 0x00000002 },
391 { 0x00000058, 0x00000004 },
392 { 0x000380e6, 0x00000002 },
393 { 0x040025c5, 0x00000002 },
394 { 0x01e655b4, 0x00000002 },
395 { 0x4401b0e4, 0x00000002 },
396 { 0x01c110e4, 0x00000002 },
397 { 0x26667066, 0x00000018 },
398 { 0x040c2565, 0x00000002 },
399 { 0x00000066, 0x00000018 },
400 { 0x04002564, 0x00000002 },
401 { 0x00007566, 0x00000002 },
402 { 0x0000005d, 0x00000004 },
403 { 0x00401069, 0x00000008 },
404 { 0x00101000, 0x00000002 },
405 { 0x000d80ff, 0x00000002 },
406 { 0x0080006c, 0x00000008 },
407 { 0x000f9000, 0x00000002 },
408 { 0x000e00ff, 0x00000002 },
409 { 0000000000, 0x00000006 },
410 { 0x0000008f, 0x00000018 },
411 { 0x0000005b, 0x00000004 },
412 { 0x000380e6, 0x00000002 },
413 { 0x040025c5, 0x00000002 },
414 { 0x00007576, 0x00000002 },
415 { 0x00065000, 0x00000002 },
416 { 0x00009000, 0x00000002 },
417 { 0x00041000, 0x00000002 },
418 { 0x0c00350e, 0x00000002 },
419 { 0x00049000, 0x00000002 },
420 { 0x00051000, 0x00000002 },
421 { 0x01e785f8, 0x00000002 },
422 { 0x00200000, 0x00000002 },
423 { 0x0060007e, 0x0000000c },
424 { 0x00007563, 0x00000002 },
425 { 0x006075f0, 0x00000021 },
426 { 0x20007073, 0x00000004 },
427 { 0x00005073, 0x00000004 },
428 { 0x000380e6, 0x00000002 },
429 { 0x040025c5, 0x00000002 },
430 { 0x00007576, 0x00000002 },
431 { 0x00007577, 0x00000002 },
432 { 0x0000750e, 0x00000002 },
433 { 0x0000750f, 0x00000002 },
434 { 0x00a05000, 0x00000002 },
435 { 0x00600083, 0x0000000c },
436 { 0x006075f0, 0x00000021 },
437 { 0x000075f8, 0x00000002 },
438 { 0x00000083, 0x00000004 },
439 { 0x000a750e, 0x00000002 },
440 { 0x000380e6, 0x00000002 },
441 { 0x040025c5, 0x00000002 },
442 { 0x0020750f, 0x00000002 },
443 { 0x00600086, 0x00000004 },
444 { 0x00007570, 0x00000002 },
445 { 0x00007571, 0x00000002 },
446 { 0x00007572, 0x00000006 },
447 { 0x000380e6, 0x00000002 },
448 { 0x040025c5, 0x00000002 },
449 { 0x00005000, 0x00000002 },
450 { 0x00a05000, 0x00000002 },
451 { 0x00007568, 0x00000002 },
452 { 0x00061000, 0x00000002 },
453 { 0x00000095, 0x0000000c },
454 { 0x00058000, 0x00000002 },
455 { 0x0c607562, 0x00000002 },
456 { 0x00000097, 0x00000004 },
457 { 0x000380e6, 0x00000002 },
458 { 0x040025c5, 0x00000002 },
459 { 0x00600096, 0x00000004 },
460 { 0x400070e5, 0000000000 },
461 { 0x000380e6, 0x00000002 },
462 { 0x040025c5, 0x00000002 },
463 { 0x000380e5, 0x00000002 },
464 { 0x000000a8, 0x0000001c },
465 { 0x000650aa, 0x00000018 },
466 { 0x040025bb, 0x00000002 },
467 { 0x000610ab, 0x00000018 },
468 { 0x040075bc, 0000000000 },
469 { 0x000075bb, 0x00000002 },
470 { 0x000075bc, 0000000000 },
471 { 0x00090000, 0x00000006 },
472 { 0x00090000, 0x00000002 },
473 { 0x000d8002, 0x00000006 },
474 { 0x00007832, 0x00000002 },
475 { 0x00005000, 0x00000002 },
476 { 0x000380e7, 0x00000002 },
477 { 0x04002c97, 0x00000002 },
478 { 0x00007820, 0x00000002 },
479 { 0x00007821, 0x00000002 },
480 { 0x00007800, 0000000000 },
481 { 0x01200000, 0x00000002 },
482 { 0x20077000, 0x00000002 },
483 { 0x01200000, 0x00000002 },
484 { 0x20007000, 0x00000002 },
485 { 0x00061000, 0x00000002 },
486 { 0x0120751b, 0x00000002 },
487 { 0x8040750a, 0x00000002 },
488 { 0x8040750b, 0x00000002 },
489 { 0x00110000, 0x00000002 },
490 { 0x000380e5, 0x00000002 },
491 { 0x000000c6, 0x0000001c },
492 { 0x000610ab, 0x00000018 },
493 { 0x844075bd, 0x00000002 },
494 { 0x000610aa, 0x00000018 },
495 { 0x840075bb, 0x00000002 },
496 { 0x000610ab, 0x00000018 },
497 { 0x844075bc, 0x00000002 },
498 { 0x000000c9, 0x00000004 },
499 { 0x804075bd, 0x00000002 },
500 { 0x800075bb, 0x00000002 },
501 { 0x804075bc, 0x00000002 },
502 { 0x00108000, 0x00000002 },
503 { 0x01400000, 0x00000002 },
504 { 0x006000cd, 0x0000000c },
505 { 0x20c07000, 0x00000020 },
506 { 0x000000cf, 0x00000012 },
507 { 0x00800000, 0x00000006 },
508 { 0x0080751d, 0x00000006 },
509 { 0000000000, 0000000000 },
510 { 0x0000775c, 0x00000002 },
511 { 0x00a05000, 0x00000002 },
512 { 0x00661000, 0x00000002 },
513 { 0x0460275d, 0x00000020 },
514 { 0x00004000, 0000000000 },
515 { 0x01e00830, 0x00000002 },
516 { 0x21007000, 0000000000 },
517 { 0x6464614d, 0000000000 },
518 { 0x69687420, 0000000000 },
519 { 0x00000073, 0000000000 },
520 { 0000000000, 0000000000 },
521 { 0x00005000, 0x00000002 },
522 { 0x000380d0, 0x00000002 },
523 { 0x040025e0, 0x00000002 },
524 { 0x000075e1, 0000000000 },
525 { 0x00000001, 0000000000 },
526 { 0x000380e0, 0x00000002 },
527 { 0x04002394, 0x00000002 },
528 { 0x00005000, 0000000000 },
529 { 0000000000, 0000000000 },
530 { 0000000000, 0000000000 },
531 { 0x00000008, 0000000000 },
532 { 0x00000004, 0000000000 },
533 { 0000000000, 0000000000 },
534 { 0000000000, 0000000000 },
535 { 0000000000, 0000000000 },
536 { 0000000000, 0000000000 },
537 { 0000000000, 0000000000 },
538 { 0000000000, 0000000000 },
539 { 0000000000, 0000000000 },
540 { 0000000000, 0000000000 },
541 { 0000000000, 0000000000 },
542 { 0000000000, 0000000000 },
543 { 0000000000, 0000000000 },
544 { 0000000000, 0000000000 },
545 { 0000000000, 0000000000 },
546 { 0000000000, 0000000000 },
547 { 0000000000, 0000000000 },
548 { 0000000000, 0000000000 },
549 { 0000000000, 0000000000 },
550 { 0000000000, 0000000000 },
551 { 0000000000, 0000000000 },
552 { 0000000000, 0000000000 },
553 { 0000000000, 0000000000 },
554 { 0000000000, 0000000000 },
555 { 0000000000, 0000000000 },
556 { 0000000000, 0000000000 },
560 int RADEON_READ_PLL(drm_device_t *dev, int addr)
562 drm_radeon_private_t *dev_priv = dev->dev_private;
564 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
565 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
568 #if RADEON_FIFO_DEBUG
569 static void radeon_status( drm_radeon_private_t *dev_priv )
571 printk( "%s:\n", __FUNCTION__ );
572 printk( "RBBM_STATUS = 0x%08x\n",
573 (unsigned int)RADEON_READ( RADEON_RBBM_STATUS ) );
574 printk( "CP_RB_RTPR = 0x%08x\n",
575 (unsigned int)RADEON_READ( RADEON_CP_RB_RPTR ) );
576 printk( "CP_RB_WTPR = 0x%08x\n",
577 (unsigned int)RADEON_READ( RADEON_CP_RB_WPTR ) );
578 printk( "AIC_CNTL = 0x%08x\n",
579 (unsigned int)RADEON_READ( RADEON_AIC_CNTL ) );
580 printk( "AIC_STAT = 0x%08x\n",
581 (unsigned int)RADEON_READ( RADEON_AIC_STAT ) );
582 printk( "AIC_PT_BASE = 0x%08x\n",
583 (unsigned int)RADEON_READ( RADEON_AIC_PT_BASE ) );
584 printk( "TLB_ADDR = 0x%08x\n",
585 (unsigned int)RADEON_READ( RADEON_AIC_TLB_ADDR ) );
586 printk( "TLB_DATA = 0x%08x\n",
587 (unsigned int)RADEON_READ( RADEON_AIC_TLB_DATA ) );
592 /* ================================================================
593 * Engine, FIFO control
596 static int radeon_do_pixcache_flush( drm_radeon_private_t *dev_priv )
601 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
603 tmp = RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT );
604 tmp |= RADEON_RB2D_DC_FLUSH_ALL;
605 RADEON_WRITE( RADEON_RB2D_DSTCACHE_CTLSTAT, tmp );
607 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
608 if ( !(RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT )
609 & RADEON_RB2D_DC_BUSY) ) {
615 #if RADEON_FIFO_DEBUG
616 DRM_ERROR( "failed!\n" );
617 radeon_status( dev_priv );
619 return DRM_ERR(EBUSY);
622 static int radeon_do_wait_for_fifo( drm_radeon_private_t *dev_priv,
627 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
629 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
630 int slots = ( RADEON_READ( RADEON_RBBM_STATUS )
631 & RADEON_RBBM_FIFOCNT_MASK );
632 if ( slots >= entries ) return 0;
636 #if RADEON_FIFO_DEBUG
637 DRM_ERROR( "failed!\n" );
638 radeon_status( dev_priv );
640 return DRM_ERR(EBUSY);
643 static int radeon_do_wait_for_idle( drm_radeon_private_t *dev_priv )
647 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
649 ret = radeon_do_wait_for_fifo( dev_priv, 64 );
650 if ( ret ) return ret;
652 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
653 if ( !(RADEON_READ( RADEON_RBBM_STATUS )
654 & RADEON_RBBM_ACTIVE) ) {
655 radeon_do_pixcache_flush( dev_priv );
661 #if RADEON_FIFO_DEBUG
662 DRM_ERROR( "failed!\n" );
663 radeon_status( dev_priv );
665 return DRM_ERR(EBUSY);
669 /* ================================================================
670 * CP control, initialization
673 /* Load the microcode for the CP */
674 static void radeon_cp_load_microcode( drm_radeon_private_t *dev_priv )
679 radeon_do_wait_for_idle( dev_priv );
681 RADEON_WRITE( RADEON_CP_ME_RAM_ADDR, 0 );
683 if (dev_priv->is_r200)
685 DRM_INFO("Loading R200 Microcode\n");
686 for ( i = 0 ; i < 256 ; i++ )
688 RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
689 R200_cp_microcode[i][1] );
690 RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
691 R200_cp_microcode[i][0] );
696 for ( i = 0 ; i < 256 ; i++ ) {
697 RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
698 radeon_cp_microcode[i][1] );
699 RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
700 radeon_cp_microcode[i][0] );
705 /* Flush any pending commands to the CP. This should only be used just
706 * prior to a wait for idle, as it informs the engine that the command
709 static void radeon_do_cp_flush( drm_radeon_private_t *dev_priv )
715 tmp = RADEON_READ( RADEON_CP_RB_WPTR ) | (1 << 31);
716 RADEON_WRITE( RADEON_CP_RB_WPTR, tmp );
720 /* Wait for the CP to go idle.
722 int radeon_do_cp_idle( drm_radeon_private_t *dev_priv )
729 RADEON_PURGE_CACHE();
730 RADEON_PURGE_ZCACHE();
731 RADEON_WAIT_UNTIL_IDLE();
736 return radeon_do_wait_for_idle( dev_priv );
739 /* Start the Command Processor.
741 static void radeon_do_cp_start( drm_radeon_private_t *dev_priv )
746 radeon_do_wait_for_idle( dev_priv );
748 RADEON_WRITE( RADEON_CP_CSQ_CNTL, dev_priv->cp_mode );
750 dev_priv->cp_running = 1;
754 RADEON_PURGE_CACHE();
755 RADEON_PURGE_ZCACHE();
756 RADEON_WAIT_UNTIL_IDLE();
762 /* Reset the Command Processor. This will not flush any pending
763 * commands, so you must wait for the CP command stream to complete
764 * before calling this routine.
766 static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv )
771 cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
772 RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
773 SET_RING_HEAD( dev_priv, cur_read_ptr );
774 dev_priv->ring.tail = cur_read_ptr;
777 /* Stop the Command Processor. This will not flush any pending
778 * commands, so you must flush the command stream and wait for the CP
779 * to go idle before calling this routine.
781 static void radeon_do_cp_stop( drm_radeon_private_t *dev_priv )
785 RADEON_WRITE( RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS );
787 dev_priv->cp_running = 0;
790 /* Reset the engine. This will stop the CP if it is running.
792 static int radeon_do_engine_reset( drm_device_t *dev )
794 drm_radeon_private_t *dev_priv = dev->dev_private;
795 u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
798 radeon_do_pixcache_flush( dev_priv );
800 clock_cntl_index = RADEON_READ( RADEON_CLOCK_CNTL_INDEX );
801 mclk_cntl = RADEON_READ_PLL( dev, RADEON_MCLK_CNTL );
803 RADEON_WRITE_PLL( RADEON_MCLK_CNTL, ( mclk_cntl |
804 RADEON_FORCEON_MCLKA |
805 RADEON_FORCEON_MCLKB |
806 RADEON_FORCEON_YCLKA |
807 RADEON_FORCEON_YCLKB |
809 RADEON_FORCEON_AIC ) );
811 rbbm_soft_reset = RADEON_READ( RADEON_RBBM_SOFT_RESET );
813 RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset |
814 RADEON_SOFT_RESET_CP |
815 RADEON_SOFT_RESET_HI |
816 RADEON_SOFT_RESET_SE |
817 RADEON_SOFT_RESET_RE |
818 RADEON_SOFT_RESET_PP |
819 RADEON_SOFT_RESET_E2 |
820 RADEON_SOFT_RESET_RB ) );
821 RADEON_READ( RADEON_RBBM_SOFT_RESET );
822 RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset &
823 ~( RADEON_SOFT_RESET_CP |
824 RADEON_SOFT_RESET_HI |
825 RADEON_SOFT_RESET_SE |
826 RADEON_SOFT_RESET_RE |
827 RADEON_SOFT_RESET_PP |
828 RADEON_SOFT_RESET_E2 |
829 RADEON_SOFT_RESET_RB ) ) );
830 RADEON_READ( RADEON_RBBM_SOFT_RESET );
833 RADEON_WRITE_PLL( RADEON_MCLK_CNTL, mclk_cntl );
834 RADEON_WRITE( RADEON_CLOCK_CNTL_INDEX, clock_cntl_index );
835 RADEON_WRITE( RADEON_RBBM_SOFT_RESET, rbbm_soft_reset );
837 /* Reset the CP ring */
838 radeon_do_cp_reset( dev_priv );
840 /* The CP is no longer running after an engine reset */
841 dev_priv->cp_running = 0;
843 /* Reset any pending vertex, indirect buffers */
844 radeon_freelist_reset( dev );
849 static void radeon_cp_init_ring_buffer( drm_device_t *dev,
850 drm_radeon_private_t *dev_priv )
852 u32 ring_start, cur_read_ptr;
855 /* Initialize the memory controller */
856 RADEON_WRITE( RADEON_MC_FB_LOCATION,
857 ( ( dev_priv->gart_vm_start - 1 ) & 0xffff0000 )
858 | ( dev_priv->fb_location >> 16 ) );
861 if (dev_priv->flags & CHIP_IS_AGP) {
862 RADEON_WRITE( RADEON_MC_AGP_LOCATION,
863 (((dev_priv->gart_vm_start - 1 +
864 dev_priv->gart_size) & 0xffff0000) |
865 (dev_priv->gart_vm_start >> 16)) );
867 ring_start = (dev_priv->cp_ring->offset
869 + dev_priv->gart_vm_start);
872 ring_start = (dev_priv->cp_ring->offset
874 + dev_priv->gart_vm_start);
876 RADEON_WRITE( RADEON_CP_RB_BASE, ring_start );
878 /* Set the write pointer delay */
879 RADEON_WRITE( RADEON_CP_RB_WPTR_DELAY, 0 );
881 /* Initialize the ring buffer's read and write pointers */
882 cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
883 RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
884 SET_RING_HEAD( dev_priv, cur_read_ptr );
885 dev_priv->ring.tail = cur_read_ptr;
888 if (dev_priv->flags & CHIP_IS_AGP) {
889 /* set RADEON_AGP_BASE here instead of relying on X from user space */
890 RADEON_WRITE( RADEON_AGP_BASE, (unsigned int)dev->agp->base );
891 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
892 dev_priv->ring_rptr->offset
894 + dev_priv->gart_vm_start);
898 drm_sg_mem_t *entry = dev->sg;
899 unsigned long tmp_ofs, page_ofs;
901 tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle;
902 page_ofs = tmp_ofs >> PAGE_SHIFT;
904 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
905 entry->busaddr[page_ofs]);
906 DRM_DEBUG( "ring rptr: offset=0x%08lx handle=0x%08lx\n",
907 (unsigned long) entry->busaddr[page_ofs],
908 entry->handle + tmp_ofs );
911 /* Initialize the scratch register pointer. This will cause
912 * the scratch register values to be written out to memory
913 * whenever they are updated.
915 * We simply put this behind the ring read pointer, this works
916 * with PCI GART as well as (whatever kind of) AGP GART
918 RADEON_WRITE( RADEON_SCRATCH_ADDR, RADEON_READ( RADEON_CP_RB_RPTR_ADDR )
919 + RADEON_SCRATCH_REG_OFFSET );
921 dev_priv->scratch = ((__volatile__ u32 *)
922 dev_priv->ring_rptr->handle +
923 (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
925 RADEON_WRITE( RADEON_SCRATCH_UMSK, 0x7 );
927 /* Writeback doesn't seem to work everywhere, test it first */
928 DRM_WRITE32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0 );
929 RADEON_WRITE( RADEON_SCRATCH_REG1, 0xdeadbeef );
931 for ( tmp = 0 ; tmp < dev_priv->usec_timeout ; tmp++ ) {
932 if ( DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1) ) == 0xdeadbeef )
937 if ( tmp < dev_priv->usec_timeout ) {
938 dev_priv->writeback_works = 1;
939 DRM_DEBUG( "writeback test succeeded, tmp=%d\n", tmp );
941 dev_priv->writeback_works = 0;
942 DRM_DEBUG( "writeback test failed\n" );
945 dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
946 RADEON_WRITE( RADEON_LAST_FRAME_REG,
947 dev_priv->sarea_priv->last_frame );
949 dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
950 RADEON_WRITE( RADEON_LAST_DISPATCH_REG,
951 dev_priv->sarea_priv->last_dispatch );
953 dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
954 RADEON_WRITE( RADEON_LAST_CLEAR_REG,
955 dev_priv->sarea_priv->last_clear );
957 /* Set ring buffer size */
959 RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT );
961 RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw );
964 radeon_do_wait_for_idle( dev_priv );
966 /* Turn on bus mastering */
967 tmp = RADEON_READ( RADEON_BUS_CNTL ) & ~RADEON_BUS_MASTER_DIS;
968 RADEON_WRITE( RADEON_BUS_CNTL, tmp );
970 /* Sync everything up */
971 RADEON_WRITE( RADEON_ISYNC_CNTL,
972 (RADEON_ISYNC_ANY2D_IDLE3D |
973 RADEON_ISYNC_ANY3D_IDLE2D |
974 RADEON_ISYNC_WAIT_IDLEGUI |
975 RADEON_ISYNC_CPSCRATCH_IDLEGUI) );
978 /* Enable or disable PCI GART on the chip */
979 static void radeon_set_pcigart( drm_radeon_private_t *dev_priv, int on )
981 u32 tmp = RADEON_READ( RADEON_AIC_CNTL );
984 RADEON_WRITE( RADEON_AIC_CNTL, tmp | RADEON_PCIGART_TRANSLATE_EN );
986 /* set PCI GART page-table base address
988 RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart );
990 /* set address range for PCI address translate
992 RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start );
993 RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
994 + dev_priv->gart_size - 1);
996 /* Turn off AGP aperture -- is this required for PCI GART?
998 RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
999 RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
1001 RADEON_WRITE( RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN );
1005 static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
1007 drm_radeon_private_t *dev_priv = dev->dev_private;
1010 if ( (!(dev_priv->flags & CHIP_IS_AGP)) && !dev->sg ) {
1011 DRM_ERROR( "PCI GART memory not allocated!\n" );
1012 radeon_do_cleanup_cp(dev);
1013 return DRM_ERR(EINVAL);
1016 dev_priv->usec_timeout = init->usec_timeout;
1017 if ( dev_priv->usec_timeout < 1 ||
1018 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT ) {
1019 DRM_DEBUG( "TIMEOUT problem!\n" );
1020 radeon_do_cleanup_cp(dev);
1021 return DRM_ERR(EINVAL);
1024 dev_priv->is_r200 = (init->func == RADEON_INIT_R200_CP);
1025 dev_priv->do_boxes = 0;
1026 dev_priv->cp_mode = init->cp_mode;
1028 /* We don't support anything other than bus-mastering ring mode,
1029 * but the ring can be in either AGP or PCI space for the ring
1032 if ( ( init->cp_mode != RADEON_CSQ_PRIBM_INDDIS ) &&
1033 ( init->cp_mode != RADEON_CSQ_PRIBM_INDBM ) ) {
1034 DRM_DEBUG( "BAD cp_mode (%x)!\n", init->cp_mode );
1035 radeon_do_cleanup_cp(dev);
1036 return DRM_ERR(EINVAL);
1039 switch ( init->fb_bpp ) {
1041 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1045 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1048 dev_priv->front_offset = init->front_offset;
1049 dev_priv->front_pitch = init->front_pitch;
1050 dev_priv->back_offset = init->back_offset;
1051 dev_priv->back_pitch = init->back_pitch;
1053 switch ( init->depth_bpp ) {
1055 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1059 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1062 dev_priv->depth_offset = init->depth_offset;
1063 dev_priv->depth_pitch = init->depth_pitch;
1065 /* Hardware state for depth clears. Remove this if/when we no
1066 * longer clear the depth buffer with a 3D rectangle. Hard-code
1067 * all values to prevent unwanted 3D state from slipping through
1068 * and screwing with the clear operation.
1070 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1071 (dev_priv->color_fmt << 10) |
1074 dev_priv->depth_clear.rb3d_zstencilcntl =
1075 (dev_priv->depth_fmt |
1076 RADEON_Z_TEST_ALWAYS |
1077 RADEON_STENCIL_TEST_ALWAYS |
1078 RADEON_STENCIL_S_FAIL_REPLACE |
1079 RADEON_STENCIL_ZPASS_REPLACE |
1080 RADEON_STENCIL_ZFAIL_REPLACE |
1081 RADEON_Z_WRITE_ENABLE);
1083 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1084 RADEON_BFACE_SOLID |
1085 RADEON_FFACE_SOLID |
1086 RADEON_FLAT_SHADE_VTX_LAST |
1087 RADEON_DIFFUSE_SHADE_FLAT |
1088 RADEON_ALPHA_SHADE_FLAT |
1089 RADEON_SPECULAR_SHADE_FLAT |
1090 RADEON_FOG_SHADE_FLAT |
1091 RADEON_VTX_PIX_CENTER_OGL |
1092 RADEON_ROUND_MODE_TRUNC |
1093 RADEON_ROUND_PREC_8TH_PIX);
1097 dev_priv->fb_offset = init->fb_offset;
1098 dev_priv->mmio_offset = init->mmio_offset;
1099 dev_priv->ring_offset = init->ring_offset;
1100 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1101 dev_priv->buffers_offset = init->buffers_offset;
1102 dev_priv->gart_textures_offset = init->gart_textures_offset;
1104 if(!dev_priv->sarea) {
1105 DRM_ERROR("could not find sarea!\n");
1106 radeon_do_cleanup_cp(dev);
1107 return DRM_ERR(EINVAL);
1110 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
1111 if(!dev_priv->mmio) {
1112 DRM_ERROR("could not find mmio region!\n");
1113 radeon_do_cleanup_cp(dev);
1114 return DRM_ERR(EINVAL);
1116 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1117 if(!dev_priv->cp_ring) {
1118 DRM_ERROR("could not find cp ring region!\n");
1119 radeon_do_cleanup_cp(dev);
1120 return DRM_ERR(EINVAL);
1122 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1123 if(!dev_priv->ring_rptr) {
1124 DRM_ERROR("could not find ring read pointer!\n");
1125 radeon_do_cleanup_cp(dev);
1126 return DRM_ERR(EINVAL);
1128 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1129 if(!dev->agp_buffer_map) {
1130 DRM_ERROR("could not find dma buffer region!\n");
1131 radeon_do_cleanup_cp(dev);
1132 return DRM_ERR(EINVAL);
1135 if ( init->gart_textures_offset ) {
1136 dev_priv->gart_textures = drm_core_findmap(dev, init->gart_textures_offset);
1137 if ( !dev_priv->gart_textures ) {
1138 DRM_ERROR("could not find GART texture region!\n");
1139 radeon_do_cleanup_cp(dev);
1140 return DRM_ERR(EINVAL);
1144 dev_priv->sarea_priv =
1145 (drm_radeon_sarea_t *)((u8 *)dev_priv->sarea->handle +
1146 init->sarea_priv_offset);
1149 if ( dev_priv->flags & CHIP_IS_AGP ) {
1150 drm_core_ioremap( dev_priv->cp_ring, dev );
1151 drm_core_ioremap( dev_priv->ring_rptr, dev );
1152 drm_core_ioremap( dev->agp_buffer_map, dev );
1153 if(!dev_priv->cp_ring->handle ||
1154 !dev_priv->ring_rptr->handle ||
1155 !dev->agp_buffer_map->handle) {
1156 DRM_ERROR("could not find ioremap agp regions!\n");
1157 radeon_do_cleanup_cp(dev);
1158 return DRM_ERR(EINVAL);
1163 dev_priv->cp_ring->handle =
1164 (void *)dev_priv->cp_ring->offset;
1165 dev_priv->ring_rptr->handle =
1166 (void *)dev_priv->ring_rptr->offset;
1167 dev->agp_buffer_map->handle = (void *)dev->agp_buffer_map->offset;
1169 DRM_DEBUG( "dev_priv->cp_ring->handle %p\n",
1170 dev_priv->cp_ring->handle );
1171 DRM_DEBUG( "dev_priv->ring_rptr->handle %p\n",
1172 dev_priv->ring_rptr->handle );
1173 DRM_DEBUG( "dev->agp_buffer_map->handle %p\n",
1174 dev->agp_buffer_map->handle );
1177 dev_priv->fb_location = ( RADEON_READ( RADEON_MC_FB_LOCATION )
1180 dev_priv->front_pitch_offset = (((dev_priv->front_pitch/64) << 22) |
1181 ( ( dev_priv->front_offset
1182 + dev_priv->fb_location ) >> 10 ) );
1184 dev_priv->back_pitch_offset = (((dev_priv->back_pitch/64) << 22) |
1185 ( ( dev_priv->back_offset
1186 + dev_priv->fb_location ) >> 10 ) );
1188 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch/64) << 22) |
1189 ( ( dev_priv->depth_offset
1190 + dev_priv->fb_location ) >> 10 ) );
1193 dev_priv->gart_size = init->gart_size;
1194 dev_priv->gart_vm_start = dev_priv->fb_location
1195 + RADEON_READ( RADEON_CONFIG_APER_SIZE );
1198 if (dev_priv->flags & CHIP_IS_AGP)
1199 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1201 + dev_priv->gart_vm_start);
1204 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1206 + dev_priv->gart_vm_start);
1208 DRM_DEBUG( "dev_priv->gart_size %d\n",
1209 dev_priv->gart_size );
1210 DRM_DEBUG( "dev_priv->gart_vm_start 0x%x\n",
1211 dev_priv->gart_vm_start );
1212 DRM_DEBUG( "dev_priv->gart_buffers_offset 0x%lx\n",
1213 dev_priv->gart_buffers_offset );
1215 dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle;
1216 dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle
1217 + init->ring_size / sizeof(u32));
1218 dev_priv->ring.size = init->ring_size;
1219 dev_priv->ring.size_l2qw = DRM(order)( init->ring_size / 8 );
1221 dev_priv->ring.tail_mask =
1222 (dev_priv->ring.size / sizeof(u32)) - 1;
1224 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1227 if (dev_priv->flags & CHIP_IS_AGP) {
1228 /* Turn off PCI GART */
1229 radeon_set_pcigart( dev_priv, 0 );
1233 if (!DRM(ati_pcigart_init)( dev, &dev_priv->phys_pci_gart,
1234 &dev_priv->bus_pci_gart)) {
1235 DRM_ERROR( "failed to init PCI GART!\n" );
1236 radeon_do_cleanup_cp(dev);
1237 return DRM_ERR(ENOMEM);
1240 /* Turn on PCI GART */
1241 radeon_set_pcigart( dev_priv, 1 );
1244 radeon_cp_load_microcode( dev_priv );
1245 radeon_cp_init_ring_buffer( dev, dev_priv );
1247 dev_priv->last_buf = 0;
1249 radeon_do_engine_reset( dev );
1254 int radeon_do_cleanup_cp( drm_device_t *dev )
1256 drm_radeon_private_t *dev_priv = dev->dev_private;
1259 /* Make sure interrupts are disabled here because the uninstall ioctl
1260 * may not have been called from userspace and after dev_private
1261 * is freed, it's too late.
1263 if ( dev->irq_enabled ) DRM(irq_uninstall)(dev);
1266 if (dev_priv->flags & CHIP_IS_AGP) {
1267 if ( dev_priv->cp_ring != NULL ) {
1268 drm_core_ioremapfree( dev_priv->cp_ring, dev );
1269 dev_priv->cp_ring = NULL;
1271 if ( dev_priv->ring_rptr != NULL ) {
1272 drm_core_ioremapfree( dev_priv->ring_rptr, dev );
1273 dev_priv->ring_rptr = NULL;
1275 if ( dev->agp_buffer_map != NULL ) {
1276 drm_core_ioremapfree( dev->agp_buffer_map, dev );
1277 dev->agp_buffer_map = NULL;
1282 if (!DRM(ati_pcigart_cleanup)( dev,
1283 dev_priv->phys_pci_gart,
1284 dev_priv->bus_pci_gart ))
1285 DRM_ERROR( "failed to cleanup PCI GART!\n" );
1287 /* only clear to the start of flags */
1288 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1293 /* This code will reinit the Radeon CP hardware after a resume from disc.
1294 * AFAIK, it would be very difficult to pickle the state at suspend time, so
1295 * here we make sure that all Radeon hardware initialisation is re-done without
1296 * affecting running applications.
1298 * Charl P. Botha <http://cpbotha.net>
1300 static int radeon_do_resume_cp( drm_device_t *dev )
1302 drm_radeon_private_t *dev_priv = dev->dev_private;
1305 DRM_ERROR( "Called with no initialization\n" );
1306 return DRM_ERR( EINVAL );
1309 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1312 if (dev_priv->flags & CHIP_IS_AGP) {
1313 /* Turn off PCI GART */
1314 radeon_set_pcigart( dev_priv, 0 );
1318 /* Turn on PCI GART */
1319 radeon_set_pcigart( dev_priv, 1 );
1322 radeon_cp_load_microcode( dev_priv );
1323 radeon_cp_init_ring_buffer( dev, dev_priv );
1325 radeon_do_engine_reset( dev );
1327 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1333 int radeon_cp_init( DRM_IOCTL_ARGS )
1336 drm_radeon_init_t init;
1338 LOCK_TEST_WITH_RETURN( dev, filp );
1340 DRM_COPY_FROM_USER_IOCTL( init, (drm_radeon_init_t __user *)data, sizeof(init) );
1342 switch ( init.func ) {
1343 case RADEON_INIT_CP:
1344 case RADEON_INIT_R200_CP:
1345 return radeon_do_init_cp( dev, &init );
1346 case RADEON_CLEANUP_CP:
1347 return radeon_do_cleanup_cp( dev );
1350 return DRM_ERR(EINVAL);
1353 int radeon_cp_start( DRM_IOCTL_ARGS )
1356 drm_radeon_private_t *dev_priv = dev->dev_private;
1359 LOCK_TEST_WITH_RETURN( dev, filp );
1361 if ( dev_priv->cp_running ) {
1362 DRM_DEBUG( "%s while CP running\n", __FUNCTION__ );
1365 if ( dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS ) {
1366 DRM_DEBUG( "%s called with bogus CP mode (%d)\n",
1367 __FUNCTION__, dev_priv->cp_mode );
1371 radeon_do_cp_start( dev_priv );
1376 /* Stop the CP. The engine must have been idled before calling this
1379 int radeon_cp_stop( DRM_IOCTL_ARGS )
1382 drm_radeon_private_t *dev_priv = dev->dev_private;
1383 drm_radeon_cp_stop_t stop;
1387 LOCK_TEST_WITH_RETURN( dev, filp );
1389 DRM_COPY_FROM_USER_IOCTL( stop, (drm_radeon_cp_stop_t __user *)data, sizeof(stop) );
1391 if (!dev_priv->cp_running)
1394 /* Flush any pending CP commands. This ensures any outstanding
1395 * commands are exectuted by the engine before we turn it off.
1398 radeon_do_cp_flush( dev_priv );
1401 /* If we fail to make the engine go idle, we return an error
1402 * code so that the DRM ioctl wrapper can try again.
1405 ret = radeon_do_cp_idle( dev_priv );
1406 if ( ret ) return ret;
1409 /* Finally, we can turn off the CP. If the engine isn't idle,
1410 * we will get some dropped triangles as they won't be fully
1411 * rendered before the CP is shut down.
1413 radeon_do_cp_stop( dev_priv );
1415 /* Reset the engine */
1416 radeon_do_engine_reset( dev );
1422 void radeon_do_release( drm_device_t *dev )
1424 drm_radeon_private_t *dev_priv = dev->dev_private;
1429 if (dev_priv->cp_running) {
1431 while ((ret = radeon_do_cp_idle( dev_priv )) != 0) {
1432 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1436 tsleep(&ret, PZERO, "rdnrel", 1);
1439 radeon_do_cp_stop( dev_priv );
1440 radeon_do_engine_reset( dev );
1443 /* Disable *all* interrupts */
1444 if (dev_priv->mmio) /* remove this after permanent addmaps */
1445 RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );
1447 /* Free memory heap structures */
1448 radeon_mem_takedown( &(dev_priv->gart_heap) );
1449 radeon_mem_takedown( &(dev_priv->fb_heap) );
1451 /* deallocate kernel resources */
1452 radeon_do_cleanup_cp( dev );
1456 /* Just reset the CP ring. Called as part of an X Server engine reset.
1458 int radeon_cp_reset( DRM_IOCTL_ARGS )
1461 drm_radeon_private_t *dev_priv = dev->dev_private;
1464 LOCK_TEST_WITH_RETURN( dev, filp );
1467 DRM_DEBUG( "%s called before init done\n", __FUNCTION__ );
1468 return DRM_ERR(EINVAL);
1471 radeon_do_cp_reset( dev_priv );
1473 /* The CP is no longer running after an engine reset */
1474 dev_priv->cp_running = 0;
1479 int radeon_cp_idle( DRM_IOCTL_ARGS )
1482 drm_radeon_private_t *dev_priv = dev->dev_private;
1485 LOCK_TEST_WITH_RETURN( dev, filp );
1487 return radeon_do_cp_idle( dev_priv );
1490 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1492 int radeon_cp_resume( DRM_IOCTL_ARGS )
1496 return radeon_do_resume_cp(dev);
1500 int radeon_engine_reset( DRM_IOCTL_ARGS )
1505 LOCK_TEST_WITH_RETURN( dev, filp );
1507 return radeon_do_engine_reset( dev );
1511 /* ================================================================
1515 /* KW: Deprecated to say the least:
1517 int radeon_fullscreen( DRM_IOCTL_ARGS )
1523 /* ================================================================
1524 * Freelist management
1527 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1528 * bufs until freelist code is used. Note this hides a problem with
1529 * the scratch register * (used to keep track of last buffer
1530 * completed) being written to before * the last buffer has actually
1531 * completed rendering.
1533 * KW: It's also a good way to find free buffers quickly.
1535 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1536 * sleep. However, bugs in older versions of radeon_accel.c mean that
1537 * we essentially have to do this, else old clients will break.
1539 * However, it does leave open a potential deadlock where all the
1540 * buffers are held by other clients, which can't release them because
1541 * they can't get the lock.
1544 drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1546 drm_device_dma_t *dma = dev->dma;
1547 drm_radeon_private_t *dev_priv = dev->dev_private;
1548 drm_radeon_buf_priv_t *buf_priv;
1553 if ( ++dev_priv->last_buf >= dma->buf_count )
1554 dev_priv->last_buf = 0;
1556 start = dev_priv->last_buf;
1558 for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) {
1559 u32 done_age = GET_SCRATCH( 1 );
1560 DRM_DEBUG("done_age = %d\n",done_age);
1561 for ( i = start ; i < dma->buf_count ; i++ ) {
1562 buf = dma->buflist[i];
1563 buf_priv = buf->dev_private;
1564 if ( buf->filp == 0 || (buf->pending &&
1565 buf_priv->age <= done_age) ) {
1566 dev_priv->stats.requested_bufs++;
1575 dev_priv->stats.freelist_loops++;
1579 DRM_DEBUG( "returning NULL!\n" );
1583 drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1585 drm_device_dma_t *dma = dev->dma;
1586 drm_radeon_private_t *dev_priv = dev->dev_private;
1587 drm_radeon_buf_priv_t *buf_priv;
1591 u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1593 if ( ++dev_priv->last_buf >= dma->buf_count )
1594 dev_priv->last_buf = 0;
1596 start = dev_priv->last_buf;
1597 dev_priv->stats.freelist_loops++;
1599 for ( t = 0 ; t < 2 ; t++ ) {
1600 for ( i = start ; i < dma->buf_count ; i++ ) {
1601 buf = dma->buflist[i];
1602 buf_priv = buf->dev_private;
1603 if ( buf->filp == 0 || (buf->pending &&
1604 buf_priv->age <= done_age) ) {
1605 dev_priv->stats.requested_bufs++;
1617 void radeon_freelist_reset( drm_device_t *dev )
1619 drm_device_dma_t *dma = dev->dma;
1620 drm_radeon_private_t *dev_priv = dev->dev_private;
1623 dev_priv->last_buf = 0;
1624 for ( i = 0 ; i < dma->buf_count ; i++ ) {
1625 drm_buf_t *buf = dma->buflist[i];
1626 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1632 /* ================================================================
1633 * CP command submission
1636 int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n )
1638 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1640 u32 last_head = GET_RING_HEAD( dev_priv );
1642 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
1643 u32 head = GET_RING_HEAD( dev_priv );
1645 ring->space = (head - ring->tail) * sizeof(u32);
1646 if ( ring->space <= 0 )
1647 ring->space += ring->size;
1648 if ( ring->space > n )
1651 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1653 if (head != last_head)
1660 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1661 #if RADEON_FIFO_DEBUG
1662 radeon_status( dev_priv );
1663 DRM_ERROR( "failed!\n" );
1665 return DRM_ERR(EBUSY);
1668 static int radeon_cp_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d )
1673 for ( i = d->granted_count ; i < d->request_count ; i++ ) {
1674 buf = radeon_freelist_get( dev );
1675 if ( !buf ) return DRM_ERR(EBUSY); /* NOTE: broken client */
1679 if ( DRM_COPY_TO_USER( &d->request_indices[i], &buf->idx,
1680 sizeof(buf->idx) ) )
1681 return DRM_ERR(EFAULT);
1682 if ( DRM_COPY_TO_USER( &d->request_sizes[i], &buf->total,
1683 sizeof(buf->total) ) )
1684 return DRM_ERR(EFAULT);
1691 int radeon_cp_buffers( DRM_IOCTL_ARGS )
1694 drm_device_dma_t *dma = dev->dma;
1696 drm_dma_t __user *argp = (void __user *)data;
1699 LOCK_TEST_WITH_RETURN( dev, filp );
1701 DRM_COPY_FROM_USER_IOCTL( d, argp, sizeof(d) );
1703 /* Please don't send us buffers.
1705 if ( d.send_count != 0 ) {
1706 DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n",
1707 DRM_CURRENTPID, d.send_count );
1708 return DRM_ERR(EINVAL);
1711 /* We'll send you buffers.
1713 if ( d.request_count < 0 || d.request_count > dma->buf_count ) {
1714 DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n",
1715 DRM_CURRENTPID, d.request_count, dma->buf_count );
1716 return DRM_ERR(EINVAL);
1719 d.granted_count = 0;
1721 if ( d.request_count ) {
1722 ret = radeon_cp_get_buffers( filp, dev, &d );
1725 DRM_COPY_TO_USER_IOCTL( argp, d, sizeof(d) );
1730 /* Always create a map record for MMIO and FB memory, done from DRIVER_POSTINIT */
1731 int radeon_preinit( struct drm_device *dev, unsigned long flags )
1734 drm_radeon_private_t *dev_priv;
1737 dev_priv = DRM(alloc)( sizeof(drm_radeon_private_t), DRM_MEM_DRIVER );
1738 if ( dev_priv == NULL )
1739 return DRM_ERR(ENOMEM);
1741 memset( dev_priv, 0, sizeof(drm_radeon_private_t) );
1742 dev->dev_private = (void *)dev_priv;
1743 dev_priv->flags = flags;
1746 if( (ret = DRM(initmap)( dev, pci_resource_start( dev->pdev, 2 ),
1747 pci_resource_len( dev->pdev, 2 ), _DRM_REGISTERS, 0 )))
1751 if( (ret = DRM(initmap)( dev, pci_resource_start( dev->pdev, 0 ),
1752 pci_resource_len( dev->pdev, 0 ), _DRM_FRAME_BUFFER, _DRM_WRITE_COMBINING )))
1755 /* There are signatures in BIOS and PCI-SSID for a PCI card, but they are not very reliable.
1756 Following detection method works for all cards tested so far.
1757 Note, checking AGP_ENABLE bit after drmAgpEnable call can also give the correct result.
1758 However, calling drmAgpEnable on a PCI card can cause some strange lockup when the server
1761 pci_read_config_dword(dev->pdev, RADEON_AGP_COMMAND_PCI_CONFIG, &save);
1762 pci_write_config_dword(dev->pdev, RADEON_AGP_COMMAND_PCI_CONFIG, save | RADEON_AGP_ENABLE);
1763 pci_read_config_dword(dev->pdev, RADEON_AGP_COMMAND_PCI_CONFIG, &temp);
1764 if (temp & RADEON_AGP_ENABLE)
1765 dev_priv->flags |= CHIP_IS_AGP;
1766 DRM_DEBUG("%s card detected\n", ((dev_priv->flags & CHIP_IS_AGP) ? "AGP" : "PCI"));
1767 pci_write_config_dword(dev->pdev, RADEON_AGP_COMMAND_PCI_CONFIG, save);
1769 /* Check if we need a reset */
1770 if (!(dev_priv->mmio = drm_core_findmap(dev , pci_resource_start( dev->pdev, 2 ))))
1771 return DRM_ERR(ENOMEM);
1773 #if defined(__linux__)
1774 ret = radeon_create_i2c_busses(dev);
1779 int radeon_postinit( struct drm_device *dev, unsigned long flags )
1784 int radeon_postcleanup( struct drm_device *dev )
1786 drm_radeon_private_t *dev_priv = dev->dev_private;
1789 #if defined(__linux__)
1790 radeon_delete_i2c_busses(dev);
1792 DRM(free)( dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER );
1794 dev->dev_private = NULL;