shared-core/radeon_cp.c

   1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*-
   2  *
   3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11  * and/or sell copies of the Software, and to permit persons to whom the
  12  * Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the next
  15  * paragraph) shall be included in all copies or substantial portions of the
  16  * Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  21  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  22  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  23  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  24  * DEALINGS IN THE SOFTWARE.
  25  *
  26  * Authors:
  27  *    Kevin E. Martin <martin@valinux.com>
  28  *    Gareth Hughes <gareth@valinux.com>
  29  */
  30
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "radeon_drm.h"
  34 #include "radeon_drv.h"
  35
  36 #define RADEON_FIFO_DEBUG       0
  37
  38 /* CP microcode (from ATI) */
  39 static u32 R200_cp_microcode[][2] = {
  40         { 0x21007000, 0000000000 },
  41         { 0x20007000, 0000000000 },
  42         { 0x000000ab, 0x00000004 },
  43         { 0x000000af, 0x00000004 },
  44         { 0x66544a49, 0000000000 },
  45         { 0x49494174, 0000000000 },
  46         { 0x54517d83, 0000000000 },
  47         { 0x498d8b64, 0000000000 },
  48         { 0x49494949, 0000000000 },
  49         { 0x49da493c, 0000000000 },
  50         { 0x49989898, 0000000000 },
  51         { 0xd34949d5, 0000000000 },
  52         { 0x9dc90e11, 0000000000 },
  53         { 0xce9b9b9b, 0000000000 },
  54         { 0x000f0000, 0x00000016 },
  55         { 0x352e232c, 0000000000 },
  56         { 0x00000013, 0x00000004 },
  57         { 0x000f0000, 0x00000016 },
  58         { 0x352e272c, 0000000000 },
  59         { 0x000f0001, 0x00000016 },
  60         { 0x3239362f, 0000000000 },
  61         { 0x000077ef, 0x00000002 },
  62         { 0x00061000, 0x00000002 },
  63         { 0x00000020, 0x0000001a },
  64         { 0x00004000, 0x0000001e },
  65         { 0x00061000, 0x00000002 },
  66         { 0x00000020, 0x0000001a },
  67         { 0x00004000, 0x0000001e },
  68         { 0x00061000, 0x00000002 },
  69         { 0x00000020, 0x0000001a },
  70         { 0x00004000, 0x0000001e },
  71         { 0x00000016, 0x00000004 },
  72         { 0x0003802a, 0x00000002 },
  73         { 0x040067e0, 0x00000002 },
  74         { 0x00000016, 0x00000004 },
  75         { 0x000077e0, 0x00000002 },
  76         { 0x00065000, 0x00000002 },
  77         { 0x000037e1, 0x00000002 },
  78         { 0x040067e1, 0x00000006 },
  79         { 0x000077e0, 0x00000002 },
  80         { 0x000077e1, 0x00000002 },
  81         { 0x000077e1, 0x00000006 },
  82         { 0xffffffff, 0000000000 },
  83         { 0x10000000, 0000000000 },
  84         { 0x0003802a, 0x00000002 },
  85         { 0x040067e0, 0x00000006 },
  86         { 0x00007675, 0x00000002 },
  87         { 0x00007676, 0x00000002 },
  88         { 0x00007677, 0x00000002 },
  89         { 0x00007678, 0x00000006 },
  90         { 0x0003802b, 0x00000002 },
  91         { 0x04002676, 0x00000002 },
  92         { 0x00007677, 0x00000002 },
  93         { 0x00007678, 0x00000006 },
  94         { 0x0000002e, 0x00000018 },
  95         { 0x0000002e, 0x00000018 },
  96         { 0000000000, 0x00000006 },
  97         { 0x0000002f, 0x00000018 },
  98         { 0x0000002f, 0x00000018 },
  99         { 0000000000, 0x00000006 },
 100         { 0x01605000, 0x00000002 },
 101         { 0x00065000, 0x00000002 },
 102         { 0x00098000, 0x00000002 },
 103         { 0x00061000, 0x00000002 },
 104         { 0x64c0603d, 0x00000004 },
 105         { 0x00080000, 0x00000016 },
 106         { 0000000000, 0000000000 },
 107         { 0x0400251d, 0x00000002 },
 108         { 0x00007580, 0x00000002 },
 109         { 0x00067581, 0x00000002 },
 110         { 0x04002580, 0x00000002 },
 111         { 0x00067581, 0x00000002 },
 112         { 0x00000046, 0x00000004 },
 113         { 0x00005000, 0000000000 },
 114         { 0x00061000, 0x00000002 },
 115         { 0x0000750e, 0x00000002 },
 116         { 0x00019000, 0x00000002 },
 117         { 0x00011055, 0x00000014 },
 118         { 0x00000055, 0x00000012 },
 119         { 0x0400250f, 0x00000002 },
 120         { 0x0000504a, 0x00000004 },
 121         { 0x00007565, 0x00000002 },
 122         { 0x00007566, 0x00000002 },
 123         { 0x00000051, 0x00000004 },
 124         { 0x01e655b4, 0x00000002 },
 125         { 0x4401b0dc, 0x00000002 },
 126         { 0x01c110dc, 0x00000002 },
 127         { 0x2666705d, 0x00000018 },
 128         { 0x040c2565, 0x00000002 },
 129         { 0x0000005d, 0x00000018 },
 130         { 0x04002564, 0x00000002 },
 131         { 0x00007566, 0x00000002 },
 132         { 0x00000054, 0x00000004 },
 133         { 0x00401060, 0x00000008 },
 134         { 0x00101000, 0x00000002 },
 135         { 0x000d80ff, 0x00000002 },
 136         { 0x00800063, 0x00000008 },
 137         { 0x000f9000, 0x00000002 },
 138         { 0x000e00ff, 0x00000002 },
 139         { 0000000000, 0x00000006 },
 140         { 0x00000080, 0x00000018 },
 141         { 0x00000054, 0x00000004 },
 142         { 0x00007576, 0x00000002 },
 143         { 0x00065000, 0x00000002 },
 144         { 0x00009000, 0x00000002 },
 145         { 0x00041000, 0x00000002 },
 146         { 0x0c00350e, 0x00000002 },
 147         { 0x00049000, 0x00000002 },
 148         { 0x00051000, 0x00000002 },
 149         { 0x01e785f8, 0x00000002 },
 150         { 0x00200000, 0x00000002 },
 151         { 0x00600073, 0x0000000c },
 152         { 0x00007563, 0x00000002 },
 153         { 0x006075f0, 0x00000021 },
 154         { 0x20007068, 0x00000004 },
 155         { 0x00005068, 0x00000004 },
 156         { 0x00007576, 0x00000002 },
 157         { 0x00007577, 0x00000002 },
 158         { 0x0000750e, 0x00000002 },
 159         { 0x0000750f, 0x00000002 },
 160         { 0x00a05000, 0x00000002 },
 161         { 0x00600076, 0x0000000c },
 162         { 0x006075f0, 0x00000021 },
 163         { 0x000075f8, 0x00000002 },
 164         { 0x00000076, 0x00000004 },
 165         { 0x000a750e, 0x00000002 },
 166         { 0x0020750f, 0x00000002 },
 167         { 0x00600079, 0x00000004 },
 168         { 0x00007570, 0x00000002 },
 169         { 0x00007571, 0x00000002 },
 170         { 0x00007572, 0x00000006 },
 171         { 0x00005000, 0x00000002 },
 172         { 0x00a05000, 0x00000002 },
 173         { 0x00007568, 0x00000002 },
 174         { 0x00061000, 0x00000002 },
 175         { 0x00000084, 0x0000000c },
 176         { 0x00058000, 0x00000002 },
 177         { 0x0c607562, 0x00000002 },
 178         { 0x00000086, 0x00000004 },
 179         { 0x00600085, 0x00000004 },
 180         { 0x400070dd, 0000000000 },
 181         { 0x000380dd, 0x00000002 },
 182         { 0x00000093, 0x0000001c },
 183         { 0x00065095, 0x00000018 },
 184         { 0x040025bb, 0x00000002 },
 185         { 0x00061096, 0x00000018 },
 186         { 0x040075bc, 0000000000 },
 187         { 0x000075bb, 0x00000002 },
 188         { 0x000075bc, 0000000000 },
 189         { 0x00090000, 0x00000006 },
 190         { 0x00090000, 0x00000002 },
 191         { 0x000d8002, 0x00000006 },
 192         { 0x00005000, 0x00000002 },
 193         { 0x00007821, 0x00000002 },
 194         { 0x00007800, 0000000000 },
 195         { 0x00007821, 0x00000002 },
 196         { 0x00007800, 0000000000 },
 197         { 0x01665000, 0x00000002 },
 198         { 0x000a0000, 0x00000002 },
 199         { 0x000671cc, 0x00000002 },
 200         { 0x0286f1cd, 0x00000002 },
 201         { 0x000000a3, 0x00000010 },
 202         { 0x21007000, 0000000000 },
 203         { 0x000000aa, 0x0000001c },
 204         { 0x00065000, 0x00000002 },
 205         { 0x000a0000, 0x00000002 },
 206         { 0x00061000, 0x00000002 },
 207         { 0x000b0000, 0x00000002 },
 208         { 0x38067000, 0x00000002 },
 209         { 0x000a00a6, 0x00000004 },
 210         { 0x20007000, 0000000000 },
 211         { 0x01200000, 0x00000002 },
 212         { 0x20077000, 0x00000002 },
 213         { 0x01200000, 0x00000002 },
 214         { 0x20007000, 0000000000 },
 215         { 0x00061000, 0x00000002 },
 216         { 0x0120751b, 0x00000002 },
 217         { 0x8040750a, 0x00000002 },
 218         { 0x8040750b, 0x00000002 },
 219         { 0x00110000, 0x00000002 },
 220         { 0x000380dd, 0x00000002 },
 221         { 0x000000bd, 0x0000001c },
 222         { 0x00061096, 0x00000018 },
 223         { 0x844075bd, 0x00000002 },
 224         { 0x00061095, 0x00000018 },
 225         { 0x840075bb, 0x00000002 },
 226         { 0x00061096, 0x00000018 },
 227         { 0x844075bc, 0x00000002 },
 228         { 0x000000c0, 0x00000004 },
 229         { 0x804075bd, 0x00000002 },
 230         { 0x800075bb, 0x00000002 },
 231         { 0x804075bc, 0x00000002 },
 232         { 0x00108000, 0x00000002 },
 233         { 0x01400000, 0x00000002 },
 234         { 0x006000c4, 0x0000000c },
 235         { 0x20c07000, 0x00000020 },
 236         { 0x000000c6, 0x00000012 },
 237         { 0x00800000, 0x00000006 },
 238         { 0x0080751d, 0x00000006 },
 239         { 0x000025bb, 0x00000002 },
 240         { 0x000040c0, 0x00000004 },
 241         { 0x0000775c, 0x00000002 },
 242         { 0x00a05000, 0x00000002 },
 243         { 0x00661000, 0x00000002 },
 244         { 0x0460275d, 0x00000020 },
 245         { 0x00004000, 0000000000 },
 246         { 0x00007999, 0x00000002 },
 247         { 0x00a05000, 0x00000002 },
 248         { 0x00661000, 0x00000002 },
 249         { 0x0460299b, 0x00000020 },
 250         { 0x00004000, 0000000000 },
 251         { 0x01e00830, 0x00000002 },
 252         { 0x21007000, 0000000000 },
 253         { 0x00005000, 0x00000002 },
 254         { 0x00038042, 0x00000002 },
 255         { 0x040025e0, 0x00000002 },
 256         { 0x000075e1, 0000000000 },
 257         { 0x00000001, 0000000000 },
 258         { 0x000380d9, 0x00000002 },
 259         { 0x04007394, 0000000000 },
 260         { 0000000000, 0000000000 },
 261         { 0000000000, 0000000000 },
 262         { 0000000000, 0000000000 },
 263         { 0000000000, 0000000000 },
 264         { 0000000000, 0000000000 },
 265         { 0000000000, 0000000000 },
 266         { 0000000000, 0000000000 },
 267         { 0000000000, 0000000000 },
 268         { 0000000000, 0000000000 },
 269         { 0000000000, 0000000000 },
 270         { 0000000000, 0000000000 },
 271         { 0000000000, 0000000000 },
 272         { 0000000000, 0000000000 },
 273         { 0000000000, 0000000000 },
 274         { 0000000000, 0000000000 },
 275         { 0000000000, 0000000000 },
 276         { 0000000000, 0000000000 },
 277         { 0000000000, 0000000000 },
 278         { 0000000000, 0000000000 },
 279         { 0000000000, 0000000000 },
 280         { 0000000000, 0000000000 },
 281         { 0000000000, 0000000000 },
 282         { 0000000000, 0000000000 },
 283         { 0000000000, 0000000000 },
 284         { 0000000000, 0000000000 },
 285         { 0000000000, 0000000000 },
 286         { 0000000000, 0000000000 },
 287         { 0000000000, 0000000000 },
 288         { 0000000000, 0000000000 },
 289         { 0000000000, 0000000000 },
 290         { 0000000000, 0000000000 },
 291         { 0000000000, 0000000000 },
 292         { 0000000000, 0000000000 },
 293         { 0000000000, 0000000000 },
 294         { 0000000000, 0000000000 },
 295         { 0000000000, 0000000000 },
 296 };
 297
 298
 299 static u32 radeon_cp_microcode[][2] = {
 300         { 0x21007000, 0000000000 },
 301         { 0x20007000, 0000000000 },
 302         { 0x000000b4, 0x00000004 },
 303         { 0x000000b8, 0x00000004 },
 304         { 0x6f5b4d4c, 0000000000 },
 305         { 0x4c4c427f, 0000000000 },
 306         { 0x5b568a92, 0000000000 },
 307         { 0x4ca09c6d, 0000000000 },
 308         { 0xad4c4c4c, 0000000000 },
 309         { 0x4ce1af3d, 0000000000 },
 310         { 0xd8afafaf, 0000000000 },
 311         { 0xd64c4cdc, 0000000000 },
 312         { 0x4cd10d10, 0000000000 },
 313         { 0x000f0000, 0x00000016 },
 314         { 0x362f242d, 0000000000 },
 315         { 0x00000012, 0x00000004 },
 316         { 0x000f0000, 0x00000016 },
 317         { 0x362f282d, 0000000000 },
 318         { 0x000380e7, 0x00000002 },
 319         { 0x04002c97, 0x00000002 },
 320         { 0x000f0001, 0x00000016 },
 321         { 0x333a3730, 0000000000 },
 322         { 0x000077ef, 0x00000002 },
 323         { 0x00061000, 0x00000002 },
 324         { 0x00000021, 0x0000001a },
 325         { 0x00004000, 0x0000001e },
 326         { 0x00061000, 0x00000002 },
 327         { 0x00000021, 0x0000001a },
 328         { 0x00004000, 0x0000001e },
 329         { 0x00061000, 0x00000002 },
 330         { 0x00000021, 0x0000001a },
 331         { 0x00004000, 0x0000001e },
 332         { 0x00000017, 0x00000004 },
 333         { 0x0003802b, 0x00000002 },
 334         { 0x040067e0, 0x00000002 },
 335         { 0x00000017, 0x00000004 },
 336         { 0x000077e0, 0x00000002 },
 337         { 0x00065000, 0x00000002 },
 338         { 0x000037e1, 0x00000002 },
 339         { 0x040067e1, 0x00000006 },
 340         { 0x000077e0, 0x00000002 },
 341         { 0x000077e1, 0x00000002 },
 342         { 0x000077e1, 0x00000006 },
 343         { 0xffffffff, 0000000000 },
 344         { 0x10000000, 0000000000 },
 345         { 0x0003802b, 0x00000002 },
 346         { 0x040067e0, 0x00000006 },
 347         { 0x00007675, 0x00000002 },
 348         { 0x00007676, 0x00000002 },
 349         { 0x00007677, 0x00000002 },
 350         { 0x00007678, 0x00000006 },
 351         { 0x0003802c, 0x00000002 },
 352         { 0x04002676, 0x00000002 },
 353         { 0x00007677, 0x00000002 },
 354         { 0x00007678, 0x00000006 },
 355         { 0x0000002f, 0x00000018 },
 356         { 0x0000002f, 0x00000018 },
 357         { 0000000000, 0x00000006 },
 358         { 0x00000030, 0x00000018 },
 359         { 0x00000030, 0x00000018 },
 360         { 0000000000, 0x00000006 },
 361         { 0x01605000, 0x00000002 },
 362         { 0x00065000, 0x00000002 },
 363         { 0x00098000, 0x00000002 },
 364         { 0x00061000, 0x00000002 },
 365         { 0x64c0603e, 0x00000004 },
 366         { 0x000380e6, 0x00000002 },
 367         { 0x040025c5, 0x00000002 },
 368         { 0x00080000, 0x00000016 },
 369         { 0000000000, 0000000000 },
 370         { 0x0400251d, 0x00000002 },
 371         { 0x00007580, 0x00000002 },
 372         { 0x00067581, 0x00000002 },
 373         { 0x04002580, 0x00000002 },
 374         { 0x00067581, 0x00000002 },
 375         { 0x00000049, 0x00000004 },
 376         { 0x00005000, 0000000000 },
 377         { 0x000380e6, 0x00000002 },
 378         { 0x040025c5, 0x00000002 },
 379         { 0x00061000, 0x00000002 },
 380         { 0x0000750e, 0x00000002 },
 381         { 0x00019000, 0x00000002 },
 382         { 0x00011055, 0x00000014 },
 383         { 0x00000055, 0x00000012 },
 384         { 0x0400250f, 0x00000002 },
 385         { 0x0000504f, 0x00000004 },
 386         { 0x000380e6, 0x00000002 },
 387         { 0x040025c5, 0x00000002 },
 388         { 0x00007565, 0x00000002 },
 389         { 0x00007566, 0x00000002 },
 390         { 0x00000058, 0x00000004 },
 391         { 0x000380e6, 0x00000002 },
 392         { 0x040025c5, 0x00000002 },
 393         { 0x01e655b4, 0x00000002 },
 394         { 0x4401b0e4, 0x00000002 },
 395         { 0x01c110e4, 0x00000002 },
 396         { 0x26667066, 0x00000018 },
 397         { 0x040c2565, 0x00000002 },
 398         { 0x00000066, 0x00000018 },
 399         { 0x04002564, 0x00000002 },
 400         { 0x00007566, 0x00000002 },
 401         { 0x0000005d, 0x00000004 },
 402         { 0x00401069, 0x00000008 },
 403         { 0x00101000, 0x00000002 },
 404         { 0x000d80ff, 0x00000002 },
 405         { 0x0080006c, 0x00000008 },
 406         { 0x000f9000, 0x00000002 },
 407         { 0x000e00ff, 0x00000002 },
 408         { 0000000000, 0x00000006 },
 409         { 0x0000008f, 0x00000018 },
 410         { 0x0000005b, 0x00000004 },
 411         { 0x000380e6, 0x00000002 },
 412         { 0x040025c5, 0x00000002 },
 413         { 0x00007576, 0x00000002 },
 414         { 0x00065000, 0x00000002 },
 415         { 0x00009000, 0x00000002 },
 416         { 0x00041000, 0x00000002 },
 417         { 0x0c00350e, 0x00000002 },
 418         { 0x00049000, 0x00000002 },
 419         { 0x00051000, 0x00000002 },
 420         { 0x01e785f8, 0x00000002 },
 421         { 0x00200000, 0x00000002 },
 422         { 0x0060007e, 0x0000000c },
 423         { 0x00007563, 0x00000002 },
 424         { 0x006075f0, 0x00000021 },
 425         { 0x20007073, 0x00000004 },
 426         { 0x00005073, 0x00000004 },
 427         { 0x000380e6, 0x00000002 },
 428         { 0x040025c5, 0x00000002 },
 429         { 0x00007576, 0x00000002 },
 430         { 0x00007577, 0x00000002 },
 431         { 0x0000750e, 0x00000002 },
 432         { 0x0000750f, 0x00000002 },
 433         { 0x00a05000, 0x00000002 },
 434         { 0x00600083, 0x0000000c },
 435         { 0x006075f0, 0x00000021 },
 436         { 0x000075f8, 0x00000002 },
 437         { 0x00000083, 0x00000004 },
 438         { 0x000a750e, 0x00000002 },
 439         { 0x000380e6, 0x00000002 },
 440         { 0x040025c5, 0x00000002 },
 441         { 0x0020750f, 0x00000002 },
 442         { 0x00600086, 0x00000004 },
 443         { 0x00007570, 0x00000002 },
 444         { 0x00007571, 0x00000002 },
 445         { 0x00007572, 0x00000006 },
 446         { 0x000380e6, 0x00000002 },
 447         { 0x040025c5, 0x00000002 },
 448         { 0x00005000, 0x00000002 },
 449         { 0x00a05000, 0x00000002 },
 450         { 0x00007568, 0x00000002 },
 451         { 0x00061000, 0x00000002 },
 452         { 0x00000095, 0x0000000c },
 453         { 0x00058000, 0x00000002 },
 454         { 0x0c607562, 0x00000002 },
 455         { 0x00000097, 0x00000004 },
 456         { 0x000380e6, 0x00000002 },
 457         { 0x040025c5, 0x00000002 },
 458         { 0x00600096, 0x00000004 },
 459         { 0x400070e5, 0000000000 },
 460         { 0x000380e6, 0x00000002 },
 461         { 0x040025c5, 0x00000002 },
 462         { 0x000380e5, 0x00000002 },
 463         { 0x000000a8, 0x0000001c },
 464         { 0x000650aa, 0x00000018 },
 465         { 0x040025bb, 0x00000002 },
 466         { 0x000610ab, 0x00000018 },
 467         { 0x040075bc, 0000000000 },
 468         { 0x000075bb, 0x00000002 },
 469         { 0x000075bc, 0000000000 },
 470         { 0x00090000, 0x00000006 },
 471         { 0x00090000, 0x00000002 },
 472         { 0x000d8002, 0x00000006 },
 473         { 0x00007832, 0x00000002 },
 474         { 0x00005000, 0x00000002 },
 475         { 0x000380e7, 0x00000002 },
 476         { 0x04002c97, 0x00000002 },
 477         { 0x00007820, 0x00000002 },
 478         { 0x00007821, 0x00000002 },
 479         { 0x00007800, 0000000000 },
 480         { 0x01200000, 0x00000002 },
 481         { 0x20077000, 0x00000002 },
 482         { 0x01200000, 0x00000002 },
 483         { 0x20007000, 0x00000002 },
 484         { 0x00061000, 0x00000002 },
 485         { 0x0120751b, 0x00000002 },
 486         { 0x8040750a, 0x00000002 },
 487         { 0x8040750b, 0x00000002 },
 488         { 0x00110000, 0x00000002 },
 489         { 0x000380e5, 0x00000002 },
 490         { 0x000000c6, 0x0000001c },
 491         { 0x000610ab, 0x00000018 },
 492         { 0x844075bd, 0x00000002 },
 493         { 0x000610aa, 0x00000018 },
 494         { 0x840075bb, 0x00000002 },
 495         { 0x000610ab, 0x00000018 },
 496         { 0x844075bc, 0x00000002 },
 497         { 0x000000c9, 0x00000004 },
 498         { 0x804075bd, 0x00000002 },
 499         { 0x800075bb, 0x00000002 },
 500         { 0x804075bc, 0x00000002 },
 501         { 0x00108000, 0x00000002 },
 502         { 0x01400000, 0x00000002 },
 503         { 0x006000cd, 0x0000000c },
 504         { 0x20c07000, 0x00000020 },
 505         { 0x000000cf, 0x00000012 },
 506         { 0x00800000, 0x00000006 },
 507         { 0x0080751d, 0x00000006 },
 508         { 0000000000, 0000000000 },
 509         { 0x0000775c, 0x00000002 },
 510         { 0x00a05000, 0x00000002 },
 511         { 0x00661000, 0x00000002 },
 512         { 0x0460275d, 0x00000020 },
 513         { 0x00004000, 0000000000 },
 514         { 0x01e00830, 0x00000002 },
 515         { 0x21007000, 0000000000 },
 516         { 0x6464614d, 0000000000 },
 517         { 0x69687420, 0000000000 },
 518         { 0x00000073, 0000000000 },
 519         { 0000000000, 0000000000 },
 520         { 0x00005000, 0x00000002 },
 521         { 0x000380d0, 0x00000002 },
 522         { 0x040025e0, 0x00000002 },
 523         { 0x000075e1, 0000000000 },
 524         { 0x00000001, 0000000000 },
 525         { 0x000380e0, 0x00000002 },
 526         { 0x04002394, 0x00000002 },
 527         { 0x00005000, 0000000000 },
 528         { 0000000000, 0000000000 },
 529         { 0000000000, 0000000000 },
 530         { 0x00000008, 0000000000 },
 531         { 0x00000004, 0000000000 },
 532         { 0000000000, 0000000000 },
 533         { 0000000000, 0000000000 },
 534         { 0000000000, 0000000000 },
 535         { 0000000000, 0000000000 },
 536         { 0000000000, 0000000000 },
 537         { 0000000000, 0000000000 },
 538         { 0000000000, 0000000000 },
 539         { 0000000000, 0000000000 },
 540         { 0000000000, 0000000000 },
 541         { 0000000000, 0000000000 },
 542         { 0000000000, 0000000000 },
 543         { 0000000000, 0000000000 },
 544         { 0000000000, 0000000000 },
 545         { 0000000000, 0000000000 },
 546         { 0000000000, 0000000000 },
 547         { 0000000000, 0000000000 },
 548         { 0000000000, 0000000000 },
 549         { 0000000000, 0000000000 },
 550         { 0000000000, 0000000000 },
 551         { 0000000000, 0000000000 },
 552         { 0000000000, 0000000000 },
 553         { 0000000000, 0000000000 },
 554         { 0000000000, 0000000000 },
 555         { 0000000000, 0000000000 },
 556 };
 557
 558
 559 int RADEON_READ_PLL(drm_device_t *dev, int addr)
 560 {
 561         drm_radeon_private_t *dev_priv = dev->dev_private;
 562
 563         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
 564         return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 565 }
 566
 567 #if RADEON_FIFO_DEBUG
 568 static void radeon_status( drm_radeon_private_t *dev_priv )
 569 {
 570         printk( "%s:\n", __FUNCTION__ );
 571         printk( "RBBM_STATUS = 0x%08x\n",
 572                 (unsigned int)RADEON_READ( RADEON_RBBM_STATUS ) );
 573         printk( "CP_RB_RTPR = 0x%08x\n",
 574                 (unsigned int)RADEON_READ( RADEON_CP_RB_RPTR ) );
 575         printk( "CP_RB_WTPR = 0x%08x\n",
 576                 (unsigned int)RADEON_READ( RADEON_CP_RB_WPTR ) );
 577         printk( "AIC_CNTL = 0x%08x\n",
 578                 (unsigned int)RADEON_READ( RADEON_AIC_CNTL ) );
 579         printk( "AIC_STAT = 0x%08x\n",
 580                 (unsigned int)RADEON_READ( RADEON_AIC_STAT ) );
 581         printk( "AIC_PT_BASE = 0x%08x\n",
 582                 (unsigned int)RADEON_READ( RADEON_AIC_PT_BASE ) );
 583         printk( "TLB_ADDR = 0x%08x\n",
 584                 (unsigned int)RADEON_READ( RADEON_AIC_TLB_ADDR ) );
 585         printk( "TLB_DATA = 0x%08x\n",
 586                 (unsigned int)RADEON_READ( RADEON_AIC_TLB_DATA ) );
 587 }
 588 #endif
 589
 590
 591 /* ================================================================
 592  * Engine, FIFO control
 593  */
 594
 595 static int radeon_do_pixcache_flush( drm_radeon_private_t *dev_priv )
 596 {
 597         u32 tmp;
 598         int i;
 599
 600         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 601
 602         tmp  = RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT );
 603         tmp |= RADEON_RB2D_DC_FLUSH_ALL;
 604         RADEON_WRITE( RADEON_RB2D_DSTCACHE_CTLSTAT, tmp );
 605
 606         for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
 607                 if ( !(RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT )
 608                        & RADEON_RB2D_DC_BUSY) ) {
 609                         return 0;
 610                 }
 611                 DRM_UDELAY( 1 );
 612         }
 613
 614 #if RADEON_FIFO_DEBUG
 615         DRM_ERROR( "failed!\n" );
 616         radeon_status( dev_priv );
 617 #endif
 618         return DRM_ERR(EBUSY);
 619 }
 620
 621 static int radeon_do_wait_for_fifo( drm_radeon_private_t *dev_priv,
 622                                     int entries )
 623 {
 624         int i;
 625
 626         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 627
 628         for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
 629                 int slots = ( RADEON_READ( RADEON_RBBM_STATUS )
 630                               & RADEON_RBBM_FIFOCNT_MASK );
 631                 if ( slots >= entries ) return 0;
 632                 DRM_UDELAY( 1 );
 633         }
 634
 635 #if RADEON_FIFO_DEBUG
 636         DRM_ERROR( "failed!\n" );
 637         radeon_status( dev_priv );
 638 #endif
 639         return DRM_ERR(EBUSY);
 640 }
 641
 642 static int radeon_do_wait_for_idle( drm_radeon_private_t *dev_priv )
 643 {
 644         int i, ret;
 645
 646         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 647
 648         ret = radeon_do_wait_for_fifo( dev_priv, 64 );
 649         if ( ret ) return ret;
 650
 651         for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
 652                 if ( !(RADEON_READ( RADEON_RBBM_STATUS )
 653                        & RADEON_RBBM_ACTIVE) ) {
 654                         radeon_do_pixcache_flush( dev_priv );
 655                         return 0;
 656                 }
 657                 DRM_UDELAY( 1 );
 658         }
 659
 660 #if RADEON_FIFO_DEBUG
 661         DRM_ERROR( "failed!\n" );
 662         radeon_status( dev_priv );
 663 #endif
 664         return DRM_ERR(EBUSY);
 665 }
 666
 667
 668 /* ================================================================
 669  * CP control, initialization
 670  */
 671
 672 /* Load the microcode for the CP */
 673 static void radeon_cp_load_microcode( drm_radeon_private_t *dev_priv )
 674 {
 675         int i;
 676         DRM_DEBUG( "\n" );
 677
 678         radeon_do_wait_for_idle( dev_priv );
 679
 680         RADEON_WRITE( RADEON_CP_ME_RAM_ADDR, 0 );
 681
 682         if (dev_priv->is_r200)
 683         {
 684                 DRM_INFO("Loading R200 Microcode\n");
 685                 for ( i = 0 ; i < 256 ; i++ )
 686                 {
 687                         RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
 688                                       R200_cp_microcode[i][1] );
 689                         RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
 690                                       R200_cp_microcode[i][0] );
 691                 }
 692         }
 693         else
 694         {
 695                 for ( i = 0 ; i < 256 ; i++ ) {
 696                         RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
 697                                       radeon_cp_microcode[i][1] );
 698                         RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
 699                                       radeon_cp_microcode[i][0] );
 700                 }
 701         }
 702 }
 703
 704 /* Flush any pending commands to the CP.  This should only be used just
 705  * prior to a wait for idle, as it informs the engine that the command
 706  * stream is ending.
 707  */
 708 static void radeon_do_cp_flush( drm_radeon_private_t *dev_priv )
 709 {
 710         DRM_DEBUG( "\n" );
 711 #if 0
 712         u32 tmp;
 713
 714         tmp = RADEON_READ( RADEON_CP_RB_WPTR ) | (1 << 31);
 715         RADEON_WRITE( RADEON_CP_RB_WPTR, tmp );
 716 #endif
 717 }
 718
 719 /* Wait for the CP to go idle.
 720  */
 721 int radeon_do_cp_idle( drm_radeon_private_t *dev_priv )
 722 {
 723         RING_LOCALS;
 724         DRM_DEBUG( "\n" );
 725
 726         BEGIN_RING( 6 );
 727
 728         RADEON_PURGE_CACHE();
 729         RADEON_PURGE_ZCACHE();
 730         RADEON_WAIT_UNTIL_IDLE();
 731
 732         ADVANCE_RING();
 733         COMMIT_RING();
 734
 735         return radeon_do_wait_for_idle( dev_priv );
 736 }
 737
 738 /* Start the Command Processor.
 739  */
 740 static void radeon_do_cp_start( drm_radeon_private_t *dev_priv )
 741 {
 742         RING_LOCALS;
 743         DRM_DEBUG( "\n" );
 744
 745         radeon_do_wait_for_idle( dev_priv );
 746
 747         RADEON_WRITE( RADEON_CP_CSQ_CNTL, dev_priv->cp_mode );
 748
 749         dev_priv->cp_running = 1;
 750
 751         BEGIN_RING( 6 );
 752
 753         RADEON_PURGE_CACHE();
 754         RADEON_PURGE_ZCACHE();
 755         RADEON_WAIT_UNTIL_IDLE();
 756
 757         ADVANCE_RING();
 758         COMMIT_RING();
 759 }
 760
 761 /* Reset the Command Processor.  This will not flush any pending
 762  * commands, so you must wait for the CP command stream to complete
 763  * before calling this routine.
 764  */
 765 static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv )
 766 {
 767         u32 cur_read_ptr;
 768         DRM_DEBUG( "\n" );
 769
 770         cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
 771         RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
 772         SET_RING_HEAD( dev_priv, cur_read_ptr );
 773         dev_priv->ring.tail = cur_read_ptr;
 774 }
 775
 776 /* Stop the Command Processor.  This will not flush any pending
 777  * commands, so you must flush the command stream and wait for the CP
 778  * to go idle before calling this routine.
 779  */
 780 static void radeon_do_cp_stop( drm_radeon_private_t *dev_priv )
 781 {
 782         DRM_DEBUG( "\n" );
 783
 784         RADEON_WRITE( RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS );
 785
 786         dev_priv->cp_running = 0;
 787 }
 788
 789 /* Reset the engine.  This will stop the CP if it is running.
 790  */
 791 static int radeon_do_engine_reset( drm_device_t *dev )
 792 {
 793         drm_radeon_private_t *dev_priv = dev->dev_private;
 794         u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
 795         DRM_DEBUG( "\n" );
 796
 797         radeon_do_pixcache_flush( dev_priv );
 798
 799         clock_cntl_index = RADEON_READ( RADEON_CLOCK_CNTL_INDEX );
 800         mclk_cntl = RADEON_READ_PLL( dev, RADEON_MCLK_CNTL );
 801
 802         RADEON_WRITE_PLL( RADEON_MCLK_CNTL, ( mclk_cntl |
 803                                               RADEON_FORCEON_MCLKA |
 804                                               RADEON_FORCEON_MCLKB |
 805                                               RADEON_FORCEON_YCLKA |
 806                                               RADEON_FORCEON_YCLKB |
 807                                               RADEON_FORCEON_MC |
 808                                               RADEON_FORCEON_AIC ) );
 809
 810         rbbm_soft_reset = RADEON_READ( RADEON_RBBM_SOFT_RESET );
 811
 812         RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset |
 813                                                 RADEON_SOFT_RESET_CP |
 814                                                 RADEON_SOFT_RESET_HI |
 815                                                 RADEON_SOFT_RESET_SE |
 816                                                 RADEON_SOFT_RESET_RE |
 817                                                 RADEON_SOFT_RESET_PP |
 818                                                 RADEON_SOFT_RESET_E2 |
 819                                                 RADEON_SOFT_RESET_RB ) );
 820         RADEON_READ( RADEON_RBBM_SOFT_RESET );
 821         RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset &
 822                                                 ~( RADEON_SOFT_RESET_CP |
 823                                                    RADEON_SOFT_RESET_HI |
 824                                                    RADEON_SOFT_RESET_SE |
 825                                                    RADEON_SOFT_RESET_RE |
 826                                                    RADEON_SOFT_RESET_PP |
 827                                                    RADEON_SOFT_RESET_E2 |
 828                                                    RADEON_SOFT_RESET_RB ) ) );
 829         RADEON_READ( RADEON_RBBM_SOFT_RESET );
 830
 831
 832         RADEON_WRITE_PLL( RADEON_MCLK_CNTL, mclk_cntl );
 833         RADEON_WRITE( RADEON_CLOCK_CNTL_INDEX, clock_cntl_index );
 834         RADEON_WRITE( RADEON_RBBM_SOFT_RESET,  rbbm_soft_reset );
 835
 836         /* Reset the CP ring */
 837         radeon_do_cp_reset( dev_priv );
 838
 839         /* The CP is no longer running after an engine reset */
 840         dev_priv->cp_running = 0;
 841
 842         /* Reset any pending vertex, indirect buffers */
 843         radeon_freelist_reset( dev );
 844
 845         return 0;
 846 }
 847
 848 static void radeon_cp_init_ring_buffer( drm_device_t *dev,
 849                                         drm_radeon_private_t *dev_priv )
 850 {
 851         u32 ring_start, cur_read_ptr;
 852         u32 tmp;
 853
 854         /* Initialize the memory controller */
 855         RADEON_WRITE( RADEON_MC_FB_LOCATION,
 856                       ( ( dev_priv->gart_vm_start - 1 ) & 0xffff0000 )
 857                     | ( dev_priv->fb_location >> 16 ) );
 858
 859 #if __OS_HAS_AGP
 860         if (dev_priv->flags & CHIP_IS_AGP) {
 861                 RADEON_WRITE( RADEON_MC_AGP_LOCATION,
 862                               (((dev_priv->gart_vm_start - 1 +
 863                                  dev_priv->gart_size) & 0xffff0000) |
 864                                (dev_priv->gart_vm_start >> 16)) );
 865
 866                 ring_start = (dev_priv->cp_ring->offset
 867                               - dev->agp->base
 868                               + dev_priv->gart_vm_start);
 869         } else
 870 #endif
 871                 ring_start = (dev_priv->cp_ring->offset
 872                               - dev->sg->handle
 873                               + dev_priv->gart_vm_start);
 874
 875         RADEON_WRITE( RADEON_CP_RB_BASE, ring_start );
 876
 877         /* Set the write pointer delay */
 878         RADEON_WRITE( RADEON_CP_RB_WPTR_DELAY, 0 );
 879
 880         /* Initialize the ring buffer's read and write pointers */
 881         cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
 882         RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
 883         SET_RING_HEAD( dev_priv, cur_read_ptr );
 884         dev_priv->ring.tail = cur_read_ptr;
 885
 886 #if __OS_HAS_AGP
 887         if (dev_priv->flags & CHIP_IS_AGP) {
 888                 /* set RADEON_AGP_BASE here instead of relying on X from user space */
 889                 RADEON_WRITE( RADEON_AGP_BASE, (unsigned int)dev->agp->base );
 890                 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
 891                               dev_priv->ring_rptr->offset
 892                               - dev->agp->base
 893                               + dev_priv->gart_vm_start);
 894         } else
 895 #endif
 896         {
 897                 drm_sg_mem_t *entry = dev->sg;
 898                 unsigned long tmp_ofs, page_ofs;
 899
 900                 tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle;
 901                 page_ofs = tmp_ofs >> PAGE_SHIFT;
 902
 903                 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
 904                              entry->busaddr[page_ofs]);
 905                 DRM_DEBUG( "ring rptr: offset=0x%08lx handle=0x%08lx\n",
 906                            (unsigned long) entry->busaddr[page_ofs],
 907                            entry->handle + tmp_ofs );
 908         }
 909
 910         /* Initialize the scratch register pointer.  This will cause
 911          * the scratch register values to be written out to memory
 912          * whenever they are updated.
 913          *
 914          * We simply put this behind the ring read pointer, this works
 915          * with PCI GART as well as (whatever kind of) AGP GART
 916          */
 917         RADEON_WRITE( RADEON_SCRATCH_ADDR, RADEON_READ( RADEON_CP_RB_RPTR_ADDR )
 918                                          + RADEON_SCRATCH_REG_OFFSET );
 919
 920         dev_priv->scratch = ((__volatile__ u32 *)
 921                              dev_priv->ring_rptr->handle +
 922                              (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
 923
 924         RADEON_WRITE( RADEON_SCRATCH_UMSK, 0x7 );
 925
 926         /* Writeback doesn't seem to work everywhere, test it first */
 927         DRM_WRITE32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0 );
 928         RADEON_WRITE( RADEON_SCRATCH_REG1, 0xdeadbeef );
 929
 930         for ( tmp = 0 ; tmp < dev_priv->usec_timeout ; tmp++ ) {
 931                 if ( DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1) ) == 0xdeadbeef )
 932                         break;
 933                 DRM_UDELAY( 1 );
 934         }
 935
 936         if ( tmp < dev_priv->usec_timeout ) {
 937                 dev_priv->writeback_works = 1;
 938                 DRM_DEBUG( "writeback test succeeded, tmp=%d\n", tmp );
 939         } else {
 940                 dev_priv->writeback_works = 0;
 941                 DRM_DEBUG( "writeback test failed\n" );
 942         }
 943
 944         dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
 945         RADEON_WRITE( RADEON_LAST_FRAME_REG,
 946                       dev_priv->sarea_priv->last_frame );
 947
 948         dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
 949         RADEON_WRITE( RADEON_LAST_DISPATCH_REG,
 950                       dev_priv->sarea_priv->last_dispatch );
 951
 952         dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
 953         RADEON_WRITE( RADEON_LAST_CLEAR_REG,
 954                       dev_priv->sarea_priv->last_clear );
 955
 956         /* Set ring buffer size */
 957 #ifdef __BIG_ENDIAN
 958         RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT );
 959 #else
 960         RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw );
 961 #endif
 962
 963         radeon_do_wait_for_idle( dev_priv );
 964
 965         /* Turn on bus mastering */
 966         tmp = RADEON_READ( RADEON_BUS_CNTL ) & ~RADEON_BUS_MASTER_DIS;
 967         RADEON_WRITE( RADEON_BUS_CNTL, tmp );
 968
 969         /* Sync everything up */
 970         RADEON_WRITE( RADEON_ISYNC_CNTL,
 971                       (RADEON_ISYNC_ANY2D_IDLE3D |
 972                        RADEON_ISYNC_ANY3D_IDLE2D |
 973                        RADEON_ISYNC_WAIT_IDLEGUI |
 974                        RADEON_ISYNC_CPSCRATCH_IDLEGUI) );
 975 }
 976
 977 /* Enable or disable PCI GART on the chip */
 978 static void radeon_set_pcigart( drm_radeon_private_t *dev_priv, int on )
 979 {
 980         u32 tmp = RADEON_READ( RADEON_AIC_CNTL );
 981
 982         if ( on ) {
 983                 RADEON_WRITE( RADEON_AIC_CNTL, tmp | RADEON_PCIGART_TRANSLATE_EN );
 984
 985                 /* set PCI GART page-table base address
 986                  */
 987                 RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart );
 988
 989                 /* set address range for PCI address translate
 990                  */
 991                 RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start );
 992                 RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
 993                                                   + dev_priv->gart_size - 1);
 994
 995                 /* Turn off AGP aperture -- is this required for PCI GART?
 996                  */
 997                 RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
 998                 RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
 999         } else {
1000                 RADEON_WRITE( RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN );
1001         }
1002 }
1003
1004 static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
1005 {
1006         drm_radeon_private_t *dev_priv = dev->dev_private;
1007         DRM_DEBUG( "\n" );
1008
1009         if ( (!(dev_priv->flags & CHIP_IS_AGP)) && !dev->sg ) {
1010                 DRM_ERROR( "PCI GART memory not allocated!\n" );
1011                 radeon_do_cleanup_cp(dev);
1012                 return DRM_ERR(EINVAL);
1013         }
1014
1015         dev_priv->usec_timeout = init->usec_timeout;
1016         if ( dev_priv->usec_timeout < 1 ||
1017              dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT ) {
1018                 DRM_DEBUG( "TIMEOUT problem!\n" );
1019                 radeon_do_cleanup_cp(dev);
1020                 return DRM_ERR(EINVAL);
1021         }
1022
1023         dev_priv->is_r200 = (init->func == RADEON_INIT_R200_CP);
1024         dev_priv->do_boxes = 0;
1025         dev_priv->cp_mode = init->cp_mode;
1026
1027         /* We don't support anything other than bus-mastering ring mode,
1028          * but the ring can be in either AGP or PCI space for the ring
1029          * read pointer.
1030          */
1031         if ( ( init->cp_mode != RADEON_CSQ_PRIBM_INDDIS ) &&
1032              ( init->cp_mode != RADEON_CSQ_PRIBM_INDBM ) ) {
1033                 DRM_DEBUG( "BAD cp_mode (%x)!\n", init->cp_mode );
1034                 radeon_do_cleanup_cp(dev);
1035                 return DRM_ERR(EINVAL);
1036         }
1037
1038         switch ( init->fb_bpp ) {
1039         case 16:
1040                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1041                 break;
1042         case 32:
1043         default:
1044                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1045                 break;
1046         }
1047         dev_priv->front_offset  = init->front_offset;
1048         dev_priv->front_pitch   = init->front_pitch;
1049         dev_priv->back_offset   = init->back_offset;
1050         dev_priv->back_pitch    = init->back_pitch;
1051
1052         switch ( init->depth_bpp ) {
1053         case 16:
1054                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1055                 break;
1056         case 32:
1057         default:
1058                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1059                 break;
1060         }
1061         dev_priv->depth_offset  = init->depth_offset;
1062         dev_priv->depth_pitch   = init->depth_pitch;
1063
1064         /* Hardware state for depth clears.  Remove this if/when we no
1065          * longer clear the depth buffer with a 3D rectangle.  Hard-code
1066          * all values to prevent unwanted 3D state from slipping through
1067          * and screwing with the clear operation.
1068          */
1069         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1070                                            (dev_priv->color_fmt << 10) |
1071                                            (1<<15));
1072
1073         dev_priv->depth_clear.rb3d_zstencilcntl =
1074                 (dev_priv->depth_fmt |
1075                  RADEON_Z_TEST_ALWAYS |
1076                  RADEON_STENCIL_TEST_ALWAYS |
1077                  RADEON_STENCIL_S_FAIL_REPLACE |
1078                  RADEON_STENCIL_ZPASS_REPLACE |
1079                  RADEON_STENCIL_ZFAIL_REPLACE |
1080                  RADEON_Z_WRITE_ENABLE);
1081
1082         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1083                                          RADEON_BFACE_SOLID |
1084                                          RADEON_FFACE_SOLID |
1085                                          RADEON_FLAT_SHADE_VTX_LAST |
1086                                          RADEON_DIFFUSE_SHADE_FLAT |
1087                                          RADEON_ALPHA_SHADE_FLAT |
1088                                          RADEON_SPECULAR_SHADE_FLAT |
1089                                          RADEON_FOG_SHADE_FLAT |
1090                                          RADEON_VTX_PIX_CENTER_OGL |
1091                                          RADEON_ROUND_MODE_TRUNC |
1092                                          RADEON_ROUND_PREC_8TH_PIX);
1093
1094         DRM_GETSAREA();
1095
1096         dev_priv->fb_offset = init->fb_offset;
1097         dev_priv->mmio_offset = init->mmio_offset;
1098         dev_priv->ring_offset = init->ring_offset;
1099         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1100         dev_priv->buffers_offset = init->buffers_offset;
1101         dev_priv->gart_textures_offset = init->gart_textures_offset;
1102
1103         if(!dev_priv->sarea) {
1104                 DRM_ERROR("could not find sarea!\n");
1105                 radeon_do_cleanup_cp(dev);
1106                 return DRM_ERR(EINVAL);
1107         }
1108
1109         dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
1110         if(!dev_priv->mmio) {
1111                 DRM_ERROR("could not find mmio region!\n");
1112                 radeon_do_cleanup_cp(dev);
1113                 return DRM_ERR(EINVAL);
1114         }
1115         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1116         if(!dev_priv->cp_ring) {
1117                 DRM_ERROR("could not find cp ring region!\n");
1118                 radeon_do_cleanup_cp(dev);
1119                 return DRM_ERR(EINVAL);
1120         }
1121         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1122         if(!dev_priv->ring_rptr) {
1123                 DRM_ERROR("could not find ring read pointer!\n");
1124                 radeon_do_cleanup_cp(dev);
1125                 return DRM_ERR(EINVAL);
1126         }
1127         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1128         if(!dev->agp_buffer_map) {
1129                 DRM_ERROR("could not find dma buffer region!\n");
1130                 radeon_do_cleanup_cp(dev);
1131                 return DRM_ERR(EINVAL);
1132         }
1133
1134         if ( init->gart_textures_offset ) {
1135                 dev_priv->gart_textures = drm_core_findmap(dev, init->gart_textures_offset);
1136                 if ( !dev_priv->gart_textures ) {
1137                         DRM_ERROR("could not find GART texture region!\n");
1138                         radeon_do_cleanup_cp(dev);
1139                         return DRM_ERR(EINVAL);
1140                 }
1141         }
1142
1143         dev_priv->sarea_priv =
1144                 (drm_radeon_sarea_t *)((u8 *)dev_priv->sarea->handle +
1145                                        init->sarea_priv_offset);
1146
1147 #if __OS_HAS_AGP
1148         if ( dev_priv->flags & CHIP_IS_AGP ) {
1149                 drm_core_ioremap( dev_priv->cp_ring, dev );
1150                 drm_core_ioremap( dev_priv->ring_rptr, dev );
1151                 drm_core_ioremap( dev->agp_buffer_map, dev );
1152                 if(!dev_priv->cp_ring->handle ||
1153                    !dev_priv->ring_rptr->handle ||
1154                    !dev->agp_buffer_map->handle) {
1155                         DRM_ERROR("could not find ioremap agp regions!\n");
1156                         radeon_do_cleanup_cp(dev);
1157                         return DRM_ERR(EINVAL);
1158                 }
1159         } else
1160 #endif
1161         {
1162                 dev_priv->cp_ring->handle =
1163                         (void *)dev_priv->cp_ring->offset;
1164                 dev_priv->ring_rptr->handle =
1165                         (void *)dev_priv->ring_rptr->offset;
1166                 dev->agp_buffer_map->handle = (void *)dev->agp_buffer_map->offset;
1167
1168                 DRM_DEBUG( "dev_priv->cp_ring->handle %p\n",
1169                            dev_priv->cp_ring->handle );
1170                 DRM_DEBUG( "dev_priv->ring_rptr->handle %p\n",
1171                            dev_priv->ring_rptr->handle );
1172                 DRM_DEBUG( "dev->agp_buffer_map->handle %p\n",
1173                            dev->agp_buffer_map->handle );
1174         }
1175
1176         dev_priv->fb_location = ( RADEON_READ( RADEON_MC_FB_LOCATION )
1177                                 & 0xffff ) << 16;
1178
1179         dev_priv->front_pitch_offset = (((dev_priv->front_pitch/64) << 22) |
1180                                         ( ( dev_priv->front_offset
1181                                           + dev_priv->fb_location ) >> 10 ) );
1182
1183         dev_priv->back_pitch_offset = (((dev_priv->back_pitch/64) << 22) |
1184                                        ( ( dev_priv->back_offset
1185                                          + dev_priv->fb_location ) >> 10 ) );
1186
1187         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch/64) << 22) |
1188                                         ( ( dev_priv->depth_offset
1189                                           + dev_priv->fb_location ) >> 10 ) );
1190
1191
1192         dev_priv->gart_size = init->gart_size;
1193         dev_priv->gart_vm_start = dev_priv->fb_location
1194                                 + RADEON_READ( RADEON_CONFIG_APER_SIZE );
1195
1196 #if __OS_HAS_AGP
1197         if (dev_priv->flags & CHIP_IS_AGP)
1198                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1199                                                 - dev->agp->base
1200                                                 + dev_priv->gart_vm_start);
1201         else
1202 #endif
1203                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1204                                                 - dev->sg->handle
1205                                                 + dev_priv->gart_vm_start);
1206
1207         DRM_DEBUG( "dev_priv->gart_size %d\n",
1208                    dev_priv->gart_size );
1209         DRM_DEBUG( "dev_priv->gart_vm_start 0x%x\n",
1210                    dev_priv->gart_vm_start );
1211         DRM_DEBUG( "dev_priv->gart_buffers_offset 0x%lx\n",
1212                    dev_priv->gart_buffers_offset );
1213
1214         dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle;
1215         dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle
1216                               + init->ring_size / sizeof(u32));
1217         dev_priv->ring.size = init->ring_size;
1218         dev_priv->ring.size_l2qw = get_order( init->ring_size / 8 );
1219
1220         dev_priv->ring.tail_mask =
1221                 (dev_priv->ring.size / sizeof(u32)) - 1;
1222
1223         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1224
1225 #if __OS_HAS_AGP
1226         if (dev_priv->flags & CHIP_IS_AGP) {
1227                 /* Turn off PCI GART */
1228                 radeon_set_pcigart( dev_priv, 0 );
1229         } else
1230 #endif
1231         {
1232                 if (!drm_ati_pcigart_init( dev, &dev_priv->phys_pci_gart,
1233                                             &dev_priv->bus_pci_gart)) {
1234                         DRM_ERROR( "failed to init PCI GART!\n" );
1235                         radeon_do_cleanup_cp(dev);
1236                         return DRM_ERR(ENOMEM);
1237                 }
1238
1239                 /* Turn on PCI GART */
1240                 radeon_set_pcigart( dev_priv, 1 );
1241         }
1242
1243         radeon_cp_load_microcode( dev_priv );
1244         radeon_cp_init_ring_buffer( dev, dev_priv );
1245
1246         dev_priv->last_buf = 0;
1247
1248         radeon_do_engine_reset( dev );
1249
1250         return 0;
1251 }
1252
1253 int radeon_do_cleanup_cp( drm_device_t *dev )
1254 {
1255         drm_radeon_private_t *dev_priv = dev->dev_private;
1256         DRM_DEBUG( "\n" );
1257
1258         /* Make sure interrupts are disabled here because the uninstall ioctl
1259          * may not have been called from userspace and after dev_private
1260          * is freed, it's too late.
1261          */
1262         if ( dev->irq_enabled ) drm_irq_uninstall(dev);
1263
1264 #if __OS_HAS_AGP
1265         if (dev_priv->flags & CHIP_IS_AGP) {
1266                 if ( dev_priv->cp_ring != NULL ) {
1267                         drm_core_ioremapfree( dev_priv->cp_ring, dev );
1268                         dev_priv->cp_ring = NULL;
1269                 }
1270                 if ( dev_priv->ring_rptr != NULL ) {
1271                         drm_core_ioremapfree( dev_priv->ring_rptr, dev );
1272                         dev_priv->ring_rptr = NULL;
1273                 }
1274                 if ( dev->agp_buffer_map != NULL ) {
1275                         drm_core_ioremapfree( dev->agp_buffer_map, dev );
1276                         dev->agp_buffer_map = NULL;
1277                 }
1278         } else
1279 #endif
1280         {
1281                 if (!drm_ati_pcigart_cleanup( dev,
1282                                                dev_priv->phys_pci_gart,
1283                                                dev_priv->bus_pci_gart ))
1284                         DRM_ERROR( "failed to cleanup PCI GART!\n" );
1285         }
1286         /* only clear to the start of flags */
1287         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1288
1289         return 0;
1290 }
1291
1292 /* This code will reinit the Radeon CP hardware after a resume from disc.
1293  * AFAIK, it would be very difficult to pickle the state at suspend time, so
1294  * here we make sure that all Radeon hardware initialisation is re-done without
1295  * affecting running applications.
1296  *
1297  * Charl P. Botha <http://cpbotha.net>
1298  */
1299 static int radeon_do_resume_cp( drm_device_t *dev )
1300 {
1301         drm_radeon_private_t *dev_priv = dev->dev_private;
1302
1303         if ( !dev_priv ) {
1304                 DRM_ERROR( "Called with no initialization\n" );
1305                 return DRM_ERR( EINVAL );
1306         }
1307
1308         DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1309
1310 #if __OS_HAS_AGP
1311         if (dev_priv->flags & CHIP_IS_AGP) {
1312                 /* Turn off PCI GART */
1313                 radeon_set_pcigart( dev_priv, 0 );
1314         } else
1315 #endif
1316         {
1317                 /* Turn on PCI GART */
1318                 radeon_set_pcigart( dev_priv, 1 );
1319         }
1320
1321         radeon_cp_load_microcode( dev_priv );
1322         radeon_cp_init_ring_buffer( dev, dev_priv );
1323
1324         radeon_do_engine_reset( dev );
1325
1326         DRM_DEBUG("radeon_do_resume_cp() complete\n");
1327
1328         return 0;
1329 }
1330
1331
1332 int radeon_cp_init( DRM_IOCTL_ARGS )
1333 {
1334         DRM_DEVICE;
1335         drm_radeon_init_t init;
1336
1337         LOCK_TEST_WITH_RETURN( dev, filp );
1338
1339         DRM_COPY_FROM_USER_IOCTL( init, (drm_radeon_init_t __user *)data, sizeof(init) );
1340
1341         switch ( init.func ) {
1342         case RADEON_INIT_CP:
1343         case RADEON_INIT_R200_CP:
1344                 return radeon_do_init_cp( dev, &init );
1345         case RADEON_CLEANUP_CP:
1346                 return radeon_do_cleanup_cp( dev );
1347         }
1348
1349         return DRM_ERR(EINVAL);
1350 }
1351
1352 int radeon_cp_start( DRM_IOCTL_ARGS )
1353 {
1354         DRM_DEVICE;
1355         drm_radeon_private_t *dev_priv = dev->dev_private;
1356         DRM_DEBUG( "\n" );
1357
1358         LOCK_TEST_WITH_RETURN( dev, filp );
1359
1360         if ( dev_priv->cp_running ) {
1361                 DRM_DEBUG( "%s while CP running\n", __FUNCTION__ );
1362                 return 0;
1363         }
1364         if ( dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS ) {
1365                 DRM_DEBUG( "%s called with bogus CP mode (%d)\n",
1366                            __FUNCTION__, dev_priv->cp_mode );
1367                 return 0;
1368         }
1369
1370         radeon_do_cp_start( dev_priv );
1371
1372         return 0;
1373 }
1374
1375 /* Stop the CP.  The engine must have been idled before calling this
1376  * routine.
1377  */
1378 int radeon_cp_stop( DRM_IOCTL_ARGS )
1379 {
1380         DRM_DEVICE;
1381         drm_radeon_private_t *dev_priv = dev->dev_private;
1382         drm_radeon_cp_stop_t stop;
1383         int ret;
1384         DRM_DEBUG( "\n" );
1385
1386         LOCK_TEST_WITH_RETURN( dev, filp );
1387
1388         DRM_COPY_FROM_USER_IOCTL( stop, (drm_radeon_cp_stop_t __user *)data, sizeof(stop) );
1389
1390         if (!dev_priv->cp_running)
1391                 return 0;
1392
1393         /* Flush any pending CP commands.  This ensures any outstanding
1394          * commands are exectuted by the engine before we turn it off.
1395          */
1396         if ( stop.flush ) {
1397                 radeon_do_cp_flush( dev_priv );
1398         }
1399
1400         /* If we fail to make the engine go idle, we return an error
1401          * code so that the DRM ioctl wrapper can try again.
1402          */
1403         if ( stop.idle ) {
1404                 ret = radeon_do_cp_idle( dev_priv );
1405                 if ( ret ) return ret;
1406         }
1407
1408         /* Finally, we can turn off the CP.  If the engine isn't idle,
1409          * we will get some dropped triangles as they won't be fully
1410          * rendered before the CP is shut down.
1411          */
1412         radeon_do_cp_stop( dev_priv );
1413
1414         /* Reset the engine */
1415         radeon_do_engine_reset( dev );
1416
1417         return 0;
1418 }
1419
1420
1421 void radeon_do_release( drm_device_t *dev )
1422 {
1423         drm_radeon_private_t *dev_priv = dev->dev_private;
1424         int ret;
1425
1426         if (dev_priv) {
1427
1428                 if (dev_priv->cp_running) {
1429                         /* Stop the cp */
1430                         while ((ret = radeon_do_cp_idle( dev_priv )) != 0) {
1431                                 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1432 #ifdef __linux__
1433                                 schedule();
1434 #else
1435                                 tsleep(&ret, PZERO, "rdnrel", 1);
1436 #endif
1437                         }
1438                         radeon_do_cp_stop( dev_priv );
1439                         radeon_do_engine_reset( dev );
1440                 }
1441
1442                 /* Disable *all* interrupts */
1443                 if (dev_priv->mmio) /* remove this after permanent addmaps */
1444                         RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );
1445
1446                 /* Free memory heap structures */
1447                 radeon_mem_takedown( &(dev_priv->gart_heap) );
1448                 radeon_mem_takedown( &(dev_priv->fb_heap) );
1449
1450                 /* deallocate kernel resources */
1451                 radeon_do_cleanup_cp( dev );
1452         }
1453 }
1454
1455 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1456  */
1457 int radeon_cp_reset( DRM_IOCTL_ARGS )
1458 {
1459         DRM_DEVICE;
1460         drm_radeon_private_t *dev_priv = dev->dev_private;
1461         DRM_DEBUG( "\n" );
1462
1463         LOCK_TEST_WITH_RETURN( dev, filp );
1464
1465         if ( !dev_priv ) {
1466                 DRM_DEBUG( "%s called before init done\n", __FUNCTION__ );
1467                 return DRM_ERR(EINVAL);
1468         }
1469
1470         radeon_do_cp_reset( dev_priv );
1471
1472         /* The CP is no longer running after an engine reset */
1473         dev_priv->cp_running = 0;
1474
1475         return 0;
1476 }
1477
1478 int radeon_cp_idle( DRM_IOCTL_ARGS )
1479 {
1480         DRM_DEVICE;
1481         drm_radeon_private_t *dev_priv = dev->dev_private;
1482         DRM_DEBUG( "\n" );
1483
1484         LOCK_TEST_WITH_RETURN( dev, filp );
1485
1486         return radeon_do_cp_idle( dev_priv );
1487 }
1488
1489 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1490  */
1491 int radeon_cp_resume( DRM_IOCTL_ARGS )
1492 {
1493         DRM_DEVICE;
1494
1495         return radeon_do_resume_cp(dev);
1496 }
1497
1498
1499 int radeon_engine_reset( DRM_IOCTL_ARGS )
1500 {
1501         DRM_DEVICE;
1502         DRM_DEBUG( "\n" );
1503
1504         LOCK_TEST_WITH_RETURN( dev, filp );
1505
1506         return radeon_do_engine_reset( dev );
1507 }
1508
1509
1510 /* ================================================================
1511  * Fullscreen mode
1512  */
1513
1514 /* KW: Deprecated to say the least:
1515  */
1516 int radeon_fullscreen( DRM_IOCTL_ARGS )
1517 {
1518         return 0;
1519 }
1520
1521
1522 /* ================================================================
1523  * Freelist management
1524  */
1525
1526 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1527  *   bufs until freelist code is used.  Note this hides a problem with
1528  *   the scratch register * (used to keep track of last buffer
1529  *   completed) being written to before * the last buffer has actually
1530  *   completed rendering.
1531  *
1532  * KW:  It's also a good way to find free buffers quickly.
1533  *
1534  * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1535  * sleep.  However, bugs in older versions of radeon_accel.c mean that
1536  * we essentially have to do this, else old clients will break.
1537  *
1538  * However, it does leave open a potential deadlock where all the
1539  * buffers are held by other clients, which can't release them because
1540  * they can't get the lock.
1541  */
1542
1543 drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1544 {
1545         drm_device_dma_t *dma = dev->dma;
1546         drm_radeon_private_t *dev_priv = dev->dev_private;
1547         drm_radeon_buf_priv_t *buf_priv;
1548         drm_buf_t *buf;
1549         int i, t;
1550         int start;
1551
1552         if ( ++dev_priv->last_buf >= dma->buf_count )
1553                 dev_priv->last_buf = 0;
1554
1555         start = dev_priv->last_buf;
1556
1557         for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) {
1558                 u32 done_age = GET_SCRATCH( 1 );
1559                 DRM_DEBUG("done_age = %d\n",done_age);
1560                 for ( i = start ; i < dma->buf_count ; i++ ) {
1561                         buf = dma->buflist[i];
1562                         buf_priv = buf->dev_private;
1563                         if ( buf->filp == 0 || (buf->pending &&
1564                                                buf_priv->age <= done_age) ) {
1565                                 dev_priv->stats.requested_bufs++;
1566                                 buf->pending = 0;
1567                                 return buf;
1568                         }
1569                         start = 0;
1570                 }
1571
1572                 if (t) {
1573                         DRM_UDELAY( 1 );
1574                         dev_priv->stats.freelist_loops++;
1575                 }
1576         }
1577
1578         DRM_DEBUG( "returning NULL!\n" );
1579         return NULL;
1580 }
1581 #if 0
1582 drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1583 {
1584         drm_device_dma_t *dma = dev->dma;
1585         drm_radeon_private_t *dev_priv = dev->dev_private;
1586         drm_radeon_buf_priv_t *buf_priv;
1587         drm_buf_t *buf;
1588         int i, t;
1589         int start;
1590         u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1591
1592         if ( ++dev_priv->last_buf >= dma->buf_count )
1593                 dev_priv->last_buf = 0;
1594
1595         start = dev_priv->last_buf;
1596         dev_priv->stats.freelist_loops++;
1597
1598         for ( t = 0 ; t < 2 ; t++ ) {
1599                 for ( i = start ; i < dma->buf_count ; i++ ) {
1600                         buf = dma->buflist[i];
1601                         buf_priv = buf->dev_private;
1602                         if ( buf->filp == 0 || (buf->pending &&
1603                                                buf_priv->age <= done_age) ) {
1604                                 dev_priv->stats.requested_bufs++;
1605                                 buf->pending = 0;
1606                                 return buf;
1607                         }
1608                 }
1609                 start = 0;
1610         }
1611
1612         return NULL;
1613 }
1614 #endif
1615
1616 void radeon_freelist_reset( drm_device_t *dev )
1617 {
1618         drm_device_dma_t *dma = dev->dma;
1619         drm_radeon_private_t *dev_priv = dev->dev_private;
1620         int i;
1621
1622         dev_priv->last_buf = 0;
1623         for ( i = 0 ; i < dma->buf_count ; i++ ) {
1624                 drm_buf_t *buf = dma->buflist[i];
1625                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1626                 buf_priv->age = 0;
1627         }
1628 }
1629
1630
1631 /* ================================================================
1632  * CP command submission
1633  */
1634
1635 int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n )
1636 {
1637         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1638         int i;
1639         u32 last_head = GET_RING_HEAD( dev_priv );
1640
1641         for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
1642                 u32 head = GET_RING_HEAD( dev_priv );
1643
1644                 ring->space = (head - ring->tail) * sizeof(u32);
1645                 if ( ring->space <= 0 )
1646                         ring->space += ring->size;
1647                 if ( ring->space > n )
1648                         return 0;
1649
1650                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1651
1652                 if (head != last_head)
1653                         i = 0;
1654                 last_head = head;
1655
1656                 DRM_UDELAY( 1 );
1657         }
1658
1659         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1660 #if RADEON_FIFO_DEBUG
1661         radeon_status( dev_priv );
1662         DRM_ERROR( "failed!\n" );
1663 #endif
1664         return DRM_ERR(EBUSY);
1665 }
1666
1667 static int radeon_cp_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d )
1668 {
1669         int i;
1670         drm_buf_t *buf;
1671
1672         for ( i = d->granted_count ; i < d->request_count ; i++ ) {
1673                 buf = radeon_freelist_get( dev );
1674                 if ( !buf ) return DRM_ERR(EBUSY); /* NOTE: broken client */
1675
1676                 buf->filp = filp;
1677
1678                 if ( DRM_COPY_TO_USER( &d->request_indices[i], &buf->idx,
1679                                    sizeof(buf->idx) ) )
1680                         return DRM_ERR(EFAULT);
1681                 if ( DRM_COPY_TO_USER( &d->request_sizes[i], &buf->total,
1682                                    sizeof(buf->total) ) )
1683                         return DRM_ERR(EFAULT);
1684
1685                 d->granted_count++;
1686         }
1687         return 0;
1688 }
1689
1690 int radeon_cp_buffers( DRM_IOCTL_ARGS )
1691 {
1692         DRM_DEVICE;
1693         drm_device_dma_t *dma = dev->dma;
1694         int ret = 0;
1695         drm_dma_t __user *argp = (void __user *)data;
1696         drm_dma_t d;
1697
1698         LOCK_TEST_WITH_RETURN( dev, filp );
1699
1700         DRM_COPY_FROM_USER_IOCTL( d, argp, sizeof(d) );
1701
1702         /* Please don't send us buffers.
1703          */
1704         if ( d.send_count != 0 ) {
1705                 DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n",
1706                            DRM_CURRENTPID, d.send_count );
1707                 return DRM_ERR(EINVAL);
1708         }
1709
1710         /* We'll send you buffers.
1711          */
1712         if ( d.request_count < 0 || d.request_count > dma->buf_count ) {
1713                 DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n",
1714                            DRM_CURRENTPID, d.request_count, dma->buf_count );
1715                 return DRM_ERR(EINVAL);
1716         }
1717
1718         d.granted_count = 0;
1719
1720         if ( d.request_count ) {
1721                 ret = radeon_cp_get_buffers( filp, dev, &d );
1722         }
1723
1724         DRM_COPY_TO_USER_IOCTL( argp, d, sizeof(d) );
1725
1726         return ret;
1727 }
1728
1729 /* Always create a map record for MMIO and FB memory, done from DRIVER_POSTINIT */
1730 int radeon_preinit( struct drm_device *dev, unsigned long flags )
1731 {
1732         u32 save, temp;
1733         drm_radeon_private_t *dev_priv;
1734         int ret = 0;
1735
1736         dev_priv = drm_alloc( sizeof(drm_radeon_private_t), DRM_MEM_DRIVER );
1737         if ( dev_priv == NULL )
1738                 return DRM_ERR(ENOMEM);
1739
1740         memset( dev_priv, 0, sizeof(drm_radeon_private_t) );
1741         dev->dev_private = (void *)dev_priv;
1742         dev_priv->flags = flags;
1743
1744         /* registers */
1745         if( (ret = drm_initmap( dev, pci_resource_start( dev->pdev, 2 ),
1746                         pci_resource_len( dev->pdev, 2 ), _DRM_REGISTERS, 0 )))
1747                 return ret;
1748
1749         /* framebuffer */
1750         if( (ret = drm_initmap( dev, pci_resource_start( dev->pdev, 0 ),
1751                         pci_resource_len( dev->pdev, 0 ), _DRM_FRAME_BUFFER, _DRM_WRITE_COMBINING )))
1752                 return ret;
1753
1754         /* There are signatures in BIOS and PCI-SSID for a PCI card, but they are not very reliable.
1755                 Following detection method works for all cards tested so far.
1756                 Note, checking AGP_ENABLE bit after drmAgpEnable call can also give the correct result.
1757                 However, calling drmAgpEnable on a PCI card can cause some strange lockup when the server
1758                 restarts next time.
1759         */
1760         pci_read_config_dword(dev->pdev, RADEON_AGP_COMMAND_PCI_CONFIG, &save);
1761         pci_write_config_dword(dev->pdev, RADEON_AGP_COMMAND_PCI_CONFIG, save | RADEON_AGP_ENABLE);
1762         pci_read_config_dword(dev->pdev, RADEON_AGP_COMMAND_PCI_CONFIG, &temp);
1763         if (temp & RADEON_AGP_ENABLE)
1764                 dev_priv->flags |= CHIP_IS_AGP;
1765         DRM_DEBUG("%s card detected\n", ((dev_priv->flags & CHIP_IS_AGP) ? "AGP" : "PCI"));
1766         pci_write_config_dword(dev->pdev, RADEON_AGP_COMMAND_PCI_CONFIG, save);
1767
1768         /* Check if we need a reset */
1769         if (!(dev_priv->mmio = drm_core_findmap(dev , pci_resource_start( dev->pdev, 2 ))))
1770                 return DRM_ERR(ENOMEM);
1771
1772 #if defined(__linux__)
1773         ret = radeon_create_i2c_busses(dev);
1774 #endif
1775         return ret;
1776 }
1777
1778 int radeon_postcleanup( struct drm_device *dev )
1779 {
1780         drm_radeon_private_t *dev_priv = dev->dev_private;
1781
1782         DRM_DEBUG("\n");
1783 #if defined(__linux__)
1784         radeon_delete_i2c_busses(dev);
1785 #endif
1786         drm_free( dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER );
1787
1788         dev->dev_private = NULL;
1789         return 0;
1790 }