shared-core/radeon_cp.c

   1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*-
   2  *
   3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11  * and/or sell copies of the Software, and to permit persons to whom the
  12  * Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the next
  15  * paragraph) shall be included in all copies or substantial portions of the
  16  * Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  21  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  22  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  23  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  24  * DEALINGS IN THE SOFTWARE.
  25  *
  26  * Authors:
  27  *    Kevin E. Martin <martin@valinux.com>
  28  *    Gareth Hughes <gareth@valinux.com>
  29  */
  30
  31 #include "radeon.h"
  32 #include "drmP.h"
  33 #include "drm.h"
  34 #include "radeon_drm.h"
  35 #include "radeon_drv.h"
  36
  37 #define RADEON_FIFO_DEBUG       0
  38
  39 #if defined(__alpha__) || defined(__powerpc__)
  40 # define PCIGART_ENABLED
  41 #else
  42 # undef PCIGART_ENABLED
  43 #endif
  44
  45
  46 /* CP microcode (from ATI) */
  47 static u32 R200_cp_microcode[][2] = {
  48         { 0x21007000, 0000000000 },
  49         { 0x20007000, 0000000000 },
  50         { 0x000000ab, 0x00000004 },
  51         { 0x000000af, 0x00000004 },
  52         { 0x66544a49, 0000000000 },
  53         { 0x49494174, 0000000000 },
  54         { 0x54517d83, 0000000000 },
  55         { 0x498d8b64, 0000000000 },
  56         { 0x49494949, 0000000000 },
  57         { 0x49da493c, 0000000000 },
  58         { 0x49989898, 0000000000 },
  59         { 0xd34949d5, 0000000000 },
  60         { 0x9dc90e11, 0000000000 },
  61         { 0xce9b9b9b, 0000000000 },
  62         { 0x000f0000, 0x00000016 },
  63         { 0x352e232c, 0000000000 },
  64         { 0x00000013, 0x00000004 },
  65         { 0x000f0000, 0x00000016 },
  66         { 0x352e272c, 0000000000 },
  67         { 0x000f0001, 0x00000016 },
  68         { 0x3239362f, 0000000000 },
  69         { 0x000077ef, 0x00000002 },
  70         { 0x00061000, 0x00000002 },
  71         { 0x00000020, 0x0000001a },
  72         { 0x00004000, 0x0000001e },
  73         { 0x00061000, 0x00000002 },
  74         { 0x00000020, 0x0000001a },
  75         { 0x00004000, 0x0000001e },
  76         { 0x00061000, 0x00000002 },
  77         { 0x00000020, 0x0000001a },
  78         { 0x00004000, 0x0000001e },
  79         { 0x00000016, 0x00000004 },
  80         { 0x0003802a, 0x00000002 },
  81         { 0x040067e0, 0x00000002 },
  82         { 0x00000016, 0x00000004 },
  83         { 0x000077e0, 0x00000002 },
  84         { 0x00065000, 0x00000002 },
  85         { 0x000037e1, 0x00000002 },
  86         { 0x040067e1, 0x00000006 },
  87         { 0x000077e0, 0x00000002 },
  88         { 0x000077e1, 0x00000002 },
  89         { 0x000077e1, 0x00000006 },
  90         { 0xffffffff, 0000000000 },
  91         { 0x10000000, 0000000000 },
  92         { 0x0003802a, 0x00000002 },
  93         { 0x040067e0, 0x00000006 },
  94         { 0x00007675, 0x00000002 },
  95         { 0x00007676, 0x00000002 },
  96         { 0x00007677, 0x00000002 },
  97         { 0x00007678, 0x00000006 },
  98         { 0x0003802b, 0x00000002 },
  99         { 0x04002676, 0x00000002 },
 100         { 0x00007677, 0x00000002 },
 101         { 0x00007678, 0x00000006 },
 102         { 0x0000002e, 0x00000018 },
 103         { 0x0000002e, 0x00000018 },
 104         { 0000000000, 0x00000006 },
 105         { 0x0000002f, 0x00000018 },
 106         { 0x0000002f, 0x00000018 },
 107         { 0000000000, 0x00000006 },
 108         { 0x01605000, 0x00000002 },
 109         { 0x00065000, 0x00000002 },
 110         { 0x00098000, 0x00000002 },
 111         { 0x00061000, 0x00000002 },
 112         { 0x64c0603d, 0x00000004 },
 113         { 0x00080000, 0x00000016 },
 114         { 0000000000, 0000000000 },
 115         { 0x0400251d, 0x00000002 },
 116         { 0x00007580, 0x00000002 },
 117         { 0x00067581, 0x00000002 },
 118         { 0x04002580, 0x00000002 },
 119         { 0x00067581, 0x00000002 },
 120         { 0x00000046, 0x00000004 },
 121         { 0x00005000, 0000000000 },
 122         { 0x00061000, 0x00000002 },
 123         { 0x0000750e, 0x00000002 },
 124         { 0x00019000, 0x00000002 },
 125         { 0x00011055, 0x00000014 },
 126         { 0x00000055, 0x00000012 },
 127         { 0x0400250f, 0x00000002 },
 128         { 0x0000504a, 0x00000004 },
 129         { 0x00007565, 0x00000002 },
 130         { 0x00007566, 0x00000002 },
 131         { 0x00000051, 0x00000004 },
 132         { 0x01e655b4, 0x00000002 },
 133         { 0x4401b0dc, 0x00000002 },
 134         { 0x01c110dc, 0x00000002 },
 135         { 0x2666705d, 0x00000018 },
 136         { 0x040c2565, 0x00000002 },
 137         { 0x0000005d, 0x00000018 },
 138         { 0x04002564, 0x00000002 },
 139         { 0x00007566, 0x00000002 },
 140         { 0x00000054, 0x00000004 },
 141         { 0x00401060, 0x00000008 },
 142         { 0x00101000, 0x00000002 },
 143         { 0x000d80ff, 0x00000002 },
 144         { 0x00800063, 0x00000008 },
 145         { 0x000f9000, 0x00000002 },
 146         { 0x000e00ff, 0x00000002 },
 147         { 0000000000, 0x00000006 },
 148         { 0x00000080, 0x00000018 },
 149         { 0x00000054, 0x00000004 },
 150         { 0x00007576, 0x00000002 },
 151         { 0x00065000, 0x00000002 },
 152         { 0x00009000, 0x00000002 },
 153         { 0x00041000, 0x00000002 },
 154         { 0x0c00350e, 0x00000002 },
 155         { 0x00049000, 0x00000002 },
 156         { 0x00051000, 0x00000002 },
 157         { 0x01e785f8, 0x00000002 },
 158         { 0x00200000, 0x00000002 },
 159         { 0x00600073, 0x0000000c },
 160         { 0x00007563, 0x00000002 },
 161         { 0x006075f0, 0x00000021 },
 162         { 0x20007068, 0x00000004 },
 163         { 0x00005068, 0x00000004 },
 164         { 0x00007576, 0x00000002 },
 165         { 0x00007577, 0x00000002 },
 166         { 0x0000750e, 0x00000002 },
 167         { 0x0000750f, 0x00000002 },
 168         { 0x00a05000, 0x00000002 },
 169         { 0x00600076, 0x0000000c },
 170         { 0x006075f0, 0x00000021 },
 171         { 0x000075f8, 0x00000002 },
 172         { 0x00000076, 0x00000004 },
 173         { 0x000a750e, 0x00000002 },
 174         { 0x0020750f, 0x00000002 },
 175         { 0x00600079, 0x00000004 },
 176         { 0x00007570, 0x00000002 },
 177         { 0x00007571, 0x00000002 },
 178         { 0x00007572, 0x00000006 },
 179         { 0x00005000, 0x00000002 },
 180         { 0x00a05000, 0x00000002 },
 181         { 0x00007568, 0x00000002 },
 182         { 0x00061000, 0x00000002 },
 183         { 0x00000084, 0x0000000c },
 184         { 0x00058000, 0x00000002 },
 185         { 0x0c607562, 0x00000002 },
 186         { 0x00000086, 0x00000004 },
 187         { 0x00600085, 0x00000004 },
 188         { 0x400070dd, 0000000000 },
 189         { 0x000380dd, 0x00000002 },
 190         { 0x00000093, 0x0000001c },
 191         { 0x00065095, 0x00000018 },
 192         { 0x040025bb, 0x00000002 },
 193         { 0x00061096, 0x00000018 },
 194         { 0x040075bc, 0000000000 },
 195         { 0x000075bb, 0x00000002 },
 196         { 0x000075bc, 0000000000 },
 197         { 0x00090000, 0x00000006 },
 198         { 0x00090000, 0x00000002 },
 199         { 0x000d8002, 0x00000006 },
 200         { 0x00005000, 0x00000002 },
 201         { 0x00007821, 0x00000002 },
 202         { 0x00007800, 0000000000 },
 203         { 0x00007821, 0x00000002 },
 204         { 0x00007800, 0000000000 },
 205         { 0x01665000, 0x00000002 },
 206         { 0x000a0000, 0x00000002 },
 207         { 0x000671cc, 0x00000002 },
 208         { 0x0286f1cd, 0x00000002 },
 209         { 0x000000a3, 0x00000010 },
 210         { 0x21007000, 0000000000 },
 211         { 0x000000aa, 0x0000001c },
 212         { 0x00065000, 0x00000002 },
 213         { 0x000a0000, 0x00000002 },
 214         { 0x00061000, 0x00000002 },
 215         { 0x000b0000, 0x00000002 },
 216         { 0x38067000, 0x00000002 },
 217         { 0x000a00a6, 0x00000004 },
 218         { 0x20007000, 0000000000 },
 219         { 0x01200000, 0x00000002 },
 220         { 0x20077000, 0x00000002 },
 221         { 0x01200000, 0x00000002 },
 222         { 0x20007000, 0000000000 },
 223         { 0x00061000, 0x00000002 },
 224         { 0x0120751b, 0x00000002 },
 225         { 0x8040750a, 0x00000002 },
 226         { 0x8040750b, 0x00000002 },
 227         { 0x00110000, 0x00000002 },
 228         { 0x000380dd, 0x00000002 },
 229         { 0x000000bd, 0x0000001c },
 230         { 0x00061096, 0x00000018 },
 231         { 0x844075bd, 0x00000002 },
 232         { 0x00061095, 0x00000018 },
 233         { 0x840075bb, 0x00000002 },
 234         { 0x00061096, 0x00000018 },
 235         { 0x844075bc, 0x00000002 },
 236         { 0x000000c0, 0x00000004 },
 237         { 0x804075bd, 0x00000002 },
 238         { 0x800075bb, 0x00000002 },
 239         { 0x804075bc, 0x00000002 },
 240         { 0x00108000, 0x00000002 },
 241         { 0x01400000, 0x00000002 },
 242         { 0x006000c4, 0x0000000c },
 243         { 0x20c07000, 0x00000020 },
 244         { 0x000000c6, 0x00000012 },
 245         { 0x00800000, 0x00000006 },
 246         { 0x0080751d, 0x00000006 },
 247         { 0x000025bb, 0x00000002 },
 248         { 0x000040c0, 0x00000004 },
 249         { 0x0000775c, 0x00000002 },
 250         { 0x00a05000, 0x00000002 },
 251         { 0x00661000, 0x00000002 },
 252         { 0x0460275d, 0x00000020 },
 253         { 0x00004000, 0000000000 },
 254         { 0x00007999, 0x00000002 },
 255         { 0x00a05000, 0x00000002 },
 256         { 0x00661000, 0x00000002 },
 257         { 0x0460299b, 0x00000020 },
 258         { 0x00004000, 0000000000 },
 259         { 0x01e00830, 0x00000002 },
 260         { 0x21007000, 0000000000 },
 261         { 0x00005000, 0x00000002 },
 262         { 0x00038042, 0x00000002 },
 263         { 0x040025e0, 0x00000002 },
 264         { 0x000075e1, 0000000000 },
 265         { 0x00000001, 0000000000 },
 266         { 0x000380d9, 0x00000002 },
 267         { 0x04007394, 0000000000 },
 268         { 0000000000, 0000000000 },
 269         { 0000000000, 0000000000 },
 270         { 0000000000, 0000000000 },
 271         { 0000000000, 0000000000 },
 272         { 0000000000, 0000000000 },
 273         { 0000000000, 0000000000 },
 274         { 0000000000, 0000000000 },
 275         { 0000000000, 0000000000 },
 276         { 0000000000, 0000000000 },
 277         { 0000000000, 0000000000 },
 278         { 0000000000, 0000000000 },
 279         { 0000000000, 0000000000 },
 280         { 0000000000, 0000000000 },
 281         { 0000000000, 0000000000 },
 282         { 0000000000, 0000000000 },
 283         { 0000000000, 0000000000 },
 284         { 0000000000, 0000000000 },
 285         { 0000000000, 0000000000 },
 286         { 0000000000, 0000000000 },
 287         { 0000000000, 0000000000 },
 288         { 0000000000, 0000000000 },
 289         { 0000000000, 0000000000 },
 290         { 0000000000, 0000000000 },
 291         { 0000000000, 0000000000 },
 292         { 0000000000, 0000000000 },
 293         { 0000000000, 0000000000 },
 294         { 0000000000, 0000000000 },
 295         { 0000000000, 0000000000 },
 296         { 0000000000, 0000000000 },
 297         { 0000000000, 0000000000 },
 298         { 0000000000, 0000000000 },
 299         { 0000000000, 0000000000 },
 300         { 0000000000, 0000000000 },
 301         { 0000000000, 0000000000 },
 302         { 0000000000, 0000000000 },
 303         { 0000000000, 0000000000 },
 304 };
 305
 306
 307 static u32 radeon_cp_microcode[][2] = {
 308         { 0x21007000, 0000000000 },
 309         { 0x20007000, 0000000000 },
 310         { 0x000000b4, 0x00000004 },
 311         { 0x000000b8, 0x00000004 },
 312         { 0x6f5b4d4c, 0000000000 },
 313         { 0x4c4c427f, 0000000000 },
 314         { 0x5b568a92, 0000000000 },
 315         { 0x4ca09c6d, 0000000000 },
 316         { 0xad4c4c4c, 0000000000 },
 317         { 0x4ce1af3d, 0000000000 },
 318         { 0xd8afafaf, 0000000000 },
 319         { 0xd64c4cdc, 0000000000 },
 320         { 0x4cd10d10, 0000000000 },
 321         { 0x000f0000, 0x00000016 },
 322         { 0x362f242d, 0000000000 },
 323         { 0x00000012, 0x00000004 },
 324         { 0x000f0000, 0x00000016 },
 325         { 0x362f282d, 0000000000 },
 326         { 0x000380e7, 0x00000002 },
 327         { 0x04002c97, 0x00000002 },
 328         { 0x000f0001, 0x00000016 },
 329         { 0x333a3730, 0000000000 },
 330         { 0x000077ef, 0x00000002 },
 331         { 0x00061000, 0x00000002 },
 332         { 0x00000021, 0x0000001a },
 333         { 0x00004000, 0x0000001e },
 334         { 0x00061000, 0x00000002 },
 335         { 0x00000021, 0x0000001a },
 336         { 0x00004000, 0x0000001e },
 337         { 0x00061000, 0x00000002 },
 338         { 0x00000021, 0x0000001a },
 339         { 0x00004000, 0x0000001e },
 340         { 0x00000017, 0x00000004 },
 341         { 0x0003802b, 0x00000002 },
 342         { 0x040067e0, 0x00000002 },
 343         { 0x00000017, 0x00000004 },
 344         { 0x000077e0, 0x00000002 },
 345         { 0x00065000, 0x00000002 },
 346         { 0x000037e1, 0x00000002 },
 347         { 0x040067e1, 0x00000006 },
 348         { 0x000077e0, 0x00000002 },
 349         { 0x000077e1, 0x00000002 },
 350         { 0x000077e1, 0x00000006 },
 351         { 0xffffffff, 0000000000 },
 352         { 0x10000000, 0000000000 },
 353         { 0x0003802b, 0x00000002 },
 354         { 0x040067e0, 0x00000006 },
 355         { 0x00007675, 0x00000002 },
 356         { 0x00007676, 0x00000002 },
 357         { 0x00007677, 0x00000002 },
 358         { 0x00007678, 0x00000006 },
 359         { 0x0003802c, 0x00000002 },
 360         { 0x04002676, 0x00000002 },
 361         { 0x00007677, 0x00000002 },
 362         { 0x00007678, 0x00000006 },
 363         { 0x0000002f, 0x00000018 },
 364         { 0x0000002f, 0x00000018 },
 365         { 0000000000, 0x00000006 },
 366         { 0x00000030, 0x00000018 },
 367         { 0x00000030, 0x00000018 },
 368         { 0000000000, 0x00000006 },
 369         { 0x01605000, 0x00000002 },
 370         { 0x00065000, 0x00000002 },
 371         { 0x00098000, 0x00000002 },
 372         { 0x00061000, 0x00000002 },
 373         { 0x64c0603e, 0x00000004 },
 374         { 0x000380e6, 0x00000002 },
 375         { 0x040025c5, 0x00000002 },
 376         { 0x00080000, 0x00000016 },
 377         { 0000000000, 0000000000 },
 378         { 0x0400251d, 0x00000002 },
 379         { 0x00007580, 0x00000002 },
 380         { 0x00067581, 0x00000002 },
 381         { 0x04002580, 0x00000002 },
 382         { 0x00067581, 0x00000002 },
 383         { 0x00000049, 0x00000004 },
 384         { 0x00005000, 0000000000 },
 385         { 0x000380e6, 0x00000002 },
 386         { 0x040025c5, 0x00000002 },
 387         { 0x00061000, 0x00000002 },
 388         { 0x0000750e, 0x00000002 },
 389         { 0x00019000, 0x00000002 },
 390         { 0x00011055, 0x00000014 },
 391         { 0x00000055, 0x00000012 },
 392         { 0x0400250f, 0x00000002 },
 393         { 0x0000504f, 0x00000004 },
 394         { 0x000380e6, 0x00000002 },
 395         { 0x040025c5, 0x00000002 },
 396         { 0x00007565, 0x00000002 },
 397         { 0x00007566, 0x00000002 },
 398         { 0x00000058, 0x00000004 },
 399         { 0x000380e6, 0x00000002 },
 400         { 0x040025c5, 0x00000002 },
 401         { 0x01e655b4, 0x00000002 },
 402         { 0x4401b0e4, 0x00000002 },
 403         { 0x01c110e4, 0x00000002 },
 404         { 0x26667066, 0x00000018 },
 405         { 0x040c2565, 0x00000002 },
 406         { 0x00000066, 0x00000018 },
 407         { 0x04002564, 0x00000002 },
 408         { 0x00007566, 0x00000002 },
 409         { 0x0000005d, 0x00000004 },
 410         { 0x00401069, 0x00000008 },
 411         { 0x00101000, 0x00000002 },
 412         { 0x000d80ff, 0x00000002 },
 413         { 0x0080006c, 0x00000008 },
 414         { 0x000f9000, 0x00000002 },
 415         { 0x000e00ff, 0x00000002 },
 416         { 0000000000, 0x00000006 },
 417         { 0x0000008f, 0x00000018 },
 418         { 0x0000005b, 0x00000004 },
 419         { 0x000380e6, 0x00000002 },
 420         { 0x040025c5, 0x00000002 },
 421         { 0x00007576, 0x00000002 },
 422         { 0x00065000, 0x00000002 },
 423         { 0x00009000, 0x00000002 },
 424         { 0x00041000, 0x00000002 },
 425         { 0x0c00350e, 0x00000002 },
 426         { 0x00049000, 0x00000002 },
 427         { 0x00051000, 0x00000002 },
 428         { 0x01e785f8, 0x00000002 },
 429         { 0x00200000, 0x00000002 },
 430         { 0x0060007e, 0x0000000c },
 431         { 0x00007563, 0x00000002 },
 432         { 0x006075f0, 0x00000021 },
 433         { 0x20007073, 0x00000004 },
 434         { 0x00005073, 0x00000004 },
 435         { 0x000380e6, 0x00000002 },
 436         { 0x040025c5, 0x00000002 },
 437         { 0x00007576, 0x00000002 },
 438         { 0x00007577, 0x00000002 },
 439         { 0x0000750e, 0x00000002 },
 440         { 0x0000750f, 0x00000002 },
 441         { 0x00a05000, 0x00000002 },
 442         { 0x00600083, 0x0000000c },
 443         { 0x006075f0, 0x00000021 },
 444         { 0x000075f8, 0x00000002 },
 445         { 0x00000083, 0x00000004 },
 446         { 0x000a750e, 0x00000002 },
 447         { 0x000380e6, 0x00000002 },
 448         { 0x040025c5, 0x00000002 },
 449         { 0x0020750f, 0x00000002 },
 450         { 0x00600086, 0x00000004 },
 451         { 0x00007570, 0x00000002 },
 452         { 0x00007571, 0x00000002 },
 453         { 0x00007572, 0x00000006 },
 454         { 0x000380e6, 0x00000002 },
 455         { 0x040025c5, 0x00000002 },
 456         { 0x00005000, 0x00000002 },
 457         { 0x00a05000, 0x00000002 },
 458         { 0x00007568, 0x00000002 },
 459         { 0x00061000, 0x00000002 },
 460         { 0x00000095, 0x0000000c },
 461         { 0x00058000, 0x00000002 },
 462         { 0x0c607562, 0x00000002 },
 463         { 0x00000097, 0x00000004 },
 464         { 0x000380e6, 0x00000002 },
 465         { 0x040025c5, 0x00000002 },
 466         { 0x00600096, 0x00000004 },
 467         { 0x400070e5, 0000000000 },
 468         { 0x000380e6, 0x00000002 },
 469         { 0x040025c5, 0x00000002 },
 470         { 0x000380e5, 0x00000002 },
 471         { 0x000000a8, 0x0000001c },
 472         { 0x000650aa, 0x00000018 },
 473         { 0x040025bb, 0x00000002 },
 474         { 0x000610ab, 0x00000018 },
 475         { 0x040075bc, 0000000000 },
 476         { 0x000075bb, 0x00000002 },
 477         { 0x000075bc, 0000000000 },
 478         { 0x00090000, 0x00000006 },
 479         { 0x00090000, 0x00000002 },
 480         { 0x000d8002, 0x00000006 },
 481         { 0x00007832, 0x00000002 },
 482         { 0x00005000, 0x00000002 },
 483         { 0x000380e7, 0x00000002 },
 484         { 0x04002c97, 0x00000002 },
 485         { 0x00007820, 0x00000002 },
 486         { 0x00007821, 0x00000002 },
 487         { 0x00007800, 0000000000 },
 488         { 0x01200000, 0x00000002 },
 489         { 0x20077000, 0x00000002 },
 490         { 0x01200000, 0x00000002 },
 491         { 0x20007000, 0x00000002 },
 492         { 0x00061000, 0x00000002 },
 493         { 0x0120751b, 0x00000002 },
 494         { 0x8040750a, 0x00000002 },
 495         { 0x8040750b, 0x00000002 },
 496         { 0x00110000, 0x00000002 },
 497         { 0x000380e5, 0x00000002 },
 498         { 0x000000c6, 0x0000001c },
 499         { 0x000610ab, 0x00000018 },
 500         { 0x844075bd, 0x00000002 },
 501         { 0x000610aa, 0x00000018 },
 502         { 0x840075bb, 0x00000002 },
 503         { 0x000610ab, 0x00000018 },
 504         { 0x844075bc, 0x00000002 },
 505         { 0x000000c9, 0x00000004 },
 506         { 0x804075bd, 0x00000002 },
 507         { 0x800075bb, 0x00000002 },
 508         { 0x804075bc, 0x00000002 },
 509         { 0x00108000, 0x00000002 },
 510         { 0x01400000, 0x00000002 },
 511         { 0x006000cd, 0x0000000c },
 512         { 0x20c07000, 0x00000020 },
 513         { 0x000000cf, 0x00000012 },
 514         { 0x00800000, 0x00000006 },
 515         { 0x0080751d, 0x00000006 },
 516         { 0000000000, 0000000000 },
 517         { 0x0000775c, 0x00000002 },
 518         { 0x00a05000, 0x00000002 },
 519         { 0x00661000, 0x00000002 },
 520         { 0x0460275d, 0x00000020 },
 521         { 0x00004000, 0000000000 },
 522         { 0x01e00830, 0x00000002 },
 523         { 0x21007000, 0000000000 },
 524         { 0x6464614d, 0000000000 },
 525         { 0x69687420, 0000000000 },
 526         { 0x00000073, 0000000000 },
 527         { 0000000000, 0000000000 },
 528         { 0x00005000, 0x00000002 },
 529         { 0x000380d0, 0x00000002 },
 530         { 0x040025e0, 0x00000002 },
 531         { 0x000075e1, 0000000000 },
 532         { 0x00000001, 0000000000 },
 533         { 0x000380e0, 0x00000002 },
 534         { 0x04002394, 0x00000002 },
 535         { 0x00005000, 0000000000 },
 536         { 0000000000, 0000000000 },
 537         { 0000000000, 0000000000 },
 538         { 0x00000008, 0000000000 },
 539         { 0x00000004, 0000000000 },
 540         { 0000000000, 0000000000 },
 541         { 0000000000, 0000000000 },
 542         { 0000000000, 0000000000 },
 543         { 0000000000, 0000000000 },
 544         { 0000000000, 0000000000 },
 545         { 0000000000, 0000000000 },
 546         { 0000000000, 0000000000 },
 547         { 0000000000, 0000000000 },
 548         { 0000000000, 0000000000 },
 549         { 0000000000, 0000000000 },
 550         { 0000000000, 0000000000 },
 551         { 0000000000, 0000000000 },
 552         { 0000000000, 0000000000 },
 553         { 0000000000, 0000000000 },
 554         { 0000000000, 0000000000 },
 555         { 0000000000, 0000000000 },
 556         { 0000000000, 0000000000 },
 557         { 0000000000, 0000000000 },
 558         { 0000000000, 0000000000 },
 559         { 0000000000, 0000000000 },
 560         { 0000000000, 0000000000 },
 561         { 0000000000, 0000000000 },
 562         { 0000000000, 0000000000 },
 563         { 0000000000, 0000000000 },
 564 };
 565
 566
 567 int RADEON_READ_PLL(drm_device_t *dev, int addr)
 568 {
 569         drm_radeon_private_t *dev_priv = dev->dev_private;
 570
 571         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
 572         return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 573 }
 574
 575 #if RADEON_FIFO_DEBUG
 576 static void radeon_status( drm_radeon_private_t *dev_priv )
 577 {
 578         printk( "%s:\n", __FUNCTION__ );
 579         printk( "RBBM_STATUS = 0x%08x\n",
 580                 (unsigned int)RADEON_READ( RADEON_RBBM_STATUS ) );
 581         printk( "CP_RB_RTPR = 0x%08x\n",
 582                 (unsigned int)RADEON_READ( RADEON_CP_RB_RPTR ) );
 583         printk( "CP_RB_WTPR = 0x%08x\n",
 584                 (unsigned int)RADEON_READ( RADEON_CP_RB_WPTR ) );
 585         printk( "AIC_CNTL = 0x%08x\n",
 586                 (unsigned int)RADEON_READ( RADEON_AIC_CNTL ) );
 587         printk( "AIC_STAT = 0x%08x\n",
 588                 (unsigned int)RADEON_READ( RADEON_AIC_STAT ) );
 589         printk( "AIC_PT_BASE = 0x%08x\n",
 590                 (unsigned int)RADEON_READ( RADEON_AIC_PT_BASE ) );
 591         printk( "TLB_ADDR = 0x%08x\n",
 592                 (unsigned int)RADEON_READ( RADEON_AIC_TLB_ADDR ) );
 593         printk( "TLB_DATA = 0x%08x\n",
 594                 (unsigned int)RADEON_READ( RADEON_AIC_TLB_DATA ) );
 595 }
 596 #endif
 597
 598
 599 /* ================================================================
 600  * Engine, FIFO control
 601  */
 602
 603 static int radeon_do_pixcache_flush( drm_radeon_private_t *dev_priv )
 604 {
 605         u32 tmp;
 606         int i;
 607
 608         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 609
 610         tmp  = RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT );
 611         tmp |= RADEON_RB2D_DC_FLUSH_ALL;
 612         RADEON_WRITE( RADEON_RB2D_DSTCACHE_CTLSTAT, tmp );
 613
 614         for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
 615                 if ( !(RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT )
 616                        & RADEON_RB2D_DC_BUSY) ) {
 617                         return 0;
 618                 }
 619                 DRM_UDELAY( 1 );
 620         }
 621
 622 #if RADEON_FIFO_DEBUG
 623         DRM_ERROR( "failed!\n" );
 624         radeon_status( dev_priv );
 625 #endif
 626         return DRM_ERR(EBUSY);
 627 }
 628
 629 static int radeon_do_wait_for_fifo( drm_radeon_private_t *dev_priv,
 630                                     int entries )
 631 {
 632         int i;
 633
 634         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 635
 636         for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
 637                 int slots = ( RADEON_READ( RADEON_RBBM_STATUS )
 638                               & RADEON_RBBM_FIFOCNT_MASK );
 639                 if ( slots >= entries ) return 0;
 640                 DRM_UDELAY( 1 );
 641         }
 642
 643 #if RADEON_FIFO_DEBUG
 644         DRM_ERROR( "failed!\n" );
 645         radeon_status( dev_priv );
 646 #endif
 647         return DRM_ERR(EBUSY);
 648 }
 649
 650 static int radeon_do_wait_for_idle( drm_radeon_private_t *dev_priv )
 651 {
 652         int i, ret;
 653
 654         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 655
 656         ret = radeon_do_wait_for_fifo( dev_priv, 64 );
 657         if ( ret ) return ret;
 658
 659         for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
 660                 if ( !(RADEON_READ( RADEON_RBBM_STATUS )
 661                        & RADEON_RBBM_ACTIVE) ) {
 662                         radeon_do_pixcache_flush( dev_priv );
 663                         return 0;
 664                 }
 665                 DRM_UDELAY( 1 );
 666         }
 667
 668 #if RADEON_FIFO_DEBUG
 669         DRM_ERROR( "failed!\n" );
 670         radeon_status( dev_priv );
 671 #endif
 672         return DRM_ERR(EBUSY);
 673 }
 674
 675
 676 /* ================================================================
 677  * CP control, initialization
 678  */
 679
 680 /* Load the microcode for the CP */
 681 static void radeon_cp_load_microcode( drm_radeon_private_t *dev_priv )
 682 {
 683         int i;
 684         DRM_DEBUG( "\n" );
 685
 686         radeon_do_wait_for_idle( dev_priv );
 687
 688         RADEON_WRITE( RADEON_CP_ME_RAM_ADDR, 0 );
 689
 690         if (dev_priv->is_r200)
 691         {
 692                 DRM_INFO("Loading R200 Microcode\n");
 693                 for ( i = 0 ; i < 256 ; i++ )
 694                 {
 695                         RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
 696                                       R200_cp_microcode[i][1] );
 697                         RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
 698                                       R200_cp_microcode[i][0] );
 699                 }
 700         }
 701         else
 702         {
 703                 for ( i = 0 ; i < 256 ; i++ ) {
 704                         RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
 705                                       radeon_cp_microcode[i][1] );
 706                         RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
 707                                       radeon_cp_microcode[i][0] );
 708                 }
 709         }
 710 }
 711
 712 /* Flush any pending commands to the CP.  This should only be used just
 713  * prior to a wait for idle, as it informs the engine that the command
 714  * stream is ending.
 715  */
 716 static void radeon_do_cp_flush( drm_radeon_private_t *dev_priv )
 717 {
 718         DRM_DEBUG( "\n" );
 719 #if 0
 720         u32 tmp;
 721
 722         tmp = RADEON_READ( RADEON_CP_RB_WPTR ) | (1 << 31);
 723         RADEON_WRITE( RADEON_CP_RB_WPTR, tmp );
 724 #endif
 725 }
 726
 727 /* Wait for the CP to go idle.
 728  */
 729 int radeon_do_cp_idle( drm_radeon_private_t *dev_priv )
 730 {
 731         RING_LOCALS;
 732         DRM_DEBUG( "\n" );
 733
 734         BEGIN_RING( 6 );
 735
 736         RADEON_PURGE_CACHE();
 737         RADEON_PURGE_ZCACHE();
 738         RADEON_WAIT_UNTIL_IDLE();
 739
 740         ADVANCE_RING();
 741         COMMIT_RING();
 742
 743         return radeon_do_wait_for_idle( dev_priv );
 744 }
 745
 746 /* Start the Command Processor.
 747  */
 748 static void radeon_do_cp_start( drm_radeon_private_t *dev_priv )
 749 {
 750         RING_LOCALS;
 751         DRM_DEBUG( "\n" );
 752
 753         radeon_do_wait_for_idle( dev_priv );
 754
 755         RADEON_WRITE( RADEON_CP_CSQ_CNTL, dev_priv->cp_mode );
 756
 757         dev_priv->cp_running = 1;
 758
 759         BEGIN_RING( 6 );
 760
 761         RADEON_PURGE_CACHE();
 762         RADEON_PURGE_ZCACHE();
 763         RADEON_WAIT_UNTIL_IDLE();
 764
 765         ADVANCE_RING();
 766         COMMIT_RING();
 767 }
 768
 769 /* Reset the Command Processor.  This will not flush any pending
 770  * commands, so you must wait for the CP command stream to complete
 771  * before calling this routine.
 772  */
 773 static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv )
 774 {
 775         u32 cur_read_ptr;
 776         DRM_DEBUG( "\n" );
 777
 778         cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
 779         RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
 780         *dev_priv->ring.head = cur_read_ptr;
 781         dev_priv->ring.tail = cur_read_ptr;
 782 }
 783
 784 /* Stop the Command Processor.  This will not flush any pending
 785  * commands, so you must flush the command stream and wait for the CP
 786  * to go idle before calling this routine.
 787  */
 788 static void radeon_do_cp_stop( drm_radeon_private_t *dev_priv )
 789 {
 790         DRM_DEBUG( "\n" );
 791
 792         RADEON_WRITE( RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS );
 793
 794         dev_priv->cp_running = 0;
 795 }
 796
 797 /* Reset the engine.  This will stop the CP if it is running.
 798  */
 799 static int radeon_do_engine_reset( drm_device_t *dev )
 800 {
 801         drm_radeon_private_t *dev_priv = dev->dev_private;
 802         u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
 803         DRM_DEBUG( "\n" );
 804
 805         radeon_do_pixcache_flush( dev_priv );
 806
 807         clock_cntl_index = RADEON_READ( RADEON_CLOCK_CNTL_INDEX );
 808         mclk_cntl = RADEON_READ_PLL( dev, RADEON_MCLK_CNTL );
 809
 810         RADEON_WRITE_PLL( RADEON_MCLK_CNTL, ( mclk_cntl |
 811                                               RADEON_FORCEON_MCLKA |
 812                                               RADEON_FORCEON_MCLKB |
 813                                               RADEON_FORCEON_YCLKA |
 814                                               RADEON_FORCEON_YCLKB |
 815                                               RADEON_FORCEON_MC |
 816                                               RADEON_FORCEON_AIC ) );
 817
 818         rbbm_soft_reset = RADEON_READ( RADEON_RBBM_SOFT_RESET );
 819
 820         RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset |
 821                                                 RADEON_SOFT_RESET_CP |
 822                                                 RADEON_SOFT_RESET_HI |
 823                                                 RADEON_SOFT_RESET_SE |
 824                                                 RADEON_SOFT_RESET_RE |
 825                                                 RADEON_SOFT_RESET_PP |
 826                                                 RADEON_SOFT_RESET_E2 |
 827                                                 RADEON_SOFT_RESET_RB ) );
 828         RADEON_READ( RADEON_RBBM_SOFT_RESET );
 829         RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset &
 830                                                 ~( RADEON_SOFT_RESET_CP |
 831                                                    RADEON_SOFT_RESET_HI |
 832                                                    RADEON_SOFT_RESET_SE |
 833                                                    RADEON_SOFT_RESET_RE |
 834                                                    RADEON_SOFT_RESET_PP |
 835                                                    RADEON_SOFT_RESET_E2 |
 836                                                    RADEON_SOFT_RESET_RB ) ) );
 837         RADEON_READ( RADEON_RBBM_SOFT_RESET );
 838
 839
 840         RADEON_WRITE_PLL( RADEON_MCLK_CNTL, mclk_cntl );
 841         RADEON_WRITE( RADEON_CLOCK_CNTL_INDEX, clock_cntl_index );
 842         RADEON_WRITE( RADEON_RBBM_SOFT_RESET,  rbbm_soft_reset );
 843
 844         /* Reset the CP ring */
 845         radeon_do_cp_reset( dev_priv );
 846
 847         /* The CP is no longer running after an engine reset */
 848         dev_priv->cp_running = 0;
 849
 850         /* Reset any pending vertex, indirect buffers */
 851         radeon_freelist_reset( dev );
 852
 853         return 0;
 854 }
 855
 856 static void radeon_cp_init_ring_buffer( drm_device_t *dev,
 857                                         drm_radeon_private_t *dev_priv )
 858 {
 859         u32 ring_start, cur_read_ptr;
 860         u32 tmp;
 861
 862         /* Initialize the memory controller */
 863         RADEON_WRITE( RADEON_MC_FB_LOCATION,
 864                       (dev_priv->agp_vm_start - 1) & 0xffff0000 );
 865
 866         if ( !dev_priv->is_pci ) {
 867                 RADEON_WRITE( RADEON_MC_AGP_LOCATION,
 868                               (((dev_priv->agp_vm_start - 1 +
 869                                  dev_priv->agp_size) & 0xffff0000) |
 870                                (dev_priv->agp_vm_start >> 16)) );
 871         }
 872
 873 #if __REALLY_HAVE_AGP
 874         if ( !dev_priv->is_pci )
 875                 ring_start = (dev_priv->cp_ring->offset
 876                               - dev->agp->base
 877                               + dev_priv->agp_vm_start);
 878        else
 879 #endif
 880                 ring_start = (dev_priv->cp_ring->offset
 881                               - dev->sg->handle
 882                               + dev_priv->agp_vm_start);
 883
 884         RADEON_WRITE( RADEON_CP_RB_BASE, ring_start );
 885
 886         /* Set the write pointer delay */
 887         RADEON_WRITE( RADEON_CP_RB_WPTR_DELAY, 0 );
 888
 889         /* Initialize the ring buffer's read and write pointers */
 890         cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
 891         RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
 892         *dev_priv->ring.head = cur_read_ptr;
 893         dev_priv->ring.tail = cur_read_ptr;
 894
 895         if ( !dev_priv->is_pci ) {
 896                 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
 897                               dev_priv->ring_rptr->offset );
 898         } else {
 899                 drm_sg_mem_t *entry = dev->sg;
 900                 unsigned long tmp_ofs, page_ofs;
 901
 902                 tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle;
 903                 page_ofs = tmp_ofs >> PAGE_SHIFT;
 904
 905                 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
 906                              entry->busaddr[page_ofs]);
 907                 DRM_DEBUG( "ring rptr: offset=0x%08x handle=0x%08lx\n",
 908                            entry->busaddr[page_ofs],
 909                            entry->handle + tmp_ofs );
 910         }
 911
 912         /* Initialize the scratch register pointer.  This will cause
 913          * the scratch register values to be written out to memory
 914          * whenever they are updated.
 915          *
 916          * We simply put this behind the ring read pointer, this works
 917          * with PCI GART as well as (whatever kind of) AGP GART
 918          */
 919         RADEON_WRITE( RADEON_SCRATCH_ADDR, RADEON_READ( RADEON_CP_RB_RPTR_ADDR )
 920                                          + RADEON_SCRATCH_REG_OFFSET );
 921
 922         dev_priv->scratch = ((__volatile__ u32 *)
 923                              dev_priv->ring.head +
 924                              (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
 925
 926         RADEON_WRITE( RADEON_SCRATCH_UMSK, 0x7 );
 927
 928         /* Writeback doesn't seem to work everywhere, test it first */
 929         DRM_WRITE32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0 );
 930         RADEON_WRITE( RADEON_SCRATCH_REG1, 0xdeadbeef );
 931
 932         for ( tmp = 0 ; tmp < dev_priv->usec_timeout ; tmp++ ) {
 933                 if ( DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1) ) == 0xdeadbeef )
 934                         break;
 935                 DRM_UDELAY( 1 );
 936         }
 937
 938         if ( tmp < dev_priv->usec_timeout ) {
 939                 dev_priv->writeback_works = 1;
 940                 DRM_DEBUG( "writeback test succeeded, tmp=%d\n", tmp );
 941         } else {
 942                 dev_priv->writeback_works = 0;
 943                 DRM_DEBUG( "writeback test failed\n" );
 944         }
 945
 946         dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
 947         RADEON_WRITE( RADEON_LAST_FRAME_REG,
 948                       dev_priv->sarea_priv->last_frame );
 949
 950         dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
 951         RADEON_WRITE( RADEON_LAST_DISPATCH_REG,
 952                       dev_priv->sarea_priv->last_dispatch );
 953
 954         dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
 955         RADEON_WRITE( RADEON_LAST_CLEAR_REG,
 956                       dev_priv->sarea_priv->last_clear );
 957
 958         /* Set ring buffer size */
 959 #ifdef __BIG_ENDIAN
 960         RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT );
 961 #else
 962         RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw );
 963 #endif
 964
 965         radeon_do_wait_for_idle( dev_priv );
 966
 967         /* Turn on bus mastering */
 968         tmp = RADEON_READ( RADEON_BUS_CNTL ) & ~RADEON_BUS_MASTER_DIS;
 969         RADEON_WRITE( RADEON_BUS_CNTL, tmp );
 970
 971         /* Sync everything up */
 972         RADEON_WRITE( RADEON_ISYNC_CNTL,
 973                       (RADEON_ISYNC_ANY2D_IDLE3D |
 974                        RADEON_ISYNC_ANY3D_IDLE2D |
 975                        RADEON_ISYNC_WAIT_IDLEGUI |
 976                        RADEON_ISYNC_CPSCRATCH_IDLEGUI) );
 977 }
 978
 979 static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
 980 {
 981         drm_radeon_private_t *dev_priv;
 982         u32 tmp;
 983         DRM_DEBUG( "\n" );
 984
 985         dev_priv = DRM(alloc)( sizeof(drm_radeon_private_t), DRM_MEM_DRIVER );
 986         if ( dev_priv == NULL )
 987                 return DRM_ERR(ENOMEM);
 988
 989         memset( dev_priv, 0, sizeof(drm_radeon_private_t) );
 990
 991         dev_priv->is_pci = init->is_pci;
 992
 993 #if !defined(PCIGART_ENABLED)
 994         /* PCI support is not 100% working, so we disable it here.
 995          */
 996         if ( dev_priv->is_pci ) {
 997                 DRM_ERROR( "PCI GART not yet supported for Radeon!\n" );
 998                 dev->dev_private = (void *)dev_priv;
 999                 radeon_do_cleanup_cp(dev);
1000                 return DRM_ERR(EINVAL);
1001         }
1002 #endif
1003
1004         if ( dev_priv->is_pci && !dev->sg ) {
1005                 DRM_ERROR( "PCI GART memory not allocated!\n" );
1006                 dev->dev_private = (void *)dev_priv;
1007                 radeon_do_cleanup_cp(dev);
1008                 return DRM_ERR(EINVAL);
1009         }
1010
1011         dev_priv->usec_timeout = init->usec_timeout;
1012         if ( dev_priv->usec_timeout < 1 ||
1013              dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT ) {
1014                 DRM_DEBUG( "TIMEOUT problem!\n" );
1015                 dev->dev_private = (void *)dev_priv;
1016                 radeon_do_cleanup_cp(dev);
1017                 return DRM_ERR(EINVAL);
1018         }
1019
1020         dev_priv->is_r200 = (init->func == RADEON_INIT_R200_CP);
1021         dev_priv->do_boxes = 0;
1022         dev_priv->cp_mode = init->cp_mode;
1023
1024         /* We don't support anything other than bus-mastering ring mode,
1025          * but the ring can be in either AGP or PCI space for the ring
1026          * read pointer.
1027          */
1028         if ( ( init->cp_mode != RADEON_CSQ_PRIBM_INDDIS ) &&
1029              ( init->cp_mode != RADEON_CSQ_PRIBM_INDBM ) ) {
1030                 DRM_DEBUG( "BAD cp_mode (%x)!\n", init->cp_mode );
1031                 dev->dev_private = (void *)dev_priv;
1032                 radeon_do_cleanup_cp(dev);
1033                 return DRM_ERR(EINVAL);
1034         }
1035
1036         switch ( init->fb_bpp ) {
1037         case 16:
1038                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1039                 break;
1040         case 32:
1041         default:
1042                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1043                 break;
1044         }
1045         dev_priv->front_offset  = init->front_offset;
1046         dev_priv->front_pitch   = init->front_pitch;
1047         dev_priv->back_offset   = init->back_offset;
1048         dev_priv->back_pitch    = init->back_pitch;
1049
1050         switch ( init->depth_bpp ) {
1051         case 16:
1052                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1053                 break;
1054         case 32:
1055         default:
1056                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1057                 break;
1058         }
1059         dev_priv->depth_offset  = init->depth_offset;
1060         dev_priv->depth_pitch   = init->depth_pitch;
1061
1062         dev_priv->front_pitch_offset = (((dev_priv->front_pitch/64) << 22) |
1063                                         (dev_priv->front_offset >> 10));
1064         dev_priv->back_pitch_offset = (((dev_priv->back_pitch/64) << 22) |
1065                                        (dev_priv->back_offset >> 10));
1066         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch/64) << 22) |
1067                                         (dev_priv->depth_offset >> 10));
1068
1069         /* Hardware state for depth clears.  Remove this if/when we no
1070          * longer clear the depth buffer with a 3D rectangle.  Hard-code
1071          * all values to prevent unwanted 3D state from slipping through
1072          * and screwing with the clear operation.
1073          */
1074         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1075                                            (dev_priv->color_fmt << 10) |
1076                                            (1<<15));
1077
1078         dev_priv->depth_clear.rb3d_zstencilcntl =
1079                 (dev_priv->depth_fmt |
1080                  RADEON_Z_TEST_ALWAYS |
1081                  RADEON_STENCIL_TEST_ALWAYS |
1082                  RADEON_STENCIL_S_FAIL_REPLACE |
1083                  RADEON_STENCIL_ZPASS_REPLACE |
1084                  RADEON_STENCIL_ZFAIL_REPLACE |
1085                  RADEON_Z_WRITE_ENABLE);
1086
1087         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1088                                          RADEON_BFACE_SOLID |
1089                                          RADEON_FFACE_SOLID |
1090                                          RADEON_FLAT_SHADE_VTX_LAST |
1091                                          RADEON_DIFFUSE_SHADE_FLAT |
1092                                          RADEON_ALPHA_SHADE_FLAT |
1093                                          RADEON_SPECULAR_SHADE_FLAT |
1094                                          RADEON_FOG_SHADE_FLAT |
1095                                          RADEON_VTX_PIX_CENTER_OGL |
1096                                          RADEON_ROUND_MODE_TRUNC |
1097                                          RADEON_ROUND_PREC_8TH_PIX);
1098
1099         DRM_GETSAREA();
1100
1101         dev_priv->fb_offset = init->fb_offset;
1102         dev_priv->mmio_offset = init->mmio_offset;
1103         dev_priv->ring_offset = init->ring_offset;
1104         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1105         dev_priv->buffers_offset = init->buffers_offset;
1106         dev_priv->agp_textures_offset = init->agp_textures_offset;
1107
1108         if(!dev_priv->sarea) {
1109                 DRM_ERROR("could not find sarea!\n");
1110                 dev->dev_private = (void *)dev_priv;
1111                 radeon_do_cleanup_cp(dev);
1112                 return DRM_ERR(EINVAL);
1113         }
1114
1115         DRM_FIND_MAP( dev_priv->fb, init->fb_offset );
1116         if(!dev_priv->fb) {
1117                 DRM_ERROR("could not find framebuffer!\n");
1118                 dev->dev_private = (void *)dev_priv;
1119                 radeon_do_cleanup_cp(dev);
1120                 return DRM_ERR(EINVAL);
1121         }
1122         DRM_FIND_MAP( dev_priv->mmio, init->mmio_offset );
1123         if(!dev_priv->mmio) {
1124                 DRM_ERROR("could not find mmio region!\n");
1125                 dev->dev_private = (void *)dev_priv;
1126                 radeon_do_cleanup_cp(dev);
1127                 return DRM_ERR(EINVAL);
1128         }
1129         DRM_FIND_MAP( dev_priv->cp_ring, init->ring_offset );
1130         if(!dev_priv->cp_ring) {
1131                 DRM_ERROR("could not find cp ring region!\n");
1132                 dev->dev_private = (void *)dev_priv;
1133                 radeon_do_cleanup_cp(dev);
1134                 return DRM_ERR(EINVAL);
1135         }
1136         DRM_FIND_MAP( dev_priv->ring_rptr, init->ring_rptr_offset );
1137         if(!dev_priv->ring_rptr) {
1138                 DRM_ERROR("could not find ring read pointer!\n");
1139                 dev->dev_private = (void *)dev_priv;
1140                 radeon_do_cleanup_cp(dev);
1141                 return DRM_ERR(EINVAL);
1142         }
1143         DRM_FIND_MAP( dev_priv->buffers, init->buffers_offset );
1144         if(!dev_priv->buffers) {
1145                 DRM_ERROR("could not find dma buffer region!\n");
1146                 dev->dev_private = (void *)dev_priv;
1147                 radeon_do_cleanup_cp(dev);
1148                 return DRM_ERR(EINVAL);
1149         }
1150
1151         if ( !dev_priv->is_pci ) {
1152                 DRM_FIND_MAP( dev_priv->agp_textures,
1153                               init->agp_textures_offset );
1154                 if(!dev_priv->agp_textures) {
1155                         DRM_ERROR("could not find agp texture region!\n");
1156                         dev->dev_private = (void *)dev_priv;
1157                         radeon_do_cleanup_cp(dev);
1158                         return DRM_ERR(EINVAL);
1159                 }
1160         }
1161
1162         dev_priv->sarea_priv =
1163                 (drm_radeon_sarea_t *)((u8 *)dev_priv->sarea->handle +
1164                                        init->sarea_priv_offset);
1165
1166         if ( !dev_priv->is_pci ) {
1167                 DRM_IOREMAP( dev_priv->cp_ring );
1168                 DRM_IOREMAP( dev_priv->ring_rptr );
1169                 DRM_IOREMAP( dev_priv->buffers );
1170                 if(!dev_priv->cp_ring->handle ||
1171                    !dev_priv->ring_rptr->handle ||
1172                    !dev_priv->buffers->handle) {
1173                         DRM_ERROR("could not find ioremap agp regions!\n");
1174                         dev->dev_private = (void *)dev_priv;
1175                         radeon_do_cleanup_cp(dev);
1176                         return DRM_ERR(EINVAL);
1177                 }
1178         } else {
1179                 dev_priv->cp_ring->handle =
1180                         (void *)dev_priv->cp_ring->offset;
1181                 dev_priv->ring_rptr->handle =
1182                         (void *)dev_priv->ring_rptr->offset;
1183                 dev_priv->buffers->handle = (void *)dev_priv->buffers->offset;
1184
1185                 DRM_DEBUG( "dev_priv->cp_ring->handle %p\n",
1186                            dev_priv->cp_ring->handle );
1187                 DRM_DEBUG( "dev_priv->ring_rptr->handle %p\n",
1188                            dev_priv->ring_rptr->handle );
1189                 DRM_DEBUG( "dev_priv->buffers->handle %p\n",
1190                            dev_priv->buffers->handle );
1191         }
1192
1193
1194         dev_priv->agp_size = init->agp_size;
1195         dev_priv->agp_vm_start = RADEON_READ( RADEON_CONFIG_APER_SIZE );
1196 #if __REALLY_HAVE_AGP
1197         if ( !dev_priv->is_pci )
1198                 dev_priv->agp_buffers_offset = (dev_priv->buffers->offset
1199                                                 - dev->agp->base
1200                                                 + dev_priv->agp_vm_start);
1201         else
1202 #endif
1203                 dev_priv->agp_buffers_offset = (dev_priv->buffers->offset
1204                                                 - dev->sg->handle
1205                                                 + dev_priv->agp_vm_start);
1206
1207         DRM_DEBUG( "dev_priv->agp_size %d\n",
1208                    dev_priv->agp_size );
1209         DRM_DEBUG( "dev_priv->agp_vm_start 0x%x\n",
1210                    dev_priv->agp_vm_start );
1211         DRM_DEBUG( "dev_priv->agp_buffers_offset 0x%lx\n",
1212                    dev_priv->agp_buffers_offset );
1213
1214         dev_priv->ring.head = ((__volatile__ u32 *)
1215                                dev_priv->ring_rptr->handle);
1216
1217         dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle;
1218         dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle
1219                               + init->ring_size / sizeof(u32));
1220         dev_priv->ring.size = init->ring_size;
1221         dev_priv->ring.size_l2qw = DRM(order)( init->ring_size / 8 );
1222
1223         dev_priv->ring.tail_mask =
1224                 (dev_priv->ring.size / sizeof(u32)) - 1;
1225
1226         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1227         dev_priv->ring.ring_rptr = dev_priv->ring_rptr;
1228
1229 #if __REALLY_HAVE_SG
1230         if ( dev_priv->is_pci ) {
1231                 if (!DRM(ati_pcigart_init)( dev, &dev_priv->phys_pci_gart,
1232                                             &dev_priv->bus_pci_gart)) {
1233                         DRM_ERROR( "failed to init PCI GART!\n" );
1234                         dev->dev_private = (void *)dev_priv;
1235                         radeon_do_cleanup_cp(dev);
1236                         return DRM_ERR(ENOMEM);
1237                 }
1238                 /* Turn on PCI GART
1239                  */
1240                 tmp = RADEON_READ( RADEON_AIC_CNTL )
1241                       | RADEON_PCIGART_TRANSLATE_EN;
1242                 RADEON_WRITE( RADEON_AIC_CNTL, tmp );
1243
1244                 /* set PCI GART page-table base address
1245                  */
1246                 RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart );
1247
1248                 /* set address range for PCI address translate
1249                  */
1250                 RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->agp_vm_start );
1251                 RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->agp_vm_start
1252                                                   + dev_priv->agp_size - 1);
1253
1254                 /* Turn off AGP aperture -- is this required for PCIGART?
1255                  */
1256                 RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
1257                 RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
1258         } else {
1259 #endif /* __REALLY_HAVE_SG */
1260                 /* Turn off PCI GART
1261                  */
1262                 tmp = RADEON_READ( RADEON_AIC_CNTL )
1263                       & ~RADEON_PCIGART_TRANSLATE_EN;
1264                 RADEON_WRITE( RADEON_AIC_CNTL, tmp );
1265 #if __REALLY_HAVE_SG
1266         }
1267 #endif /* __REALLY_HAVE_SG */
1268
1269         radeon_cp_load_microcode( dev_priv );
1270         radeon_cp_init_ring_buffer( dev, dev_priv );
1271
1272         dev_priv->last_buf = 0;
1273
1274         dev->dev_private = (void *)dev_priv;
1275
1276         radeon_do_engine_reset( dev );
1277
1278         return 0;
1279 }
1280
1281 int radeon_do_cleanup_cp( drm_device_t *dev )
1282 {
1283         DRM_DEBUG( "\n" );
1284
1285         if ( dev->dev_private ) {
1286                 drm_radeon_private_t *dev_priv = dev->dev_private;
1287
1288                 if ( !dev_priv->is_pci ) {
1289                         if ( dev_priv->cp_ring != NULL )
1290                                 DRM_IOREMAPFREE( dev_priv->cp_ring );
1291                         if ( dev_priv->ring_rptr != NULL )
1292                                 DRM_IOREMAPFREE( dev_priv->ring_rptr );
1293                         if ( dev_priv->buffers != NULL )
1294                                 DRM_IOREMAPFREE( dev_priv->buffers );
1295                 } else {
1296 #if __REALLY_HAVE_SG
1297                         if (!DRM(ati_pcigart_cleanup)( dev,
1298                                                 dev_priv->phys_pci_gart,
1299                                                 dev_priv->bus_pci_gart ))
1300                                 DRM_ERROR( "failed to cleanup PCI GART!\n" );
1301 #endif /* __REALLY_HAVE_SG */
1302                 }
1303
1304                 DRM(free)( dev->dev_private, sizeof(drm_radeon_private_t),
1305                            DRM_MEM_DRIVER );
1306                 dev->dev_private = NULL;
1307         }
1308
1309         return 0;
1310 }
1311
1312 int radeon_cp_init( DRM_IOCTL_ARGS )
1313 {
1314         DRM_DEVICE;
1315         drm_radeon_init_t init;
1316
1317         DRM_COPY_FROM_USER_IOCTL( init, (drm_radeon_init_t *)data, sizeof(init) );
1318
1319         switch ( init.func ) {
1320         case RADEON_INIT_CP:
1321         case RADEON_INIT_R200_CP:
1322                 return radeon_do_init_cp( dev, &init );
1323         case RADEON_CLEANUP_CP:
1324                 return radeon_do_cleanup_cp( dev );
1325         }
1326
1327         return DRM_ERR(EINVAL);
1328 }
1329
1330 int radeon_cp_start( DRM_IOCTL_ARGS )
1331 {
1332         DRM_DEVICE;
1333         drm_radeon_private_t *dev_priv = dev->dev_private;
1334         DRM_DEBUG( "\n" );
1335
1336         LOCK_TEST_WITH_RETURN( dev, filp );
1337
1338         if ( dev_priv->cp_running ) {
1339                 DRM_DEBUG( "%s while CP running\n", __FUNCTION__ );
1340                 return 0;
1341         }
1342         if ( dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS ) {
1343                 DRM_DEBUG( "%s called with bogus CP mode (%d)\n",
1344                            __FUNCTION__, dev_priv->cp_mode );
1345                 return 0;
1346         }
1347
1348         radeon_do_cp_start( dev_priv );
1349
1350         return 0;
1351 }
1352
1353 /* Stop the CP.  The engine must have been idled before calling this
1354  * routine.
1355  */
1356 int radeon_cp_stop( DRM_IOCTL_ARGS )
1357 {
1358         DRM_DEVICE;
1359         drm_radeon_private_t *dev_priv = dev->dev_private;
1360         drm_radeon_cp_stop_t stop;
1361         int ret;
1362         DRM_DEBUG( "\n" );
1363
1364         LOCK_TEST_WITH_RETURN( dev, filp );
1365
1366         DRM_COPY_FROM_USER_IOCTL( stop, (drm_radeon_cp_stop_t *)data, sizeof(stop) );
1367
1368         if (!dev_priv->cp_running)
1369                 return 0;
1370
1371         /* Flush any pending CP commands.  This ensures any outstanding
1372          * commands are exectuted by the engine before we turn it off.
1373          */
1374         if ( stop.flush ) {
1375                 radeon_do_cp_flush( dev_priv );
1376         }
1377
1378         /* If we fail to make the engine go idle, we return an error
1379          * code so that the DRM ioctl wrapper can try again.
1380          */
1381         if ( stop.idle ) {
1382                 ret = radeon_do_cp_idle( dev_priv );
1383                 if ( ret ) return ret;
1384         }
1385
1386         /* Finally, we can turn off the CP.  If the engine isn't idle,
1387          * we will get some dropped triangles as they won't be fully
1388          * rendered before the CP is shut down.
1389          */
1390         radeon_do_cp_stop( dev_priv );
1391
1392         /* Reset the engine */
1393         radeon_do_engine_reset( dev );
1394
1395         return 0;
1396 }
1397
1398
1399 void radeon_do_release( drm_device_t *dev )
1400 {
1401         drm_radeon_private_t *dev_priv = dev->dev_private;
1402         int ret;
1403
1404         if (dev_priv) {
1405                 if (dev_priv->cp_running) {
1406                         /* Stop the cp */
1407                         while ((ret = radeon_do_cp_idle( dev_priv )) != 0) {
1408                                 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1409 #ifdef __linux__
1410                                 schedule();
1411 #else
1412                                 tsleep(&ret, PZERO, "rdnrel", 1);
1413 #endif
1414                         }
1415                         radeon_do_cp_stop( dev_priv );
1416                         radeon_do_engine_reset( dev );
1417                 }
1418
1419                 /* Disable *all* interrupts */
1420                 RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );
1421
1422                 /* Free memory heap structures */
1423                 radeon_mem_takedown( &(dev_priv->agp_heap) );
1424                 radeon_mem_takedown( &(dev_priv->fb_heap) );
1425
1426                 /* deallocate kernel resources */
1427                 radeon_do_cleanup_cp( dev );
1428         }
1429 }
1430
1431 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1432  */
1433 int radeon_cp_reset( DRM_IOCTL_ARGS )
1434 {
1435         DRM_DEVICE;
1436         drm_radeon_private_t *dev_priv = dev->dev_private;
1437         DRM_DEBUG( "\n" );
1438
1439         LOCK_TEST_WITH_RETURN( dev, filp );
1440
1441         if ( !dev_priv ) {
1442                 DRM_DEBUG( "%s called before init done\n", __FUNCTION__ );
1443                 return DRM_ERR(EINVAL);
1444         }
1445
1446         radeon_do_cp_reset( dev_priv );
1447
1448         /* The CP is no longer running after an engine reset */
1449         dev_priv->cp_running = 0;
1450
1451         return 0;
1452 }
1453
1454 int radeon_cp_idle( DRM_IOCTL_ARGS )
1455 {
1456         DRM_DEVICE;
1457         drm_radeon_private_t *dev_priv = dev->dev_private;
1458         DRM_DEBUG( "\n" );
1459
1460         LOCK_TEST_WITH_RETURN( dev, filp );
1461
1462         return radeon_do_cp_idle( dev_priv );
1463 }
1464
1465 int radeon_engine_reset( DRM_IOCTL_ARGS )
1466 {
1467         DRM_DEVICE;
1468         DRM_DEBUG( "\n" );
1469
1470         LOCK_TEST_WITH_RETURN( dev, filp );
1471
1472         return radeon_do_engine_reset( dev );
1473 }
1474
1475
1476 /* ================================================================
1477  * Fullscreen mode
1478  */
1479
1480 /* KW: Deprecated to say the least:
1481  */
1482 int radeon_fullscreen( DRM_IOCTL_ARGS )
1483 {
1484         return 0;
1485 }
1486
1487
1488 /* ================================================================
1489  * Freelist management
1490  */
1491
1492 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1493  *   bufs until freelist code is used.  Note this hides a problem with
1494  *   the scratch register * (used to keep track of last buffer
1495  *   completed) being written to before * the last buffer has actually
1496  *   completed rendering.
1497  *
1498  * KW:  It's also a good way to find free buffers quickly.
1499  *
1500  * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1501  * sleep.  However, bugs in older versions of radeon_accel.c mean that
1502  * we essentially have to do this, else old clients will break.
1503  *
1504  * However, it does leave open a potential deadlock where all the
1505  * buffers are held by other clients, which can't release them because
1506  * they can't get the lock.
1507  */
1508
1509 drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1510 {
1511         drm_device_dma_t *dma = dev->dma;
1512         drm_radeon_private_t *dev_priv = dev->dev_private;
1513         drm_radeon_buf_priv_t *buf_priv;
1514         drm_buf_t *buf;
1515         int i, t;
1516         int start;
1517
1518         if ( ++dev_priv->last_buf >= dma->buf_count )
1519                 dev_priv->last_buf = 0;
1520
1521         start = dev_priv->last_buf;
1522
1523         for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) {
1524                 u32 done_age = GET_SCRATCH( 1 );
1525                 DRM_DEBUG("done_age = %d\n",done_age);
1526                 for ( i = start ; i < dma->buf_count ; i++ ) {
1527                         buf = dma->buflist[i];
1528                         buf_priv = buf->dev_private;
1529                         if ( buf->filp == 0 || (buf->pending &&
1530                                                buf_priv->age <= done_age) ) {
1531                                 dev_priv->stats.requested_bufs++;
1532                                 buf->pending = 0;
1533                                 return buf;
1534                         }
1535                         start = 0;
1536                 }
1537
1538                 if (t) {
1539                         DRM_UDELAY( 1 );
1540                         dev_priv->stats.freelist_loops++;
1541                 }
1542         }
1543
1544         DRM_DEBUG( "returning NULL!\n" );
1545         return NULL;
1546 }
1547 #if 0
1548 drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1549 {
1550         drm_device_dma_t *dma = dev->dma;
1551         drm_radeon_private_t *dev_priv = dev->dev_private;
1552         drm_radeon_buf_priv_t *buf_priv;
1553         drm_buf_t *buf;
1554         int i, t;
1555         int start;
1556         u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1557
1558         if ( ++dev_priv->last_buf >= dma->buf_count )
1559                 dev_priv->last_buf = 0;
1560
1561         start = dev_priv->last_buf;
1562         dev_priv->stats.freelist_loops++;
1563
1564         for ( t = 0 ; t < 2 ; t++ ) {
1565                 for ( i = start ; i < dma->buf_count ; i++ ) {
1566                         buf = dma->buflist[i];
1567                         buf_priv = buf->dev_private;
1568                         if ( buf->filp == 0 || (buf->pending &&
1569                                                buf_priv->age <= done_age) ) {
1570                                 dev_priv->stats.requested_bufs++;
1571                                 buf->pending = 0;
1572                                 return buf;
1573                         }
1574                 }
1575                 start = 0;
1576         }
1577
1578         return NULL;
1579 }
1580 #endif
1581
1582 void radeon_freelist_reset( drm_device_t *dev )
1583 {
1584         drm_device_dma_t *dma = dev->dma;
1585         drm_radeon_private_t *dev_priv = dev->dev_private;
1586         int i;
1587
1588         dev_priv->last_buf = 0;
1589         for ( i = 0 ; i < dma->buf_count ; i++ ) {
1590                 drm_buf_t *buf = dma->buflist[i];
1591                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1592                 buf_priv->age = 0;
1593         }
1594 }
1595
1596
1597 /* ================================================================
1598  * CP command submission
1599  */
1600
1601 int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n )
1602 {
1603         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1604         int i;
1605         u32 last_head = GET_RING_HEAD(ring);
1606
1607         for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
1608                 u32 head = GET_RING_HEAD(ring);
1609
1610                 ring->space = (head - ring->tail) * sizeof(u32);
1611                 if ( ring->space <= 0 )
1612                         ring->space += ring->size;
1613                 if ( ring->space > n )
1614                         return 0;
1615
1616                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1617
1618                 if (head != last_head)
1619                         i = 0;
1620                 last_head = head;
1621
1622                 DRM_UDELAY( 1 );
1623         }
1624
1625         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1626 #if RADEON_FIFO_DEBUG
1627         radeon_status( dev_priv );
1628         DRM_ERROR( "failed!\n" );
1629 #endif
1630         return DRM_ERR(EBUSY);
1631 }
1632
1633 static int radeon_cp_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d )
1634 {
1635         int i;
1636         drm_buf_t *buf;
1637
1638         for ( i = d->granted_count ; i < d->request_count ; i++ ) {
1639                 buf = radeon_freelist_get( dev );
1640                 if ( !buf ) return DRM_ERR(EBUSY); /* NOTE: broken client */
1641
1642                 buf->filp = filp;
1643
1644                 if ( DRM_COPY_TO_USER( &d->request_indices[i], &buf->idx,
1645                                    sizeof(buf->idx) ) )
1646                         return DRM_ERR(EFAULT);
1647                 if ( DRM_COPY_TO_USER( &d->request_sizes[i], &buf->total,
1648                                    sizeof(buf->total) ) )
1649                         return DRM_ERR(EFAULT);
1650
1651                 d->granted_count++;
1652         }
1653         return 0;
1654 }
1655
1656 int radeon_cp_buffers( DRM_IOCTL_ARGS )
1657 {
1658         DRM_DEVICE;
1659         drm_device_dma_t *dma = dev->dma;
1660         int ret = 0;
1661         drm_dma_t d;
1662
1663         LOCK_TEST_WITH_RETURN( dev, filp );
1664
1665         DRM_COPY_FROM_USER_IOCTL( d, (drm_dma_t *)data, sizeof(d) );
1666
1667         /* Please don't send us buffers.
1668          */
1669         if ( d.send_count != 0 ) {
1670                 DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n",
1671                            DRM_CURRENTPID, d.send_count );
1672                 return DRM_ERR(EINVAL);
1673         }
1674
1675         /* We'll send you buffers.
1676          */
1677         if ( d.request_count < 0 || d.request_count > dma->buf_count ) {
1678                 DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n",
1679                            DRM_CURRENTPID, d.request_count, dma->buf_count );
1680                 return DRM_ERR(EINVAL);
1681         }
1682
1683         d.granted_count = 0;
1684
1685         if ( d.request_count ) {
1686                 ret = radeon_cp_get_buffers( filp, dev, &d );
1687         }
1688
1689         DRM_COPY_TO_USER_IOCTL( (drm_dma_t *)data, d, sizeof(d) );
1690
1691         return ret;
1692 }