1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2007 Advanced Micro Devices, Inc.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 * Kevin E. Martin <martin@valinux.com>
29 * Gareth Hughes <gareth@valinux.com>
34 #include "radeon_drm.h"
35 #include "radeon_drv.h"
38 #include "radeon_microcode.h"
39 #define RADEON_FIFO_DEBUG 0
41 static int radeon_do_cleanup_cp(struct drm_device * dev);
42 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
44 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
47 RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
48 ret = RADEON_READ(R520_MC_IND_DATA);
49 RADEON_WRITE(R520_MC_IND_INDEX, 0);
53 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
56 RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
57 ret = RADEON_READ(RS480_NB_MC_DATA);
58 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
62 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
65 RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
66 ret = RADEON_READ(RS690_MC_DATA);
67 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
71 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
73 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
74 return RS690_READ_MCIND(dev_priv, addr);
76 return RS480_READ_MCIND(dev_priv, addr);
79 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
82 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
83 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
84 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
85 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
86 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
87 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
89 return RADEON_READ(RADEON_MC_FB_LOCATION);
92 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
94 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
95 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
96 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
97 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
98 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
99 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
101 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
104 static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
106 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
107 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
108 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
109 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
110 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
111 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
113 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
116 static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
118 u32 agp_base_hi = upper_32_bits(agp_base);
119 u32 agp_base_lo = agp_base & 0xffffffff;
121 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
122 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
123 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
124 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
125 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
126 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
127 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
128 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
129 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
130 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
131 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
132 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
133 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
135 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
136 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
137 RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
141 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
143 drm_radeon_private_t *dev_priv = dev->dev_private;
145 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
146 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
149 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
151 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
152 return RADEON_READ(RADEON_PCIE_DATA);
155 #if RADEON_FIFO_DEBUG
156 static void radeon_status(drm_radeon_private_t * dev_priv)
158 printk("%s:\n", __FUNCTION__);
159 printk("RBBM_STATUS = 0x%08x\n",
160 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
161 printk("CP_RB_RTPR = 0x%08x\n",
162 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
163 printk("CP_RB_WTPR = 0x%08x\n",
164 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
165 printk("AIC_CNTL = 0x%08x\n",
166 (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
167 printk("AIC_STAT = 0x%08x\n",
168 (unsigned int)RADEON_READ(RADEON_AIC_STAT));
169 printk("AIC_PT_BASE = 0x%08x\n",
170 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
171 printk("TLB_ADDR = 0x%08x\n",
172 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
173 printk("TLB_DATA = 0x%08x\n",
174 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
178 /* ================================================================
179 * Engine, FIFO control
182 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
187 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
189 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
190 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
191 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
192 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
194 for (i = 0; i < dev_priv->usec_timeout; i++) {
195 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
196 & RADEON_RB3D_DC_BUSY)) {
202 /* don't flush or purge cache here or lockup */
206 #if RADEON_FIFO_DEBUG
207 DRM_ERROR("failed!\n");
208 radeon_status(dev_priv);
213 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
217 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
219 for (i = 0; i < dev_priv->usec_timeout; i++) {
220 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
221 & RADEON_RBBM_FIFOCNT_MASK);
222 if (slots >= entries)
226 DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n",
227 RADEON_READ(RADEON_RBBM_STATUS),
228 RADEON_READ(R300_VAP_CNTL_STATUS));
230 #if RADEON_FIFO_DEBUG
231 DRM_ERROR("failed!\n");
232 radeon_status(dev_priv);
237 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
241 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
243 ret = radeon_do_wait_for_fifo(dev_priv, 64);
247 for (i = 0; i < dev_priv->usec_timeout; i++) {
248 if (!(RADEON_READ(RADEON_RBBM_STATUS)
249 & RADEON_RBBM_ACTIVE)) {
250 radeon_do_pixcache_flush(dev_priv);
255 DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n",
256 RADEON_READ(RADEON_RBBM_STATUS),
257 RADEON_READ(R300_VAP_CNTL_STATUS));
259 #if RADEON_FIFO_DEBUG
260 DRM_ERROR("failed!\n");
261 radeon_status(dev_priv);
266 static void radeon_init_pipes(drm_radeon_private_t * dev_priv)
268 uint32_t gb_tile_config, gb_pipe_sel = 0;
270 /* RS4xx/RS6xx/R4xx/R5xx */
271 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
272 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
273 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
276 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
277 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
278 dev_priv->num_gb_pipes = 2;
281 dev_priv->num_gb_pipes = 1;
284 DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
286 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
288 switch(dev_priv->num_gb_pipes) {
289 case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
290 case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
291 case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
293 case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
296 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
297 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
298 RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
300 RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
301 radeon_do_wait_for_idle(dev_priv);
302 RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
303 RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
304 R300_DC_AUTOFLUSH_ENABLE |
305 R300_DC_DC_DISABLE_IGNORE_PE));
310 /* ================================================================
311 * CP control, initialization
314 /* Load the microcode for the CP */
315 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
320 radeon_do_wait_for_idle(dev_priv);
322 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
324 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
325 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
326 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
327 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
328 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
329 DRM_INFO("Loading R100 Microcode\n");
330 for (i = 0; i < 256; i++) {
331 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
332 R100_cp_microcode[i][1]);
333 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
334 R100_cp_microcode[i][0]);
336 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
337 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
338 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
339 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
340 DRM_INFO("Loading R200 Microcode\n");
341 for (i = 0; i < 256; i++) {
342 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
343 R200_cp_microcode[i][1]);
344 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
345 R200_cp_microcode[i][0]);
347 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
348 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
349 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
350 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
351 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
352 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
353 DRM_INFO("Loading R300 Microcode\n");
354 for (i = 0; i < 256; i++) {
355 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
356 R300_cp_microcode[i][1]);
357 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
358 R300_cp_microcode[i][0]);
360 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
361 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
362 DRM_INFO("Loading R400 Microcode\n");
363 for (i = 0; i < 256; i++) {
364 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
365 R420_cp_microcode[i][1]);
366 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
367 R420_cp_microcode[i][0]);
369 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
370 DRM_INFO("Loading RS690 Microcode\n");
371 for (i = 0; i < 256; i++) {
372 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
373 RS690_cp_microcode[i][1]);
374 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
375 RS690_cp_microcode[i][0]);
377 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
378 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
379 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
380 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
381 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
382 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
383 DRM_INFO("Loading R500 Microcode\n");
384 for (i = 0; i < 256; i++) {
385 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
386 R520_cp_microcode[i][1]);
387 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
388 R520_cp_microcode[i][0]);
393 /* Flush any pending commands to the CP. This should only be used just
394 * prior to a wait for idle, as it informs the engine that the command
397 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
403 tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
404 RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
408 /* Wait for the CP to go idle.
410 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
417 RADEON_PURGE_CACHE();
418 RADEON_PURGE_ZCACHE();
419 RADEON_WAIT_UNTIL_IDLE();
424 return radeon_do_wait_for_idle(dev_priv);
427 /* Start the Command Processor.
429 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
434 radeon_do_wait_for_idle(dev_priv);
436 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
438 dev_priv->cp_running = 1;
441 /* isync can only be written through cp on r5xx write it here */
442 OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
443 OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
444 RADEON_ISYNC_ANY3D_IDLE2D |
445 RADEON_ISYNC_CPSCRATCH_IDLEGUI |
446 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
447 RADEON_PURGE_CACHE();
448 RADEON_PURGE_ZCACHE();
449 RADEON_WAIT_UNTIL_IDLE();
453 dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
456 /* Reset the Command Processor. This will not flush any pending
457 * commands, so you must wait for the CP command stream to complete
458 * before calling this routine.
460 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
465 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
466 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
467 SET_RING_HEAD(dev_priv, cur_read_ptr);
468 dev_priv->ring.tail = cur_read_ptr;
471 /* Stop the Command Processor. This will not flush any pending
472 * commands, so you must flush the command stream and wait for the CP
473 * to go idle before calling this routine.
475 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
479 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
481 dev_priv->cp_running = 0;
484 /* Reset the engine. This will stop the CP if it is running.
486 static int radeon_do_engine_reset(struct drm_device * dev)
488 drm_radeon_private_t *dev_priv = dev->dev_private;
489 u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
492 radeon_do_pixcache_flush(dev_priv);
494 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
495 /* may need something similar for newer chips */
496 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
497 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
499 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
500 RADEON_FORCEON_MCLKA |
501 RADEON_FORCEON_MCLKB |
502 RADEON_FORCEON_YCLKA |
503 RADEON_FORCEON_YCLKB |
505 RADEON_FORCEON_AIC));
508 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
510 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
511 RADEON_SOFT_RESET_CP |
512 RADEON_SOFT_RESET_HI |
513 RADEON_SOFT_RESET_SE |
514 RADEON_SOFT_RESET_RE |
515 RADEON_SOFT_RESET_PP |
516 RADEON_SOFT_RESET_E2 |
517 RADEON_SOFT_RESET_RB));
518 RADEON_READ(RADEON_RBBM_SOFT_RESET);
519 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
520 ~(RADEON_SOFT_RESET_CP |
521 RADEON_SOFT_RESET_HI |
522 RADEON_SOFT_RESET_SE |
523 RADEON_SOFT_RESET_RE |
524 RADEON_SOFT_RESET_PP |
525 RADEON_SOFT_RESET_E2 |
526 RADEON_SOFT_RESET_RB)));
527 RADEON_READ(RADEON_RBBM_SOFT_RESET);
529 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
530 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
531 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
532 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
535 /* setup the raster pipes */
536 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
537 radeon_init_pipes(dev_priv);
539 /* Reset the CP ring */
540 radeon_do_cp_reset(dev_priv);
542 /* The CP is no longer running after an engine reset */
543 dev_priv->cp_running = 0;
545 /* Reset any pending vertex, indirect buffers */
546 radeon_freelist_reset(dev);
551 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
552 drm_radeon_private_t * dev_priv)
554 u32 ring_start, cur_read_ptr;
557 /* Initialize the memory controller. With new memory map, the fb location
558 * is not changed, it should have been properly initialized already. Part
559 * of the problem is that the code below is bogus, assuming the GART is
560 * always appended to the fb which is not necessarily the case
562 if (!dev_priv->new_memmap)
563 radeon_write_fb_location(dev_priv,
564 ((dev_priv->gart_vm_start - 1) & 0xffff0000)
565 | (dev_priv->fb_location >> 16));
568 if (dev_priv->flags & RADEON_IS_AGP) {
569 radeon_write_agp_base(dev_priv, dev->agp->base);
571 radeon_write_agp_location(dev_priv,
572 (((dev_priv->gart_vm_start - 1 +
573 dev_priv->gart_size) & 0xffff0000) |
574 (dev_priv->gart_vm_start >> 16)));
576 ring_start = (dev_priv->cp_ring->offset
578 + dev_priv->gart_vm_start);
581 ring_start = (dev_priv->cp_ring->offset
582 - (unsigned long)dev->sg->virtual
583 + dev_priv->gart_vm_start);
585 RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
587 /* Set the write pointer delay */
588 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
590 /* Initialize the ring buffer's read and write pointers */
591 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
592 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
593 SET_RING_HEAD(dev_priv, cur_read_ptr);
594 dev_priv->ring.tail = cur_read_ptr;
597 if (dev_priv->flags & RADEON_IS_AGP) {
598 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
599 dev_priv->ring_rptr->offset
600 - dev->agp->base + dev_priv->gart_vm_start);
604 struct drm_sg_mem *entry = dev->sg;
605 unsigned long tmp_ofs, page_ofs;
607 tmp_ofs = dev_priv->ring_rptr->offset -
608 (unsigned long)dev->sg->virtual;
609 page_ofs = tmp_ofs >> PAGE_SHIFT;
611 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
612 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
613 (unsigned long)entry->busaddr[page_ofs],
614 entry->handle + tmp_ofs);
617 /* Set ring buffer size */
619 RADEON_WRITE(RADEON_CP_RB_CNTL,
620 RADEON_BUF_SWAP_32BIT |
621 (dev_priv->ring.fetch_size_l2ow << 18) |
622 (dev_priv->ring.rptr_update_l2qw << 8) |
623 dev_priv->ring.size_l2qw);
625 RADEON_WRITE(RADEON_CP_RB_CNTL,
626 (dev_priv->ring.fetch_size_l2ow << 18) |
627 (dev_priv->ring.rptr_update_l2qw << 8) |
628 dev_priv->ring.size_l2qw);
631 /* Start with assuming that writeback doesn't work */
632 dev_priv->writeback_works = 0;
634 /* Initialize the scratch register pointer. This will cause
635 * the scratch register values to be written out to memory
636 * whenever they are updated.
638 * We simply put this behind the ring read pointer, this works
639 * with PCI GART as well as (whatever kind of) AGP GART
641 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
642 + RADEON_SCRATCH_REG_OFFSET);
644 dev_priv->scratch = ((__volatile__ u32 *)
645 dev_priv->ring_rptr->handle +
646 (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
648 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
650 /* Turn on bus mastering */
651 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
652 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
654 dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
655 RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
657 dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
658 RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
659 dev_priv->sarea_priv->last_dispatch);
661 dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
662 RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
664 radeon_do_wait_for_idle(dev_priv);
666 /* Sync everything up */
667 RADEON_WRITE(RADEON_ISYNC_CNTL,
668 (RADEON_ISYNC_ANY2D_IDLE3D |
669 RADEON_ISYNC_ANY3D_IDLE2D |
670 RADEON_ISYNC_WAIT_IDLEGUI |
671 RADEON_ISYNC_CPSCRATCH_IDLEGUI));
675 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
679 /* Writeback doesn't seem to work everywhere, test it here and possibly
680 * enable it if it appears to work
682 DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
683 RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
685 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
686 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
692 if (tmp < dev_priv->usec_timeout) {
693 dev_priv->writeback_works = 1;
694 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
696 dev_priv->writeback_works = 0;
697 DRM_INFO("writeback test failed\n");
699 if (radeon_no_wb == 1) {
700 dev_priv->writeback_works = 0;
701 DRM_INFO("writeback forced off\n");
704 if (!dev_priv->writeback_works) {
705 /* Disable writeback to avoid unnecessary bus master transfers */
706 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) | RADEON_RB_NO_UPDATE);
707 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
711 /* Enable or disable IGP GART on the chip */
712 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
717 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
718 dev_priv->gart_vm_start,
719 (long)dev_priv->gart_info.bus_addr,
720 dev_priv->gart_size);
722 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
724 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
725 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
726 RS690_BLOCK_GFX_D3_EN));
728 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
730 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
731 RS480_VA_SIZE_32MB));
733 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
734 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
739 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
740 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
741 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
743 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
744 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
745 RS480_REQ_TYPE_SNOOP_DIS));
747 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
749 dev_priv->gart_size = 32*1024*1024;
750 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
751 0xffff0000) | (dev_priv->gart_vm_start >> 16));
753 radeon_write_agp_location(dev_priv, temp);
755 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
756 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
757 RS480_VA_SIZE_32MB));
760 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
761 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
766 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
767 RS480_GART_CACHE_INVALIDATE);
770 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
771 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
776 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
778 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
782 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
784 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
787 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
788 dev_priv->gart_vm_start,
789 (long)dev_priv->gart_info.bus_addr,
790 dev_priv->gart_size);
791 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
792 dev_priv->gart_vm_start);
793 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
794 dev_priv->gart_info.bus_addr);
795 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
796 dev_priv->gart_vm_start);
797 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
798 dev_priv->gart_vm_start +
799 dev_priv->gart_size - 1);
801 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
803 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
804 RADEON_PCIE_TX_GART_EN);
806 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
807 tmp & ~RADEON_PCIE_TX_GART_EN);
811 /* Enable or disable PCI GART on the chip */
812 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
816 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
817 (dev_priv->flags & RADEON_IS_IGPGART)) {
818 radeon_set_igpgart(dev_priv, on);
822 if (dev_priv->flags & RADEON_IS_PCIE) {
823 radeon_set_pciegart(dev_priv, on);
827 tmp = RADEON_READ(RADEON_AIC_CNTL);
830 RADEON_WRITE(RADEON_AIC_CNTL,
831 tmp | RADEON_PCIGART_TRANSLATE_EN);
833 /* set PCI GART page-table base address
835 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
837 /* set address range for PCI address translate
839 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
840 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
841 + dev_priv->gart_size - 1);
843 /* Turn off AGP aperture -- is this required for PCI GART?
845 radeon_write_agp_location(dev_priv, 0xffffffc0);
846 RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
848 RADEON_WRITE(RADEON_AIC_CNTL,
849 tmp & ~RADEON_PCIGART_TRANSLATE_EN);
853 static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
855 drm_radeon_private_t *dev_priv = dev->dev_private;
859 /* if we require new memory map but we don't have it fail */
860 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
861 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
862 radeon_do_cleanup_cp(dev);
866 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP))
868 DRM_DEBUG("Forcing AGP card to PCI mode\n");
869 dev_priv->flags &= ~RADEON_IS_AGP;
871 else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
874 DRM_DEBUG("Restoring AGP flag\n");
875 dev_priv->flags |= RADEON_IS_AGP;
878 if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
879 DRM_ERROR("PCI GART memory not allocated!\n");
880 radeon_do_cleanup_cp(dev);
884 dev_priv->usec_timeout = init->usec_timeout;
885 if (dev_priv->usec_timeout < 1 ||
886 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
887 DRM_DEBUG("TIMEOUT problem!\n");
888 radeon_do_cleanup_cp(dev);
892 /* Enable vblank on CRTC1 for older X servers
894 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
897 case RADEON_INIT_R200_CP:
898 dev_priv->microcode_version = UCODE_R200;
900 case RADEON_INIT_R300_CP:
901 dev_priv->microcode_version = UCODE_R300;
904 dev_priv->microcode_version = UCODE_R100;
907 dev_priv->do_boxes = 0;
908 dev_priv->cp_mode = init->cp_mode;
910 /* We don't support anything other than bus-mastering ring mode,
911 * but the ring can be in either AGP or PCI space for the ring
914 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
915 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
916 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
917 radeon_do_cleanup_cp(dev);
921 switch (init->fb_bpp) {
923 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
927 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
930 dev_priv->front_offset = init->front_offset;
931 dev_priv->front_pitch = init->front_pitch;
932 dev_priv->back_offset = init->back_offset;
933 dev_priv->back_pitch = init->back_pitch;
935 switch (init->depth_bpp) {
937 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
941 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
944 dev_priv->depth_offset = init->depth_offset;
945 dev_priv->depth_pitch = init->depth_pitch;
947 /* Hardware state for depth clears. Remove this if/when we no
948 * longer clear the depth buffer with a 3D rectangle. Hard-code
949 * all values to prevent unwanted 3D state from slipping through
950 * and screwing with the clear operation.
952 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
953 (dev_priv->color_fmt << 10) |
954 (dev_priv->microcode_version ==
955 UCODE_R100 ? RADEON_ZBLOCK16 : 0));
957 dev_priv->depth_clear.rb3d_zstencilcntl =
958 (dev_priv->depth_fmt |
959 RADEON_Z_TEST_ALWAYS |
960 RADEON_STENCIL_TEST_ALWAYS |
961 RADEON_STENCIL_S_FAIL_REPLACE |
962 RADEON_STENCIL_ZPASS_REPLACE |
963 RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
965 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
968 RADEON_FLAT_SHADE_VTX_LAST |
969 RADEON_DIFFUSE_SHADE_FLAT |
970 RADEON_ALPHA_SHADE_FLAT |
971 RADEON_SPECULAR_SHADE_FLAT |
972 RADEON_FOG_SHADE_FLAT |
973 RADEON_VTX_PIX_CENTER_OGL |
974 RADEON_ROUND_MODE_TRUNC |
975 RADEON_ROUND_PREC_8TH_PIX);
978 dev_priv->ring_offset = init->ring_offset;
979 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
980 dev_priv->buffers_offset = init->buffers_offset;
981 dev_priv->gart_textures_offset = init->gart_textures_offset;
983 dev_priv->sarea = drm_getsarea(dev);
984 if (!dev_priv->sarea) {
985 DRM_ERROR("could not find sarea!\n");
986 radeon_do_cleanup_cp(dev);
990 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
991 if (!dev_priv->cp_ring) {
992 DRM_ERROR("could not find cp ring region!\n");
993 radeon_do_cleanup_cp(dev);
996 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
997 if (!dev_priv->ring_rptr) {
998 DRM_ERROR("could not find ring read pointer!\n");
999 radeon_do_cleanup_cp(dev);
1002 dev->agp_buffer_token = init->buffers_offset;
1003 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1004 if (!dev->agp_buffer_map) {
1005 DRM_ERROR("could not find dma buffer region!\n");
1006 radeon_do_cleanup_cp(dev);
1010 if (init->gart_textures_offset) {
1011 dev_priv->gart_textures =
1012 drm_core_findmap(dev, init->gart_textures_offset);
1013 if (!dev_priv->gart_textures) {
1014 DRM_ERROR("could not find GART texture region!\n");
1015 radeon_do_cleanup_cp(dev);
1020 dev_priv->sarea_priv =
1021 (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
1022 init->sarea_priv_offset);
1025 if (dev_priv->flags & RADEON_IS_AGP) {
1026 drm_core_ioremap(dev_priv->cp_ring, dev);
1027 drm_core_ioremap(dev_priv->ring_rptr, dev);
1028 drm_core_ioremap(dev->agp_buffer_map, dev);
1029 if (!dev_priv->cp_ring->handle ||
1030 !dev_priv->ring_rptr->handle ||
1031 !dev->agp_buffer_map->handle) {
1032 DRM_ERROR("could not find ioremap agp regions!\n");
1033 radeon_do_cleanup_cp(dev);
1039 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1040 dev_priv->ring_rptr->handle =
1041 (void *)dev_priv->ring_rptr->offset;
1042 dev->agp_buffer_map->handle =
1043 (void *)dev->agp_buffer_map->offset;
1045 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1046 dev_priv->cp_ring->handle);
1047 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1048 dev_priv->ring_rptr->handle);
1049 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1050 dev->agp_buffer_map->handle);
1053 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1055 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1056 - dev_priv->fb_location;
1058 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1059 ((dev_priv->front_offset
1060 + dev_priv->fb_location) >> 10));
1062 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1063 ((dev_priv->back_offset
1064 + dev_priv->fb_location) >> 10));
1066 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1067 ((dev_priv->depth_offset
1068 + dev_priv->fb_location) >> 10));
1070 dev_priv->gart_size = init->gart_size;
1072 /* New let's set the memory map ... */
1073 if (dev_priv->new_memmap) {
1076 DRM_INFO("Setting GART location based on new memory map\n");
1078 /* If using AGP, try to locate the AGP aperture at the same
1079 * location in the card and on the bus, though we have to
1083 if (dev_priv->flags & RADEON_IS_AGP) {
1084 base = dev->agp->base;
1085 /* Check if valid */
1086 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1087 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1088 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1094 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1096 base = dev_priv->fb_location + dev_priv->fb_size;
1097 if (base < dev_priv->fb_location ||
1098 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1099 base = dev_priv->fb_location
1100 - dev_priv->gart_size;
1102 dev_priv->gart_vm_start = base & 0xffc00000u;
1103 if (dev_priv->gart_vm_start != base)
1104 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1105 base, dev_priv->gart_vm_start);
1107 DRM_INFO("Setting GART location based on old memory map\n");
1108 dev_priv->gart_vm_start = dev_priv->fb_location +
1109 RADEON_READ(RADEON_CONFIG_APER_SIZE);
1113 if (dev_priv->flags & RADEON_IS_AGP)
1114 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1116 + dev_priv->gart_vm_start);
1119 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1120 - (unsigned long)dev->sg->virtual
1121 + dev_priv->gart_vm_start);
1123 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1124 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1125 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1126 dev_priv->gart_buffers_offset);
1128 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1129 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1130 + init->ring_size / sizeof(u32));
1131 dev_priv->ring.size = init->ring_size;
1132 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1134 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1135 dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1137 dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1138 dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1140 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1142 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1145 if (dev_priv->flags & RADEON_IS_AGP) {
1146 /* Turn off PCI GART */
1147 radeon_set_pcigart(dev_priv, 0);
1151 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1152 /* if we have an offset set from userspace */
1153 if (dev_priv->pcigart_offset_set) {
1154 dev_priv->gart_info.bus_addr =
1155 dev_priv->pcigart_offset + dev_priv->fb_location;
1156 dev_priv->gart_info.mapping.offset =
1157 dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1158 dev_priv->gart_info.mapping.size =
1159 dev_priv->gart_info.table_size;
1161 drm_core_ioremap(&dev_priv->gart_info.mapping, dev);
1162 dev_priv->gart_info.addr =
1163 dev_priv->gart_info.mapping.handle;
1165 if (dev_priv->flags & RADEON_IS_PCIE)
1166 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1168 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1169 dev_priv->gart_info.gart_table_location =
1172 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1173 dev_priv->gart_info.addr,
1174 dev_priv->pcigart_offset);
1176 if (dev_priv->flags & RADEON_IS_IGPGART)
1177 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1179 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1180 dev_priv->gart_info.gart_table_location =
1182 dev_priv->gart_info.addr = NULL;
1183 dev_priv->gart_info.bus_addr = 0;
1184 if (dev_priv->flags & RADEON_IS_PCIE) {
1186 ("Cannot use PCI Express without GART in FB memory\n");
1187 radeon_do_cleanup_cp(dev);
1192 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
1193 DRM_ERROR("failed to init PCI GART!\n");
1194 radeon_do_cleanup_cp(dev);
1198 /* Turn on PCI GART */
1199 radeon_set_pcigart(dev_priv, 1);
1202 radeon_cp_load_microcode(dev_priv);
1203 radeon_cp_init_ring_buffer(dev, dev_priv);
1205 dev_priv->last_buf = 0;
1207 radeon_do_engine_reset(dev);
1208 radeon_test_writeback(dev_priv);
1213 static int radeon_do_cleanup_cp(struct drm_device * dev)
1215 drm_radeon_private_t *dev_priv = dev->dev_private;
1218 /* Make sure interrupts are disabled here because the uninstall ioctl
1219 * may not have been called from userspace and after dev_private
1220 * is freed, it's too late.
1222 if (dev->irq_enabled)
1223 drm_irq_uninstall(dev);
1226 if (dev_priv->flags & RADEON_IS_AGP) {
1227 if (dev_priv->cp_ring != NULL) {
1228 drm_core_ioremapfree(dev_priv->cp_ring, dev);
1229 dev_priv->cp_ring = NULL;
1231 if (dev_priv->ring_rptr != NULL) {
1232 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1233 dev_priv->ring_rptr = NULL;
1235 if (dev->agp_buffer_map != NULL) {
1236 drm_core_ioremapfree(dev->agp_buffer_map, dev);
1237 dev->agp_buffer_map = NULL;
1243 if (dev_priv->gart_info.bus_addr) {
1244 /* Turn off PCI GART */
1245 radeon_set_pcigart(dev_priv, 0);
1246 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1247 DRM_ERROR("failed to cleanup PCI GART!\n");
1250 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1252 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1253 dev_priv->gart_info.addr = 0;
1256 /* only clear to the start of flags */
1257 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1262 /* This code will reinit the Radeon CP hardware after a resume from disc.
1263 * AFAIK, it would be very difficult to pickle the state at suspend time, so
1264 * here we make sure that all Radeon hardware initialisation is re-done without
1265 * affecting running applications.
1267 * Charl P. Botha <http://cpbotha.net>
1269 static int radeon_do_resume_cp(struct drm_device * dev)
1271 drm_radeon_private_t *dev_priv = dev->dev_private;
1274 DRM_ERROR("Called with no initialization\n");
1278 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1281 if (dev_priv->flags & RADEON_IS_AGP) {
1282 /* Turn off PCI GART */
1283 radeon_set_pcigart(dev_priv, 0);
1287 /* Turn on PCI GART */
1288 radeon_set_pcigart(dev_priv, 1);
1291 radeon_cp_load_microcode(dev_priv);
1292 radeon_cp_init_ring_buffer(dev, dev_priv);
1294 radeon_do_engine_reset(dev);
1295 radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
1297 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1302 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1304 drm_radeon_init_t *init = data;
1306 LOCK_TEST_WITH_RETURN(dev, file_priv);
1308 if (init->func == RADEON_INIT_R300_CP)
1309 r300_init_reg_flags(dev);
1311 switch (init->func) {
1312 case RADEON_INIT_CP:
1313 case RADEON_INIT_R200_CP:
1314 case RADEON_INIT_R300_CP:
1315 return radeon_do_init_cp(dev, init);
1316 case RADEON_CLEANUP_CP:
1317 return radeon_do_cleanup_cp(dev);
1323 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1325 drm_radeon_private_t *dev_priv = dev->dev_private;
1328 LOCK_TEST_WITH_RETURN(dev, file_priv);
1330 if (dev_priv->cp_running) {
1331 DRM_DEBUG("while CP running\n");
1334 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1335 DRM_DEBUG("called with bogus CP mode (%d)\n",
1340 radeon_do_cp_start(dev_priv);
1345 /* Stop the CP. The engine must have been idled before calling this
1348 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1350 drm_radeon_private_t *dev_priv = dev->dev_private;
1351 drm_radeon_cp_stop_t *stop = data;
1355 LOCK_TEST_WITH_RETURN(dev, file_priv);
1357 if (!dev_priv->cp_running)
1360 /* Flush any pending CP commands. This ensures any outstanding
1361 * commands are exectuted by the engine before we turn it off.
1364 radeon_do_cp_flush(dev_priv);
1367 /* If we fail to make the engine go idle, we return an error
1368 * code so that the DRM ioctl wrapper can try again.
1371 ret = radeon_do_cp_idle(dev_priv);
1376 /* Finally, we can turn off the CP. If the engine isn't idle,
1377 * we will get some dropped triangles as they won't be fully
1378 * rendered before the CP is shut down.
1380 radeon_do_cp_stop(dev_priv);
1382 /* Reset the engine */
1383 radeon_do_engine_reset(dev);
1388 void radeon_do_release(struct drm_device * dev)
1390 drm_radeon_private_t *dev_priv = dev->dev_private;
1394 if (dev_priv->cp_running) {
1396 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1397 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1401 #if defined(__FreeBSD__) && __FreeBSD_version > 500000
1402 mtx_sleep(&ret, &dev->dev_lock, PZERO, "rdnrel",
1405 tsleep(&ret, PZERO, "rdnrel", 1);
1409 radeon_do_cp_stop(dev_priv);
1410 radeon_do_engine_reset(dev);
1413 /* Disable *all* interrupts */
1414 if (dev_priv->mmio) /* remove this after permanent addmaps */
1415 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1417 if (dev_priv->mmio) { /* remove all surfaces */
1418 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1419 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1420 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1422 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1427 /* Free memory heap structures */
1428 radeon_mem_takedown(&(dev_priv->gart_heap));
1429 radeon_mem_takedown(&(dev_priv->fb_heap));
1431 /* deallocate kernel resources */
1432 radeon_do_cleanup_cp(dev);
1436 /* Just reset the CP ring. Called as part of an X Server engine reset.
1438 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1440 drm_radeon_private_t *dev_priv = dev->dev_private;
1443 LOCK_TEST_WITH_RETURN(dev, file_priv);
1446 DRM_DEBUG("called before init done\n");
1450 radeon_do_cp_reset(dev_priv);
1452 /* The CP is no longer running after an engine reset */
1453 dev_priv->cp_running = 0;
1458 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1460 drm_radeon_private_t *dev_priv = dev->dev_private;
1463 LOCK_TEST_WITH_RETURN(dev, file_priv);
1465 return radeon_do_cp_idle(dev_priv);
1468 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1470 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1473 return radeon_do_resume_cp(dev);
1476 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1480 LOCK_TEST_WITH_RETURN(dev, file_priv);
1482 return radeon_do_engine_reset(dev);
1485 /* ================================================================
1489 /* KW: Deprecated to say the least:
1491 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1496 /* ================================================================
1497 * Freelist management
1500 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1501 * bufs until freelist code is used. Note this hides a problem with
1502 * the scratch register * (used to keep track of last buffer
1503 * completed) being written to before * the last buffer has actually
1504 * completed rendering.
1506 * KW: It's also a good way to find free buffers quickly.
1508 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1509 * sleep. However, bugs in older versions of radeon_accel.c mean that
1510 * we essentially have to do this, else old clients will break.
1512 * However, it does leave open a potential deadlock where all the
1513 * buffers are held by other clients, which can't release them because
1514 * they can't get the lock.
1517 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1519 struct drm_device_dma *dma = dev->dma;
1520 drm_radeon_private_t *dev_priv = dev->dev_private;
1521 drm_radeon_buf_priv_t *buf_priv;
1522 struct drm_buf *buf;
1526 if (++dev_priv->last_buf >= dma->buf_count)
1527 dev_priv->last_buf = 0;
1529 start = dev_priv->last_buf;
1531 for (t = 0; t < dev_priv->usec_timeout; t++) {
1532 u32 done_age = GET_SCRATCH(1);
1533 DRM_DEBUG("done_age = %d\n", done_age);
1534 for (i = start; i < dma->buf_count; i++) {
1535 buf = dma->buflist[i];
1536 buf_priv = buf->dev_private;
1537 if (buf->file_priv == NULL || (buf->pending &&
1540 dev_priv->stats.requested_bufs++;
1549 dev_priv->stats.freelist_loops++;
1553 DRM_DEBUG("returning NULL!\n");
1558 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1560 struct drm_device_dma *dma = dev->dma;
1561 drm_radeon_private_t *dev_priv = dev->dev_private;
1562 drm_radeon_buf_priv_t *buf_priv;
1563 struct drm_buf *buf;
1566 u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1568 if (++dev_priv->last_buf >= dma->buf_count)
1569 dev_priv->last_buf = 0;
1571 start = dev_priv->last_buf;
1572 dev_priv->stats.freelist_loops++;
1574 for (t = 0; t < 2; t++) {
1575 for (i = start; i < dma->buf_count; i++) {
1576 buf = dma->buflist[i];
1577 buf_priv = buf->dev_private;
1578 if (buf->file_priv == 0 || (buf->pending &&
1581 dev_priv->stats.requested_bufs++;
1593 void radeon_freelist_reset(struct drm_device * dev)
1595 struct drm_device_dma *dma = dev->dma;
1596 drm_radeon_private_t *dev_priv = dev->dev_private;
1599 dev_priv->last_buf = 0;
1600 for (i = 0; i < dma->buf_count; i++) {
1601 struct drm_buf *buf = dma->buflist[i];
1602 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1607 /* ================================================================
1608 * CP command submission
1611 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1613 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1615 u32 last_head = GET_RING_HEAD(dev_priv);
1617 for (i = 0; i < dev_priv->usec_timeout; i++) {
1618 u32 head = GET_RING_HEAD(dev_priv);
1620 ring->space = (head - ring->tail) * sizeof(u32);
1621 if (ring->space <= 0)
1622 ring->space += ring->size;
1623 if (ring->space > n)
1626 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1628 if (head != last_head)
1635 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1636 #if RADEON_FIFO_DEBUG
1637 radeon_status(dev_priv);
1638 DRM_ERROR("failed!\n");
1643 static int radeon_cp_get_buffers(struct drm_device *dev,
1644 struct drm_file *file_priv,
1648 struct drm_buf *buf;
1650 for (i = d->granted_count; i < d->request_count; i++) {
1651 buf = radeon_freelist_get(dev);
1653 return -EBUSY; /* NOTE: broken client */
1655 buf->file_priv = file_priv;
1657 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1660 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
1661 sizeof(buf->total)))
1669 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
1671 struct drm_device_dma *dma = dev->dma;
1673 struct drm_dma *d = data;
1675 LOCK_TEST_WITH_RETURN(dev, file_priv);
1677 /* Please don't send us buffers.
1679 if (d->send_count != 0) {
1680 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1681 DRM_CURRENTPID, d->send_count);
1685 /* We'll send you buffers.
1687 if (d->request_count < 0 || d->request_count > dma->buf_count) {
1688 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1689 DRM_CURRENTPID, d->request_count, dma->buf_count);
1693 d->granted_count = 0;
1695 if (d->request_count) {
1696 ret = radeon_cp_get_buffers(dev, file_priv, d);
1702 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
1704 drm_radeon_private_t *dev_priv;
1707 dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
1708 if (dev_priv == NULL)
1711 memset(dev_priv, 0, sizeof(drm_radeon_private_t));
1712 dev->dev_private = (void *)dev_priv;
1713 dev_priv->flags = flags;
1715 switch (flags & RADEON_FAMILY_MASK) {
1727 dev_priv->flags |= RADEON_HAS_HIERZ;
1730 /* all other chips have no hierarchical z buffer */
1734 if (drm_device_is_agp(dev))
1735 dev_priv->flags |= RADEON_IS_AGP;
1736 else if (drm_device_is_pcie(dev))
1737 dev_priv->flags |= RADEON_IS_PCIE;
1739 dev_priv->flags |= RADEON_IS_PCI;
1741 DRM_DEBUG("%s card detected\n",
1742 ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
1746 /* Create mappings for registers and framebuffer so userland doesn't necessarily
1747 * have to find them.
1749 int radeon_driver_firstopen(struct drm_device *dev)
1752 drm_local_map_t *map;
1753 drm_radeon_private_t *dev_priv = dev->dev_private;
1755 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
1757 ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
1758 drm_get_resource_len(dev, 2), _DRM_REGISTERS,
1759 _DRM_READ_ONLY, &dev_priv->mmio);
1763 dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
1764 ret = drm_addmap(dev, dev_priv->fb_aper_offset,
1765 drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
1766 _DRM_WRITE_COMBINING, &map);
1773 int radeon_driver_unload(struct drm_device *dev)
1775 drm_radeon_private_t *dev_priv = dev->dev_private;
1778 drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
1780 dev->dev_private = NULL;