shared-core/radeon_cp.c

   1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
   2 /*
   3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   5  * Copyright 2007 Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25  * DEALINGS IN THE SOFTWARE.
  26  *
  27  * Authors:
  28  *    Kevin E. Martin <martin@valinux.com>
  29  *    Gareth Hughes <gareth@valinux.com>
  30  */
  31
  32 #include "drmP.h"
  33 #include "drm.h"
  34 #include "radeon_drm.h"
  35 #include "radeon_drv.h"
  36 #include "r300_reg.h"
  37
  38 #include "radeon_microcode.h"
  39 #define RADEON_FIFO_DEBUG       0
  40
  41 static int radeon_do_cleanup_cp(struct drm_device * dev);
  42 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
  43
  44 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
  45 {
  46         u32 ret;
  47         RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
  48         ret = RADEON_READ(R520_MC_IND_DATA);
  49         RADEON_WRITE(R520_MC_IND_INDEX, 0);
  50         return ret;
  51 }
  52
  53 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
  54 {
  55         u32 ret;
  56         RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
  57         ret = RADEON_READ(RS480_NB_MC_DATA);
  58         RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
  59         return ret;
  60 }
  61
  62 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
  63 {
  64         u32 ret;
  65         RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
  66         ret = RADEON_READ(RS690_MC_DATA);
  67         RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
  68         return ret;
  69 }
  70
  71 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
  72 {
  73         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
  74             return RS690_READ_MCIND(dev_priv, addr);
  75         else
  76             return RS480_READ_MCIND(dev_priv, addr);
  77 }
  78
  79 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
  80 {
  81
  82         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
  83                 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
  84         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
  85                 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
  86         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
  87                 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
  88         else
  89                 return RADEON_READ(RADEON_MC_FB_LOCATION);
  90 }
  91
  92 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
  93 {
  94         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
  95                 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
  96         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
  97                 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
  98         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
  99                 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
 100         else
 101                 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
 102 }
 103
 104 static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
 105 {
 106         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 107                 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
 108         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
 109                 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
 110         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 111                 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
 112         else
 113                 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
 114 }
 115
 116 static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
 117 {
 118         u32 agp_base_hi = upper_32_bits(agp_base);
 119         u32 agp_base_lo = agp_base & 0xffffffff;
 120
 121         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
 122                 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
 123                 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
 124         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
 125                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
 126                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
 127         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
 128                 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
 129                 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
 130         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 131                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 132                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
 133                 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
 134         } else {
 135                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
 136                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
 137                         RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
 138         }
 139 }
 140
 141 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
 142 {
 143         drm_radeon_private_t *dev_priv = dev->dev_private;
 144
 145         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
 146         return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 147 }
 148
 149 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
 150 {
 151         RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
 152         return RADEON_READ(RADEON_PCIE_DATA);
 153 }
 154
 155 #if RADEON_FIFO_DEBUG
 156 static void radeon_status(drm_radeon_private_t * dev_priv)
 157 {
 158         printk("%s:\n", __FUNCTION__);
 159         printk("RBBM_STATUS = 0x%08x\n",
 160                (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
 161         printk("CP_RB_RTPR = 0x%08x\n",
 162                (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
 163         printk("CP_RB_WTPR = 0x%08x\n",
 164                (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
 165         printk("AIC_CNTL = 0x%08x\n",
 166                (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
 167         printk("AIC_STAT = 0x%08x\n",
 168                (unsigned int)RADEON_READ(RADEON_AIC_STAT));
 169         printk("AIC_PT_BASE = 0x%08x\n",
 170                (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
 171         printk("TLB_ADDR = 0x%08x\n",
 172                (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
 173         printk("TLB_DATA = 0x%08x\n",
 174                (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
 175 }
 176 #endif
 177
 178 /* ================================================================
 179  * Engine, FIFO control
 180  */
 181
 182 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
 183 {
 184         u32 tmp;
 185         int i;
 186
 187         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 188
 189         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
 190                 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
 191                 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
 192                 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
 193
 194                 for (i = 0; i < dev_priv->usec_timeout; i++) {
 195                         if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
 196                               & RADEON_RB3D_DC_BUSY)) {
 197                                 return 0;
 198                         }
 199                         DRM_UDELAY(1);
 200                 }
 201         } else {
 202                 /* don't flush or purge cache here or lockup */
 203                 return 0;
 204         }
 205
 206 #if RADEON_FIFO_DEBUG
 207         DRM_ERROR("failed!\n");
 208         radeon_status(dev_priv);
 209 #endif
 210         return -EBUSY;
 211 }
 212
 213 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
 214 {
 215         int i;
 216
 217         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 218
 219         for (i = 0; i < dev_priv->usec_timeout; i++) {
 220                 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
 221                              & RADEON_RBBM_FIFOCNT_MASK);
 222                 if (slots >= entries)
 223                         return 0;
 224                 DRM_UDELAY(1);
 225         }
 226         DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n",
 227                  RADEON_READ(RADEON_RBBM_STATUS),
 228                  RADEON_READ(R300_VAP_CNTL_STATUS));
 229
 230 #if RADEON_FIFO_DEBUG
 231         DRM_ERROR("failed!\n");
 232         radeon_status(dev_priv);
 233 #endif
 234         return -EBUSY;
 235 }
 236
 237 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
 238 {
 239         int i, ret;
 240
 241         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 242
 243         ret = radeon_do_wait_for_fifo(dev_priv, 64);
 244         if (ret)
 245                 return ret;
 246
 247         for (i = 0; i < dev_priv->usec_timeout; i++) {
 248                 if (!(RADEON_READ(RADEON_RBBM_STATUS)
 249                       & RADEON_RBBM_ACTIVE)) {
 250                         radeon_do_pixcache_flush(dev_priv);
 251                         return 0;
 252                 }
 253                 DRM_UDELAY(1);
 254         }
 255         DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n",
 256                  RADEON_READ(RADEON_RBBM_STATUS),
 257                  RADEON_READ(R300_VAP_CNTL_STATUS));
 258
 259 #if RADEON_FIFO_DEBUG
 260         DRM_ERROR("failed!\n");
 261         radeon_status(dev_priv);
 262 #endif
 263         return -EBUSY;
 264 }
 265
 266 static void radeon_init_pipes(drm_radeon_private_t * dev_priv)
 267 {
 268         uint32_t gb_tile_config, gb_pipe_sel = 0;
 269
 270         /* RS4xx/RS6xx/R4xx/R5xx */
 271         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
 272                 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
 273                 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
 274         } else {
 275                 /* R3xx */
 276                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
 277                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
 278                         dev_priv->num_gb_pipes = 2;
 279                 } else {
 280                         /* R3Vxx */
 281                         dev_priv->num_gb_pipes = 1;
 282                 }
 283         }
 284         DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
 285
 286         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
 287
 288         switch(dev_priv->num_gb_pipes) {
 289         case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
 290         case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
 291         case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
 292         default:
 293         case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
 294         }
 295
 296         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
 297                 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
 298                 RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
 299         }
 300         RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
 301         radeon_do_wait_for_idle(dev_priv);
 302         RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
 303         RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
 304                                                R300_DC_AUTOFLUSH_ENABLE |
 305                                                R300_DC_DC_DISABLE_IGNORE_PE));
 306
 307
 308 }
 309
 310 /* ================================================================
 311  * CP control, initialization
 312  */
 313
 314 /* Load the microcode for the CP */
 315 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
 316 {
 317         int i;
 318         DRM_DEBUG("\n");
 319
 320         radeon_do_wait_for_idle(dev_priv);
 321
 322         RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
 323
 324         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
 325             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
 326             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
 327             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
 328             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
 329                 DRM_INFO("Loading R100 Microcode\n");
 330                 for (i = 0; i < 256; i++) {
 331                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 332                                      R100_cp_microcode[i][1]);
 333                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 334                                      R100_cp_microcode[i][0]);
 335                 }
 336         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
 337                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
 338                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
 339                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
 340                 DRM_INFO("Loading R200 Microcode\n");
 341                 for (i = 0; i < 256; i++) {
 342                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 343                                      R200_cp_microcode[i][1]);
 344                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 345                                      R200_cp_microcode[i][0]);
 346                 }
 347         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
 348                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
 349                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
 350                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
 351                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 352                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 353                 DRM_INFO("Loading R300 Microcode\n");
 354                 for (i = 0; i < 256; i++) {
 355                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 356                                      R300_cp_microcode[i][1]);
 357                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 358                                      R300_cp_microcode[i][0]);
 359                 }
 360         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
 361                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
 362                 DRM_INFO("Loading R400 Microcode\n");
 363                 for (i = 0; i < 256; i++) {
 364                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 365                                      R420_cp_microcode[i][1]);
 366                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 367                                      R420_cp_microcode[i][0]);
 368                 }
 369         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
 370                 DRM_INFO("Loading RS690 Microcode\n");
 371                 for (i = 0; i < 256; i++) {
 372                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 373                                      RS690_cp_microcode[i][1]);
 374                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 375                                      RS690_cp_microcode[i][0]);
 376                 }
 377         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
 378                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
 379                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
 380                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
 381                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
 382                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
 383                 DRM_INFO("Loading R500 Microcode\n");
 384                 for (i = 0; i < 256; i++) {
 385                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 386                                      R520_cp_microcode[i][1]);
 387                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 388                                      R520_cp_microcode[i][0]);
 389                 }
 390         }
 391 }
 392
 393 /* Flush any pending commands to the CP.  This should only be used just
 394  * prior to a wait for idle, as it informs the engine that the command
 395  * stream is ending.
 396  */
 397 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
 398 {
 399         DRM_DEBUG("\n");
 400 #if 0
 401         u32 tmp;
 402
 403         tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
 404         RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
 405 #endif
 406 }
 407
 408 /* Wait for the CP to go idle.
 409  */
 410 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
 411 {
 412         RING_LOCALS;
 413         DRM_DEBUG("\n");
 414
 415         BEGIN_RING(6);
 416
 417         RADEON_PURGE_CACHE();
 418         RADEON_PURGE_ZCACHE();
 419         RADEON_WAIT_UNTIL_IDLE();
 420
 421         ADVANCE_RING();
 422         COMMIT_RING();
 423
 424         return radeon_do_wait_for_idle(dev_priv);
 425 }
 426
 427 /* Start the Command Processor.
 428  */
 429 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
 430 {
 431         RING_LOCALS;
 432         DRM_DEBUG("\n");
 433
 434         radeon_do_wait_for_idle(dev_priv);
 435
 436         RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
 437
 438         dev_priv->cp_running = 1;
 439
 440         BEGIN_RING(8);
 441         /* isync can only be written through cp on r5xx write it here */
 442         OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
 443         OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
 444                  RADEON_ISYNC_ANY3D_IDLE2D |
 445                  RADEON_ISYNC_WAIT_IDLEGUI |
 446                  RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 447         RADEON_PURGE_CACHE();
 448         RADEON_PURGE_ZCACHE();
 449         RADEON_WAIT_UNTIL_IDLE();
 450         ADVANCE_RING();
 451         COMMIT_RING();
 452
 453         dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
 454 }
 455
 456 /* Reset the Command Processor.  This will not flush any pending
 457  * commands, so you must wait for the CP command stream to complete
 458  * before calling this routine.
 459  */
 460 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
 461 {
 462         u32 cur_read_ptr;
 463         DRM_DEBUG("\n");
 464
 465         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 466         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 467         SET_RING_HEAD(dev_priv, cur_read_ptr);
 468         dev_priv->ring.tail = cur_read_ptr;
 469 }
 470
 471 /* Stop the Command Processor.  This will not flush any pending
 472  * commands, so you must flush the command stream and wait for the CP
 473  * to go idle before calling this routine.
 474  */
 475 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
 476 {
 477         DRM_DEBUG("\n");
 478
 479         RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
 480
 481         dev_priv->cp_running = 0;
 482 }
 483
 484 /* Reset the engine.  This will stop the CP if it is running.
 485  */
 486 static int radeon_do_engine_reset(struct drm_device * dev)
 487 {
 488         drm_radeon_private_t *dev_priv = dev->dev_private;
 489         u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
 490         DRM_DEBUG("\n");
 491
 492         radeon_do_pixcache_flush(dev_priv);
 493
 494         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
 495                 /* may need something similar for newer chips */
 496                 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
 497                 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
 498
 499                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
 500                                                     RADEON_FORCEON_MCLKA |
 501                                                     RADEON_FORCEON_MCLKB |
 502                                                     RADEON_FORCEON_YCLKA |
 503                                                     RADEON_FORCEON_YCLKB |
 504                                                     RADEON_FORCEON_MC |
 505                                                     RADEON_FORCEON_AIC));
 506         }
 507
 508         rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
 509
 510         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
 511                                               RADEON_SOFT_RESET_CP |
 512                                               RADEON_SOFT_RESET_HI |
 513                                               RADEON_SOFT_RESET_SE |
 514                                               RADEON_SOFT_RESET_RE |
 515                                               RADEON_SOFT_RESET_PP |
 516                                               RADEON_SOFT_RESET_E2 |
 517                                               RADEON_SOFT_RESET_RB));
 518         RADEON_READ(RADEON_RBBM_SOFT_RESET);
 519         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
 520                                               ~(RADEON_SOFT_RESET_CP |
 521                                                 RADEON_SOFT_RESET_HI |
 522                                                 RADEON_SOFT_RESET_SE |
 523                                                 RADEON_SOFT_RESET_RE |
 524                                                 RADEON_SOFT_RESET_PP |
 525                                                 RADEON_SOFT_RESET_E2 |
 526                                                 RADEON_SOFT_RESET_RB)));
 527         RADEON_READ(RADEON_RBBM_SOFT_RESET);
 528
 529         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
 530                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
 531                 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
 532                 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
 533         }
 534
 535         /* setup the raster pipes */
 536         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
 537             radeon_init_pipes(dev_priv);
 538
 539         /* Reset the CP ring */
 540         radeon_do_cp_reset(dev_priv);
 541
 542         /* The CP is no longer running after an engine reset */
 543         dev_priv->cp_running = 0;
 544
 545         /* Reset any pending vertex, indirect buffers */
 546         radeon_freelist_reset(dev);
 547
 548         return 0;
 549 }
 550
 551 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
 552                                        drm_radeon_private_t * dev_priv)
 553 {
 554         u32 ring_start, cur_read_ptr;
 555         u32 tmp;
 556
 557         /* Initialize the memory controller. With new memory map, the fb location
 558          * is not changed, it should have been properly initialized already. Part
 559          * of the problem is that the code below is bogus, assuming the GART is
 560          * always appended to the fb which is not necessarily the case
 561          */
 562         if (!dev_priv->new_memmap)
 563                 radeon_write_fb_location(dev_priv,
 564                              ((dev_priv->gart_vm_start - 1) & 0xffff0000)
 565                              | (dev_priv->fb_location >> 16));
 566
 567 #if __OS_HAS_AGP
 568         if (dev_priv->flags & RADEON_IS_AGP) {
 569                 radeon_write_agp_base(dev_priv, dev->agp->base);
 570
 571                 radeon_write_agp_location(dev_priv,
 572                              (((dev_priv->gart_vm_start - 1 +
 573                                 dev_priv->gart_size) & 0xffff0000) |
 574                               (dev_priv->gart_vm_start >> 16)));
 575
 576                 ring_start = (dev_priv->cp_ring->offset
 577                               - dev->agp->base
 578                               + dev_priv->gart_vm_start);
 579         } else
 580 #endif
 581                 ring_start = (dev_priv->cp_ring->offset
 582                               - (unsigned long)dev->sg->virtual
 583                               + dev_priv->gart_vm_start);
 584
 585         RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
 586
 587         /* Set the write pointer delay */
 588         RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
 589
 590         /* Initialize the ring buffer's read and write pointers */
 591         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 592         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 593         SET_RING_HEAD(dev_priv, cur_read_ptr);
 594         dev_priv->ring.tail = cur_read_ptr;
 595
 596 #if __OS_HAS_AGP
 597         if (dev_priv->flags & RADEON_IS_AGP) {
 598                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
 599                              dev_priv->ring_rptr->offset
 600                              - dev->agp->base + dev_priv->gart_vm_start);
 601         } else
 602 #endif
 603         {
 604                 struct drm_sg_mem *entry = dev->sg;
 605                 unsigned long tmp_ofs, page_ofs;
 606
 607                 tmp_ofs = dev_priv->ring_rptr->offset -
 608                                 (unsigned long)dev->sg->virtual;
 609                 page_ofs = tmp_ofs >> PAGE_SHIFT;
 610
 611                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
 612                 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
 613                           (unsigned long)entry->busaddr[page_ofs],
 614                           entry->handle + tmp_ofs);
 615         }
 616
 617         /* Set ring buffer size */
 618 #ifdef __BIG_ENDIAN
 619         RADEON_WRITE(RADEON_CP_RB_CNTL,
 620                      RADEON_BUF_SWAP_32BIT |
 621                      (dev_priv->ring.fetch_size_l2ow << 18) |
 622                      (dev_priv->ring.rptr_update_l2qw << 8) |
 623                      dev_priv->ring.size_l2qw);
 624 #else
 625         RADEON_WRITE(RADEON_CP_RB_CNTL,
 626                      (dev_priv->ring.fetch_size_l2ow << 18) |
 627                      (dev_priv->ring.rptr_update_l2qw << 8) |
 628                      dev_priv->ring.size_l2qw);
 629 #endif
 630
 631         /* Start with assuming that writeback doesn't work */
 632         dev_priv->writeback_works = 0;
 633
 634         /* Initialize the scratch register pointer.  This will cause
 635          * the scratch register values to be written out to memory
 636          * whenever they are updated.
 637          *
 638          * We simply put this behind the ring read pointer, this works
 639          * with PCI GART as well as (whatever kind of) AGP GART
 640          */
 641         RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
 642                      + RADEON_SCRATCH_REG_OFFSET);
 643
 644         dev_priv->scratch = ((__volatile__ u32 *)
 645                              dev_priv->ring_rptr->handle +
 646                              (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
 647
 648         RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
 649
 650         /* Turn on bus mastering */
 651         tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 652         RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 653
 654         dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
 655         RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
 656
 657         dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
 658         RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
 659                      dev_priv->sarea_priv->last_dispatch);
 660
 661         dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
 662         RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
 663
 664         radeon_do_wait_for_idle(dev_priv);
 665
 666         /* Sync everything up */
 667         RADEON_WRITE(RADEON_ISYNC_CNTL,
 668                      (RADEON_ISYNC_ANY2D_IDLE3D |
 669                       RADEON_ISYNC_ANY3D_IDLE2D |
 670                       RADEON_ISYNC_WAIT_IDLEGUI |
 671                       RADEON_ISYNC_CPSCRATCH_IDLEGUI));
 672
 673 }
 674
 675 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
 676 {
 677         u32 tmp;
 678
 679         /* Writeback doesn't seem to work everywhere, test it here and possibly
 680          * enable it if it appears to work
 681          */
 682         DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
 683         RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
 684
 685         for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
 686                 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
 687                     0xdeadbeef)
 688                         break;
 689                 DRM_UDELAY(1);
 690         }
 691
 692         if (tmp < dev_priv->usec_timeout) {
 693                 dev_priv->writeback_works = 1;
 694                 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
 695         } else {
 696                 dev_priv->writeback_works = 0;
 697                 DRM_INFO("writeback test failed\n");
 698         }
 699         if (radeon_no_wb == 1) {
 700                 dev_priv->writeback_works = 0;
 701                 DRM_INFO("writeback forced off\n");
 702         }
 703
 704         if (!dev_priv->writeback_works) {
 705                 /* Disable writeback to avoid unnecessary bus master transfers */
 706                 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) | RADEON_RB_NO_UPDATE);
 707                 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
 708         }
 709 }
 710
 711 /* Enable or disable IGP GART on the chip */
 712 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
 713 {
 714         u32 temp;
 715
 716         if (on) {
 717                 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
 718                          dev_priv->gart_vm_start,
 719                          (long)dev_priv->gart_info.bus_addr,
 720                          dev_priv->gart_size);
 721
 722                 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
 723
 724                 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
 725                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
 726                                                              RS690_BLOCK_GFX_D3_EN));
 727                 else
 728                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
 729
 730                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
 731                                                                RS480_VA_SIZE_32MB));
 732
 733                 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
 734                 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
 735                                                         RS480_TLB_ENABLE |
 736                                                         RS480_GTW_LAC_EN |
 737                                                         RS480_1LEVEL_GART));
 738
 739                 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
 740                 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
 741                 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
 742
 743                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
 744                 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
 745                                                       RS480_REQ_TYPE_SNOOP_DIS));
 746
 747                 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
 748
 749                 dev_priv->gart_size = 32*1024*1024;
 750                 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
 751                         0xffff0000) | (dev_priv->gart_vm_start >> 16));
 752
 753                 radeon_write_agp_location(dev_priv, temp);
 754
 755                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
 756                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
 757                                                                RS480_VA_SIZE_32MB));
 758
 759                 do {
 760                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
 761                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
 762                                 break;
 763                         DRM_UDELAY(1);
 764                 } while(1);
 765
 766                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
 767                                 RS480_GART_CACHE_INVALIDATE);
 768
 769                 do {
 770                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
 771                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
 772                                 break;
 773                         DRM_UDELAY(1);
 774                 } while(1);
 775
 776                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
 777         } else {
 778                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
 779         }
 780 }
 781
 782 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
 783 {
 784         u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
 785         if (on) {
 786
 787                 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
 788                           dev_priv->gart_vm_start,
 789                           (long)dev_priv->gart_info.bus_addr,
 790                           dev_priv->gart_size);
 791                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
 792                                   dev_priv->gart_vm_start);
 793                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
 794                                   dev_priv->gart_info.bus_addr);
 795                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
 796                                   dev_priv->gart_vm_start);
 797                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
 798                                   dev_priv->gart_vm_start +
 799                                   dev_priv->gart_size - 1);
 800
 801                 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
 802
 803                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
 804                                   RADEON_PCIE_TX_GART_EN);
 805         } else {
 806                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
 807                                   tmp & ~RADEON_PCIE_TX_GART_EN);
 808         }
 809 }
 810
 811 /* Enable or disable PCI GART on the chip */
 812 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
 813 {
 814         u32 tmp;
 815
 816         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 817             (dev_priv->flags & RADEON_IS_IGPGART)) {
 818                 radeon_set_igpgart(dev_priv, on);
 819                 return;
 820         }
 821
 822         if (dev_priv->flags & RADEON_IS_PCIE) {
 823                 radeon_set_pciegart(dev_priv, on);
 824                 return;
 825         }
 826
 827         tmp = RADEON_READ(RADEON_AIC_CNTL);
 828
 829         if (on) {
 830                 RADEON_WRITE(RADEON_AIC_CNTL,
 831                              tmp | RADEON_PCIGART_TRANSLATE_EN);
 832
 833                 /* set PCI GART page-table base address
 834                  */
 835                 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
 836
 837                 /* set address range for PCI address translate
 838                  */
 839                 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
 840                 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
 841                              + dev_priv->gart_size - 1);
 842
 843                 /* Turn off AGP aperture -- is this required for PCI GART?
 844                  */
 845                 radeon_write_agp_location(dev_priv, 0xffffffc0);
 846                 RADEON_WRITE(RADEON_AGP_COMMAND, 0);    /* clear AGP_COMMAND */
 847         } else {
 848                 RADEON_WRITE(RADEON_AIC_CNTL,
 849                              tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 850         }
 851 }
 852
 853 static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
 854 {
 855         drm_radeon_private_t *dev_priv = dev->dev_private;
 856
 857         DRM_DEBUG("\n");
 858
 859         /* if we require new memory map but we don't have it fail */
 860         if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
 861                 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
 862                 radeon_do_cleanup_cp(dev);
 863                 return -EINVAL;
 864         }
 865
 866         if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP))
 867         {
 868                 DRM_DEBUG("Forcing AGP card to PCI mode\n");
 869                 dev_priv->flags &= ~RADEON_IS_AGP;
 870         }
 871         else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
 872                  && !init->is_pci)
 873         {
 874                 DRM_DEBUG("Restoring AGP flag\n");
 875                 dev_priv->flags |= RADEON_IS_AGP;
 876         }
 877
 878         if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
 879                 DRM_ERROR("PCI GART memory not allocated!\n");
 880                 radeon_do_cleanup_cp(dev);
 881                 return -EINVAL;
 882         }
 883
 884         dev_priv->usec_timeout = init->usec_timeout;
 885         if (dev_priv->usec_timeout < 1 ||
 886             dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
 887                 DRM_DEBUG("TIMEOUT problem!\n");
 888                 radeon_do_cleanup_cp(dev);
 889                 return -EINVAL;
 890         }
 891
 892         /* Enable vblank on CRTC1 for older X servers
 893          */
 894         dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
 895
 896         dev_priv->do_boxes = 0;
 897         dev_priv->cp_mode = init->cp_mode;
 898
 899         /* We don't support anything other than bus-mastering ring mode,
 900          * but the ring can be in either AGP or PCI space for the ring
 901          * read pointer.
 902          */
 903         if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
 904             (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
 905                 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
 906                 radeon_do_cleanup_cp(dev);
 907                 return -EINVAL;
 908         }
 909
 910         switch (init->fb_bpp) {
 911         case 16:
 912                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
 913                 break;
 914         case 32:
 915         default:
 916                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
 917                 break;
 918         }
 919         dev_priv->front_offset = init->front_offset;
 920         dev_priv->front_pitch = init->front_pitch;
 921         dev_priv->back_offset = init->back_offset;
 922         dev_priv->back_pitch = init->back_pitch;
 923
 924         switch (init->depth_bpp) {
 925         case 16:
 926                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
 927                 break;
 928         case 32:
 929         default:
 930                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
 931                 break;
 932         }
 933         dev_priv->depth_offset = init->depth_offset;
 934         dev_priv->depth_pitch = init->depth_pitch;
 935
 936         /* Hardware state for depth clears.  Remove this if/when we no
 937          * longer clear the depth buffer with a 3D rectangle.  Hard-code
 938          * all values to prevent unwanted 3D state from slipping through
 939          * and screwing with the clear operation.
 940          */
 941         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
 942                                            (dev_priv->color_fmt << 10) |
 943                                            (dev_priv->chip_family < CHIP_R200 ? RADEON_ZBLOCK16 : 0));
 944
 945         dev_priv->depth_clear.rb3d_zstencilcntl =
 946             (dev_priv->depth_fmt |
 947              RADEON_Z_TEST_ALWAYS |
 948              RADEON_STENCIL_TEST_ALWAYS |
 949              RADEON_STENCIL_S_FAIL_REPLACE |
 950              RADEON_STENCIL_ZPASS_REPLACE |
 951              RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
 952
 953         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
 954                                          RADEON_BFACE_SOLID |
 955                                          RADEON_FFACE_SOLID |
 956                                          RADEON_FLAT_SHADE_VTX_LAST |
 957                                          RADEON_DIFFUSE_SHADE_FLAT |
 958                                          RADEON_ALPHA_SHADE_FLAT |
 959                                          RADEON_SPECULAR_SHADE_FLAT |
 960                                          RADEON_FOG_SHADE_FLAT |
 961                                          RADEON_VTX_PIX_CENTER_OGL |
 962                                          RADEON_ROUND_MODE_TRUNC |
 963                                          RADEON_ROUND_PREC_8TH_PIX);
 964
 965
 966         dev_priv->ring_offset = init->ring_offset;
 967         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
 968         dev_priv->buffers_offset = init->buffers_offset;
 969         dev_priv->gart_textures_offset = init->gart_textures_offset;
 970
 971         dev_priv->sarea = drm_getsarea(dev);
 972         if (!dev_priv->sarea) {
 973                 DRM_ERROR("could not find sarea!\n");
 974                 radeon_do_cleanup_cp(dev);
 975                 return -EINVAL;
 976         }
 977
 978         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
 979         if (!dev_priv->cp_ring) {
 980                 DRM_ERROR("could not find cp ring region!\n");
 981                 radeon_do_cleanup_cp(dev);
 982                 return -EINVAL;
 983         }
 984         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
 985         if (!dev_priv->ring_rptr) {
 986                 DRM_ERROR("could not find ring read pointer!\n");
 987                 radeon_do_cleanup_cp(dev);
 988                 return -EINVAL;
 989         }
 990         dev->agp_buffer_token = init->buffers_offset;
 991         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
 992         if (!dev->agp_buffer_map) {
 993                 DRM_ERROR("could not find dma buffer region!\n");
 994                 radeon_do_cleanup_cp(dev);
 995                 return -EINVAL;
 996         }
 997
 998         if (init->gart_textures_offset) {
 999                 dev_priv->gart_textures =
1000                     drm_core_findmap(dev, init->gart_textures_offset);
1001                 if (!dev_priv->gart_textures) {
1002                         DRM_ERROR("could not find GART texture region!\n");
1003                         radeon_do_cleanup_cp(dev);
1004                         return -EINVAL;
1005                 }
1006         }
1007
1008         dev_priv->sarea_priv =
1009             (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
1010                                     init->sarea_priv_offset);
1011
1012 #if __OS_HAS_AGP
1013         if (dev_priv->flags & RADEON_IS_AGP) {
1014                 drm_core_ioremap(dev_priv->cp_ring, dev);
1015                 drm_core_ioremap(dev_priv->ring_rptr, dev);
1016                 drm_core_ioremap(dev->agp_buffer_map, dev);
1017                 if (!dev_priv->cp_ring->handle ||
1018                     !dev_priv->ring_rptr->handle ||
1019                     !dev->agp_buffer_map->handle) {
1020                         DRM_ERROR("could not find ioremap agp regions!\n");
1021                         radeon_do_cleanup_cp(dev);
1022                         return -EINVAL;
1023                 }
1024         } else
1025 #endif
1026         {
1027                 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1028                 dev_priv->ring_rptr->handle =
1029                     (void *)dev_priv->ring_rptr->offset;
1030                 dev->agp_buffer_map->handle =
1031                     (void *)dev->agp_buffer_map->offset;
1032
1033                 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1034                           dev_priv->cp_ring->handle);
1035                 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1036                           dev_priv->ring_rptr->handle);
1037                 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1038                           dev->agp_buffer_map->handle);
1039         }
1040
1041         dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1042         dev_priv->fb_size =
1043                 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1044                 - dev_priv->fb_location;
1045
1046         dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1047                                         ((dev_priv->front_offset
1048                                           + dev_priv->fb_location) >> 10));
1049
1050         dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1051                                        ((dev_priv->back_offset
1052                                          + dev_priv->fb_location) >> 10));
1053
1054         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1055                                         ((dev_priv->depth_offset
1056                                           + dev_priv->fb_location) >> 10));
1057
1058         dev_priv->gart_size = init->gart_size;
1059
1060         /* New let's set the memory map ... */
1061         if (dev_priv->new_memmap) {
1062                 u32 base = 0;
1063
1064                 DRM_INFO("Setting GART location based on new memory map\n");
1065
1066                 /* If using AGP, try to locate the AGP aperture at the same
1067                  * location in the card and on the bus, though we have to
1068                  * align it down.
1069                  */
1070 #if __OS_HAS_AGP
1071                 if (dev_priv->flags & RADEON_IS_AGP) {
1072                         base = dev->agp->base;
1073                         /* Check if valid */
1074                         if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1075                             base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1076                                 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1077                                          dev->agp->base);
1078                                 base = 0;
1079                         }
1080                 }
1081 #endif
1082                 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1083                 if (base == 0) {
1084                         base = dev_priv->fb_location + dev_priv->fb_size;
1085                         if (base < dev_priv->fb_location ||
1086                             ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1087                                 base = dev_priv->fb_location
1088                                         - dev_priv->gart_size;
1089                 }
1090                 dev_priv->gart_vm_start = base & 0xffc00000u;
1091                 if (dev_priv->gart_vm_start != base)
1092                         DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1093                                  base, dev_priv->gart_vm_start);
1094         } else {
1095                 DRM_INFO("Setting GART location based on old memory map\n");
1096                 dev_priv->gart_vm_start = dev_priv->fb_location +
1097                         RADEON_READ(RADEON_CONFIG_APER_SIZE);
1098         }
1099
1100 #if __OS_HAS_AGP
1101         if (dev_priv->flags & RADEON_IS_AGP)
1102                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1103                                                  - dev->agp->base
1104                                                  + dev_priv->gart_vm_start);
1105         else
1106 #endif
1107                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1108                                         - (unsigned long)dev->sg->virtual
1109                                         + dev_priv->gart_vm_start);
1110
1111         DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1112         DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1113         DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1114                   dev_priv->gart_buffers_offset);
1115
1116         dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1117         dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1118                               + init->ring_size / sizeof(u32));
1119         dev_priv->ring.size = init->ring_size;
1120         dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1121
1122         dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1123         dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1124
1125         dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1126         dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1127
1128         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1129
1130         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1131
1132 #if __OS_HAS_AGP
1133         if (dev_priv->flags & RADEON_IS_AGP) {
1134                 /* Turn off PCI GART */
1135                 radeon_set_pcigart(dev_priv, 0);
1136         } else
1137 #endif
1138         {
1139                 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1140                 /* if we have an offset set from userspace */
1141                 if (dev_priv->pcigart_offset_set) {
1142                         dev_priv->gart_info.bus_addr =
1143                             dev_priv->pcigart_offset + dev_priv->fb_location;
1144                         dev_priv->gart_info.mapping.offset =
1145                             dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1146                         dev_priv->gart_info.mapping.size =
1147                             dev_priv->gart_info.table_size;
1148
1149                         drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
1150                         dev_priv->gart_info.addr =
1151                             dev_priv->gart_info.mapping.handle;
1152
1153                         if (dev_priv->flags & RADEON_IS_PCIE)
1154                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1155                         else
1156                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1157                         dev_priv->gart_info.gart_table_location =
1158                             DRM_ATI_GART_FB;
1159
1160                         DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1161                                   dev_priv->gart_info.addr,
1162                                   dev_priv->pcigart_offset);
1163                 } else {
1164                         if (dev_priv->flags & RADEON_IS_IGPGART)
1165                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1166                         else
1167                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1168                         dev_priv->gart_info.gart_table_location =
1169                             DRM_ATI_GART_MAIN;
1170                         dev_priv->gart_info.addr = NULL;
1171                         dev_priv->gart_info.bus_addr = 0;
1172                         if (dev_priv->flags & RADEON_IS_PCIE) {
1173                                 DRM_ERROR
1174                                     ("Cannot use PCI Express without GART in FB memory\n");
1175                                 radeon_do_cleanup_cp(dev);
1176                                 return -EINVAL;
1177                         }
1178                 }
1179
1180                 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
1181                         DRM_ERROR("failed to init PCI GART!\n");
1182                         radeon_do_cleanup_cp(dev);
1183                         return -ENOMEM;
1184                 }
1185
1186                 /* Turn on PCI GART */
1187                 radeon_set_pcigart(dev_priv, 1);
1188         }
1189
1190         radeon_cp_load_microcode(dev_priv);
1191         radeon_cp_init_ring_buffer(dev, dev_priv);
1192
1193         dev_priv->last_buf = 0;
1194
1195         radeon_do_engine_reset(dev);
1196         radeon_test_writeback(dev_priv);
1197
1198         return 0;
1199 }
1200
1201 static int radeon_do_cleanup_cp(struct drm_device * dev)
1202 {
1203         drm_radeon_private_t *dev_priv = dev->dev_private;
1204         DRM_DEBUG("\n");
1205
1206         /* Make sure interrupts are disabled here because the uninstall ioctl
1207          * may not have been called from userspace and after dev_private
1208          * is freed, it's too late.
1209          */
1210         if (dev->irq_enabled)
1211                 drm_irq_uninstall(dev);
1212
1213 #if __OS_HAS_AGP
1214         if (dev_priv->flags & RADEON_IS_AGP) {
1215                 if (dev_priv->cp_ring != NULL) {
1216                         drm_core_ioremapfree(dev_priv->cp_ring, dev);
1217                         dev_priv->cp_ring = NULL;
1218                 }
1219                 if (dev_priv->ring_rptr != NULL) {
1220                         drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1221                         dev_priv->ring_rptr = NULL;
1222                 }
1223                 if (dev->agp_buffer_map != NULL) {
1224                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
1225                         dev->agp_buffer_map = NULL;
1226                 }
1227         } else
1228 #endif
1229         {
1230
1231                 if (dev_priv->gart_info.bus_addr) {
1232                         /* Turn off PCI GART */
1233                         radeon_set_pcigart(dev_priv, 0);
1234                         if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1235                                 DRM_ERROR("failed to cleanup PCI GART!\n");
1236                 }
1237
1238                 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1239                 {
1240                         drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1241                         dev_priv->gart_info.addr = 0;
1242                 }
1243         }
1244         /* only clear to the start of flags */
1245         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1246
1247         return 0;
1248 }
1249
1250 /* This code will reinit the Radeon CP hardware after a resume from disc.
1251  * AFAIK, it would be very difficult to pickle the state at suspend time, so
1252  * here we make sure that all Radeon hardware initialisation is re-done without
1253  * affecting running applications.
1254  *
1255  * Charl P. Botha <http://cpbotha.net>
1256  */
1257 static int radeon_do_resume_cp(struct drm_device * dev)
1258 {
1259         drm_radeon_private_t *dev_priv = dev->dev_private;
1260
1261         if (!dev_priv) {
1262                 DRM_ERROR("Called with no initialization\n");
1263                 return -EINVAL;
1264         }
1265
1266         DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1267
1268 #if __OS_HAS_AGP
1269         if (dev_priv->flags & RADEON_IS_AGP) {
1270                 /* Turn off PCI GART */
1271                 radeon_set_pcigart(dev_priv, 0);
1272         } else
1273 #endif
1274         {
1275                 /* Turn on PCI GART */
1276                 radeon_set_pcigart(dev_priv, 1);
1277         }
1278
1279         radeon_cp_load_microcode(dev_priv);
1280         radeon_cp_init_ring_buffer(dev, dev_priv);
1281
1282         radeon_do_engine_reset(dev);
1283         radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
1284
1285         DRM_DEBUG("radeon_do_resume_cp() complete\n");
1286
1287         return 0;
1288 }
1289
1290 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1291 {
1292         drm_radeon_init_t *init = data;
1293
1294         LOCK_TEST_WITH_RETURN(dev, file_priv);
1295
1296         if (init->func == RADEON_INIT_R300_CP)
1297                 r300_init_reg_flags(dev);
1298
1299         switch (init->func) {
1300         case RADEON_INIT_CP:
1301         case RADEON_INIT_R200_CP:
1302         case RADEON_INIT_R300_CP:
1303                 return radeon_do_init_cp(dev, init);
1304         case RADEON_CLEANUP_CP:
1305                 return radeon_do_cleanup_cp(dev);
1306         }
1307
1308         return -EINVAL;
1309 }
1310
1311 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1312 {
1313         drm_radeon_private_t *dev_priv = dev->dev_private;
1314         DRM_DEBUG("\n");
1315
1316         LOCK_TEST_WITH_RETURN(dev, file_priv);
1317
1318         if (dev_priv->cp_running) {
1319                 DRM_DEBUG("while CP running\n");
1320                 return 0;
1321         }
1322         if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1323                 DRM_DEBUG("called with bogus CP mode (%d)\n",
1324                           dev_priv->cp_mode);
1325                 return 0;
1326         }
1327
1328         radeon_do_cp_start(dev_priv);
1329
1330         return 0;
1331 }
1332
1333 /* Stop the CP.  The engine must have been idled before calling this
1334  * routine.
1335  */
1336 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1337 {
1338         drm_radeon_private_t *dev_priv = dev->dev_private;
1339         drm_radeon_cp_stop_t *stop = data;
1340         int ret;
1341         DRM_DEBUG("\n");
1342
1343         LOCK_TEST_WITH_RETURN(dev, file_priv);
1344
1345         if (!dev_priv->cp_running)
1346                 return 0;
1347
1348         /* Flush any pending CP commands.  This ensures any outstanding
1349          * commands are exectuted by the engine before we turn it off.
1350          */
1351         if (stop->flush) {
1352                 radeon_do_cp_flush(dev_priv);
1353         }
1354
1355         /* If we fail to make the engine go idle, we return an error
1356          * code so that the DRM ioctl wrapper can try again.
1357          */
1358         if (stop->idle) {
1359                 ret = radeon_do_cp_idle(dev_priv);
1360                 if (ret)
1361                         return ret;
1362         }
1363
1364         /* Finally, we can turn off the CP.  If the engine isn't idle,
1365          * we will get some dropped triangles as they won't be fully
1366          * rendered before the CP is shut down.
1367          */
1368         radeon_do_cp_stop(dev_priv);
1369
1370         /* Reset the engine */
1371         radeon_do_engine_reset(dev);
1372
1373         return 0;
1374 }
1375
1376 void radeon_do_release(struct drm_device * dev)
1377 {
1378         drm_radeon_private_t *dev_priv = dev->dev_private;
1379         int i, ret;
1380
1381         if (dev_priv) {
1382                 if (dev_priv->cp_running) {
1383                         /* Stop the cp */
1384                         while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1385                                 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1386 #ifdef __linux__
1387                                 schedule();
1388 #else
1389 #if defined(__FreeBSD__) && __FreeBSD_version > 500000
1390                                 mtx_sleep(&ret, &dev->dev_lock, PZERO, "rdnrel",
1391                                        1);
1392 #else
1393                                 tsleep(&ret, PZERO, "rdnrel", 1);
1394 #endif
1395 #endif
1396                         }
1397                         radeon_do_cp_stop(dev_priv);
1398                         radeon_do_engine_reset(dev);
1399                 }
1400
1401                 /* Disable *all* interrupts */
1402                 if (dev_priv->mmio)     /* remove this after permanent addmaps */
1403                         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1404
1405                 if (dev_priv->mmio) {   /* remove all surfaces */
1406                         for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1407                                 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1408                                 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1409                                              16 * i, 0);
1410                                 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1411                                              16 * i, 0);
1412                         }
1413                 }
1414
1415                 /* Free memory heap structures */
1416                 radeon_mem_takedown(&(dev_priv->gart_heap));
1417                 radeon_mem_takedown(&(dev_priv->fb_heap));
1418
1419                 /* deallocate kernel resources */
1420                 radeon_do_cleanup_cp(dev);
1421         }
1422 }
1423
1424 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1425  */
1426 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1427 {
1428         drm_radeon_private_t *dev_priv = dev->dev_private;
1429         DRM_DEBUG("\n");
1430
1431         LOCK_TEST_WITH_RETURN(dev, file_priv);
1432
1433         if (!dev_priv) {
1434                 DRM_DEBUG("called before init done\n");
1435                 return -EINVAL;
1436         }
1437
1438         radeon_do_cp_reset(dev_priv);
1439
1440         /* The CP is no longer running after an engine reset */
1441         dev_priv->cp_running = 0;
1442
1443         return 0;
1444 }
1445
1446 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1447 {
1448         drm_radeon_private_t *dev_priv = dev->dev_private;
1449         DRM_DEBUG("\n");
1450
1451         LOCK_TEST_WITH_RETURN(dev, file_priv);
1452
1453         return radeon_do_cp_idle(dev_priv);
1454 }
1455
1456 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1457  */
1458 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1459 {
1460
1461         return radeon_do_resume_cp(dev);
1462 }
1463
1464 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1465 {
1466         DRM_DEBUG("\n");
1467
1468         LOCK_TEST_WITH_RETURN(dev, file_priv);
1469
1470         return radeon_do_engine_reset(dev);
1471 }
1472
1473 /* ================================================================
1474  * Fullscreen mode
1475  */
1476
1477 /* KW: Deprecated to say the least:
1478  */
1479 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1480 {
1481         return 0;
1482 }
1483
1484 /* ================================================================
1485  * Freelist management
1486  */
1487
1488 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1489  *   bufs until freelist code is used.  Note this hides a problem with
1490  *   the scratch register * (used to keep track of last buffer
1491  *   completed) being written to before * the last buffer has actually
1492  *   completed rendering.
1493  *
1494  * KW:  It's also a good way to find free buffers quickly.
1495  *
1496  * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1497  * sleep.  However, bugs in older versions of radeon_accel.c mean that
1498  * we essentially have to do this, else old clients will break.
1499  *
1500  * However, it does leave open a potential deadlock where all the
1501  * buffers are held by other clients, which can't release them because
1502  * they can't get the lock.
1503  */
1504
1505 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1506 {
1507         struct drm_device_dma *dma = dev->dma;
1508         drm_radeon_private_t *dev_priv = dev->dev_private;
1509         drm_radeon_buf_priv_t *buf_priv;
1510         struct drm_buf *buf;
1511         int i, t;
1512         int start;
1513
1514         if (++dev_priv->last_buf >= dma->buf_count)
1515                 dev_priv->last_buf = 0;
1516
1517         start = dev_priv->last_buf;
1518
1519         for (t = 0; t < dev_priv->usec_timeout; t++) {
1520                 u32 done_age = GET_SCRATCH(1);
1521                 DRM_DEBUG("done_age = %d\n", done_age);
1522                 for (i = start; i < dma->buf_count; i++) {
1523                         buf = dma->buflist[i];
1524                         buf_priv = buf->dev_private;
1525                         if (buf->file_priv == NULL || (buf->pending &&
1526                                                        buf_priv->age <=
1527                                                        done_age)) {
1528                                 dev_priv->stats.requested_bufs++;
1529                                 buf->pending = 0;
1530                                 return buf;
1531                         }
1532                         start = 0;
1533                 }
1534
1535                 if (t) {
1536                         DRM_UDELAY(1);
1537                         dev_priv->stats.freelist_loops++;
1538                 }
1539         }
1540
1541         DRM_DEBUG("returning NULL!\n");
1542         return NULL;
1543 }
1544
1545 #if 0
1546 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1547 {
1548         struct drm_device_dma *dma = dev->dma;
1549         drm_radeon_private_t *dev_priv = dev->dev_private;
1550         drm_radeon_buf_priv_t *buf_priv;
1551         struct drm_buf *buf;
1552         int i, t;
1553         int start;
1554         u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1555
1556         if (++dev_priv->last_buf >= dma->buf_count)
1557                 dev_priv->last_buf = 0;
1558
1559         start = dev_priv->last_buf;
1560         dev_priv->stats.freelist_loops++;
1561
1562         for (t = 0; t < 2; t++) {
1563                 for (i = start; i < dma->buf_count; i++) {
1564                         buf = dma->buflist[i];
1565                         buf_priv = buf->dev_private;
1566                         if (buf->file_priv == 0 || (buf->pending &&
1567                                                     buf_priv->age <=
1568                                                     done_age)) {
1569                                 dev_priv->stats.requested_bufs++;
1570                                 buf->pending = 0;
1571                                 return buf;
1572                         }
1573                 }
1574                 start = 0;
1575         }
1576
1577         return NULL;
1578 }
1579 #endif
1580
1581 void radeon_freelist_reset(struct drm_device * dev)
1582 {
1583         struct drm_device_dma *dma = dev->dma;
1584         drm_radeon_private_t *dev_priv = dev->dev_private;
1585         int i;
1586
1587         dev_priv->last_buf = 0;
1588         for (i = 0; i < dma->buf_count; i++) {
1589                 struct drm_buf *buf = dma->buflist[i];
1590                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1591                 buf_priv->age = 0;
1592         }
1593 }
1594
1595 /* ================================================================
1596  * CP command submission
1597  */
1598
1599 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1600 {
1601         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1602         int i;
1603         u32 last_head = GET_RING_HEAD(dev_priv);
1604
1605         for (i = 0; i < dev_priv->usec_timeout; i++) {
1606                 u32 head = GET_RING_HEAD(dev_priv);
1607
1608                 ring->space = (head - ring->tail) * sizeof(u32);
1609                 if (ring->space <= 0)
1610                         ring->space += ring->size;
1611                 if (ring->space > n)
1612                         return 0;
1613
1614                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1615
1616                 if (head != last_head)
1617                         i = 0;
1618                 last_head = head;
1619
1620                 DRM_UDELAY(1);
1621         }
1622
1623         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1624 #if RADEON_FIFO_DEBUG
1625         radeon_status(dev_priv);
1626         DRM_ERROR("failed!\n");
1627 #endif
1628         return -EBUSY;
1629 }
1630
1631 static int radeon_cp_get_buffers(struct drm_device *dev,
1632                                  struct drm_file *file_priv,
1633                                  struct drm_dma * d)
1634 {
1635         int i;
1636         struct drm_buf *buf;
1637
1638         for (i = d->granted_count; i < d->request_count; i++) {
1639                 buf = radeon_freelist_get(dev);
1640                 if (!buf)
1641                         return -EBUSY;  /* NOTE: broken client */
1642
1643                 buf->file_priv = file_priv;
1644
1645                 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1646                                      sizeof(buf->idx)))
1647                         return -EFAULT;
1648                 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
1649                                      sizeof(buf->total)))
1650                         return -EFAULT;
1651
1652                 d->granted_count++;
1653         }
1654         return 0;
1655 }
1656
1657 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
1658 {
1659         struct drm_device_dma *dma = dev->dma;
1660         int ret = 0;
1661         struct drm_dma *d = data;
1662
1663         LOCK_TEST_WITH_RETURN(dev, file_priv);
1664
1665         /* Please don't send us buffers.
1666          */
1667         if (d->send_count != 0) {
1668                 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1669                           DRM_CURRENTPID, d->send_count);
1670                 return -EINVAL;
1671         }
1672
1673         /* We'll send you buffers.
1674          */
1675         if (d->request_count < 0 || d->request_count > dma->buf_count) {
1676                 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1677                           DRM_CURRENTPID, d->request_count, dma->buf_count);
1678                 return -EINVAL;
1679         }
1680
1681         d->granted_count = 0;
1682
1683         if (d->request_count) {
1684                 ret = radeon_cp_get_buffers(dev, file_priv, d);
1685         }
1686
1687         return ret;
1688 }
1689
1690 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
1691 {
1692         drm_radeon_private_t *dev_priv;
1693         int ret = 0;
1694
1695         dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
1696         if (dev_priv == NULL)
1697                 return -ENOMEM;
1698
1699         memset(dev_priv, 0, sizeof(drm_radeon_private_t));
1700         dev->dev_private = (void *)dev_priv;
1701         dev_priv->flags = flags;
1702
1703         switch (flags & RADEON_FAMILY_MASK) {
1704         case CHIP_R100:
1705         case CHIP_RV200:
1706         case CHIP_R200:
1707         case CHIP_R300:
1708         case CHIP_R350:
1709         case CHIP_R420:
1710         case CHIP_RV410:
1711         case CHIP_RV515:
1712         case CHIP_R520:
1713         case CHIP_RV570:
1714         case CHIP_R580:
1715                 dev_priv->flags |= RADEON_HAS_HIERZ;
1716                 break;
1717         default:
1718                 /* all other chips have no hierarchical z buffer */
1719                 break;
1720         }
1721
1722         dev_priv->chip_family = flags & RADEON_FAMILY_MASK;
1723         if (drm_device_is_agp(dev))
1724                 dev_priv->flags |= RADEON_IS_AGP;
1725         else if (drm_device_is_pcie(dev))
1726                 dev_priv->flags |= RADEON_IS_PCIE;
1727         else
1728                 dev_priv->flags |= RADEON_IS_PCI;
1729
1730         DRM_DEBUG("%s card detected\n",
1731                   ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
1732         return ret;
1733 }
1734
1735 /* Create mappings for registers and framebuffer so userland doesn't necessarily
1736  * have to find them.
1737  */
1738 int radeon_driver_firstopen(struct drm_device *dev)
1739 {
1740         int ret;
1741         drm_local_map_t *map;
1742         drm_radeon_private_t *dev_priv = dev->dev_private;
1743
1744         dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
1745
1746         ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
1747                          drm_get_resource_len(dev, 2), _DRM_REGISTERS,
1748                          _DRM_READ_ONLY, &dev_priv->mmio);
1749         if (ret != 0)
1750                 return ret;
1751
1752         dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
1753         ret = drm_addmap(dev, dev_priv->fb_aper_offset,
1754                          drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
1755                          _DRM_WRITE_COMBINING, &map);
1756         if (ret != 0)
1757                 return ret;
1758
1759         return 0;
1760 }
1761
1762 int radeon_driver_unload(struct drm_device *dev)
1763 {
1764         drm_radeon_private_t *dev_priv = dev->dev_private;
1765
1766         DRM_DEBUG("\n");
1767         drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
1768
1769         dev->dev_private = NULL;
1770         return 0;
1771 }