shared-core/radeon_cp.c

   1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
   2 /*
   3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   5  * Copyright 2007 Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25  * DEALINGS IN THE SOFTWARE.
  26  *
  27  * Authors:
  28  *    Kevin E. Martin <martin@valinux.com>
  29  *    Gareth Hughes <gareth@valinux.com>
  30  */
  31
  32 #include "drmP.h"
  33 #include "drm.h"
  34 #include "drm_sarea.h"
  35 #include "radeon_drm.h"
  36 #include "radeon_drv.h"
  37 #include "r300_reg.h"
  38
  39 #include "radeon_microcode.h"
  40 #define RADEON_FIFO_DEBUG       0
  41
  42 static int radeon_do_cleanup_cp(struct drm_device * dev);
  43
  44 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
  45 {
  46         u32 ret;
  47         RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
  48         ret = RADEON_READ(R520_MC_IND_DATA);
  49         RADEON_WRITE(R520_MC_IND_INDEX, 0);
  50         return ret;
  51 }
  52
  53 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
  54 {
  55         u32 ret;
  56         RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
  57         ret = RADEON_READ(RS480_NB_MC_DATA);
  58         RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
  59         return ret;
  60 }
  61
  62 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
  63 {
  64         u32 ret;
  65         RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
  66         ret = RADEON_READ(RS690_MC_DATA);
  67         RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
  68         return ret;
  69 }
  70
  71 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
  72 {
  73         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
  74             return RS690_READ_MCIND(dev_priv, addr);
  75         else
  76             return RS480_READ_MCIND(dev_priv, addr);
  77 }
  78
  79 u32 radeon_read_mc_reg(drm_radeon_private_t *dev_priv, int addr)
  80 {
  81         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
  82                 return IGP_READ_MCIND(dev_priv, addr);
  83         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515)
  84                 return R500_READ_MCIND(dev_priv, addr);
  85         return 0;
  86 }
  87
  88 void radeon_write_mc_reg(drm_radeon_private_t *dev_priv, u32 addr, u32 val)
  89 {
  90         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
  91                 IGP_WRITE_MCIND(addr, val);
  92         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515)
  93                 R500_WRITE_MCIND(addr, val);
  94 }
  95
  96 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
  97 {
  98
  99         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 100                 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
 101         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
 102                 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
 103         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 104                 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
 105         else
 106                 return RADEON_READ(RADEON_MC_FB_LOCATION);
 107 }
 108
 109 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
 110 {
 111         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 112                 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
 113         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
 114                 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
 115         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 116                 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
 117         else
 118                 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
 119 }
 120
 121 static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
 122 {
 123         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 124                 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
 125         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
 126                 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
 127         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 128                 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
 129         else
 130                 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
 131 }
 132
 133 static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
 134 {
 135         u32 agp_base_hi = upper_32_bits(agp_base);
 136         u32 agp_base_lo = agp_base & 0xffffffff;
 137
 138         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
 139                 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
 140                 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
 141         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
 142                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
 143                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
 144         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
 145                 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
 146                 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
 147         } else {
 148                 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_base_lo);
 149                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
 150                         RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
 151         }
 152 }
 153
 154
 155 void radeon_pll_errata_after_index(struct drm_radeon_private *dev_priv)
 156 {
 157         if (!(dev_priv->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS))
 158                 return;
 159
 160         (void)RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 161         (void)RADEON_READ(RADEON_CRTC_GEN_CNTL);
 162 }
 163
 164 void radeon_pll_errata_after_data(struct drm_radeon_private *dev_priv)
 165 {
 166         /* This workarounds is necessary on RV100, RS100 and RS200 chips
 167          * or the chip could hang on a subsequent access
 168          */
 169         if (dev_priv->pll_errata & CHIP_ERRATA_PLL_DELAY)
 170                 udelay(5000);
 171
 172         /* This function is required to workaround a hardware bug in some (all?)
 173          * revisions of the R300.  This workaround should be called after every
 174          * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
 175          * may not be correct.
 176          */
 177         if (dev_priv->pll_errata & CHIP_ERRATA_R300_CG) {
 178                 uint32_t save, tmp;
 179
 180                 save = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
 181                 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
 182                 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, tmp);
 183                 tmp = RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 184                 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, save);
 185         }
 186 }
 187
 188 u32 RADEON_READ_PLL(struct drm_radeon_private *dev_priv, int addr)
 189 {
 190         uint32_t data;
 191
 192         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x3f);
 193         radeon_pll_errata_after_index(dev_priv);
 194         data = RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 195         radeon_pll_errata_after_data(dev_priv);
 196         return data;
 197 }
 198
 199 void RADEON_WRITE_PLL(struct drm_radeon_private *dev_priv, int addr, uint32_t data)
 200 {
 201         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, ((addr & 0x3f) | RADEON_PLL_WR_EN));
 202         radeon_pll_errata_after_index(dev_priv);
 203         RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, data);
 204         radeon_pll_errata_after_data(dev_priv);
 205 }
 206
 207 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
 208 {
 209         RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
 210         return RADEON_READ(RADEON_PCIE_DATA);
 211 }
 212
 213 /* ATOM accessor methods */
 214 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
 215 {
 216         uint32_t ret = radeon_read_mc_reg(info->dev->dev_private, reg);
 217
 218         //      DRM_DEBUG("(%x) = %x\n", reg, ret);
 219         return ret;
 220 }
 221
 222 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
 223 {
 224   //    DRM_DEBUG("(%x,  %x)\n", reg, val);
 225         radeon_write_mc_reg(info->dev->dev_private, reg, val);
 226 }
 227
 228 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
 229 {
 230         drm_radeon_private_t *dev_priv = info->dev->dev_private;
 231
 232         //      DRM_DEBUG("(%x,  %x)\n", reg*4, val);
 233         RADEON_WRITE(reg*4, val);
 234 }
 235
 236 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
 237 {
 238         uint32_t ret;
 239         drm_radeon_private_t *dev_priv = info->dev->dev_private;
 240
 241         ret = RADEON_READ(reg*4);
 242         //      DRM_DEBUG("(%x) = %x\n", reg*4, ret);
 243         return ret;
 244 }
 245
 246 #if RADEON_FIFO_DEBUG
 247 static void radeon_status(drm_radeon_private_t * dev_priv)
 248 {
 249         printk("%s:\n", __FUNCTION__);
 250         printk("RBBM_STATUS = 0x%08x\n",
 251                (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
 252         printk("CP_RB_RTPR = 0x%08x\n",
 253                (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
 254         printk("CP_RB_WTPR = 0x%08x\n",
 255                (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
 256         printk("AIC_CNTL = 0x%08x\n",
 257                (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
 258         printk("AIC_STAT = 0x%08x\n",
 259                (unsigned int)RADEON_READ(RADEON_AIC_STAT));
 260         printk("AIC_PT_BASE = 0x%08x\n",
 261                (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
 262         printk("TLB_ADDR = 0x%08x\n",
 263                (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
 264         printk("TLB_DATA = 0x%08x\n",
 265                (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
 266 }
 267 #endif
 268
 269 /* ================================================================
 270  * Engine, FIFO control
 271  */
 272
 273 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
 274 {
 275         u32 tmp;
 276         int i;
 277
 278         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 279
 280         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
 281                 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
 282                 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
 283                 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
 284
 285                 for (i = 0; i < dev_priv->usec_timeout; i++) {
 286                         if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
 287                               & RADEON_RB3D_DC_BUSY)) {
 288                                 return 0;
 289                         }
 290                         DRM_UDELAY(1);
 291                 }
 292         } else {
 293                 /* 3D */
 294                 tmp = RADEON_READ(R300_RB3D_DSTCACHE_CTLSTAT);
 295                 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
 296                 RADEON_WRITE(R300_RB3D_DSTCACHE_CTLSTAT, tmp);
 297
 298                 /* 2D */
 299                 tmp = RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT);
 300                 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
 301                 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
 302
 303                 for (i = 0; i < dev_priv->usec_timeout; i++) {
 304                         if (!(RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT)
 305                           & RADEON_RB3D_DC_BUSY)) {
 306                                 return 0;
 307                         }
 308                         DRM_UDELAY(1);
 309                 }
 310         }
 311
 312 #if RADEON_FIFO_DEBUG
 313         DRM_ERROR("failed!\n");
 314         radeon_status(dev_priv);
 315 #endif
 316         return -EBUSY;
 317 }
 318
 319 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
 320 {
 321         int i;
 322
 323         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 324
 325         for (i = 0; i < dev_priv->usec_timeout; i++) {
 326                 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
 327                              & RADEON_RBBM_FIFOCNT_MASK);
 328                 if (slots >= entries)
 329                         return 0;
 330                 DRM_UDELAY(1);
 331         }
 332
 333 #if RADEON_FIFO_DEBUG
 334         DRM_ERROR("failed!\n");
 335         radeon_status(dev_priv);
 336 #endif
 337         return -EBUSY;
 338 }
 339
 340 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
 341 {
 342         int i, ret;
 343
 344         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 345
 346         ret = radeon_do_wait_for_fifo(dev_priv, 64);
 347         if (ret)
 348                 return ret;
 349
 350         for (i = 0; i < dev_priv->usec_timeout; i++) {
 351                 if (!(RADEON_READ(RADEON_RBBM_STATUS)
 352                       & RADEON_RBBM_ACTIVE)) {
 353                         radeon_do_pixcache_flush(dev_priv);
 354                         return 0;
 355                 }
 356                 DRM_UDELAY(1);
 357         }
 358
 359 #if RADEON_FIFO_DEBUG
 360         DRM_ERROR("failed!\n");
 361         radeon_status(dev_priv);
 362 #endif
 363         return -EBUSY;
 364 }
 365
 366 static void radeon_init_pipes(drm_radeon_private_t * dev_priv)
 367 {
 368         uint32_t gb_tile_config, gb_pipe_sel = 0;
 369
 370         /* RS4xx/RS6xx/R4xx/R5xx */
 371         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
 372                 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
 373                 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
 374         } else {
 375                 /* R3xx */
 376                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
 377                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
 378                         dev_priv->num_gb_pipes = 2;
 379                 } else {
 380                         /* R3Vxx */
 381                         dev_priv->num_gb_pipes = 1;
 382                 }
 383         }
 384         DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
 385
 386         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
 387
 388         switch(dev_priv->num_gb_pipes) {
 389         case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
 390         case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
 391         case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
 392         default:
 393         case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
 394         }
 395
 396         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
 397                 RADEON_WRITE_PLL(dev_priv, R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
 398                 RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
 399         }
 400         RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
 401         radeon_do_wait_for_idle(dev_priv);
 402         RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
 403         RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
 404                                                R300_DC_AUTOFLUSH_ENABLE |
 405                                                R300_DC_DC_DISABLE_IGNORE_PE));
 406
 407
 408 }
 409
 410 /* ================================================================
 411  * CP control, initialization
 412  */
 413
 414 /* Load the microcode for the CP */
 415 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
 416 {
 417         int i;
 418         DRM_DEBUG("\n");
 419
 420         radeon_do_wait_for_idle(dev_priv);
 421
 422         RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
 423
 424         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
 425             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
 426             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
 427             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
 428             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
 429                 DRM_INFO("Loading R100 Microcode\n");
 430                 for (i = 0; i < 256; i++) {
 431                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 432                                      R100_cp_microcode[i][1]);
 433                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 434                                      R100_cp_microcode[i][0]);
 435                 }
 436         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
 437                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
 438                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
 439                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
 440                 DRM_INFO("Loading R200 Microcode\n");
 441                 for (i = 0; i < 256; i++) {
 442                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 443                                      R200_cp_microcode[i][1]);
 444                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 445                                      R200_cp_microcode[i][0]);
 446                 }
 447         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
 448                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
 449                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
 450                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
 451                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 452                 DRM_INFO("Loading R300 Microcode\n");
 453                 for (i = 0; i < 256; i++) {
 454                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 455                                      R300_cp_microcode[i][1]);
 456                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 457                                      R300_cp_microcode[i][0]);
 458                 }
 459         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
 460                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
 461                 DRM_INFO("Loading R400 Microcode\n");
 462                 for (i = 0; i < 256; i++) {
 463                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 464                                      R420_cp_microcode[i][1]);
 465                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 466                                      R420_cp_microcode[i][0]);
 467                 }
 468         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
 469                 DRM_INFO("Loading RS690 Microcode\n");
 470                 for (i = 0; i < 256; i++) {
 471                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 472                                      RS690_cp_microcode[i][1]);
 473                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 474                                      RS690_cp_microcode[i][0]);
 475                 }
 476         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
 477                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
 478                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
 479                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
 480                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
 481                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
 482                 DRM_INFO("Loading R500 Microcode\n");
 483                 for (i = 0; i < 256; i++) {
 484                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 485                                      R520_cp_microcode[i][1]);
 486                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 487                                      R520_cp_microcode[i][0]);
 488                 }
 489         }
 490 }
 491
 492 /* Flush any pending commands to the CP.  This should only be used just
 493  * prior to a wait for idle, as it informs the engine that the command
 494  * stream is ending.
 495  */
 496 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
 497 {
 498         DRM_DEBUG("\n");
 499 #if 0
 500         u32 tmp;
 501
 502         tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
 503         RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
 504 #endif
 505 }
 506
 507 /* Wait for the CP to go idle.
 508  */
 509 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
 510 {
 511         RING_LOCALS;
 512         DRM_DEBUG("\n");
 513
 514         BEGIN_RING(6);
 515
 516         RADEON_PURGE_CACHE();
 517         RADEON_PURGE_ZCACHE();
 518         RADEON_WAIT_UNTIL_IDLE();
 519
 520         ADVANCE_RING();
 521         COMMIT_RING();
 522
 523         return radeon_do_wait_for_idle(dev_priv);
 524 }
 525
 526 /* Start the Command Processor.
 527  */
 528 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
 529 {
 530         RING_LOCALS;
 531         DRM_DEBUG("\n");
 532
 533         radeon_do_wait_for_idle(dev_priv);
 534
 535         RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
 536
 537         dev_priv->cp_running = 1;
 538
 539         BEGIN_RING(6);
 540
 541         RADEON_PURGE_CACHE();
 542         RADEON_PURGE_ZCACHE();
 543         RADEON_WAIT_UNTIL_IDLE();
 544
 545         ADVANCE_RING();
 546         COMMIT_RING();
 547 }
 548
 549 /* Reset the Command Processor.  This will not flush any pending
 550  * commands, so you must wait for the CP command stream to complete
 551  * before calling this routine.
 552  */
 553 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
 554 {
 555         u32 cur_read_ptr;
 556         DRM_DEBUG("\n");
 557
 558         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 559         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 560         SET_RING_HEAD(dev_priv, cur_read_ptr);
 561         dev_priv->ring.tail = cur_read_ptr;
 562 }
 563
 564 /* Stop the Command Processor.  This will not flush any pending
 565  * commands, so you must flush the command stream and wait for the CP
 566  * to go idle before calling this routine.
 567  */
 568 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
 569 {
 570         DRM_DEBUG("\n");
 571
 572         RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
 573
 574         dev_priv->cp_running = 0;
 575 }
 576
 577 /* Reset the engine.  This will stop the CP if it is running.
 578  */
 579 static int radeon_do_engine_reset(struct drm_device * dev)
 580 {
 581         drm_radeon_private_t *dev_priv = dev->dev_private;
 582         u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
 583         DRM_DEBUG("\n");
 584
 585         radeon_do_pixcache_flush(dev_priv);
 586
 587         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
 588                 /* may need something similar for newer chips */
 589                 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
 590                 mclk_cntl = RADEON_READ_PLL(dev_priv, RADEON_MCLK_CNTL);
 591
 592                 RADEON_WRITE_PLL(dev_priv, RADEON_MCLK_CNTL, (mclk_cntl |
 593                                                               RADEON_FORCEON_MCLKA |
 594                                                               RADEON_FORCEON_MCLKB |
 595                                                               RADEON_FORCEON_YCLKA |
 596                                                               RADEON_FORCEON_YCLKB |
 597                                                               RADEON_FORCEON_MC |
 598                                                               RADEON_FORCEON_AIC));
 599         }
 600
 601         rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
 602
 603         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
 604                                               RADEON_SOFT_RESET_CP |
 605                                               RADEON_SOFT_RESET_HI |
 606                                               RADEON_SOFT_RESET_SE |
 607                                               RADEON_SOFT_RESET_RE |
 608                                               RADEON_SOFT_RESET_PP |
 609                                               RADEON_SOFT_RESET_E2 |
 610                                               RADEON_SOFT_RESET_RB));
 611         RADEON_READ(RADEON_RBBM_SOFT_RESET);
 612         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
 613                                               ~(RADEON_SOFT_RESET_CP |
 614                                                 RADEON_SOFT_RESET_HI |
 615                                                 RADEON_SOFT_RESET_SE |
 616                                                 RADEON_SOFT_RESET_RE |
 617                                                 RADEON_SOFT_RESET_PP |
 618                                                 RADEON_SOFT_RESET_E2 |
 619                                                 RADEON_SOFT_RESET_RB)));
 620         RADEON_READ(RADEON_RBBM_SOFT_RESET);
 621
 622         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
 623                 RADEON_WRITE_PLL(dev_priv, RADEON_MCLK_CNTL, mclk_cntl);
 624                 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
 625                 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
 626         }
 627
 628         /* setup the raster pipes */
 629         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
 630             radeon_init_pipes(dev_priv);
 631
 632         /* Reset the CP ring */
 633         radeon_do_cp_reset(dev_priv);
 634
 635         /* The CP is no longer running after an engine reset */
 636         dev_priv->cp_running = 0;
 637
 638         /* Reset any pending vertex, indirect buffers */
 639         if (dev->dma)
 640                 radeon_freelist_reset(dev);
 641
 642         return 0;
 643 }
 644
 645 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
 646                                        drm_radeon_private_t * dev_priv)
 647 {
 648         u32 ring_start, cur_read_ptr;
 649         u32 tmp;
 650
 651         /* Initialize the memory controller. With new memory map, the fb location
 652          * is not changed, it should have been properly initialized already. Part
 653          * of the problem is that the code below is bogus, assuming the GART is
 654          * always appended to the fb which is not necessarily the case
 655          */
 656         if (!dev_priv->new_memmap)
 657                 radeon_write_fb_location(dev_priv,
 658                                          ((dev_priv->gart_vm_start - 1) & 0xffff0000)
 659                                          | (dev_priv->fb_location >> 16));
 660
 661         if (dev_priv->mm.ring.bo) {
 662                 ring_start = dev_priv->mm.ring.bo->offset +
 663                         dev_priv->gart_vm_start;
 664         } else
 665 #if __OS_HAS_AGP
 666         if (dev_priv->flags & RADEON_IS_AGP) {
 667                 radeon_write_agp_base(dev_priv, dev->agp->base);
 668
 669                 radeon_write_agp_location(dev_priv,
 670                              (((dev_priv->gart_vm_start - 1 +
 671                                 dev_priv->gart_size) & 0xffff0000) |
 672                               (dev_priv->gart_vm_start >> 16)));
 673
 674                 ring_start = (dev_priv->cp_ring->offset
 675                               - dev->agp->base
 676                               + dev_priv->gart_vm_start);
 677         } else
 678 #endif
 679                 ring_start = (dev_priv->cp_ring->offset
 680                               - (unsigned long)dev->sg->virtual
 681                               + dev_priv->gart_vm_start);
 682
 683         RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
 684
 685         /* Set the write pointer delay */
 686         RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
 687
 688         /* Initialize the ring buffer's read and write pointers */
 689         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 690         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 691         SET_RING_HEAD(dev_priv, cur_read_ptr);
 692         dev_priv->ring.tail = cur_read_ptr;
 693
 694
 695         if (dev_priv->mm.ring_read.bo) {
 696                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
 697                              dev_priv->mm.ring_read.bo->offset +
 698                              dev_priv->gart_vm_start);
 699         } else
 700 #if __OS_HAS_AGP
 701         if (dev_priv->flags & RADEON_IS_AGP) {
 702                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
 703                              dev_priv->ring_rptr->offset
 704                              - dev->agp->base + dev_priv->gart_vm_start);
 705         } else
 706 #endif
 707         {
 708                 struct drm_sg_mem *entry = dev->sg;
 709                 unsigned long tmp_ofs, page_ofs;
 710
 711                 tmp_ofs = dev_priv->ring_rptr->offset -
 712                                 (unsigned long)dev->sg->virtual;
 713                 page_ofs = tmp_ofs >> PAGE_SHIFT;
 714
 715                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
 716                 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
 717                           (unsigned long)entry->busaddr[page_ofs],
 718                           entry->handle + tmp_ofs);
 719         }
 720
 721         /* Set ring buffer size */
 722 #ifdef __BIG_ENDIAN
 723         RADEON_WRITE(RADEON_CP_RB_CNTL,
 724                      RADEON_BUF_SWAP_32BIT |
 725                      (dev_priv->ring.fetch_size_l2ow << 18) |
 726                      (dev_priv->ring.rptr_update_l2qw << 8) |
 727                      dev_priv->ring.size_l2qw);
 728 #else
 729         RADEON_WRITE(RADEON_CP_RB_CNTL,
 730                      (dev_priv->ring.fetch_size_l2ow << 18) |
 731                      (dev_priv->ring.rptr_update_l2qw << 8) |
 732                      dev_priv->ring.size_l2qw);
 733 #endif
 734
 735         /* Start with assuming that writeback doesn't work */
 736         dev_priv->writeback_works = 0;
 737
 738         /* Initialize the scratch register pointer.  This will cause
 739          * the scratch register values to be written out to memory
 740          * whenever they are updated.
 741          *
 742          * We simply put this behind the ring read pointer, this works
 743          * with PCI GART as well as (whatever kind of) AGP GART
 744          */
 745         RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
 746                      + RADEON_SCRATCH_REG_OFFSET);
 747
 748         if (dev_priv->mm.ring_read.bo)
 749                 dev_priv->scratch = ((__volatile__ u32 *)
 750                                      dev_priv->mm.ring_read.kmap.virtual +
 751                                      (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
 752         else
 753                 dev_priv->scratch = ((__volatile__ u32 *)
 754                                      dev_priv->ring_rptr->handle +
 755                                      (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
 756
 757         RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
 758
 759         /* Turn on bus mastering */
 760         tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 761         RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 762
 763         dev_priv->scratch[0] = 0;
 764         RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
 765
 766         dev_priv->scratch[1] = 0;
 767         RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
 768
 769         dev_priv->scratch[2] = 0;
 770         RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
 771
 772         radeon_do_wait_for_idle(dev_priv);
 773
 774         /* Sync everything up */
 775         if (dev_priv->chip_family > CHIP_RV280) {
 776         RADEON_WRITE(RADEON_ISYNC_CNTL,
 777                      (RADEON_ISYNC_ANY2D_IDLE3D |
 778                       RADEON_ISYNC_ANY3D_IDLE2D |
 779                       RADEON_ISYNC_WAIT_IDLEGUI |
 780                       RADEON_ISYNC_CPSCRATCH_IDLEGUI));
 781         } else {
 782         RADEON_WRITE(RADEON_ISYNC_CNTL,
 783                      (RADEON_ISYNC_ANY2D_IDLE3D |
 784                       RADEON_ISYNC_ANY3D_IDLE2D |
 785                       RADEON_ISYNC_WAIT_IDLEGUI));
 786         }
 787 }
 788
 789 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
 790 {
 791         u32 tmp;
 792         void *ring_read_ptr;
 793
 794         if (dev_priv->mm.ring_read.bo)
 795                 ring_read_ptr = dev_priv->mm.ring_read.kmap.virtual;
 796         else
 797                 ring_read_ptr = dev_priv->ring_rptr->handle;
 798
 799         /* Writeback doesn't seem to work everywhere, test it here and possibly
 800          * enable it if it appears to work
 801          */
 802         writel(0, ring_read_ptr + RADEON_SCRATCHOFF(1));
 803         RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
 804
 805         for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
 806                 if (readl(ring_read_ptr + RADEON_SCRATCHOFF(1)) ==
 807                     0xdeadbeef)
 808                         break;
 809                 DRM_UDELAY(1);
 810         }
 811
 812         if (tmp < dev_priv->usec_timeout) {
 813                 dev_priv->writeback_works = 1;
 814                 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
 815         } else {
 816                 dev_priv->writeback_works = 0;
 817                 DRM_INFO("writeback test failed\n");
 818         }
 819         if (radeon_no_wb == 1) {
 820                 dev_priv->writeback_works = 0;
 821                 DRM_INFO("writeback forced off\n");
 822         }
 823
 824         if (!dev_priv->writeback_works) {
 825                 /* Disable writeback to avoid unnecessary bus master transfers */
 826                 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) | RADEON_RB_NO_UPDATE);
 827                 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
 828         }
 829 }
 830
 831 /* Enable or disable IGP GART on the chip */
 832 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
 833 {
 834         u32 temp;
 835
 836         if (on) {
 837                 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
 838                          dev_priv->gart_vm_start,
 839                          (long)dev_priv->gart_info.bus_addr,
 840                          dev_priv->gart_size);
 841
 842                 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
 843
 844                 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
 845                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
 846                                                              RS690_BLOCK_GFX_D3_EN));
 847                 else
 848                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
 849
 850                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
 851                                                                RS480_VA_SIZE_32MB));
 852
 853                 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
 854                 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
 855                                                         RS480_TLB_ENABLE |
 856                                                         RS480_GTW_LAC_EN |
 857                                                         RS480_1LEVEL_GART));
 858
 859                 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
 860                 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
 861                 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
 862
 863                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
 864                 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
 865                                                       RS480_REQ_TYPE_SNOOP_DIS));
 866
 867                 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
 868                         IGP_WRITE_MCIND(RS690_MC_AGP_BASE,
 869                                         (unsigned int)dev_priv->gart_vm_start);
 870                         IGP_WRITE_MCIND(RS690_MC_AGP_BASE_2, 0);
 871                 } else {
 872                         RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start);
 873                         RADEON_WRITE(RS480_AGP_BASE_2, 0);
 874                 }
 875
 876                 dev_priv->gart_size = 32*1024*1024;
 877                 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
 878                         0xffff0000) | (dev_priv->gart_vm_start >> 16));
 879
 880                 radeon_write_agp_location(dev_priv, temp);
 881
 882                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
 883                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
 884                                                                RS480_VA_SIZE_32MB));
 885
 886                 do {
 887                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
 888                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
 889                                 break;
 890                         DRM_UDELAY(1);
 891                 } while(1);
 892
 893                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
 894                                 RS480_GART_CACHE_INVALIDATE);
 895
 896                 do {
 897                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
 898                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
 899                                 break;
 900                         DRM_UDELAY(1);
 901                 } while(1);
 902
 903                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
 904         } else {
 905                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
 906         }
 907 }
 908
 909 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
 910 {
 911         u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
 912         if (on) {
 913
 914                 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
 915                           dev_priv->gart_vm_start,
 916                           (long)dev_priv->gart_info.bus_addr,
 917                           dev_priv->gart_size);
 918                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
 919                                   dev_priv->gart_vm_start);
 920                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
 921                                   dev_priv->gart_info.bus_addr);
 922                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
 923                                   dev_priv->gart_vm_start);
 924                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
 925                                   dev_priv->gart_vm_start +
 926                                   dev_priv->gart_size - 1);
 927
 928                 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
 929
 930                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
 931                                   RADEON_PCIE_TX_GART_EN);
 932         } else {
 933                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
 934                                   tmp & ~RADEON_PCIE_TX_GART_EN);
 935         }
 936 }
 937
 938 /* Enable or disable PCI GART on the chip */
 939 void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
 940 {
 941         u32 tmp;
 942
 943         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 944             (dev_priv->flags & RADEON_IS_IGPGART)) {
 945                 radeon_set_igpgart(dev_priv, on);
 946                 return;
 947         }
 948
 949         if (dev_priv->flags & RADEON_IS_PCIE) {
 950                 radeon_set_pciegart(dev_priv, on);
 951                 return;
 952         }
 953
 954         tmp = RADEON_READ(RADEON_AIC_CNTL);
 955
 956         if (on) {
 957                 RADEON_WRITE(RADEON_AIC_CNTL,
 958                              tmp | RADEON_PCIGART_TRANSLATE_EN);
 959
 960                 /* set PCI GART page-table base address
 961                  */
 962                 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
 963
 964                 /* set address range for PCI address translate
 965                  */
 966                 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
 967                 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
 968                              + dev_priv->gart_size - 1);
 969
 970                 /* Turn off AGP aperture -- is this required for PCI GART?
 971                  */
 972                 radeon_write_agp_location(dev_priv, 0xffffffc0);
 973                 RADEON_WRITE(RADEON_AGP_COMMAND, 0);    /* clear AGP_COMMAND */
 974         } else {
 975                 RADEON_WRITE(RADEON_AIC_CNTL,
 976                              tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 977         }
 978 }
 979
 980 static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
 981                              struct drm_file *file_priv)
 982 {
 983         drm_radeon_private_t *dev_priv = dev->dev_private;
 984         struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
 985
 986         DRM_DEBUG("\n");
 987
 988         /* if we require new memory map but we don't have it fail */
 989         if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
 990                 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
 991                 radeon_do_cleanup_cp(dev);
 992                 return -EINVAL;
 993         }
 994
 995         if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP))
 996         {
 997                 DRM_DEBUG("Forcing AGP card to PCI mode\n");
 998                 dev_priv->flags &= ~RADEON_IS_AGP;
 999         }
1000         else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1001                  && !init->is_pci)
1002         {
1003                 DRM_DEBUG("Restoring AGP flag\n");
1004                 dev_priv->flags |= RADEON_IS_AGP;
1005         }
1006
1007         if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
1008                 DRM_ERROR("PCI GART memory not allocated!\n");
1009                 radeon_do_cleanup_cp(dev);
1010                 return -EINVAL;
1011         }
1012
1013         dev_priv->usec_timeout = init->usec_timeout;
1014         if (dev_priv->usec_timeout < 1 ||
1015             dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1016                 DRM_DEBUG("TIMEOUT problem!\n");
1017                 radeon_do_cleanup_cp(dev);
1018                 return -EINVAL;
1019         }
1020
1021         /* Enable vblank on CRTC1 for older X servers
1022          */
1023         dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1024
1025         dev_priv->do_boxes = 0;
1026         dev_priv->cp_mode = init->cp_mode;
1027
1028         /* We don't support anything other than bus-mastering ring mode,
1029          * but the ring can be in either AGP or PCI space for the ring
1030          * read pointer.
1031          */
1032         if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1033             (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1034                 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1035                 radeon_do_cleanup_cp(dev);
1036                 return -EINVAL;
1037         }
1038
1039         switch (init->fb_bpp) {
1040         case 16:
1041                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1042                 break;
1043         case 32:
1044         default:
1045                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1046                 break;
1047         }
1048         dev_priv->front_offset = init->front_offset;
1049         dev_priv->front_pitch = init->front_pitch;
1050         dev_priv->back_offset = init->back_offset;
1051         dev_priv->back_pitch = init->back_pitch;
1052
1053         switch (init->depth_bpp) {
1054         case 16:
1055                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1056                 break;
1057         case 32:
1058         default:
1059                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1060                 break;
1061         }
1062         dev_priv->depth_offset = init->depth_offset;
1063         dev_priv->depth_pitch = init->depth_pitch;
1064
1065         /* Hardware state for depth clears.  Remove this if/when we no
1066          * longer clear the depth buffer with a 3D rectangle.  Hard-code
1067          * all values to prevent unwanted 3D state from slipping through
1068          * and screwing with the clear operation.
1069          */
1070         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1071                                            (dev_priv->color_fmt << 10) |
1072                                            (dev_priv->chip_family < CHIP_R200 ? RADEON_ZBLOCK16 : 0));
1073
1074         dev_priv->depth_clear.rb3d_zstencilcntl =
1075             (dev_priv->depth_fmt |
1076              RADEON_Z_TEST_ALWAYS |
1077              RADEON_STENCIL_TEST_ALWAYS |
1078              RADEON_STENCIL_S_FAIL_REPLACE |
1079              RADEON_STENCIL_ZPASS_REPLACE |
1080              RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1081
1082         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1083                                          RADEON_BFACE_SOLID |
1084                                          RADEON_FFACE_SOLID |
1085                                          RADEON_FLAT_SHADE_VTX_LAST |
1086                                          RADEON_DIFFUSE_SHADE_FLAT |
1087                                          RADEON_ALPHA_SHADE_FLAT |
1088                                          RADEON_SPECULAR_SHADE_FLAT |
1089                                          RADEON_FOG_SHADE_FLAT |
1090                                          RADEON_VTX_PIX_CENTER_OGL |
1091                                          RADEON_ROUND_MODE_TRUNC |
1092                                          RADEON_ROUND_PREC_8TH_PIX);
1093
1094
1095         dev_priv->ring_offset = init->ring_offset;
1096         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1097         dev_priv->buffers_offset = init->buffers_offset;
1098         dev_priv->gart_textures_offset = init->gart_textures_offset;
1099
1100         master_priv->sarea = drm_getsarea(dev);
1101         if (!master_priv->sarea) {
1102                 DRM_ERROR("could not find sarea!\n");
1103                 radeon_do_cleanup_cp(dev);
1104                 return -EINVAL;
1105         }
1106
1107         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1108         if (!dev_priv->cp_ring) {
1109                 DRM_ERROR("could not find cp ring region!\n");
1110                 radeon_do_cleanup_cp(dev);
1111                 return -EINVAL;
1112         }
1113         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1114         if (!dev_priv->ring_rptr) {
1115                 DRM_ERROR("could not find ring read pointer!\n");
1116                 radeon_do_cleanup_cp(dev);
1117                 return -EINVAL;
1118         }
1119         dev->agp_buffer_token = init->buffers_offset;
1120         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1121         if (!dev->agp_buffer_map) {
1122                 DRM_ERROR("could not find dma buffer region!\n");
1123                 radeon_do_cleanup_cp(dev);
1124                 return -EINVAL;
1125         }
1126
1127         if (init->gart_textures_offset) {
1128                 dev_priv->gart_textures =
1129                     drm_core_findmap(dev, init->gart_textures_offset);
1130                 if (!dev_priv->gart_textures) {
1131                         DRM_ERROR("could not find GART texture region!\n");
1132                         radeon_do_cleanup_cp(dev);
1133                         return -EINVAL;
1134                 }
1135         }
1136
1137 #if __OS_HAS_AGP
1138         if (dev_priv->flags & RADEON_IS_AGP) {
1139                 drm_core_ioremap(dev_priv->cp_ring, dev);
1140                 drm_core_ioremap(dev_priv->ring_rptr, dev);
1141                 drm_core_ioremap(dev->agp_buffer_map, dev);
1142                 if (!dev_priv->cp_ring->handle ||
1143                     !dev_priv->ring_rptr->handle ||
1144                     !dev->agp_buffer_map->handle) {
1145                         DRM_ERROR("could not find ioremap agp regions!\n");
1146                         radeon_do_cleanup_cp(dev);
1147                         return -EINVAL;
1148                 }
1149         } else
1150 #endif
1151         {
1152                 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1153                 dev_priv->ring_rptr->handle =
1154                     (void *)dev_priv->ring_rptr->offset;
1155                 dev->agp_buffer_map->handle =
1156                     (void *)dev->agp_buffer_map->offset;
1157
1158                 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1159                           dev_priv->cp_ring->handle);
1160                 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1161                           dev_priv->ring_rptr->handle);
1162                 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1163                           dev->agp_buffer_map->handle);
1164         }
1165
1166         dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1167         dev_priv->fb_size =
1168                 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1169                 - dev_priv->fb_location;
1170
1171         dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1172                                         ((dev_priv->front_offset
1173                                           + dev_priv->fb_location) >> 10));
1174
1175         dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1176                                        ((dev_priv->back_offset
1177                                          + dev_priv->fb_location) >> 10));
1178
1179         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1180                                         ((dev_priv->depth_offset
1181                                           + dev_priv->fb_location) >> 10));
1182
1183         dev_priv->gart_size = init->gart_size;
1184
1185         /* New let's set the memory map ... */
1186         if (dev_priv->new_memmap) {
1187                 u32 base = 0;
1188
1189                 DRM_INFO("Setting GART location based on new memory map\n");
1190
1191                 /* If using AGP, try to locate the AGP aperture at the same
1192                  * location in the card and on the bus, though we have to
1193                  * align it down.
1194                  */
1195 #if __OS_HAS_AGP
1196                 if (dev_priv->flags & RADEON_IS_AGP) {
1197                         base = dev->agp->base;
1198                         /* Check if valid */
1199                         if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1200                             base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1201                                 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1202                                          dev->agp->base);
1203                                 base = 0;
1204                         }
1205                 }
1206 #endif
1207                 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1208                 if (base == 0) {
1209                         base = dev_priv->fb_location + dev_priv->fb_size;
1210                         if (base < dev_priv->fb_location ||
1211                             ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1212                                 base = dev_priv->fb_location
1213                                         - dev_priv->gart_size;
1214                 }
1215                 dev_priv->gart_vm_start = base & 0xffc00000u;
1216                 if (dev_priv->gart_vm_start != base)
1217                         DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1218                                  base, dev_priv->gart_vm_start);
1219         } else {
1220                 DRM_INFO("Setting GART location based on old memory map\n");
1221                 dev_priv->gart_vm_start = dev_priv->fb_location +
1222                         RADEON_READ(RADEON_CONFIG_APER_SIZE);
1223         }
1224
1225 #if __OS_HAS_AGP
1226         if (dev_priv->flags & RADEON_IS_AGP)
1227                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1228                                                  - dev->agp->base
1229                                                  + dev_priv->gart_vm_start);
1230         else
1231 #endif
1232                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1233                                         - (unsigned long)dev->sg->virtual
1234                                         + dev_priv->gart_vm_start);
1235
1236         DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1237         DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1238         DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1239                   dev_priv->gart_buffers_offset);
1240
1241         dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1242         dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1243                               + init->ring_size / sizeof(u32));
1244         dev_priv->ring.size = init->ring_size;
1245         dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1246
1247         dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1248         dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1249
1250         dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1251         dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1252
1253         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1254
1255         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1256
1257 #if __OS_HAS_AGP
1258         if (dev_priv->flags & RADEON_IS_AGP) {
1259                 /* Turn off PCI GART */
1260                 radeon_set_pcigart(dev_priv, 0);
1261         } else
1262 #endif
1263         {
1264                 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1265                 /* if we have an offset set from userspace */
1266                 if (dev_priv->pcigart_offset_set) {
1267
1268                         /* if it came from userspace - remap it */
1269                         if (dev_priv->pcigart_offset_set == 1) {
1270                                 dev_priv->gart_info.bus_addr =
1271                                         dev_priv->pcigart_offset + dev_priv->fb_location;
1272                                 dev_priv->gart_info.mapping.offset =
1273                                         dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1274                                 dev_priv->gart_info.mapping.size =
1275                                         dev_priv->gart_info.table_size;
1276
1277                                 /* this is done by the mm now */
1278                                 drm_core_ioremap(&dev_priv->gart_info.mapping, dev);
1279                                 dev_priv->gart_info.addr =
1280                                         dev_priv->gart_info.mapping.handle;
1281
1282                                 memset(dev_priv->gart_info.addr, 0, dev_priv->gart_info.table_size);
1283                                 if (dev_priv->flags & RADEON_IS_PCIE)
1284                                         dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1285                                 else
1286                                         dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1287                                 dev_priv->gart_info.gart_table_location =
1288                                         DRM_ATI_GART_FB;
1289
1290                                 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1291                                           dev_priv->gart_info.addr,
1292                                           dev_priv->pcigart_offset);
1293                         }
1294                 } else {
1295
1296                         if (dev_priv->flags & RADEON_IS_PCIE) {
1297                                 DRM_ERROR
1298                                     ("Cannot use PCI Express without GART in FB memory\n");
1299                                 radeon_do_cleanup_cp(dev);
1300                                 return -EINVAL;
1301                         }
1302                         if (dev_priv->flags & RADEON_IS_IGPGART)
1303                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1304                         else
1305                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1306                         dev_priv->gart_info.gart_table_location =
1307                             DRM_ATI_GART_MAIN;
1308                         dev_priv->gart_info.addr = NULL;
1309                         dev_priv->gart_info.bus_addr = 0;
1310
1311                 }
1312
1313                 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
1314                         DRM_ERROR("failed to init PCI GART!\n");
1315                         radeon_do_cleanup_cp(dev);
1316                         return -ENOMEM;
1317                 }
1318
1319                 /* Turn on PCI GART */
1320                 radeon_set_pcigart(dev_priv, 1);
1321         }
1322
1323         radeon_cp_load_microcode(dev_priv);
1324         radeon_cp_init_ring_buffer(dev, dev_priv);
1325
1326         dev_priv->last_buf = 0;
1327
1328         radeon_do_engine_reset(dev);
1329         radeon_test_writeback(dev_priv);
1330
1331         return 0;
1332 }
1333
1334 static int radeon_do_cleanup_cp(struct drm_device * dev)
1335 {
1336         drm_radeon_private_t *dev_priv = dev->dev_private;
1337         DRM_DEBUG("\n");
1338
1339         /* Make sure interrupts are disabled here because the uninstall ioctl
1340          * may not have been called from userspace and after dev_private
1341          * is freed, it's too late.
1342          */
1343         if (dev->irq_enabled)
1344                 drm_irq_uninstall(dev);
1345
1346 #if __OS_HAS_AGP
1347         if (dev_priv->flags & RADEON_IS_AGP) {
1348                 if (dev_priv->cp_ring != NULL) {
1349                         drm_core_ioremapfree(dev_priv->cp_ring, dev);
1350                         dev_priv->cp_ring = NULL;
1351                 }
1352                 if (dev_priv->ring_rptr != NULL) {
1353                         drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1354                         dev_priv->ring_rptr = NULL;
1355                 }
1356                 if (dev->agp_buffer_map != NULL) {
1357                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
1358                         dev->agp_buffer_map = NULL;
1359                 }
1360         } else
1361 #endif
1362         {
1363
1364                 if (dev_priv->gart_info.bus_addr) {
1365                         /* Turn off PCI GART */
1366                         radeon_set_pcigart(dev_priv, 0);
1367                         drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info);
1368                 }
1369
1370                 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1371                 {
1372                         if (dev_priv->pcigart_offset_set == 1) {
1373                                 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1374                                 dev_priv->gart_info.addr = NULL;
1375                                 dev_priv->pcigart_offset_set = 0;
1376                         }
1377                 }
1378         }
1379         /* only clear to the start of flags */
1380         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1381
1382         return 0;
1383 }
1384
1385 /* This code will reinit the Radeon CP hardware after a resume from disc.
1386  * AFAIK, it would be very difficult to pickle the state at suspend time, so
1387  * here we make sure that all Radeon hardware initialisation is re-done without
1388  * affecting running applications.
1389  *
1390  * Charl P. Botha <http://cpbotha.net>
1391  */
1392 static int radeon_do_resume_cp(struct drm_device * dev)
1393 {
1394         drm_radeon_private_t *dev_priv = dev->dev_private;
1395
1396         if (!dev_priv) {
1397                 DRM_ERROR("Called with no initialization\n");
1398                 return -EINVAL;
1399         }
1400
1401         DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1402
1403 #if __OS_HAS_AGP
1404         if (dev_priv->flags & RADEON_IS_AGP) {
1405                 /* Turn off PCI GART */
1406                 radeon_set_pcigart(dev_priv, 0);
1407         } else
1408 #endif
1409         {
1410                 /* Turn on PCI GART */
1411                 radeon_set_pcigart(dev_priv, 1);
1412         }
1413
1414         radeon_cp_load_microcode(dev_priv);
1415         radeon_cp_init_ring_buffer(dev, dev_priv);
1416
1417         radeon_do_engine_reset(dev);
1418
1419         DRM_DEBUG("radeon_do_resume_cp() complete\n");
1420
1421         return 0;
1422 }
1423
1424 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1425 {
1426         drm_radeon_init_t *init = data;
1427
1428         /* on a modesetting driver ignore this stuff */
1429         if (drm_core_check_feature(dev, DRIVER_MODESET))
1430                 return 0;
1431
1432         LOCK_TEST_WITH_RETURN(dev, file_priv);
1433
1434         if (init->func == RADEON_INIT_R300_CP)
1435                 r300_init_reg_flags(dev);
1436
1437         switch (init->func) {
1438         case RADEON_INIT_CP:
1439         case RADEON_INIT_R200_CP:
1440         case RADEON_INIT_R300_CP:
1441                 return radeon_do_init_cp(dev, init, file_priv);
1442         case RADEON_CLEANUP_CP:
1443                 return radeon_do_cleanup_cp(dev);
1444         }
1445
1446         return -EINVAL;
1447 }
1448
1449 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1450 {
1451         drm_radeon_private_t *dev_priv = dev->dev_private;
1452         DRM_DEBUG("\n");
1453
1454         if (drm_core_check_feature(dev, DRIVER_MODESET))
1455                 return 0;
1456
1457         LOCK_TEST_WITH_RETURN(dev, file_priv);
1458
1459         if (dev_priv->cp_running) {
1460                 DRM_DEBUG("while CP running\n");
1461                 return 0;
1462         }
1463         if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1464                 DRM_DEBUG("called with bogus CP mode (%d)\n",
1465                           dev_priv->cp_mode);
1466                 return 0;
1467         }
1468
1469         radeon_do_cp_start(dev_priv);
1470
1471         return 0;
1472 }
1473
1474 /* Stop the CP.  The engine must have been idled before calling this
1475  * routine.
1476  */
1477 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1478 {
1479         drm_radeon_private_t *dev_priv = dev->dev_private;
1480         drm_radeon_cp_stop_t *stop = data;
1481         int ret;
1482         DRM_DEBUG("\n");
1483
1484         if (drm_core_check_feature(dev, DRIVER_MODESET))
1485                 return 0;
1486
1487         LOCK_TEST_WITH_RETURN(dev, file_priv);
1488
1489         if (!dev_priv->cp_running)
1490                 return 0;
1491
1492         /* Flush any pending CP commands.  This ensures any outstanding
1493          * commands are exectuted by the engine before we turn it off.
1494          */
1495         if (stop->flush) {
1496                 radeon_do_cp_flush(dev_priv);
1497         }
1498
1499         /* If we fail to make the engine go idle, we return an error
1500          * code so that the DRM ioctl wrapper can try again.
1501          */
1502         if (stop->idle) {
1503                 ret = radeon_do_cp_idle(dev_priv);
1504                 if (ret)
1505                         return ret;
1506         }
1507
1508         /* Finally, we can turn off the CP.  If the engine isn't idle,
1509          * we will get some dropped triangles as they won't be fully
1510          * rendered before the CP is shut down.
1511          */
1512         radeon_do_cp_stop(dev_priv);
1513
1514         /* Reset the engine */
1515         radeon_do_engine_reset(dev);
1516
1517         return 0;
1518 }
1519
1520 void radeon_do_release(struct drm_device * dev)
1521 {
1522         drm_radeon_private_t *dev_priv = dev->dev_private;
1523         int i, ret;
1524
1525         if (drm_core_check_feature(dev, DRIVER_MODESET))
1526                 return;
1527
1528         if (dev_priv) {
1529                 if (dev_priv->cp_running) {
1530                         /* Stop the cp */
1531                         while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1532                                 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1533 #ifdef __linux__
1534                                 schedule();
1535 #else
1536 #if defined(__FreeBSD__) && __FreeBSD_version > 500000
1537                                 mtx_sleep(&ret, &dev->dev_lock, PZERO, "rdnrel",
1538                                        1);
1539 #else
1540                                 tsleep(&ret, PZERO, "rdnrel", 1);
1541 #endif
1542 #endif
1543                         }
1544                         radeon_do_cp_stop(dev_priv);
1545                         radeon_do_engine_reset(dev);
1546                 }
1547
1548                 /* Disable *all* interrupts */
1549                 if (dev_priv->mmio)     /* remove this after permanent addmaps */
1550                         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1551
1552                 if (dev_priv->mmio) {   /* remove all surfaces */
1553                         for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1554                                 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1555                                 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1556                                              16 * i, 0);
1557                                 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1558                                              16 * i, 0);
1559                         }
1560                 }
1561
1562                 /* Free memory heap structures */
1563                 radeon_mem_takedown(&(dev_priv->gart_heap));
1564                 radeon_mem_takedown(&(dev_priv->fb_heap));
1565
1566                 if (dev_priv->user_mm_enable) {
1567                         radeon_gem_mm_fini(dev);
1568                         dev_priv->user_mm_enable = false;
1569                 }
1570
1571                 /* deallocate kernel resources */
1572                 radeon_do_cleanup_cp(dev);
1573         }
1574 }
1575
1576 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1577  */
1578 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1579 {
1580         drm_radeon_private_t *dev_priv = dev->dev_private;
1581         DRM_DEBUG("\n");
1582
1583         if (drm_core_check_feature(dev, DRIVER_MODESET))
1584                 return 0;
1585
1586         LOCK_TEST_WITH_RETURN(dev, file_priv);
1587
1588         if (!dev_priv) {
1589                 DRM_DEBUG("called before init done\n");
1590                 return -EINVAL;
1591         }
1592
1593         radeon_do_cp_reset(dev_priv);
1594
1595         /* The CP is no longer running after an engine reset */
1596         dev_priv->cp_running = 0;
1597
1598         return 0;
1599 }
1600
1601 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1602 {
1603         drm_radeon_private_t *dev_priv = dev->dev_private;
1604         DRM_DEBUG("\n");
1605
1606
1607         if (!drm_core_check_feature(dev, DRIVER_MODESET))
1608                 LOCK_TEST_WITH_RETURN(dev, file_priv);
1609
1610         return radeon_do_cp_idle(dev_priv);
1611 }
1612
1613 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1614  */
1615 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1616 {
1617
1618         if (drm_core_check_feature(dev, DRIVER_MODESET))
1619                 return 0;
1620
1621         return radeon_do_resume_cp(dev);
1622 }
1623
1624 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1625 {
1626         DRM_DEBUG("\n");
1627
1628         if (drm_core_check_feature(dev, DRIVER_MODESET))
1629                 return 0;
1630
1631         LOCK_TEST_WITH_RETURN(dev, file_priv);
1632
1633         return radeon_do_engine_reset(dev);
1634 }
1635
1636 /* ================================================================
1637  * Fullscreen mode
1638  */
1639
1640 /* KW: Deprecated to say the least:
1641  */
1642 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1643 {
1644         return 0;
1645 }
1646
1647 /* ================================================================
1648  * Freelist management
1649  */
1650
1651 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1652  *   bufs until freelist code is used.  Note this hides a problem with
1653  *   the scratch register * (used to keep track of last buffer
1654  *   completed) being written to before * the last buffer has actually
1655  *   completed rendering.
1656  *
1657  * KW:  It's also a good way to find free buffers quickly.
1658  *
1659  * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1660  * sleep.  However, bugs in older versions of radeon_accel.c mean that
1661  * we essentially have to do this, else old clients will break.
1662  *
1663  * However, it does leave open a potential deadlock where all the
1664  * buffers are held by other clients, which can't release them because
1665  * they can't get the lock.
1666  */
1667
1668 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1669 {
1670         struct drm_device_dma *dma = dev->dma;
1671         drm_radeon_private_t *dev_priv = dev->dev_private;
1672         drm_radeon_buf_priv_t *buf_priv;
1673         struct drm_buf *buf;
1674         int i, t;
1675         int start;
1676
1677         if (++dev_priv->last_buf >= dma->buf_count)
1678                 dev_priv->last_buf = 0;
1679
1680         start = dev_priv->last_buf;
1681
1682         for (t = 0; t < dev_priv->usec_timeout; t++) {
1683                 u32 done_age = GET_SCRATCH(1);
1684                 DRM_DEBUG("done_age = %d\n", done_age);
1685                 for (i = start; i < dma->buf_count; i++) {
1686                         buf = dma->buflist[i];
1687                         buf_priv = buf->dev_private;
1688                         if (buf->file_priv == NULL || (buf->pending &&
1689                                                        buf_priv->age <=
1690                                                        done_age)) {
1691                                 dev_priv->stats.requested_bufs++;
1692                                 buf->pending = 0;
1693                                 return buf;
1694                         }
1695                         start = 0;
1696                 }
1697
1698                 if (t) {
1699                         DRM_UDELAY(1);
1700                         dev_priv->stats.freelist_loops++;
1701                 }
1702         }
1703
1704         DRM_DEBUG("returning NULL!\n");
1705         return NULL;
1706 }
1707
1708 #if 0
1709 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1710 {
1711         struct drm_device_dma *dma = dev->dma;
1712         drm_radeon_private_t *dev_priv = dev->dev_private;
1713         drm_radeon_buf_priv_t *buf_priv;
1714         struct drm_buf *buf;
1715         int i, t;
1716         int start;
1717         u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1718
1719         if (++dev_priv->last_buf >= dma->buf_count)
1720                 dev_priv->last_buf = 0;
1721
1722         start = dev_priv->last_buf;
1723         dev_priv->stats.freelist_loops++;
1724
1725         for (t = 0; t < 2; t++) {
1726                 for (i = start; i < dma->buf_count; i++) {
1727                         buf = dma->buflist[i];
1728                         buf_priv = buf->dev_private;
1729                         if (buf->file_priv == 0 || (buf->pending &&
1730                                                     buf_priv->age <=
1731                                                     done_age)) {
1732                                 dev_priv->stats.requested_bufs++;
1733                                 buf->pending = 0;
1734                                 return buf;
1735                         }
1736                 }
1737                 start = 0;
1738         }
1739
1740         return NULL;
1741 }
1742 #endif
1743
1744 void radeon_freelist_reset(struct drm_device * dev)
1745 {
1746         struct drm_device_dma *dma = dev->dma;
1747         drm_radeon_private_t *dev_priv = dev->dev_private;
1748         int i;
1749
1750         dev_priv->last_buf = 0;
1751         for (i = 0; i < dma->buf_count; i++) {
1752                 struct drm_buf *buf = dma->buflist[i];
1753                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1754                 buf_priv->age = 0;
1755         }
1756 }
1757
1758 /* ================================================================
1759  * CP command submission
1760  */
1761
1762 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1763 {
1764         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1765         int i;
1766         u32 last_head = GET_RING_HEAD(dev_priv);
1767
1768         for (i = 0; i < dev_priv->usec_timeout; i++) {
1769                 u32 head = GET_RING_HEAD(dev_priv);
1770
1771                 ring->space = (head - ring->tail) * sizeof(u32);
1772                 if (ring->space <= 0)
1773                         ring->space += ring->size;
1774                 if (ring->space > n)
1775                         return 0;
1776
1777                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1778
1779                 if (head != last_head)
1780                         i = 0;
1781                 last_head = head;
1782
1783                 DRM_UDELAY(1);
1784         }
1785
1786         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1787 #if RADEON_FIFO_DEBUG
1788         radeon_status(dev_priv);
1789         DRM_ERROR("failed!\n");
1790 #endif
1791         return -EBUSY;
1792 }
1793
1794 static int radeon_cp_get_buffers(struct drm_device *dev,
1795                                  struct drm_file *file_priv,
1796                                  struct drm_dma * d)
1797 {
1798         int i;
1799         struct drm_buf *buf;
1800
1801         for (i = d->granted_count; i < d->request_count; i++) {
1802                 buf = radeon_freelist_get(dev);
1803                 if (!buf)
1804                         return -EBUSY;  /* NOTE: broken client */
1805
1806                 buf->file_priv = file_priv;
1807
1808                 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1809                                      sizeof(buf->idx)))
1810                         return -EFAULT;
1811                 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
1812                                      sizeof(buf->total)))
1813                         return -EFAULT;
1814
1815                 d->granted_count++;
1816         }
1817         return 0;
1818 }
1819
1820 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
1821 {
1822         struct drm_device_dma *dma = dev->dma;
1823         int ret = 0;
1824         struct drm_dma *d = data;
1825
1826         LOCK_TEST_WITH_RETURN(dev, file_priv);
1827
1828         /* Please don't send us buffers.
1829          */
1830         if (d->send_count != 0) {
1831                 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1832                           DRM_CURRENTPID, d->send_count);
1833                 return -EINVAL;
1834         }
1835
1836         /* We'll send you buffers.
1837          */
1838         if (d->request_count < 0 || d->request_count > dma->buf_count) {
1839                 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1840                           DRM_CURRENTPID, d->request_count, dma->buf_count);
1841                 return -EINVAL;
1842         }
1843
1844         d->granted_count = 0;
1845
1846         if (d->request_count) {
1847                 ret = radeon_cp_get_buffers(dev, file_priv, d);
1848         }
1849
1850         return ret;
1851 }
1852
1853 static void radeon_get_vram_type(struct drm_device *dev)
1854 {
1855         struct drm_radeon_private *dev_priv = dev->dev_private;
1856         uint32_t tmp;
1857
1858         if (dev_priv->flags & RADEON_IS_IGP || (dev_priv->chip_family >= CHIP_R300))
1859                 dev_priv->is_ddr = true;
1860         else if (RADEON_READ(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
1861                 dev_priv->is_ddr = true;
1862         else
1863                 dev_priv->is_ddr = false;
1864
1865         if ((dev_priv->chip_family >= CHIP_R600) &&
1866             (dev_priv->chip_family <= CHIP_RV635)) {
1867                 int chansize;
1868
1869                 tmp = RADEON_READ(R600_RAMCFG);
1870                 if (tmp & R600_CHANSIZE_OVERRIDE)
1871                         chansize = 16;
1872                 else if (tmp & R600_CHANSIZE)
1873                         chansize = 64;
1874                 else
1875                         chansize = 32;
1876
1877                 if (dev_priv->chip_family == CHIP_R600)
1878                         dev_priv->ram_width = 8 * chansize;
1879                 else if (dev_priv->chip_family == CHIP_RV670)
1880                         dev_priv->ram_width = 4 * chansize;
1881                 else if ((dev_priv->chip_family == CHIP_RV610) ||
1882                          (dev_priv->chip_family == CHIP_RV620))
1883                         dev_priv->ram_width = chansize;
1884                 else if ((dev_priv->chip_family == CHIP_RV630) ||
1885                          (dev_priv->chip_family == CHIP_RV635))
1886                         dev_priv->ram_width = 2 * chansize;
1887         } else if (dev_priv->chip_family == CHIP_RV515) {
1888                 tmp = radeon_read_mc_reg(dev_priv, RV515_MC_CNTL);
1889                 tmp &= RV515_MEM_NUM_CHANNELS_MASK;
1890                 switch (tmp) {
1891                 case 0: dev_priv->ram_width = 64; break;
1892                 case 1: dev_priv->ram_width = 128; break;
1893                 default: dev_priv->ram_width = 128; break;
1894                 }
1895         } else if ((dev_priv->chip_family >= CHIP_R520) &&
1896                    (dev_priv->chip_family <= CHIP_RV570)) {
1897                 tmp = radeon_read_mc_reg(dev_priv, R520_MC_CNTL0);
1898                 switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) {
1899                 case 0: dev_priv->ram_width = 32; break;
1900                 case 1: dev_priv->ram_width = 64; break;
1901                 case 2: dev_priv->ram_width = 128; break;
1902                 case 3: dev_priv->ram_width = 256; break;
1903                 default: dev_priv->ram_width = 128; break;
1904                 }
1905         } else if ((dev_priv->chip_family == CHIP_RV100) ||
1906                    (dev_priv->chip_family == CHIP_RS100) ||
1907                    (dev_priv->chip_family == CHIP_RS200)) {
1908                 tmp = RADEON_READ(RADEON_MEM_CNTL);
1909                 if (tmp & RV100_HALF_MODE)
1910                         dev_priv->ram_width = 32;
1911                 else
1912                         dev_priv->ram_width = 64;
1913
1914                 if (dev_priv->flags & RADEON_SINGLE_CRTC) {
1915                         dev_priv->ram_width /= 4;
1916                         dev_priv->is_ddr = true;
1917                 }
1918         } else if (dev_priv->chip_family <= CHIP_RV280) {
1919                 tmp = RADEON_READ(RADEON_MEM_CNTL);
1920                 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK)
1921                         dev_priv->ram_width = 128;
1922                 else
1923                         dev_priv->ram_width = 64;
1924         } else {
1925                 /* newer IGPs */
1926                 dev_priv->ram_width = 128;
1927         }
1928         DRM_DEBUG("RAM width %d bits %cDR\n", dev_priv->ram_width, dev_priv->is_ddr ? 'D' : 'S');
1929 }
1930
1931 static void radeon_force_some_clocks(struct drm_device *dev)
1932 {
1933         struct drm_radeon_private *dev_priv = dev->dev_private;
1934         uint32_t tmp;
1935
1936         tmp = RADEON_READ_PLL(dev_priv, RADEON_SCLK_CNTL);
1937         tmp |= RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_VIP;
1938         RADEON_WRITE_PLL(dev_priv, RADEON_SCLK_CNTL, tmp);
1939 }
1940
1941 static void radeon_set_dynamic_clock(struct drm_device *dev, int mode)
1942 {
1943         struct drm_radeon_private *dev_priv = dev->dev_private;
1944         uint32_t tmp;
1945
1946         switch(mode) {
1947         case 0:
1948                 if (dev_priv->flags & RADEON_SINGLE_CRTC) {
1949                         tmp = RADEON_READ_PLL(dev_priv, RADEON_SCLK_CNTL);
1950                         tmp |= (RADEON_SCLK_FORCE_CP   | RADEON_SCLK_FORCE_HDP |
1951                                 RADEON_SCLK_FORCE_DISP1 | RADEON_SCLK_FORCE_TOP |
1952                                 RADEON_SCLK_FORCE_E2   | RADEON_SCLK_FORCE_SE  |
1953                                 RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_VIP |
1954                                 RADEON_SCLK_FORCE_RE   | RADEON_SCLK_FORCE_PB  |
1955                                 RADEON_SCLK_FORCE_TAM  | RADEON_SCLK_FORCE_TDM |
1956                                 RADEON_SCLK_FORCE_RB);
1957                         RADEON_WRITE_PLL(dev_priv, RADEON_SCLK_CNTL, tmp);
1958                 } else if (dev_priv->chip_family == CHIP_RV350) {
1959                         /* for RV350/M10, no delays are required. */
1960                         tmp = RADEON_READ_PLL(dev_priv, R300_SCLK_CNTL2);
1961                         tmp |= (R300_SCLK_FORCE_TCL |
1962                                 R300_SCLK_FORCE_GA |
1963                                 R300_SCLK_FORCE_CBA);
1964                         RADEON_WRITE_PLL(dev_priv, R300_SCLK_CNTL2, tmp);
1965
1966                         tmp = RADEON_READ_PLL(dev_priv, RADEON_SCLK_CNTL);
1967                         tmp &= ~(RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP      |
1968                                  RADEON_SCLK_FORCE_HDP   | RADEON_SCLK_FORCE_DISP1   |
1969                                  RADEON_SCLK_FORCE_TOP   | RADEON_SCLK_FORCE_E2      |
1970                                  R300_SCLK_FORCE_VAP     | RADEON_SCLK_FORCE_IDCT    |
1971                                  RADEON_SCLK_FORCE_VIP   | R300_SCLK_FORCE_SR        |
1972                                  R300_SCLK_FORCE_PX      | R300_SCLK_FORCE_TX        |
1973                                  R300_SCLK_FORCE_US      | RADEON_SCLK_FORCE_TV_SCLK |
1974                                  R300_SCLK_FORCE_SU      | RADEON_SCLK_FORCE_OV0);
1975                         tmp |=  RADEON_DYN_STOP_LAT_MASK;
1976                         RADEON_WRITE_PLL(dev_priv, RADEON_SCLK_CNTL, tmp);
1977
1978                         tmp = RADEON_READ_PLL(dev_priv, RADEON_SCLK_MORE_CNTL);
1979                         tmp &= ~RADEON_SCLK_MORE_FORCEON;
1980                         tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT;
1981                         RADEON_WRITE_PLL(dev_priv, RADEON_SCLK_MORE_CNTL, tmp);
1982
1983                         tmp = RADEON_READ_PLL(dev_priv, RADEON_VCLK_ECP_CNTL);
1984                         tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
1985                                 RADEON_PIXCLK_DAC_ALWAYS_ONb);
1986                         RADEON_WRITE_PLL(dev_priv, RADEON_VCLK_ECP_CNTL, tmp);
1987
1988                         tmp = RADEON_READ_PLL(dev_priv, RADEON_PIXCLKS_CNTL);
1989                         tmp |= (RADEON_PIX2CLK_ALWAYS_ONb         |
1990                                 RADEON_PIX2CLK_DAC_ALWAYS_ONb     |
1991                                 RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
1992                                 R300_DVOCLK_ALWAYS_ONb            |
1993                                 RADEON_PIXCLK_BLEND_ALWAYS_ONb    |
1994                                 RADEON_PIXCLK_GV_ALWAYS_ONb       |
1995                                 R300_PIXCLK_DVO_ALWAYS_ONb        |
1996                                 RADEON_PIXCLK_LVDS_ALWAYS_ONb     |
1997                                 RADEON_PIXCLK_TMDS_ALWAYS_ONb     |
1998                                 R300_PIXCLK_TRANS_ALWAYS_ONb      |
1999                                 R300_PIXCLK_TVO_ALWAYS_ONb        |
2000                                 R300_P2G2CLK_ALWAYS_ONb           |
2001                                 R300_P2G2CLK_ALWAYS_ONb);
2002                         RADEON_WRITE_PLL(dev_priv, RADEON_PIXCLKS_CNTL, tmp);
2003                 } else {
2004                         tmp = RADEON_READ_PLL(dev_priv, RADEON_SCLK_CNTL);
2005                         tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_E2);
2006                         tmp |= RADEON_SCLK_FORCE_SE;
2007
2008                         if ( dev_priv->flags & RADEON_SINGLE_CRTC ) {
2009                                 tmp |= ( RADEON_SCLK_FORCE_RB    |
2010                                          RADEON_SCLK_FORCE_TDM   |
2011                                          RADEON_SCLK_FORCE_TAM   |
2012                                          RADEON_SCLK_FORCE_PB    |
2013                                          RADEON_SCLK_FORCE_RE    |
2014                                          RADEON_SCLK_FORCE_VIP   |
2015                                          RADEON_SCLK_FORCE_IDCT  |
2016                                          RADEON_SCLK_FORCE_TOP   |
2017                                          RADEON_SCLK_FORCE_DISP1 |
2018                                          RADEON_SCLK_FORCE_DISP2 |
2019                                          RADEON_SCLK_FORCE_HDP    );
2020                         } else if ((dev_priv->chip_family == CHIP_R300) ||
2021                                    (dev_priv->chip_family == CHIP_R350)) {
2022                                 tmp |= ( RADEON_SCLK_FORCE_HDP   |
2023                                          RADEON_SCLK_FORCE_DISP1 |
2024                                          RADEON_SCLK_FORCE_DISP2 |
2025                                          RADEON_SCLK_FORCE_TOP   |
2026                                          RADEON_SCLK_FORCE_IDCT  |
2027                                          RADEON_SCLK_FORCE_VIP);
2028                         }
2029
2030                         RADEON_WRITE_PLL(dev_priv, RADEON_SCLK_CNTL, tmp);
2031
2032                         udelay(16000);
2033
2034                         if ((dev_priv->chip_family == CHIP_R300) ||
2035                             (dev_priv->chip_family == CHIP_R350)) {
2036                                 tmp = RADEON_READ_PLL(dev_priv, R300_SCLK_CNTL2);
2037                                 tmp |= ( R300_SCLK_FORCE_TCL |
2038                                          R300_SCLK_FORCE_GA  |
2039                                          R300_SCLK_FORCE_CBA);
2040                                 RADEON_WRITE_PLL(dev_priv, R300_SCLK_CNTL2, tmp);
2041                                 udelay(16000);
2042                         }
2043
2044                         if (dev_priv->flags & RADEON_IS_IGP) {
2045                                 tmp = RADEON_READ_PLL(dev_priv, RADEON_MCLK_CNTL);
2046                                 tmp &= ~(RADEON_FORCEON_MCLKA |
2047                                          RADEON_FORCEON_YCLKA);
2048                                 RADEON_WRITE_PLL(dev_priv, RADEON_MCLK_CNTL, tmp);
2049                                 udelay(16000);
2050                         }
2051
2052                         if ((dev_priv->chip_family == CHIP_RV200) ||
2053                             (dev_priv->chip_family == CHIP_RV250) ||
2054                             (dev_priv->chip_family == CHIP_RV280)) {
2055                                 tmp = RADEON_READ_PLL(dev_priv, RADEON_SCLK_MORE_CNTL);
2056                                 tmp |= RADEON_SCLK_MORE_FORCEON;
2057                                 RADEON_WRITE_PLL(dev_priv, RADEON_SCLK_MORE_CNTL, tmp);
2058                                 udelay(16000);
2059                         }
2060
2061                         tmp = RADEON_READ_PLL(dev_priv, RADEON_PIXCLKS_CNTL);
2062                         tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb         |
2063                                  RADEON_PIX2CLK_DAC_ALWAYS_ONb     |
2064                                  RADEON_PIXCLK_BLEND_ALWAYS_ONb    |
2065                                  RADEON_PIXCLK_GV_ALWAYS_ONb       |
2066                                  RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb |
2067                                  RADEON_PIXCLK_LVDS_ALWAYS_ONb     |
2068                                  RADEON_PIXCLK_TMDS_ALWAYS_ONb);
2069
2070                         RADEON_WRITE_PLL(dev_priv, RADEON_PIXCLKS_CNTL, tmp);
2071                         udelay(16000);
2072
2073                         tmp = RADEON_READ_PLL(dev_priv, RADEON_VCLK_ECP_CNTL);
2074                         tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb  |
2075                                  RADEON_PIXCLK_DAC_ALWAYS_ONb);
2076                         RADEON_WRITE_PLL(dev_priv, RADEON_VCLK_ECP_CNTL, tmp);
2077                 }
2078                 DRM_DEBUG("Dynamic Clock Scaling Disabled\n");
2079                 break;
2080         case 1:
2081                 if (dev_priv->flags & RADEON_SINGLE_CRTC) {
2082                         tmp = RADEON_READ_PLL(dev_priv, RADEON_SCLK_CNTL);
2083                         if ((RADEON_READ(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) >
2084                             RADEON_CFG_ATI_REV_A13) {
2085                                 tmp &= ~(RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_RB);
2086                         }
2087                         tmp &= ~(RADEON_SCLK_FORCE_HDP  | RADEON_SCLK_FORCE_DISP1 |
2088                                  RADEON_SCLK_FORCE_TOP  | RADEON_SCLK_FORCE_SE   |
2089                                  RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_RE   |
2090                                  RADEON_SCLK_FORCE_PB   | RADEON_SCLK_FORCE_TAM  |
2091                                  RADEON_SCLK_FORCE_TDM);
2092                         RADEON_WRITE_PLL(dev_priv, RADEON_SCLK_CNTL, tmp);
2093                 } else if ((dev_priv->chip_family == CHIP_R300) ||
2094                            (dev_priv->chip_family == CHIP_R350) ||
2095                            (dev_priv->chip_family == CHIP_RV350)) {
2096                         if (dev_priv->chip_family == CHIP_RV350) {
2097                                 tmp = RADEON_READ_PLL(dev_priv, R300_SCLK_CNTL2);
2098                                 tmp &= ~(R300_SCLK_FORCE_TCL |
2099                                          R300_SCLK_FORCE_GA  |
2100                                          R300_SCLK_FORCE_CBA);
2101                                 tmp |=  (R300_SCLK_TCL_MAX_DYN_STOP_LAT |
2102                                          R300_SCLK_GA_MAX_DYN_STOP_LAT  |
2103                                          R300_SCLK_CBA_MAX_DYN_STOP_LAT);
2104                                 RADEON_WRITE_PLL(dev_priv, R300_SCLK_CNTL2, tmp);
2105
2106                                 tmp = RADEON_READ_PLL(dev_priv, RADEON_SCLK_CNTL);
2107                                 tmp &= ~(RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP      |
2108                                          RADEON_SCLK_FORCE_HDP   | RADEON_SCLK_FORCE_DISP1   |
2109                                          RADEON_SCLK_FORCE_TOP   | RADEON_SCLK_FORCE_E2      |
2110                                          R300_SCLK_FORCE_VAP     | RADEON_SCLK_FORCE_IDCT    |
2111                                          RADEON_SCLK_FORCE_VIP   | R300_SCLK_FORCE_SR        |
2112                                          R300_SCLK_FORCE_PX      | R300_SCLK_FORCE_TX        |
2113                                          R300_SCLK_FORCE_US      | RADEON_SCLK_FORCE_TV_SCLK |
2114                                          R300_SCLK_FORCE_SU      | RADEON_SCLK_FORCE_OV0);
2115                                 tmp |=  RADEON_DYN_STOP_LAT_MASK;
2116                                 RADEON_WRITE_PLL(dev_priv, RADEON_SCLK_CNTL, tmp);
2117
2118                                 tmp = RADEON_READ_PLL(dev_priv, RADEON_SCLK_MORE_CNTL);
2119                                 tmp &= ~RADEON_SCLK_MORE_FORCEON;
2120                                 tmp |=  RADEON_SCLK_MORE_MAX_DYN_STOP_LAT;
2121                                 RADEON_WRITE_PLL(dev_priv, RADEON_SCLK_MORE_CNTL, tmp);
2122
2123                                 tmp = RADEON_READ_PLL(dev_priv, RADEON_VCLK_ECP_CNTL);
2124                                 tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
2125                                         RADEON_PIXCLK_DAC_ALWAYS_ONb);
2126                                 RADEON_WRITE_PLL(dev_priv, RADEON_VCLK_ECP_CNTL, tmp);
2127
2128                                 tmp = RADEON_READ_PLL(dev_priv, RADEON_PIXCLKS_CNTL);
2129                                 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb         |
2130                                         RADEON_PIX2CLK_DAC_ALWAYS_ONb     |
2131                                         RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
2132                                         R300_DVOCLK_ALWAYS_ONb            |
2133                                         RADEON_PIXCLK_BLEND_ALWAYS_ONb    |
2134                                         RADEON_PIXCLK_GV_ALWAYS_ONb       |
2135                                         R300_PIXCLK_DVO_ALWAYS_ONb        |
2136                                         RADEON_PIXCLK_LVDS_ALWAYS_ONb     |
2137                                         RADEON_PIXCLK_TMDS_ALWAYS_ONb     |
2138                                         R300_PIXCLK_TRANS_ALWAYS_ONb      |
2139                                         R300_PIXCLK_TVO_ALWAYS_ONb        |
2140                                         R300_P2G2CLK_ALWAYS_ONb           |
2141                                         R300_P2G2CLK_ALWAYS_ONb);
2142                                 RADEON_WRITE_PLL(dev_priv, RADEON_PIXCLKS_CNTL, tmp);
2143
2144                                 tmp = RADEON_READ_PLL(dev_priv, RADEON_MCLK_MISC);
2145                                 tmp |= (RADEON_MC_MCLK_DYN_ENABLE |
2146                                         RADEON_IO_MCLK_DYN_ENABLE);
2147                                 RADEON_WRITE_PLL(dev_priv, RADEON_MCLK_MISC, tmp);
2148
2149                                 tmp = RADEON_READ_PLL(dev_priv, RADEON_MCLK_CNTL);
2150                                 tmp |= (RADEON_FORCEON_MCLKA |
2151                                         RADEON_FORCEON_MCLKB);
2152
2153                                 tmp &= ~(RADEON_FORCEON_YCLKA  |
2154                                          RADEON_FORCEON_YCLKB  |
2155                                          RADEON_FORCEON_MC);
2156
2157                                 /* Some releases of vbios have set DISABLE_MC_MCLKA
2158                                    and DISABLE_MC_MCLKB bits in the vbios table.  Setting these
2159                                    bits will cause H/W hang when reading video memory with dynamic clocking
2160                                    enabled. */
2161                                 if ((tmp & R300_DISABLE_MC_MCLKA) &&
2162                                     (tmp & R300_DISABLE_MC_MCLKB)) {
2163                                         /* If both bits are set, then check the active channels */
2164                                         tmp = RADEON_READ_PLL(dev_priv, RADEON_MCLK_CNTL);
2165                                         if (dev_priv->ram_width == 64) {
2166                                                 if (RADEON_READ(RADEON_MEM_CNTL) & R300_MEM_USE_CD_CH_ONLY)
2167                                                         tmp &= ~R300_DISABLE_MC_MCLKB;
2168                                                 else
2169                                                         tmp &= ~R300_DISABLE_MC_MCLKA;
2170                                         } else {
2171                                                 tmp &= ~(R300_DISABLE_MC_MCLKA |
2172                                                          R300_DISABLE_MC_MCLKB);
2173                                         }
2174                                 }
2175
2176                                 RADEON_WRITE_PLL(dev_priv, RADEON_MCLK_CNTL, tmp);
2177                         } else {
2178                                 tmp = RADEON_READ_PLL(dev_priv, RADEON_SCLK_CNTL);
2179                                 tmp &= ~(R300_SCLK_FORCE_VAP);
2180                                 tmp |= RADEON_SCLK_FORCE_CP;
2181                                 RADEON_WRITE_PLL(dev_priv, RADEON_SCLK_CNTL, tmp);
2182                                 udelay(15000);
2183
2184                                 tmp = RADEON_READ_PLL(dev_priv, R300_SCLK_CNTL2);
2185                                 tmp &= ~(R300_SCLK_FORCE_TCL |
2186                                          R300_SCLK_FORCE_GA  |
2187                                          R300_SCLK_FORCE_CBA);
2188                                 RADEON_WRITE_PLL(dev_priv, R300_SCLK_CNTL2, tmp);
2189                         }
2190                 } else {
2191                         tmp = RADEON_READ_PLL(dev_priv, RADEON_CLK_PWRMGT_CNTL);
2192                         tmp &= ~(RADEON_ACTIVE_HILO_LAT_MASK     |
2193                                  RADEON_DISP_DYN_STOP_LAT_MASK   |
2194                                  RADEON_DYN_STOP_MODE_MASK);
2195
2196                         tmp |= (RADEON_ENGIN_DYNCLK_MODE |
2197                                 (0x01 << RADEON_ACTIVE_HILO_LAT_SHIFT));
2198                         RADEON_WRITE_PLL(dev_priv, RADEON_CLK_PWRMGT_CNTL, tmp);
2199                         udelay(15000);
2200
2201                         tmp = RADEON_READ_PLL(dev_priv, RADEON_CLK_PIN_CNTL);
2202                         tmp |= RADEON_SCLK_DYN_START_CNTL;
2203                         RADEON_WRITE_PLL(dev_priv, RADEON_CLK_PIN_CNTL, tmp);
2204                         udelay(15000);
2205
2206                         /* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200
2207                            to lockup randomly, leave them as set by BIOS.
2208                         */
2209                         tmp = RADEON_READ_PLL(dev_priv, RADEON_SCLK_CNTL);
2210                         /*tmp &= RADEON_SCLK_SRC_SEL_MASK;*/
2211                         tmp &= ~RADEON_SCLK_FORCEON_MASK;
2212
2213                         /*RAGE_6::A11 A12 A12N1 A13, RV250::A11 A12, R300*/
2214                         if (((dev_priv->chip_family == CHIP_RV250) &&
2215                              ((RADEON_READ(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) <
2216                               RADEON_CFG_ATI_REV_A13)) ||
2217                             ((dev_priv->chip_family == CHIP_RV100) &&
2218                              ((RADEON_READ(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) <=
2219                               RADEON_CFG_ATI_REV_A13))){
2220                                 tmp |= RADEON_SCLK_FORCE_CP;
2221                                 tmp |= RADEON_SCLK_FORCE_VIP;
2222                         }
2223
2224                         RADEON_WRITE_PLL(dev_priv, RADEON_SCLK_CNTL, tmp);
2225
2226                         if ((dev_priv->chip_family == CHIP_RV200) ||
2227                             (dev_priv->chip_family == CHIP_RV250) ||
2228                             (dev_priv->chip_family == CHIP_RV280)) {
2229                                 tmp = RADEON_READ_PLL(dev_priv, RADEON_SCLK_MORE_CNTL);
2230                                 tmp &= ~RADEON_SCLK_MORE_FORCEON;
2231
2232                                 /* RV200::A11 A12 RV250::A11 A12 */
2233                                 if (((dev_priv->chip_family == CHIP_RV200) ||
2234                                      (dev_priv->chip_family == CHIP_RV250)) &&
2235                                     ((RADEON_READ(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) <
2236                                      RADEON_CFG_ATI_REV_A13)) {
2237                                         tmp |= RADEON_SCLK_MORE_FORCEON;
2238                                 }
2239                                 RADEON_WRITE_PLL(dev_priv, RADEON_SCLK_MORE_CNTL, tmp);
2240                                 udelay(15000);
2241                         }
2242
2243                         /* RV200::A11 A12, RV250::A11 A12 */
2244                         if (((dev_priv->chip_family == CHIP_RV200) ||
2245                              (dev_priv->chip_family == CHIP_RV250)) &&
2246                             ((RADEON_READ(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) <
2247                              RADEON_CFG_ATI_REV_A13)) {
2248                                 tmp = RADEON_READ_PLL(dev_priv, RADEON_PLL_PWRMGT_CNTL);
2249                                 tmp |= RADEON_TCL_BYPASS_DISABLE;
2250                                 RADEON_WRITE_PLL(dev_priv, RADEON_PLL_PWRMGT_CNTL, tmp);
2251                         }
2252                         udelay(15000);
2253
2254                         /*enable dynamic mode for display clocks (PIXCLK and PIX2CLK)*/
2255                         tmp = RADEON_READ_PLL(dev_priv, RADEON_PIXCLKS_CNTL);
2256                         tmp |=  (RADEON_PIX2CLK_ALWAYS_ONb         |
2257                                  RADEON_PIX2CLK_DAC_ALWAYS_ONb     |
2258                                  RADEON_PIXCLK_BLEND_ALWAYS_ONb    |
2259                                  RADEON_PIXCLK_GV_ALWAYS_ONb       |
2260                                  RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb |
2261                                  RADEON_PIXCLK_LVDS_ALWAYS_ONb     |
2262                                  RADEON_PIXCLK_TMDS_ALWAYS_ONb);
2263
2264                         RADEON_WRITE_PLL(dev_priv, RADEON_PIXCLKS_CNTL, tmp);
2265                         udelay(15000);
2266
2267                         tmp = RADEON_READ_PLL(dev_priv, RADEON_VCLK_ECP_CNTL);
2268                         tmp |= (RADEON_PIXCLK_ALWAYS_ONb  |
2269                                 RADEON_PIXCLK_DAC_ALWAYS_ONb);
2270
2271                         RADEON_WRITE_PLL(dev_priv, RADEON_VCLK_ECP_CNTL, tmp);
2272                         udelay(15000);
2273                 }
2274                 DRM_DEBUG("Dynamic Clock Scaling Enabled\n");
2275                 break;
2276         default:
2277                 break;
2278         }
2279
2280 }
2281
2282 int radeon_modeset_cp_init(struct drm_device *dev)
2283 {
2284         drm_radeon_private_t *dev_priv = dev->dev_private;
2285         uint32_t tmp;
2286
2287         /* allocate a ring and ring rptr bits from GART space */
2288         /* these are allocated in GEM files */
2289
2290         dev_priv->usec_timeout = RADEON_DEFAULT_CP_TIMEOUT;
2291         dev_priv->ring.size = RADEON_DEFAULT_RING_SIZE;
2292         dev_priv->cp_mode = RADEON_CSQ_PRIBM_INDBM;
2293
2294         dev_priv->ring.start = (u32 *)(void *)(unsigned long)dev_priv->mm.ring.kmap.virtual;
2295         dev_priv->ring.end = (u32 *)(void *)(unsigned long)dev_priv->mm.ring.kmap.virtual +
2296                 dev_priv->ring.size / sizeof(u32);
2297         dev_priv->ring.size_l2qw = drm_order(dev_priv->ring.size / 8);
2298         dev_priv->ring.rptr_update = 4096;
2299         dev_priv->ring.rptr_update_l2qw = drm_order(4096 / 8);
2300         dev_priv->ring.fetch_size = 32;
2301         dev_priv->ring.fetch_size_l2ow = drm_order(32 / 16);
2302         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
2303         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
2304
2305         dev_priv->new_memmap = true;
2306
2307         r300_init_reg_flags(dev);
2308
2309         radeon_cp_load_microcode(dev_priv);
2310
2311         DRM_DEBUG("ring offset is %x %x\n", dev_priv->mm.ring.bo->offset, dev_priv->mm.ring_read.bo->offset);
2312
2313         radeon_cp_init_ring_buffer(dev, dev_priv);
2314
2315         /* need to enable BUS mastering in Buscntl */
2316         tmp = RADEON_READ(RADEON_BUS_CNTL);
2317         tmp &= ~RADEON_BUS_MASTER_DIS;
2318         RADEON_WRITE(RADEON_BUS_CNTL, tmp);
2319
2320         radeon_do_engine_reset(dev);
2321         radeon_test_writeback(dev_priv);
2322
2323         radeon_do_cp_start(dev_priv);
2324         return 0;
2325 }
2326
2327 static bool radeon_get_bios(struct drm_device *dev)
2328 {
2329         drm_radeon_private_t *dev_priv = dev->dev_private;
2330         u8 __iomem *bios;
2331         size_t size;
2332         uint16_t tmp;
2333
2334         bios = pci_map_rom(dev->pdev, &size);
2335         if (!bios)
2336                 return -1;
2337
2338         dev_priv->bios = kmalloc(size, GFP_KERNEL);
2339         if (!dev_priv->bios) {
2340                 pci_unmap_rom(dev->pdev, bios);
2341                 return -1;
2342         }
2343
2344         memcpy(dev_priv->bios, bios, size);
2345
2346         pci_unmap_rom(dev->pdev, bios);
2347
2348         if (dev_priv->bios[0] != 0x55 || dev_priv->bios[1] != 0xaa)
2349                 goto free_bios;
2350
2351         dev_priv->bios_header_start = radeon_bios16(dev_priv, 0x48);
2352
2353         if (!dev_priv->bios_header_start)
2354                 goto free_bios;
2355
2356         tmp = dev_priv->bios_header_start + 4;
2357
2358         if (!memcmp(dev_priv->bios + tmp, "ATOM", 4) ||
2359             !memcmp(dev_priv->bios + tmp, "MOTA", 4))
2360                 dev_priv->is_atom_bios = true;
2361         else
2362                 dev_priv->is_atom_bios = false;
2363
2364         DRM_DEBUG("%sBIOS detected\n", dev_priv->is_atom_bios ? "ATOM" : "COM");
2365         return true;
2366 free_bios:
2367         kfree(dev_priv->bios);
2368         dev_priv->bios = NULL;
2369         return false;
2370 }
2371
2372 int radeon_modeset_preinit(struct drm_device *dev)
2373 {
2374         drm_radeon_private_t *dev_priv = dev->dev_private;
2375         static struct card_info card;
2376         int ret;
2377
2378         card.dev = dev;
2379         card.reg_read = cail_reg_read;
2380         card.reg_write = cail_reg_write;
2381         card.mc_read = cail_mc_read;
2382         card.mc_write = cail_mc_write;
2383
2384         ret = radeon_get_bios(dev);
2385         if (!ret)
2386                 return -1;
2387
2388         if (dev_priv->is_atom_bios) {
2389                 dev_priv->mode_info.atom_context = atom_parse(&card, dev_priv->bios);
2390         }
2391         radeon_get_clock_info(dev);
2392         return 0;
2393 }
2394
2395
2396 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
2397 {
2398         drm_radeon_private_t *dev_priv;
2399         int ret = 0;
2400
2401         dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
2402         if (dev_priv == NULL)
2403                 return -ENOMEM;
2404
2405         memset(dev_priv, 0, sizeof(drm_radeon_private_t));
2406         dev->dev_private = (void *)dev_priv;
2407         dev_priv->flags = flags;
2408
2409         switch (flags & RADEON_FAMILY_MASK) {
2410         case CHIP_R100:
2411         case CHIP_RV200:
2412         case CHIP_R200:
2413         case CHIP_R300:
2414         case CHIP_R350:
2415         case CHIP_R420:
2416         case CHIP_RV410:
2417         case CHIP_RV515:
2418         case CHIP_R520:
2419         case CHIP_RV570:
2420         case CHIP_R580:
2421                 dev_priv->flags |= RADEON_HAS_HIERZ;
2422                 break;
2423         default:
2424                 /* all other chips have no hierarchical z buffer */
2425                 break;
2426         }
2427
2428         dev_priv->chip_family = flags & RADEON_FAMILY_MASK;
2429         if (drm_device_is_agp(dev))
2430                 dev_priv->flags |= RADEON_IS_AGP;
2431         else if (drm_device_is_pcie(dev))
2432                 dev_priv->flags |= RADEON_IS_PCIE;
2433         else
2434                 dev_priv->flags |= RADEON_IS_PCI;
2435
2436
2437
2438         DRM_DEBUG("%s card detected\n",
2439                   ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
2440
2441         ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
2442                          drm_get_resource_len(dev, 2), _DRM_REGISTERS,
2443                          _DRM_DRIVER | _DRM_READ_ONLY, &dev_priv->mmio);
2444         if (ret != 0)
2445                 return ret;
2446
2447         if (drm_core_check_feature(dev, DRIVER_MODESET))
2448                 radeon_modeset_preinit(dev);
2449
2450
2451         radeon_get_vram_type(dev);
2452
2453         dev_priv->pll_errata = 0;
2454
2455         if (dev_priv->chip_family == CHIP_R300 &&
2456             (RADEON_READ(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11)
2457                 dev_priv->pll_errata |= CHIP_ERRATA_R300_CG;
2458
2459         if (dev_priv->chip_family == CHIP_RV200 ||
2460             dev_priv->chip_family == CHIP_RS200)
2461                 dev_priv->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2462
2463
2464         if (dev_priv->chip_family == CHIP_RV100 ||
2465             dev_priv->chip_family == CHIP_RS100 ||
2466             dev_priv->chip_family == CHIP_RS200)
2467                 dev_priv->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2468
2469
2470         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2471                 if ((dev_priv->flags & RADEON_IS_MOBILITY) && !radeon_is_avivo(dev_priv)) {
2472                         radeon_set_dynamic_clock(dev, radeon_dynclks);
2473                 } else if (radeon_is_avivo(dev_priv)) {
2474                         if (radeon_dynclks) {
2475                                 radeon_atom_static_pwrmgt_setup(dev, 1);
2476                                 radeon_atom_dyn_clk_setup(dev, 1);
2477                         }
2478                 }
2479                 radeon_force_some_clocks(dev);
2480         }
2481
2482         /* init memory manager - start with all of VRAM and a 32MB GART aperture for now */
2483         dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
2484
2485         drm_bo_driver_init(dev);
2486
2487         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2488
2489                 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
2490                 dev_priv->fb_size =
2491                         ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
2492                         - dev_priv->fb_location;
2493                 radeon_gem_mm_init(dev);
2494                 radeon_modeset_init(dev);
2495
2496                 radeon_modeset_cp_init(dev);
2497                 dev->devname = kstrdup(DRIVER_NAME, GFP_KERNEL);
2498
2499                 drm_irq_install(dev);
2500         }
2501
2502
2503         return ret;
2504 }
2505
2506
2507 int radeon_master_create(struct drm_device *dev, struct drm_master *master)
2508 {
2509         struct drm_radeon_master_private *master_priv;
2510         unsigned long sareapage;
2511         int ret;
2512
2513         master_priv = drm_calloc(1, sizeof(*master_priv), DRM_MEM_DRIVER);
2514         if (!master_priv)
2515                 return -ENOMEM;
2516
2517         /* prebuild the SAREA */
2518         sareapage = max(SAREA_MAX, PAGE_SIZE);
2519         ret = drm_addmap(dev, 0, sareapage, _DRM_SHM, _DRM_CONTAINS_LOCK|_DRM_DRIVER,
2520                          &master_priv->sarea);
2521         if (ret) {
2522                 DRM_ERROR("SAREA setup failed\n");
2523                 return ret;
2524         }
2525         master_priv->sarea_priv = master_priv->sarea->handle + sizeof(struct drm_sarea);
2526         master_priv->sarea_priv->pfCurrentPage = 0;
2527
2528         master->driver_priv = master_priv;
2529         return 0;
2530 }
2531
2532 void radeon_master_destroy(struct drm_device *dev, struct drm_master *master)
2533 {
2534         struct drm_radeon_master_private *master_priv = master->driver_priv;
2535         struct drm_radeon_private *dev_priv = dev->dev_private;
2536
2537         if (!master_priv)
2538                 return;
2539
2540         if (master_priv->sarea_priv &&
2541             master_priv->sarea_priv->pfCurrentPage != 0)
2542                 radeon_cp_dispatch_flip(dev, master);
2543
2544         master_priv->sarea_priv = NULL;
2545         if (master_priv->sarea)
2546                 drm_rmmap_locked(dev, master_priv->sarea);
2547
2548         drm_free(master_priv, sizeof(*master_priv), DRM_MEM_DRIVER);
2549
2550         master->driver_priv = NULL;
2551 }
2552 /* Create mappings for registers and framebuffer so userland doesn't necessarily
2553  * have to find them.
2554  */
2555 int radeon_driver_firstopen(struct drm_device *dev)
2556 {
2557         int ret;
2558         drm_local_map_t *map;
2559         drm_radeon_private_t *dev_priv = dev->dev_private;
2560
2561         dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
2562
2563         if (!drm_core_check_feature(dev, DRIVER_MODESET))
2564                 radeon_gem_mm_init(dev);
2565
2566         ret = drm_addmap(dev, dev_priv->fb_aper_offset,
2567                          drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
2568                          _DRM_WRITE_COMBINING, &map);
2569         if (ret != 0)
2570                 return ret;
2571
2572         return 0;
2573 }
2574
2575 int radeon_driver_unload(struct drm_device *dev)
2576 {
2577         drm_radeon_private_t *dev_priv = dev->dev_private;
2578
2579         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2580                 drm_irq_uninstall(dev);
2581                 radeon_modeset_cleanup(dev);
2582                 radeon_gem_mm_fini(dev);
2583         }
2584
2585         drm_bo_driver_finish(dev);
2586         drm_rmmap(dev, dev_priv->mmio);
2587
2588         DRM_DEBUG("\n");
2589         drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
2590
2591         dev->dev_private = NULL;
2592         return 0;
2593 }
2594
2595 void radeon_gart_flush(struct drm_device *dev)
2596 {
2597         drm_radeon_private_t *dev_priv = dev->dev_private;
2598
2599         if (dev_priv->flags & RADEON_IS_IGPGART) {
2600                 IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
2601                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE);
2602                 IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
2603                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
2604         } else if (dev_priv->flags & RADEON_IS_PCIE) {
2605                 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
2606                 tmp |= RADEON_PCIE_TX_GART_INVALIDATE_TLB;
2607                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
2608                 tmp &= ~RADEON_PCIE_TX_GART_INVALIDATE_TLB;
2609                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
2610         } else {
2611
2612
2613         }
2614
2615 }