1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
33 #include "radeon_drm.h"
34 #include "radeon_drv.h"
37 #define RADEON_FIFO_DEBUG 0
39 static int radeon_do_cleanup_cp(struct drm_device * dev);
41 /* CP microcode (from ATI) */
42 static const u32 R200_cp_microcode[][2] = {
43 {0x21007000, 0000000000},
44 {0x20007000, 0000000000},
45 {0x000000ab, 0x00000004},
46 {0x000000af, 0x00000004},
47 {0x66544a49, 0000000000},
48 {0x49494174, 0000000000},
49 {0x54517d83, 0000000000},
50 {0x498d8b64, 0000000000},
51 {0x49494949, 0000000000},
52 {0x49da493c, 0000000000},
53 {0x49989898, 0000000000},
54 {0xd34949d5, 0000000000},
55 {0x9dc90e11, 0000000000},
56 {0xce9b9b9b, 0000000000},
57 {0x000f0000, 0x00000016},
58 {0x352e232c, 0000000000},
59 {0x00000013, 0x00000004},
60 {0x000f0000, 0x00000016},
61 {0x352e272c, 0000000000},
62 {0x000f0001, 0x00000016},
63 {0x3239362f, 0000000000},
64 {0x000077ef, 0x00000002},
65 {0x00061000, 0x00000002},
66 {0x00000020, 0x0000001a},
67 {0x00004000, 0x0000001e},
68 {0x00061000, 0x00000002},
69 {0x00000020, 0x0000001a},
70 {0x00004000, 0x0000001e},
71 {0x00061000, 0x00000002},
72 {0x00000020, 0x0000001a},
73 {0x00004000, 0x0000001e},
74 {0x00000016, 0x00000004},
75 {0x0003802a, 0x00000002},
76 {0x040067e0, 0x00000002},
77 {0x00000016, 0x00000004},
78 {0x000077e0, 0x00000002},
79 {0x00065000, 0x00000002},
80 {0x000037e1, 0x00000002},
81 {0x040067e1, 0x00000006},
82 {0x000077e0, 0x00000002},
83 {0x000077e1, 0x00000002},
84 {0x000077e1, 0x00000006},
85 {0xffffffff, 0000000000},
86 {0x10000000, 0000000000},
87 {0x0003802a, 0x00000002},
88 {0x040067e0, 0x00000006},
89 {0x00007675, 0x00000002},
90 {0x00007676, 0x00000002},
91 {0x00007677, 0x00000002},
92 {0x00007678, 0x00000006},
93 {0x0003802b, 0x00000002},
94 {0x04002676, 0x00000002},
95 {0x00007677, 0x00000002},
96 {0x00007678, 0x00000006},
97 {0x0000002e, 0x00000018},
98 {0x0000002e, 0x00000018},
99 {0000000000, 0x00000006},
100 {0x0000002f, 0x00000018},
101 {0x0000002f, 0x00000018},
102 {0000000000, 0x00000006},
103 {0x01605000, 0x00000002},
104 {0x00065000, 0x00000002},
105 {0x00098000, 0x00000002},
106 {0x00061000, 0x00000002},
107 {0x64c0603d, 0x00000004},
108 {0x00080000, 0x00000016},
109 {0000000000, 0000000000},
110 {0x0400251d, 0x00000002},
111 {0x00007580, 0x00000002},
112 {0x00067581, 0x00000002},
113 {0x04002580, 0x00000002},
114 {0x00067581, 0x00000002},
115 {0x00000046, 0x00000004},
116 {0x00005000, 0000000000},
117 {0x00061000, 0x00000002},
118 {0x0000750e, 0x00000002},
119 {0x00019000, 0x00000002},
120 {0x00011055, 0x00000014},
121 {0x00000055, 0x00000012},
122 {0x0400250f, 0x00000002},
123 {0x0000504a, 0x00000004},
124 {0x00007565, 0x00000002},
125 {0x00007566, 0x00000002},
126 {0x00000051, 0x00000004},
127 {0x01e655b4, 0x00000002},
128 {0x4401b0dc, 0x00000002},
129 {0x01c110dc, 0x00000002},
130 {0x2666705d, 0x00000018},
131 {0x040c2565, 0x00000002},
132 {0x0000005d, 0x00000018},
133 {0x04002564, 0x00000002},
134 {0x00007566, 0x00000002},
135 {0x00000054, 0x00000004},
136 {0x00401060, 0x00000008},
137 {0x00101000, 0x00000002},
138 {0x000d80ff, 0x00000002},
139 {0x00800063, 0x00000008},
140 {0x000f9000, 0x00000002},
141 {0x000e00ff, 0x00000002},
142 {0000000000, 0x00000006},
143 {0x00000080, 0x00000018},
144 {0x00000054, 0x00000004},
145 {0x00007576, 0x00000002},
146 {0x00065000, 0x00000002},
147 {0x00009000, 0x00000002},
148 {0x00041000, 0x00000002},
149 {0x0c00350e, 0x00000002},
150 {0x00049000, 0x00000002},
151 {0x00051000, 0x00000002},
152 {0x01e785f8, 0x00000002},
153 {0x00200000, 0x00000002},
154 {0x00600073, 0x0000000c},
155 {0x00007563, 0x00000002},
156 {0x006075f0, 0x00000021},
157 {0x20007068, 0x00000004},
158 {0x00005068, 0x00000004},
159 {0x00007576, 0x00000002},
160 {0x00007577, 0x00000002},
161 {0x0000750e, 0x00000002},
162 {0x0000750f, 0x00000002},
163 {0x00a05000, 0x00000002},
164 {0x00600076, 0x0000000c},
165 {0x006075f0, 0x00000021},
166 {0x000075f8, 0x00000002},
167 {0x00000076, 0x00000004},
168 {0x000a750e, 0x00000002},
169 {0x0020750f, 0x00000002},
170 {0x00600079, 0x00000004},
171 {0x00007570, 0x00000002},
172 {0x00007571, 0x00000002},
173 {0x00007572, 0x00000006},
174 {0x00005000, 0x00000002},
175 {0x00a05000, 0x00000002},
176 {0x00007568, 0x00000002},
177 {0x00061000, 0x00000002},
178 {0x00000084, 0x0000000c},
179 {0x00058000, 0x00000002},
180 {0x0c607562, 0x00000002},
181 {0x00000086, 0x00000004},
182 {0x00600085, 0x00000004},
183 {0x400070dd, 0000000000},
184 {0x000380dd, 0x00000002},
185 {0x00000093, 0x0000001c},
186 {0x00065095, 0x00000018},
187 {0x040025bb, 0x00000002},
188 {0x00061096, 0x00000018},
189 {0x040075bc, 0000000000},
190 {0x000075bb, 0x00000002},
191 {0x000075bc, 0000000000},
192 {0x00090000, 0x00000006},
193 {0x00090000, 0x00000002},
194 {0x000d8002, 0x00000006},
195 {0x00005000, 0x00000002},
196 {0x00007821, 0x00000002},
197 {0x00007800, 0000000000},
198 {0x00007821, 0x00000002},
199 {0x00007800, 0000000000},
200 {0x01665000, 0x00000002},
201 {0x000a0000, 0x00000002},
202 {0x000671cc, 0x00000002},
203 {0x0286f1cd, 0x00000002},
204 {0x000000a3, 0x00000010},
205 {0x21007000, 0000000000},
206 {0x000000aa, 0x0000001c},
207 {0x00065000, 0x00000002},
208 {0x000a0000, 0x00000002},
209 {0x00061000, 0x00000002},
210 {0x000b0000, 0x00000002},
211 {0x38067000, 0x00000002},
212 {0x000a00a6, 0x00000004},
213 {0x20007000, 0000000000},
214 {0x01200000, 0x00000002},
215 {0x20077000, 0x00000002},
216 {0x01200000, 0x00000002},
217 {0x20007000, 0000000000},
218 {0x00061000, 0x00000002},
219 {0x0120751b, 0x00000002},
220 {0x8040750a, 0x00000002},
221 {0x8040750b, 0x00000002},
222 {0x00110000, 0x00000002},
223 {0x000380dd, 0x00000002},
224 {0x000000bd, 0x0000001c},
225 {0x00061096, 0x00000018},
226 {0x844075bd, 0x00000002},
227 {0x00061095, 0x00000018},
228 {0x840075bb, 0x00000002},
229 {0x00061096, 0x00000018},
230 {0x844075bc, 0x00000002},
231 {0x000000c0, 0x00000004},
232 {0x804075bd, 0x00000002},
233 {0x800075bb, 0x00000002},
234 {0x804075bc, 0x00000002},
235 {0x00108000, 0x00000002},
236 {0x01400000, 0x00000002},
237 {0x006000c4, 0x0000000c},
238 {0x20c07000, 0x00000020},
239 {0x000000c6, 0x00000012},
240 {0x00800000, 0x00000006},
241 {0x0080751d, 0x00000006},
242 {0x000025bb, 0x00000002},
243 {0x000040c0, 0x00000004},
244 {0x0000775c, 0x00000002},
245 {0x00a05000, 0x00000002},
246 {0x00661000, 0x00000002},
247 {0x0460275d, 0x00000020},
248 {0x00004000, 0000000000},
249 {0x00007999, 0x00000002},
250 {0x00a05000, 0x00000002},
251 {0x00661000, 0x00000002},
252 {0x0460299b, 0x00000020},
253 {0x00004000, 0000000000},
254 {0x01e00830, 0x00000002},
255 {0x21007000, 0000000000},
256 {0x00005000, 0x00000002},
257 {0x00038042, 0x00000002},
258 {0x040025e0, 0x00000002},
259 {0x000075e1, 0000000000},
260 {0x00000001, 0000000000},
261 {0x000380d9, 0x00000002},
262 {0x04007394, 0000000000},
263 {0000000000, 0000000000},
264 {0000000000, 0000000000},
265 {0000000000, 0000000000},
266 {0000000000, 0000000000},
267 {0000000000, 0000000000},
268 {0000000000, 0000000000},
269 {0000000000, 0000000000},
270 {0000000000, 0000000000},
271 {0000000000, 0000000000},
272 {0000000000, 0000000000},
273 {0000000000, 0000000000},
274 {0000000000, 0000000000},
275 {0000000000, 0000000000},
276 {0000000000, 0000000000},
277 {0000000000, 0000000000},
278 {0000000000, 0000000000},
279 {0000000000, 0000000000},
280 {0000000000, 0000000000},
281 {0000000000, 0000000000},
282 {0000000000, 0000000000},
283 {0000000000, 0000000000},
284 {0000000000, 0000000000},
285 {0000000000, 0000000000},
286 {0000000000, 0000000000},
287 {0000000000, 0000000000},
288 {0000000000, 0000000000},
289 {0000000000, 0000000000},
290 {0000000000, 0000000000},
291 {0000000000, 0000000000},
292 {0000000000, 0000000000},
293 {0000000000, 0000000000},
294 {0000000000, 0000000000},
295 {0000000000, 0000000000},
296 {0000000000, 0000000000},
297 {0000000000, 0000000000},
298 {0000000000, 0000000000},
301 static const u32 radeon_cp_microcode[][2] = {
302 {0x21007000, 0000000000},
303 {0x20007000, 0000000000},
304 {0x000000b4, 0x00000004},
305 {0x000000b8, 0x00000004},
306 {0x6f5b4d4c, 0000000000},
307 {0x4c4c427f, 0000000000},
308 {0x5b568a92, 0000000000},
309 {0x4ca09c6d, 0000000000},
310 {0xad4c4c4c, 0000000000},
311 {0x4ce1af3d, 0000000000},
312 {0xd8afafaf, 0000000000},
313 {0xd64c4cdc, 0000000000},
314 {0x4cd10d10, 0000000000},
315 {0x000f0000, 0x00000016},
316 {0x362f242d, 0000000000},
317 {0x00000012, 0x00000004},
318 {0x000f0000, 0x00000016},
319 {0x362f282d, 0000000000},
320 {0x000380e7, 0x00000002},
321 {0x04002c97, 0x00000002},
322 {0x000f0001, 0x00000016},
323 {0x333a3730, 0000000000},
324 {0x000077ef, 0x00000002},
325 {0x00061000, 0x00000002},
326 {0x00000021, 0x0000001a},
327 {0x00004000, 0x0000001e},
328 {0x00061000, 0x00000002},
329 {0x00000021, 0x0000001a},
330 {0x00004000, 0x0000001e},
331 {0x00061000, 0x00000002},
332 {0x00000021, 0x0000001a},
333 {0x00004000, 0x0000001e},
334 {0x00000017, 0x00000004},
335 {0x0003802b, 0x00000002},
336 {0x040067e0, 0x00000002},
337 {0x00000017, 0x00000004},
338 {0x000077e0, 0x00000002},
339 {0x00065000, 0x00000002},
340 {0x000037e1, 0x00000002},
341 {0x040067e1, 0x00000006},
342 {0x000077e0, 0x00000002},
343 {0x000077e1, 0x00000002},
344 {0x000077e1, 0x00000006},
345 {0xffffffff, 0000000000},
346 {0x10000000, 0000000000},
347 {0x0003802b, 0x00000002},
348 {0x040067e0, 0x00000006},
349 {0x00007675, 0x00000002},
350 {0x00007676, 0x00000002},
351 {0x00007677, 0x00000002},
352 {0x00007678, 0x00000006},
353 {0x0003802c, 0x00000002},
354 {0x04002676, 0x00000002},
355 {0x00007677, 0x00000002},
356 {0x00007678, 0x00000006},
357 {0x0000002f, 0x00000018},
358 {0x0000002f, 0x00000018},
359 {0000000000, 0x00000006},
360 {0x00000030, 0x00000018},
361 {0x00000030, 0x00000018},
362 {0000000000, 0x00000006},
363 {0x01605000, 0x00000002},
364 {0x00065000, 0x00000002},
365 {0x00098000, 0x00000002},
366 {0x00061000, 0x00000002},
367 {0x64c0603e, 0x00000004},
368 {0x000380e6, 0x00000002},
369 {0x040025c5, 0x00000002},
370 {0x00080000, 0x00000016},
371 {0000000000, 0000000000},
372 {0x0400251d, 0x00000002},
373 {0x00007580, 0x00000002},
374 {0x00067581, 0x00000002},
375 {0x04002580, 0x00000002},
376 {0x00067581, 0x00000002},
377 {0x00000049, 0x00000004},
378 {0x00005000, 0000000000},
379 {0x000380e6, 0x00000002},
380 {0x040025c5, 0x00000002},
381 {0x00061000, 0x00000002},
382 {0x0000750e, 0x00000002},
383 {0x00019000, 0x00000002},
384 {0x00011055, 0x00000014},
385 {0x00000055, 0x00000012},
386 {0x0400250f, 0x00000002},
387 {0x0000504f, 0x00000004},
388 {0x000380e6, 0x00000002},
389 {0x040025c5, 0x00000002},
390 {0x00007565, 0x00000002},
391 {0x00007566, 0x00000002},
392 {0x00000058, 0x00000004},
393 {0x000380e6, 0x00000002},
394 {0x040025c5, 0x00000002},
395 {0x01e655b4, 0x00000002},
396 {0x4401b0e4, 0x00000002},
397 {0x01c110e4, 0x00000002},
398 {0x26667066, 0x00000018},
399 {0x040c2565, 0x00000002},
400 {0x00000066, 0x00000018},
401 {0x04002564, 0x00000002},
402 {0x00007566, 0x00000002},
403 {0x0000005d, 0x00000004},
404 {0x00401069, 0x00000008},
405 {0x00101000, 0x00000002},
406 {0x000d80ff, 0x00000002},
407 {0x0080006c, 0x00000008},
408 {0x000f9000, 0x00000002},
409 {0x000e00ff, 0x00000002},
410 {0000000000, 0x00000006},
411 {0x0000008f, 0x00000018},
412 {0x0000005b, 0x00000004},
413 {0x000380e6, 0x00000002},
414 {0x040025c5, 0x00000002},
415 {0x00007576, 0x00000002},
416 {0x00065000, 0x00000002},
417 {0x00009000, 0x00000002},
418 {0x00041000, 0x00000002},
419 {0x0c00350e, 0x00000002},
420 {0x00049000, 0x00000002},
421 {0x00051000, 0x00000002},
422 {0x01e785f8, 0x00000002},
423 {0x00200000, 0x00000002},
424 {0x0060007e, 0x0000000c},
425 {0x00007563, 0x00000002},
426 {0x006075f0, 0x00000021},
427 {0x20007073, 0x00000004},
428 {0x00005073, 0x00000004},
429 {0x000380e6, 0x00000002},
430 {0x040025c5, 0x00000002},
431 {0x00007576, 0x00000002},
432 {0x00007577, 0x00000002},
433 {0x0000750e, 0x00000002},
434 {0x0000750f, 0x00000002},
435 {0x00a05000, 0x00000002},
436 {0x00600083, 0x0000000c},
437 {0x006075f0, 0x00000021},
438 {0x000075f8, 0x00000002},
439 {0x00000083, 0x00000004},
440 {0x000a750e, 0x00000002},
441 {0x000380e6, 0x00000002},
442 {0x040025c5, 0x00000002},
443 {0x0020750f, 0x00000002},
444 {0x00600086, 0x00000004},
445 {0x00007570, 0x00000002},
446 {0x00007571, 0x00000002},
447 {0x00007572, 0x00000006},
448 {0x000380e6, 0x00000002},
449 {0x040025c5, 0x00000002},
450 {0x00005000, 0x00000002},
451 {0x00a05000, 0x00000002},
452 {0x00007568, 0x00000002},
453 {0x00061000, 0x00000002},
454 {0x00000095, 0x0000000c},
455 {0x00058000, 0x00000002},
456 {0x0c607562, 0x00000002},
457 {0x00000097, 0x00000004},
458 {0x000380e6, 0x00000002},
459 {0x040025c5, 0x00000002},
460 {0x00600096, 0x00000004},
461 {0x400070e5, 0000000000},
462 {0x000380e6, 0x00000002},
463 {0x040025c5, 0x00000002},
464 {0x000380e5, 0x00000002},
465 {0x000000a8, 0x0000001c},
466 {0x000650aa, 0x00000018},
467 {0x040025bb, 0x00000002},
468 {0x000610ab, 0x00000018},
469 {0x040075bc, 0000000000},
470 {0x000075bb, 0x00000002},
471 {0x000075bc, 0000000000},
472 {0x00090000, 0x00000006},
473 {0x00090000, 0x00000002},
474 {0x000d8002, 0x00000006},
475 {0x00007832, 0x00000002},
476 {0x00005000, 0x00000002},
477 {0x000380e7, 0x00000002},
478 {0x04002c97, 0x00000002},
479 {0x00007820, 0x00000002},
480 {0x00007821, 0x00000002},
481 {0x00007800, 0000000000},
482 {0x01200000, 0x00000002},
483 {0x20077000, 0x00000002},
484 {0x01200000, 0x00000002},
485 {0x20007000, 0x00000002},
486 {0x00061000, 0x00000002},
487 {0x0120751b, 0x00000002},
488 {0x8040750a, 0x00000002},
489 {0x8040750b, 0x00000002},
490 {0x00110000, 0x00000002},
491 {0x000380e5, 0x00000002},
492 {0x000000c6, 0x0000001c},
493 {0x000610ab, 0x00000018},
494 {0x844075bd, 0x00000002},
495 {0x000610aa, 0x00000018},
496 {0x840075bb, 0x00000002},
497 {0x000610ab, 0x00000018},
498 {0x844075bc, 0x00000002},
499 {0x000000c9, 0x00000004},
500 {0x804075bd, 0x00000002},
501 {0x800075bb, 0x00000002},
502 {0x804075bc, 0x00000002},
503 {0x00108000, 0x00000002},
504 {0x01400000, 0x00000002},
505 {0x006000cd, 0x0000000c},
506 {0x20c07000, 0x00000020},
507 {0x000000cf, 0x00000012},
508 {0x00800000, 0x00000006},
509 {0x0080751d, 0x00000006},
510 {0000000000, 0000000000},
511 {0x0000775c, 0x00000002},
512 {0x00a05000, 0x00000002},
513 {0x00661000, 0x00000002},
514 {0x0460275d, 0x00000020},
515 {0x00004000, 0000000000},
516 {0x01e00830, 0x00000002},
517 {0x21007000, 0000000000},
518 {0x6464614d, 0000000000},
519 {0x69687420, 0000000000},
520 {0x00000073, 0000000000},
521 {0000000000, 0000000000},
522 {0x00005000, 0x00000002},
523 {0x000380d0, 0x00000002},
524 {0x040025e0, 0x00000002},
525 {0x000075e1, 0000000000},
526 {0x00000001, 0000000000},
527 {0x000380e0, 0x00000002},
528 {0x04002394, 0x00000002},
529 {0x00005000, 0000000000},
530 {0000000000, 0000000000},
531 {0000000000, 0000000000},
532 {0x00000008, 0000000000},
533 {0x00000004, 0000000000},
534 {0000000000, 0000000000},
535 {0000000000, 0000000000},
536 {0000000000, 0000000000},
537 {0000000000, 0000000000},
538 {0000000000, 0000000000},
539 {0000000000, 0000000000},
540 {0000000000, 0000000000},
541 {0000000000, 0000000000},
542 {0000000000, 0000000000},
543 {0000000000, 0000000000},
544 {0000000000, 0000000000},
545 {0000000000, 0000000000},
546 {0000000000, 0000000000},
547 {0000000000, 0000000000},
548 {0000000000, 0000000000},
549 {0000000000, 0000000000},
550 {0000000000, 0000000000},
551 {0000000000, 0000000000},
552 {0000000000, 0000000000},
553 {0000000000, 0000000000},
554 {0000000000, 0000000000},
555 {0000000000, 0000000000},
556 {0000000000, 0000000000},
557 {0000000000, 0000000000},
560 static const u32 R300_cp_microcode[][2] = {
561 { 0x4200e000, 0000000000 },
562 { 0x4000e000, 0000000000 },
563 { 0x000000af, 0x00000008 },
564 { 0x000000b3, 0x00000008 },
565 { 0x6c5a504f, 0000000000 },
566 { 0x4f4f497a, 0000000000 },
567 { 0x5a578288, 0000000000 },
568 { 0x4f91906a, 0000000000 },
569 { 0x4f4f4f4f, 0000000000 },
570 { 0x4fe24f44, 0000000000 },
571 { 0x4f9c9c9c, 0000000000 },
572 { 0xdc4f4fde, 0000000000 },
573 { 0xa1cd4f4f, 0000000000 },
574 { 0xd29d9d9d, 0000000000 },
575 { 0x4f0f9fd7, 0000000000 },
576 { 0x000ca000, 0x00000004 },
577 { 0x000d0012, 0x00000038 },
578 { 0x0000e8b4, 0x00000004 },
579 { 0x000d0014, 0x00000038 },
580 { 0x0000e8b6, 0x00000004 },
581 { 0x000d0016, 0x00000038 },
582 { 0x0000e854, 0x00000004 },
583 { 0x000d0018, 0x00000038 },
584 { 0x0000e855, 0x00000004 },
585 { 0x000d001a, 0x00000038 },
586 { 0x0000e856, 0x00000004 },
587 { 0x000d001c, 0x00000038 },
588 { 0x0000e857, 0x00000004 },
589 { 0x000d001e, 0x00000038 },
590 { 0x0000e824, 0x00000004 },
591 { 0x000d0020, 0x00000038 },
592 { 0x0000e825, 0x00000004 },
593 { 0x000d0022, 0x00000038 },
594 { 0x0000e830, 0x00000004 },
595 { 0x000d0024, 0x00000038 },
596 { 0x0000f0c0, 0x00000004 },
597 { 0x000d0026, 0x00000038 },
598 { 0x0000f0c1, 0x00000004 },
599 { 0x000d0028, 0x00000038 },
600 { 0x0000f041, 0x00000004 },
601 { 0x000d002a, 0x00000038 },
602 { 0x0000f184, 0x00000004 },
603 { 0x000d002c, 0x00000038 },
604 { 0x0000f185, 0x00000004 },
605 { 0x000d002e, 0x00000038 },
606 { 0x0000f186, 0x00000004 },
607 { 0x000d0030, 0x00000038 },
608 { 0x0000f187, 0x00000004 },
609 { 0x000d0032, 0x00000038 },
610 { 0x0000f180, 0x00000004 },
611 { 0x000d0034, 0x00000038 },
612 { 0x0000f393, 0x00000004 },
613 { 0x000d0036, 0x00000038 },
614 { 0x0000f38a, 0x00000004 },
615 { 0x000d0038, 0x00000038 },
616 { 0x0000f38e, 0x00000004 },
617 { 0x0000e821, 0x00000004 },
618 { 0x0140a000, 0x00000004 },
619 { 0x00000043, 0x00000018 },
620 { 0x00cce800, 0x00000004 },
621 { 0x001b0001, 0x00000004 },
622 { 0x08004800, 0x00000004 },
623 { 0x001b0001, 0x00000004 },
624 { 0x08004800, 0x00000004 },
625 { 0x001b0001, 0x00000004 },
626 { 0x08004800, 0x00000004 },
627 { 0x0000003a, 0x00000008 },
628 { 0x0000a000, 0000000000 },
629 { 0x02c0a000, 0x00000004 },
630 { 0x000ca000, 0x00000004 },
631 { 0x00130000, 0x00000004 },
632 { 0x000c2000, 0x00000004 },
633 { 0xc980c045, 0x00000008 },
634 { 0x2000451d, 0x00000004 },
635 { 0x0000e580, 0x00000004 },
636 { 0x000ce581, 0x00000004 },
637 { 0x08004580, 0x00000004 },
638 { 0x000ce581, 0x00000004 },
639 { 0x0000004c, 0x00000008 },
640 { 0x0000a000, 0000000000 },
641 { 0x000c2000, 0x00000004 },
642 { 0x0000e50e, 0x00000004 },
643 { 0x00032000, 0x00000004 },
644 { 0x00022056, 0x00000028 },
645 { 0x00000056, 0x00000024 },
646 { 0x0800450f, 0x00000004 },
647 { 0x0000a050, 0x00000008 },
648 { 0x0000e565, 0x00000004 },
649 { 0x0000e566, 0x00000004 },
650 { 0x00000057, 0x00000008 },
651 { 0x03cca5b4, 0x00000004 },
652 { 0x05432000, 0x00000004 },
653 { 0x00022000, 0x00000004 },
654 { 0x4ccce063, 0x00000030 },
655 { 0x08274565, 0x00000004 },
656 { 0x00000063, 0x00000030 },
657 { 0x08004564, 0x00000004 },
658 { 0x0000e566, 0x00000004 },
659 { 0x0000005a, 0x00000008 },
660 { 0x00802066, 0x00000010 },
661 { 0x00202000, 0x00000004 },
662 { 0x001b00ff, 0x00000004 },
663 { 0x01000069, 0x00000010 },
664 { 0x001f2000, 0x00000004 },
665 { 0x001c00ff, 0x00000004 },
666 { 0000000000, 0x0000000c },
667 { 0x00000085, 0x00000030 },
668 { 0x0000005a, 0x00000008 },
669 { 0x0000e576, 0x00000004 },
670 { 0x000ca000, 0x00000004 },
671 { 0x00012000, 0x00000004 },
672 { 0x00082000, 0x00000004 },
673 { 0x1800650e, 0x00000004 },
674 { 0x00092000, 0x00000004 },
675 { 0x000a2000, 0x00000004 },
676 { 0x000f0000, 0x00000004 },
677 { 0x00400000, 0x00000004 },
678 { 0x00000079, 0x00000018 },
679 { 0x0000e563, 0x00000004 },
680 { 0x00c0e5f9, 0x000000c2 },
681 { 0x0000006e, 0x00000008 },
682 { 0x0000a06e, 0x00000008 },
683 { 0x0000e576, 0x00000004 },
684 { 0x0000e577, 0x00000004 },
685 { 0x0000e50e, 0x00000004 },
686 { 0x0000e50f, 0x00000004 },
687 { 0x0140a000, 0x00000004 },
688 { 0x0000007c, 0x00000018 },
689 { 0x00c0e5f9, 0x000000c2 },
690 { 0x0000007c, 0x00000008 },
691 { 0x0014e50e, 0x00000004 },
692 { 0x0040e50f, 0x00000004 },
693 { 0x00c0007f, 0x00000008 },
694 { 0x0000e570, 0x00000004 },
695 { 0x0000e571, 0x00000004 },
696 { 0x0000e572, 0x0000000c },
697 { 0x0000a000, 0x00000004 },
698 { 0x0140a000, 0x00000004 },
699 { 0x0000e568, 0x00000004 },
700 { 0x000c2000, 0x00000004 },
701 { 0x00000089, 0x00000018 },
702 { 0x000b0000, 0x00000004 },
703 { 0x18c0e562, 0x00000004 },
704 { 0x0000008b, 0x00000008 },
705 { 0x00c0008a, 0x00000008 },
706 { 0x000700e4, 0x00000004 },
707 { 0x00000097, 0x00000038 },
708 { 0x000ca099, 0x00000030 },
709 { 0x080045bb, 0x00000004 },
710 { 0x000c209a, 0x00000030 },
711 { 0x0800e5bc, 0000000000 },
712 { 0x0000e5bb, 0x00000004 },
713 { 0x0000e5bc, 0000000000 },
714 { 0x00120000, 0x0000000c },
715 { 0x00120000, 0x00000004 },
716 { 0x001b0002, 0x0000000c },
717 { 0x0000a000, 0x00000004 },
718 { 0x0000e821, 0x00000004 },
719 { 0x0000e800, 0000000000 },
720 { 0x0000e821, 0x00000004 },
721 { 0x0000e82e, 0000000000 },
722 { 0x02cca000, 0x00000004 },
723 { 0x00140000, 0x00000004 },
724 { 0x000ce1cc, 0x00000004 },
725 { 0x050de1cd, 0x00000004 },
726 { 0x000000a7, 0x00000020 },
727 { 0x4200e000, 0000000000 },
728 { 0x000000ae, 0x00000038 },
729 { 0x000ca000, 0x00000004 },
730 { 0x00140000, 0x00000004 },
731 { 0x000c2000, 0x00000004 },
732 { 0x00160000, 0x00000004 },
733 { 0x700ce000, 0x00000004 },
734 { 0x001400aa, 0x00000008 },
735 { 0x4000e000, 0000000000 },
736 { 0x02400000, 0x00000004 },
737 { 0x400ee000, 0x00000004 },
738 { 0x02400000, 0x00000004 },
739 { 0x4000e000, 0000000000 },
740 { 0x000c2000, 0x00000004 },
741 { 0x0240e51b, 0x00000004 },
742 { 0x0080e50a, 0x00000005 },
743 { 0x0080e50b, 0x00000005 },
744 { 0x00220000, 0x00000004 },
745 { 0x000700e4, 0x00000004 },
746 { 0x000000c1, 0x00000038 },
747 { 0x000c209a, 0x00000030 },
748 { 0x0880e5bd, 0x00000005 },
749 { 0x000c2099, 0x00000030 },
750 { 0x0800e5bb, 0x00000005 },
751 { 0x000c209a, 0x00000030 },
752 { 0x0880e5bc, 0x00000005 },
753 { 0x000000c4, 0x00000008 },
754 { 0x0080e5bd, 0x00000005 },
755 { 0x0000e5bb, 0x00000005 },
756 { 0x0080e5bc, 0x00000005 },
757 { 0x00210000, 0x00000004 },
758 { 0x02800000, 0x00000004 },
759 { 0x00c000c8, 0x00000018 },
760 { 0x4180e000, 0x00000040 },
761 { 0x000000ca, 0x00000024 },
762 { 0x01000000, 0x0000000c },
763 { 0x0100e51d, 0x0000000c },
764 { 0x000045bb, 0x00000004 },
765 { 0x000080c4, 0x00000008 },
766 { 0x0000f3ce, 0x00000004 },
767 { 0x0140a000, 0x00000004 },
768 { 0x00cc2000, 0x00000004 },
769 { 0x08c053cf, 0x00000040 },
770 { 0x00008000, 0000000000 },
771 { 0x0000f3d2, 0x00000004 },
772 { 0x0140a000, 0x00000004 },
773 { 0x00cc2000, 0x00000004 },
774 { 0x08c053d3, 0x00000040 },
775 { 0x00008000, 0000000000 },
776 { 0x0000f39d, 0x00000004 },
777 { 0x0140a000, 0x00000004 },
778 { 0x00cc2000, 0x00000004 },
779 { 0x08c0539e, 0x00000040 },
780 { 0x00008000, 0000000000 },
781 { 0x03c00830, 0x00000004 },
782 { 0x4200e000, 0000000000 },
783 { 0x0000a000, 0x00000004 },
784 { 0x200045e0, 0x00000004 },
785 { 0x0000e5e1, 0000000000 },
786 { 0x00000001, 0000000000 },
787 { 0x000700e1, 0x00000004 },
788 { 0x0800e394, 0000000000 },
789 { 0000000000, 0000000000 },
790 { 0000000000, 0000000000 },
791 { 0000000000, 0000000000 },
792 { 0000000000, 0000000000 },
793 { 0000000000, 0000000000 },
794 { 0000000000, 0000000000 },
795 { 0000000000, 0000000000 },
796 { 0000000000, 0000000000 },
797 { 0000000000, 0000000000 },
798 { 0000000000, 0000000000 },
799 { 0000000000, 0000000000 },
800 { 0000000000, 0000000000 },
801 { 0000000000, 0000000000 },
802 { 0000000000, 0000000000 },
803 { 0000000000, 0000000000 },
804 { 0000000000, 0000000000 },
805 { 0000000000, 0000000000 },
806 { 0000000000, 0000000000 },
807 { 0000000000, 0000000000 },
808 { 0000000000, 0000000000 },
809 { 0000000000, 0000000000 },
810 { 0000000000, 0000000000 },
811 { 0000000000, 0000000000 },
812 { 0000000000, 0000000000 },
813 { 0000000000, 0000000000 },
814 { 0000000000, 0000000000 },
815 { 0000000000, 0000000000 },
816 { 0000000000, 0000000000 },
819 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
821 drm_radeon_private_t *dev_priv = dev->dev_private;
823 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
824 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
827 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
829 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
830 return RADEON_READ(RADEON_PCIE_DATA);
833 static u32 RADEON_READ_IGPGART(drm_radeon_private_t *dev_priv, int addr)
836 RADEON_WRITE(RADEON_IGPGART_INDEX, addr & 0x7f);
837 ret = RADEON_READ(RADEON_IGPGART_DATA);
838 RADEON_WRITE(RADEON_IGPGART_INDEX, 0x7f);
842 #if RADEON_FIFO_DEBUG
843 static void radeon_status(drm_radeon_private_t * dev_priv)
845 printk("%s:\n", __FUNCTION__);
846 printk("RBBM_STATUS = 0x%08x\n",
847 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
848 printk("CP_RB_RTPR = 0x%08x\n",
849 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
850 printk("CP_RB_WTPR = 0x%08x\n",
851 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
852 printk("AIC_CNTL = 0x%08x\n",
853 (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
854 printk("AIC_STAT = 0x%08x\n",
855 (unsigned int)RADEON_READ(RADEON_AIC_STAT));
856 printk("AIC_PT_BASE = 0x%08x\n",
857 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
858 printk("TLB_ADDR = 0x%08x\n",
859 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
860 printk("TLB_DATA = 0x%08x\n",
861 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
865 /* ================================================================
866 * Engine, FIFO control
869 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
874 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
876 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
877 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
878 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
880 for (i = 0; i < dev_priv->usec_timeout; i++) {
881 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
882 & RADEON_RB3D_DC_BUSY)) {
888 #if RADEON_FIFO_DEBUG
889 DRM_ERROR("failed!\n");
890 radeon_status(dev_priv);
895 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
899 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
901 for (i = 0; i < dev_priv->usec_timeout; i++) {
902 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
903 & RADEON_RBBM_FIFOCNT_MASK);
904 if (slots >= entries)
909 #if RADEON_FIFO_DEBUG
910 DRM_ERROR("failed!\n");
911 radeon_status(dev_priv);
916 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
920 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
922 ret = radeon_do_wait_for_fifo(dev_priv, 64);
926 for (i = 0; i < dev_priv->usec_timeout; i++) {
927 if (!(RADEON_READ(RADEON_RBBM_STATUS)
928 & RADEON_RBBM_ACTIVE)) {
929 radeon_do_pixcache_flush(dev_priv);
935 #if RADEON_FIFO_DEBUG
936 DRM_ERROR("failed!\n");
937 radeon_status(dev_priv);
942 /* ================================================================
943 * CP control, initialization
946 /* Load the microcode for the CP */
947 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
952 radeon_do_wait_for_idle(dev_priv);
954 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
956 if (dev_priv->microcode_version == UCODE_R200) {
957 DRM_INFO("Loading R200 Microcode\n");
958 for (i = 0; i < 256; i++) {
959 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
960 R200_cp_microcode[i][1]);
961 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
962 R200_cp_microcode[i][0]);
964 } else if (dev_priv->microcode_version == UCODE_R300) {
965 DRM_INFO("Loading R300 Microcode\n");
966 for (i = 0; i < 256; i++) {
967 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
968 R300_cp_microcode[i][1]);
969 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
970 R300_cp_microcode[i][0]);
973 for (i = 0; i < 256; i++) {
974 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
975 radeon_cp_microcode[i][1]);
976 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
977 radeon_cp_microcode[i][0]);
982 /* Flush any pending commands to the CP. This should only be used just
983 * prior to a wait for idle, as it informs the engine that the command
986 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
992 tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
993 RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
997 /* Wait for the CP to go idle.
999 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
1006 RADEON_PURGE_CACHE();
1007 RADEON_PURGE_ZCACHE();
1008 RADEON_WAIT_UNTIL_IDLE();
1013 return radeon_do_wait_for_idle(dev_priv);
1016 /* Start the Command Processor.
1018 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
1023 radeon_do_wait_for_idle(dev_priv);
1025 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
1027 dev_priv->cp_running = 1;
1031 RADEON_PURGE_CACHE();
1032 RADEON_PURGE_ZCACHE();
1033 RADEON_WAIT_UNTIL_IDLE();
1039 /* Reset the Command Processor. This will not flush any pending
1040 * commands, so you must wait for the CP command stream to complete
1041 * before calling this routine.
1043 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
1048 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
1049 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
1050 SET_RING_HEAD(dev_priv, cur_read_ptr);
1051 dev_priv->ring.tail = cur_read_ptr;
1054 /* Stop the Command Processor. This will not flush any pending
1055 * commands, so you must flush the command stream and wait for the CP
1056 * to go idle before calling this routine.
1058 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
1062 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
1064 dev_priv->cp_running = 0;
1067 /* Reset the engine. This will stop the CP if it is running.
1069 static int radeon_do_engine_reset(struct drm_device * dev)
1071 drm_radeon_private_t *dev_priv = dev->dev_private;
1072 u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
1075 radeon_do_pixcache_flush(dev_priv);
1077 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
1078 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
1080 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
1081 RADEON_FORCEON_MCLKA |
1082 RADEON_FORCEON_MCLKB |
1083 RADEON_FORCEON_YCLKA |
1084 RADEON_FORCEON_YCLKB |
1086 RADEON_FORCEON_AIC));
1088 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
1090 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
1091 RADEON_SOFT_RESET_CP |
1092 RADEON_SOFT_RESET_HI |
1093 RADEON_SOFT_RESET_SE |
1094 RADEON_SOFT_RESET_RE |
1095 RADEON_SOFT_RESET_PP |
1096 RADEON_SOFT_RESET_E2 |
1097 RADEON_SOFT_RESET_RB));
1098 RADEON_READ(RADEON_RBBM_SOFT_RESET);
1099 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
1100 ~(RADEON_SOFT_RESET_CP |
1101 RADEON_SOFT_RESET_HI |
1102 RADEON_SOFT_RESET_SE |
1103 RADEON_SOFT_RESET_RE |
1104 RADEON_SOFT_RESET_PP |
1105 RADEON_SOFT_RESET_E2 |
1106 RADEON_SOFT_RESET_RB)));
1107 RADEON_READ(RADEON_RBBM_SOFT_RESET);
1109 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
1110 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
1111 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
1113 /* Reset the CP ring */
1114 radeon_do_cp_reset(dev_priv);
1116 /* The CP is no longer running after an engine reset */
1117 dev_priv->cp_running = 0;
1119 /* Reset any pending vertex, indirect buffers */
1120 radeon_freelist_reset(dev);
1125 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
1126 drm_radeon_private_t * dev_priv)
1128 u32 ring_start, cur_read_ptr;
1131 /* Initialize the memory controller. With new memory map, the fb location
1132 * is not changed, it should have been properly initialized already. Part
1133 * of the problem is that the code below is bogus, assuming the GART is
1134 * always appended to the fb which is not necessarily the case
1136 if (!dev_priv->new_memmap)
1137 RADEON_WRITE(RADEON_MC_FB_LOCATION,
1138 ((dev_priv->gart_vm_start - 1) & 0xffff0000)
1139 | (dev_priv->fb_location >> 16));
1142 if (dev_priv->flags & RADEON_IS_AGP) {
1143 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);
1144 RADEON_WRITE(RADEON_MC_AGP_LOCATION,
1145 (((dev_priv->gart_vm_start - 1 +
1146 dev_priv->gart_size) & 0xffff0000) |
1147 (dev_priv->gart_vm_start >> 16)));
1149 ring_start = (dev_priv->cp_ring->offset
1151 + dev_priv->gart_vm_start);
1154 ring_start = (dev_priv->cp_ring->offset
1155 - (unsigned long)dev->sg->virtual
1156 + dev_priv->gart_vm_start);
1158 RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
1160 /* Set the write pointer delay */
1161 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
1163 /* Initialize the ring buffer's read and write pointers */
1164 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
1165 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
1166 SET_RING_HEAD(dev_priv, cur_read_ptr);
1167 dev_priv->ring.tail = cur_read_ptr;
1170 if (dev_priv->flags & RADEON_IS_AGP) {
1171 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
1172 dev_priv->ring_rptr->offset
1173 - dev->agp->base + dev_priv->gart_vm_start);
1177 struct drm_sg_mem *entry = dev->sg;
1178 unsigned long tmp_ofs, page_ofs;
1180 tmp_ofs = dev_priv->ring_rptr->offset -
1181 (unsigned long)dev->sg->virtual;
1182 page_ofs = tmp_ofs >> PAGE_SHIFT;
1184 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
1185 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
1186 (unsigned long)entry->busaddr[page_ofs],
1187 entry->handle + tmp_ofs);
1190 /* Set ring buffer size */
1192 RADEON_WRITE(RADEON_CP_RB_CNTL,
1193 RADEON_BUF_SWAP_32BIT |
1194 (dev_priv->ring.fetch_size_l2ow << 18) |
1195 (dev_priv->ring.rptr_update_l2qw << 8) |
1196 dev_priv->ring.size_l2qw);
1198 RADEON_WRITE(RADEON_CP_RB_CNTL,
1199 (dev_priv->ring.fetch_size_l2ow << 18) |
1200 (dev_priv->ring.rptr_update_l2qw << 8) |
1201 dev_priv->ring.size_l2qw);
1204 /* Start with assuming that writeback doesn't work */
1205 dev_priv->writeback_works = 0;
1207 /* Initialize the scratch register pointer. This will cause
1208 * the scratch register values to be written out to memory
1209 * whenever they are updated.
1211 * We simply put this behind the ring read pointer, this works
1212 * with PCI GART as well as (whatever kind of) AGP GART
1214 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
1215 + RADEON_SCRATCH_REG_OFFSET);
1217 dev_priv->scratch = ((__volatile__ u32 *)
1218 dev_priv->ring_rptr->handle +
1219 (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
1221 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
1223 /* Turn on bus mastering */
1224 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
1225 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
1227 dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
1228 RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
1230 dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
1231 RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
1232 dev_priv->sarea_priv->last_dispatch);
1234 dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
1235 RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
1237 radeon_do_wait_for_idle(dev_priv);
1239 /* Sync everything up */
1240 RADEON_WRITE(RADEON_ISYNC_CNTL,
1241 (RADEON_ISYNC_ANY2D_IDLE3D |
1242 RADEON_ISYNC_ANY3D_IDLE2D |
1243 RADEON_ISYNC_WAIT_IDLEGUI |
1244 RADEON_ISYNC_CPSCRATCH_IDLEGUI));
1248 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
1252 /* Writeback doesn't seem to work everywhere, test it here and possibly
1253 * enable it if it appears to work
1255 DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
1256 RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
1258 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
1259 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
1265 if (tmp < dev_priv->usec_timeout) {
1266 dev_priv->writeback_works = 1;
1267 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
1269 dev_priv->writeback_works = 0;
1270 DRM_INFO("writeback test failed\n");
1272 if (radeon_no_wb == 1) {
1273 dev_priv->writeback_works = 0;
1274 DRM_INFO("writeback forced off\n");
1277 if (!dev_priv->writeback_works) {
1278 /* Disable writeback to avoid unnecessary bus master transfers */
1279 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) | RADEON_RB_NO_UPDATE);
1280 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
1284 /* Enable or disable IGP GART on the chip */
1285 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
1289 tmp = RADEON_READ(RADEON_AIC_CNTL);
1290 DRM_DEBUG("setting igpgart AIC CNTL is %08X\n", tmp);
1292 DRM_DEBUG("programming igpgart %08X %08lX %08X\n",
1293 dev_priv->gart_vm_start,
1294 (long)dev_priv->gart_info.bus_addr,
1295 dev_priv->gart_size);
1297 RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_18, 0x1000);
1298 RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, 0x1);
1299 RADEON_WRITE_IGPGART(RADEON_IGPGART_CTRL, 0x42040800);
1300 RADEON_WRITE_IGPGART(RADEON_IGPGART_BASE_ADDR,
1301 dev_priv->gart_info.bus_addr);
1303 temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_39);
1304 RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_39, temp);
1306 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start);
1307 dev_priv->gart_size = 32*1024*1024;
1308 RADEON_WRITE(RADEON_MC_AGP_LOCATION,
1309 (((dev_priv->gart_vm_start - 1 +
1310 dev_priv->gart_size) & 0xffff0000) |
1311 (dev_priv->gart_vm_start >> 16)));
1313 temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_ENABLE);
1314 RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, temp);
1316 RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
1317 RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x1);
1318 RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
1319 RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x0);
1323 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
1325 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
1328 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
1329 dev_priv->gart_vm_start,
1330 (long)dev_priv->gart_info.bus_addr,
1331 dev_priv->gart_size);
1332 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
1333 dev_priv->gart_vm_start);
1334 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
1335 dev_priv->gart_info.bus_addr);
1336 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
1337 dev_priv->gart_vm_start);
1338 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
1339 dev_priv->gart_vm_start +
1340 dev_priv->gart_size - 1);
1342 RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0); /* ?? */
1344 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1345 RADEON_PCIE_TX_GART_EN);
1347 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1348 tmp & ~RADEON_PCIE_TX_GART_EN);
1352 /* Enable or disable PCI GART on the chip */
1353 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1357 if (dev_priv->flags & RADEON_IS_IGPGART) {
1358 radeon_set_igpgart(dev_priv, on);
1362 if (dev_priv->flags & RADEON_IS_PCIE) {
1363 radeon_set_pciegart(dev_priv, on);
1367 tmp = RADEON_READ(RADEON_AIC_CNTL);
1370 RADEON_WRITE(RADEON_AIC_CNTL,
1371 tmp | RADEON_PCIGART_TRANSLATE_EN);
1373 /* set PCI GART page-table base address
1375 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
1377 /* set address range for PCI address translate
1379 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1380 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1381 + dev_priv->gart_size - 1);
1383 /* Turn off AGP aperture -- is this required for PCI GART?
1385 RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0); /* ?? */
1386 RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
1388 RADEON_WRITE(RADEON_AIC_CNTL,
1389 tmp & ~RADEON_PCIGART_TRANSLATE_EN);
1393 void radeon_gart_flush(struct drm_device *dev)
1395 drm_radeon_private_t *dev_priv = dev->dev_private;
1397 if (dev_priv->flags & RADEON_IS_IGPGART) {
1398 RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
1399 RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x1);
1400 RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
1401 RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x0);
1402 } else if (dev_priv->flags & RADEON_IS_PCIE) {
1403 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
1404 tmp |= RADEON_PCIE_TX_GART_INVALIDATE_TLB;
1405 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
1406 tmp &= ~RADEON_PCIE_TX_GART_INVALIDATE_TLB;
1407 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
1415 static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
1417 drm_radeon_private_t *dev_priv = dev->dev_private;
1421 /* if we require new memory map but we don't have it fail */
1422 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1423 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1424 radeon_do_cleanup_cp(dev);
1428 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP))
1430 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1431 dev_priv->flags &= ~RADEON_IS_AGP;
1433 else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1436 DRM_DEBUG("Restoring AGP flag\n");
1437 dev_priv->flags |= RADEON_IS_AGP;
1440 if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
1441 DRM_ERROR("PCI GART memory not allocated!\n");
1442 radeon_do_cleanup_cp(dev);
1446 dev_priv->usec_timeout = init->usec_timeout;
1447 if (dev_priv->usec_timeout < 1 ||
1448 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1449 DRM_DEBUG("TIMEOUT problem!\n");
1450 radeon_do_cleanup_cp(dev);
1454 /* Enable vblank on CRTC1 for older X servers
1456 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1458 switch(init->func) {
1459 case RADEON_INIT_R200_CP:
1460 dev_priv->microcode_version = UCODE_R200;
1462 case RADEON_INIT_R300_CP:
1463 dev_priv->microcode_version = UCODE_R300;
1466 dev_priv->microcode_version = UCODE_R100;
1469 dev_priv->do_boxes = 0;
1470 dev_priv->cp_mode = init->cp_mode;
1472 /* We don't support anything other than bus-mastering ring mode,
1473 * but the ring can be in either AGP or PCI space for the ring
1476 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1477 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1478 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1479 radeon_do_cleanup_cp(dev);
1483 switch (init->fb_bpp) {
1485 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1489 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1492 dev_priv->front_offset = init->front_offset;
1493 dev_priv->front_pitch = init->front_pitch;
1494 dev_priv->back_offset = init->back_offset;
1495 dev_priv->back_pitch = init->back_pitch;
1497 switch (init->depth_bpp) {
1499 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1503 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1506 dev_priv->depth_offset = init->depth_offset;
1507 dev_priv->depth_pitch = init->depth_pitch;
1509 /* Hardware state for depth clears. Remove this if/when we no
1510 * longer clear the depth buffer with a 3D rectangle. Hard-code
1511 * all values to prevent unwanted 3D state from slipping through
1512 * and screwing with the clear operation.
1514 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1515 (dev_priv->color_fmt << 10) |
1516 (dev_priv->microcode_version ==
1517 UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1519 dev_priv->depth_clear.rb3d_zstencilcntl =
1520 (dev_priv->depth_fmt |
1521 RADEON_Z_TEST_ALWAYS |
1522 RADEON_STENCIL_TEST_ALWAYS |
1523 RADEON_STENCIL_S_FAIL_REPLACE |
1524 RADEON_STENCIL_ZPASS_REPLACE |
1525 RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1527 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1528 RADEON_BFACE_SOLID |
1529 RADEON_FFACE_SOLID |
1530 RADEON_FLAT_SHADE_VTX_LAST |
1531 RADEON_DIFFUSE_SHADE_FLAT |
1532 RADEON_ALPHA_SHADE_FLAT |
1533 RADEON_SPECULAR_SHADE_FLAT |
1534 RADEON_FOG_SHADE_FLAT |
1535 RADEON_VTX_PIX_CENTER_OGL |
1536 RADEON_ROUND_MODE_TRUNC |
1537 RADEON_ROUND_PREC_8TH_PIX);
1540 dev_priv->ring_offset = init->ring_offset;
1541 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1542 dev_priv->buffers_offset = init->buffers_offset;
1543 dev_priv->gart_textures_offset = init->gart_textures_offset;
1545 dev_priv->sarea = drm_getsarea(dev);
1546 if (!dev_priv->sarea) {
1547 DRM_ERROR("could not find sarea!\n");
1548 radeon_do_cleanup_cp(dev);
1552 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1553 if (!dev_priv->cp_ring) {
1554 DRM_ERROR("could not find cp ring region!\n");
1555 radeon_do_cleanup_cp(dev);
1558 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1559 if (!dev_priv->ring_rptr) {
1560 DRM_ERROR("could not find ring read pointer!\n");
1561 radeon_do_cleanup_cp(dev);
1564 dev->agp_buffer_token = init->buffers_offset;
1565 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1566 if (!dev->agp_buffer_map) {
1567 DRM_ERROR("could not find dma buffer region!\n");
1568 radeon_do_cleanup_cp(dev);
1572 if (init->gart_textures_offset) {
1573 dev_priv->gart_textures =
1574 drm_core_findmap(dev, init->gart_textures_offset);
1575 if (!dev_priv->gart_textures) {
1576 DRM_ERROR("could not find GART texture region!\n");
1577 radeon_do_cleanup_cp(dev);
1582 dev_priv->sarea_priv =
1583 (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
1584 init->sarea_priv_offset);
1587 if (dev_priv->flags & RADEON_IS_AGP) {
1588 drm_core_ioremap(dev_priv->cp_ring, dev);
1589 drm_core_ioremap(dev_priv->ring_rptr, dev);
1590 drm_core_ioremap(dev->agp_buffer_map, dev);
1591 if (!dev_priv->cp_ring->handle ||
1592 !dev_priv->ring_rptr->handle ||
1593 !dev->agp_buffer_map->handle) {
1594 DRM_ERROR("could not find ioremap agp regions!\n");
1595 radeon_do_cleanup_cp(dev);
1601 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1602 dev_priv->ring_rptr->handle =
1603 (void *)dev_priv->ring_rptr->offset;
1604 dev->agp_buffer_map->handle =
1605 (void *)dev->agp_buffer_map->offset;
1607 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1608 dev_priv->cp_ring->handle);
1609 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1610 dev_priv->ring_rptr->handle);
1611 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1612 dev->agp_buffer_map->handle);
1615 dev_priv->fb_location = (RADEON_READ(RADEON_MC_FB_LOCATION)
1618 ((RADEON_READ(RADEON_MC_FB_LOCATION) & 0xffff0000u) + 0x10000)
1619 - dev_priv->fb_location;
1621 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1622 ((dev_priv->front_offset
1623 + dev_priv->fb_location) >> 10));
1625 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1626 ((dev_priv->back_offset
1627 + dev_priv->fb_location) >> 10));
1629 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1630 ((dev_priv->depth_offset
1631 + dev_priv->fb_location) >> 10));
1633 dev_priv->gart_size = init->gart_size;
1635 /* New let's set the memory map ... */
1636 if (dev_priv->new_memmap) {
1639 DRM_INFO("Setting GART location based on new memory map\n");
1641 /* If using AGP, try to locate the AGP aperture at the same
1642 * location in the card and on the bus, though we have to
1646 if (dev_priv->flags & RADEON_IS_AGP) {
1647 base = dev->agp->base;
1648 /* Check if valid */
1649 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1650 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1651 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1657 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1659 base = dev_priv->fb_location + dev_priv->fb_size;
1660 if (base < dev_priv->fb_location ||
1661 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1662 base = dev_priv->fb_location
1663 - dev_priv->gart_size;
1665 dev_priv->gart_vm_start = base & 0xffc00000u;
1666 if (dev_priv->gart_vm_start != base)
1667 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1668 base, dev_priv->gart_vm_start);
1670 DRM_INFO("Setting GART location based on old memory map\n");
1671 dev_priv->gart_vm_start = dev_priv->fb_location +
1672 RADEON_READ(RADEON_CONFIG_APER_SIZE);
1676 if (dev_priv->flags & RADEON_IS_AGP)
1677 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1679 + dev_priv->gart_vm_start);
1682 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1683 - (unsigned long)dev->sg->virtual
1684 + dev_priv->gart_vm_start);
1686 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1687 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1688 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1689 dev_priv->gart_buffers_offset);
1691 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1692 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1693 + init->ring_size / sizeof(u32));
1694 dev_priv->ring.size = init->ring_size;
1695 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1697 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1698 dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1700 dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1701 dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1703 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1705 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1708 if (dev_priv->flags & RADEON_IS_AGP) {
1709 /* Turn off PCI GART */
1710 radeon_set_pcigart(dev_priv, 0);
1714 /* if we have an offset set from userspace */
1715 if (dev_priv->pcigart_offset_set) {
1716 dev_priv->gart_info.bus_addr =
1717 dev_priv->pcigart_offset + dev_priv->fb_location;
1718 dev_priv->gart_info.mapping.offset =
1719 dev_priv->gart_info.bus_addr;
1720 dev_priv->gart_info.mapping.size =
1721 dev_priv->gart_info.table_size;
1723 drm_core_ioremap(&dev_priv->gart_info.mapping, dev);
1724 dev_priv->gart_info.addr =
1725 dev_priv->gart_info.mapping.handle;
1727 if (dev_priv->flags & RADEON_IS_PCIE)
1728 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1730 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1731 dev_priv->gart_info.gart_table_location =
1734 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1735 dev_priv->gart_info.addr,
1736 dev_priv->pcigart_offset);
1738 if (dev_priv->flags & RADEON_IS_IGPGART)
1739 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1741 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1742 dev_priv->gart_info.gart_table_location =
1744 dev_priv->gart_info.addr = NULL;
1745 dev_priv->gart_info.bus_addr = 0;
1746 if (dev_priv->flags & RADEON_IS_PCIE) {
1748 ("Cannot use PCI Express without GART in FB memory\n");
1749 radeon_do_cleanup_cp(dev);
1754 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
1755 DRM_ERROR("failed to init PCI GART!\n");
1756 radeon_do_cleanup_cp(dev);
1760 /* Turn on PCI GART */
1761 radeon_set_pcigart(dev_priv, 1);
1764 radeon_cp_load_microcode(dev_priv);
1765 radeon_cp_init_ring_buffer(dev, dev_priv);
1767 dev_priv->last_buf = 0;
1769 radeon_do_engine_reset(dev);
1770 radeon_test_writeback(dev_priv);
1775 static int radeon_do_cleanup_cp(struct drm_device * dev)
1777 drm_radeon_private_t *dev_priv = dev->dev_private;
1780 /* Make sure interrupts are disabled here because the uninstall ioctl
1781 * may not have been called from userspace and after dev_private
1782 * is freed, it's too late.
1784 if (dev->irq_enabled)
1785 drm_irq_uninstall(dev);
1788 if (dev_priv->flags & RADEON_IS_AGP) {
1789 if (dev_priv->cp_ring != NULL) {
1790 drm_core_ioremapfree(dev_priv->cp_ring, dev);
1791 dev_priv->cp_ring = NULL;
1793 if (dev_priv->ring_rptr != NULL) {
1794 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1795 dev_priv->ring_rptr = NULL;
1797 if (dev->agp_buffer_map != NULL) {
1798 drm_core_ioremapfree(dev->agp_buffer_map, dev);
1799 dev->agp_buffer_map = NULL;
1805 if (dev_priv->gart_info.bus_addr) {
1806 /* Turn off PCI GART */
1807 radeon_set_pcigart(dev_priv, 0);
1808 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1809 DRM_ERROR("failed to cleanup PCI GART!\n");
1812 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1814 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1815 dev_priv->gart_info.addr = 0;
1818 /* only clear to the start of flags */
1819 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1824 /* This code will reinit the Radeon CP hardware after a resume from disc.
1825 * AFAIK, it would be very difficult to pickle the state at suspend time, so
1826 * here we make sure that all Radeon hardware initialisation is re-done without
1827 * affecting running applications.
1829 * Charl P. Botha <http://cpbotha.net>
1831 static int radeon_do_resume_cp(struct drm_device * dev)
1833 drm_radeon_private_t *dev_priv = dev->dev_private;
1836 DRM_ERROR("Called with no initialization\n");
1840 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1843 if (dev_priv->flags & RADEON_IS_AGP) {
1844 /* Turn off PCI GART */
1845 radeon_set_pcigart(dev_priv, 0);
1849 /* Turn on PCI GART */
1850 radeon_set_pcigart(dev_priv, 1);
1853 radeon_cp_load_microcode(dev_priv);
1854 radeon_cp_init_ring_buffer(dev, dev_priv);
1856 radeon_do_engine_reset(dev);
1858 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1863 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1865 drm_radeon_init_t *init = data;
1867 LOCK_TEST_WITH_RETURN(dev, file_priv);
1869 if (init->func == RADEON_INIT_R300_CP)
1870 r300_init_reg_flags();
1872 switch (init->func) {
1873 case RADEON_INIT_CP:
1874 case RADEON_INIT_R200_CP:
1875 case RADEON_INIT_R300_CP:
1876 return radeon_do_init_cp(dev, init);
1877 case RADEON_CLEANUP_CP:
1878 return radeon_do_cleanup_cp(dev);
1884 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1886 drm_radeon_private_t *dev_priv = dev->dev_private;
1889 LOCK_TEST_WITH_RETURN(dev, file_priv);
1891 if (dev_priv->cp_running) {
1892 DRM_DEBUG("%s while CP running\n", __FUNCTION__);
1895 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1896 DRM_DEBUG("%s called with bogus CP mode (%d)\n",
1897 __FUNCTION__, dev_priv->cp_mode);
1901 radeon_do_cp_start(dev_priv);
1906 /* Stop the CP. The engine must have been idled before calling this
1909 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1911 drm_radeon_private_t *dev_priv = dev->dev_private;
1912 drm_radeon_cp_stop_t *stop = data;
1916 LOCK_TEST_WITH_RETURN(dev, file_priv);
1918 if (!dev_priv->cp_running)
1921 /* Flush any pending CP commands. This ensures any outstanding
1922 * commands are exectuted by the engine before we turn it off.
1925 radeon_do_cp_flush(dev_priv);
1928 /* If we fail to make the engine go idle, we return an error
1929 * code so that the DRM ioctl wrapper can try again.
1932 ret = radeon_do_cp_idle(dev_priv);
1937 /* Finally, we can turn off the CP. If the engine isn't idle,
1938 * we will get some dropped triangles as they won't be fully
1939 * rendered before the CP is shut down.
1941 radeon_do_cp_stop(dev_priv);
1943 /* Reset the engine */
1944 radeon_do_engine_reset(dev);
1949 void radeon_do_release(struct drm_device * dev)
1951 drm_radeon_private_t *dev_priv = dev->dev_private;
1955 if (dev_priv->cp_running) {
1957 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1958 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1962 #if defined(__FreeBSD__) && __FreeBSD_version > 500000
1963 msleep(&ret, &dev->dev_lock, PZERO, "rdnrel",
1966 tsleep(&ret, PZERO, "rdnrel", 1);
1970 radeon_do_cp_stop(dev_priv);
1971 radeon_do_engine_reset(dev);
1974 /* Disable *all* interrupts */
1975 if (dev_priv->mmio) /* remove this after permanent addmaps */
1976 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1978 if (dev_priv->mmio) { /* remove all surfaces */
1979 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1980 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1981 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1983 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1988 /* Free memory heap structures */
1989 radeon_mem_takedown(&(dev_priv->gart_heap));
1990 radeon_mem_takedown(&(dev_priv->fb_heap));
1992 /* deallocate kernel resources */
1993 radeon_do_cleanup_cp(dev);
1997 /* Just reset the CP ring. Called as part of an X Server engine reset.
1999 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
2001 drm_radeon_private_t *dev_priv = dev->dev_private;
2004 LOCK_TEST_WITH_RETURN(dev, file_priv);
2007 DRM_DEBUG("%s called before init done\n", __FUNCTION__);
2011 radeon_do_cp_reset(dev_priv);
2013 /* The CP is no longer running after an engine reset */
2014 dev_priv->cp_running = 0;
2019 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
2021 drm_radeon_private_t *dev_priv = dev->dev_private;
2024 LOCK_TEST_WITH_RETURN(dev, file_priv);
2026 return radeon_do_cp_idle(dev_priv);
2029 /* Added by Charl P. Botha to call radeon_do_resume_cp().
2031 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
2034 return radeon_do_resume_cp(dev);
2037 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
2041 LOCK_TEST_WITH_RETURN(dev, file_priv);
2043 return radeon_do_engine_reset(dev);
2046 /* ================================================================
2050 /* KW: Deprecated to say the least:
2052 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
2057 /* ================================================================
2058 * Freelist management
2061 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
2062 * bufs until freelist code is used. Note this hides a problem with
2063 * the scratch register * (used to keep track of last buffer
2064 * completed) being written to before * the last buffer has actually
2065 * completed rendering.
2067 * KW: It's also a good way to find free buffers quickly.
2069 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
2070 * sleep. However, bugs in older versions of radeon_accel.c mean that
2071 * we essentially have to do this, else old clients will break.
2073 * However, it does leave open a potential deadlock where all the
2074 * buffers are held by other clients, which can't release them because
2075 * they can't get the lock.
2078 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
2080 struct drm_device_dma *dma = dev->dma;
2081 drm_radeon_private_t *dev_priv = dev->dev_private;
2082 drm_radeon_buf_priv_t *buf_priv;
2083 struct drm_buf *buf;
2087 if (++dev_priv->last_buf >= dma->buf_count)
2088 dev_priv->last_buf = 0;
2090 start = dev_priv->last_buf;
2092 for (t = 0; t < dev_priv->usec_timeout; t++) {
2093 u32 done_age = GET_SCRATCH(1);
2094 DRM_DEBUG("done_age = %d\n", done_age);
2095 for (i = start; i < dma->buf_count; i++) {
2096 buf = dma->buflist[i];
2097 buf_priv = buf->dev_private;
2098 if (buf->file_priv == NULL || (buf->pending &&
2101 dev_priv->stats.requested_bufs++;
2110 dev_priv->stats.freelist_loops++;
2114 DRM_DEBUG("returning NULL!\n");
2119 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
2121 struct drm_device_dma *dma = dev->dma;
2122 drm_radeon_private_t *dev_priv = dev->dev_private;
2123 drm_radeon_buf_priv_t *buf_priv;
2124 struct drm_buf *buf;
2127 u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
2129 if (++dev_priv->last_buf >= dma->buf_count)
2130 dev_priv->last_buf = 0;
2132 start = dev_priv->last_buf;
2133 dev_priv->stats.freelist_loops++;
2135 for (t = 0; t < 2; t++) {
2136 for (i = start; i < dma->buf_count; i++) {
2137 buf = dma->buflist[i];
2138 buf_priv = buf->dev_private;
2139 if (buf->file_priv == 0 || (buf->pending &&
2142 dev_priv->stats.requested_bufs++;
2154 void radeon_freelist_reset(struct drm_device * dev)
2156 struct drm_device_dma *dma = dev->dma;
2157 drm_radeon_private_t *dev_priv = dev->dev_private;
2160 dev_priv->last_buf = 0;
2161 for (i = 0; i < dma->buf_count; i++) {
2162 struct drm_buf *buf = dma->buflist[i];
2163 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
2168 /* ================================================================
2169 * CP command submission
2172 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
2174 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
2176 u32 last_head = GET_RING_HEAD(dev_priv);
2178 for (i = 0; i < dev_priv->usec_timeout; i++) {
2179 u32 head = GET_RING_HEAD(dev_priv);
2181 ring->space = (head - ring->tail) * sizeof(u32);
2182 if (ring->space <= 0)
2183 ring->space += ring->size;
2184 if (ring->space > n)
2187 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
2189 if (head != last_head)
2196 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
2197 #if RADEON_FIFO_DEBUG
2198 radeon_status(dev_priv);
2199 DRM_ERROR("failed!\n");
2204 static int radeon_cp_get_buffers(struct drm_device *dev,
2205 struct drm_file *file_priv,
2209 struct drm_buf *buf;
2211 for (i = d->granted_count; i < d->request_count; i++) {
2212 buf = radeon_freelist_get(dev);
2214 return -EBUSY; /* NOTE: broken client */
2216 buf->file_priv = file_priv;
2218 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
2221 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
2222 sizeof(buf->total)))
2230 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
2232 struct drm_device_dma *dma = dev->dma;
2234 struct drm_dma *d = data;
2236 LOCK_TEST_WITH_RETURN(dev, file_priv);
2238 /* Please don't send us buffers.
2240 if (d->send_count != 0) {
2241 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
2242 DRM_CURRENTPID, d->send_count);
2246 /* We'll send you buffers.
2248 if (d->request_count < 0 || d->request_count > dma->buf_count) {
2249 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
2250 DRM_CURRENTPID, d->request_count, dma->buf_count);
2254 d->granted_count = 0;
2256 if (d->request_count) {
2257 ret = radeon_cp_get_buffers(dev, file_priv, d);
2263 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
2265 drm_radeon_private_t *dev_priv;
2268 dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
2269 if (dev_priv == NULL)
2272 memset(dev_priv, 0, sizeof(drm_radeon_private_t));
2273 dev->dev_private = (void *)dev_priv;
2274 dev_priv->flags = flags;
2276 switch (flags & RADEON_FAMILY_MASK) {
2284 dev_priv->flags |= RADEON_HAS_HIERZ;
2287 /* all other chips have no hierarchical z buffer */
2291 if (drm_device_is_agp(dev))
2292 dev_priv->flags |= RADEON_IS_AGP;
2293 else if (drm_device_is_pcie(dev))
2294 dev_priv->flags |= RADEON_IS_PCIE;
2296 dev_priv->flags |= RADEON_IS_PCI;
2298 DRM_DEBUG("%s card detected\n",
2299 ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
2303 /* Create mappings for registers and framebuffer so userland doesn't necessarily
2304 * have to find them.
2306 int radeon_driver_firstopen(struct drm_device *dev)
2309 drm_local_map_t *map;
2310 drm_radeon_private_t *dev_priv = dev->dev_private;
2312 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
2314 ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
2315 drm_get_resource_len(dev, 2), _DRM_REGISTERS,
2316 _DRM_READ_ONLY, &dev_priv->mmio);
2320 ret = drm_addmap(dev, drm_get_resource_start(dev, 0),
2321 drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
2322 _DRM_WRITE_COMBINING, &map);
2326 #ifdef RADEON_HAVE_BUFFER
2327 drm_bo_driver_init(dev);
2332 int radeon_driver_unload(struct drm_device *dev)
2334 drm_radeon_private_t *dev_priv = dev->dev_private;
2337 drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
2339 dev->dev_private = NULL;