shared-core/r300_cmdbuf.c

   1 /* r300_cmdbuf.c -- Command buffer emission for R300 -*- linux-c -*-
   2  *
   3  * Copyright (C) The Weather Channel, Inc.  2002.
   4  * Copyright (C) 2004 Nicolai Haehnle.
   5  * All Rights Reserved.
   6  *
   7  * The Weather Channel (TM) funded Tungsten Graphics to develop the
   8  * initial release of the Radeon 8500 driver under the XFree86 license.
   9  * This notice must be preserved.
  10  *
  11  * Permission is hereby granted, free of charge, to any person obtaining a
  12  * copy of this software and associated documentation files (the "Software"),
  13  * to deal in the Software without restriction, including without limitation
  14  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  15  * and/or sell copies of the Software, and to permit persons to whom the
  16  * Software is furnished to do so, subject to the following conditions:
  17  *
  18  * The above copyright notice and this permission notice (including the next
  19  * paragraph) shall be included in all copies or substantial portions of the
  20  * Software.
  21  *
  22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  25  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  26  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  27  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  28  * DEALINGS IN THE SOFTWARE.
  29  *
  30  * Authors:
  31  *    Nicolai Haehnle <prefect_@gmx.net>
  32  */
  33
  34 #include "drmP.h"
  35 #include "drm.h"
  36 #include "radeon_drm.h"
  37 #include "radeon_drv.h"
  38 #include "r300_reg.h"
  39
  40
  41 #define R300_SIMULTANEOUS_CLIPRECTS             4
  42
  43 /* Values for R300_RE_CLIPRECT_CNTL depending on the number of cliprects
  44  */
  45 static const int r300_cliprect_cntl[4] = {
  46         0xAAAA,
  47         0xEEEE,
  48         0xFEFE,
  49         0xFFFE
  50 };
  51
  52
  53 /**
  54  * Emit up to R300_SIMULTANEOUS_CLIPRECTS cliprects from the given command
  55  * buffer, starting with index n.
  56  */
  57 static int r300_emit_cliprects(drm_radeon_private_t* dev_priv,
  58                                drm_radeon_kcmd_buffer_t* cmdbuf,
  59                                int n)
  60 {
  61         drm_clip_rect_t box;
  62         int nr;
  63         int i;
  64         RING_LOCALS;
  65
  66         nr = cmdbuf->nbox - n;
  67         if (nr > R300_SIMULTANEOUS_CLIPRECTS)
  68                 nr = R300_SIMULTANEOUS_CLIPRECTS;
  69
  70         DRM_DEBUG("%i cliprects\n", nr);
  71
  72         if (nr) {
  73                 BEGIN_RING(6 + nr*2);
  74                 OUT_RING( CP_PACKET0( R300_RE_CLIPRECT_TL_0, nr*2 - 1 ) );
  75
  76                 for(i = 0; i < nr; ++i) {
  77                         if (DRM_COPY_FROM_USER_UNCHECKED(&box, &cmdbuf->boxes[n+i], sizeof(box))) {
  78                                 DRM_ERROR("copy cliprect faulted\n");
  79                                 return DRM_ERR(EFAULT);
  80                         }
  81
  82                         box.x1 = (box.x1 + R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK;
  83                         box.y1 = (box.y1 + R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK;
  84                         box.x2 = (box.x2 + R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK;
  85                         box.y2 = (box.y2 + R300_CLIPRECT_OFFSET) & R300_CLIPRECT_MASK;
  86
  87                         OUT_RING((box.x1 << R300_CLIPRECT_X_SHIFT) |
  88                                         (box.y1 << R300_CLIPRECT_Y_SHIFT));
  89                         OUT_RING((box.x2 << R300_CLIPRECT_X_SHIFT) |
  90                                         (box.y2 << R300_CLIPRECT_Y_SHIFT));
  91                 }
  92
  93                 OUT_RING_REG( R300_RE_CLIPRECT_CNTL, r300_cliprect_cntl[nr-1] );
  94
  95                 /* TODO/SECURITY: Force scissors to a safe value, otherwise the
  96                 * client might be able to trample over memory.
  97                 * The impact should be very limited, but I'd rather be safe than
  98                 * sorry.
  99                 */
 100                 OUT_RING( CP_PACKET0( R300_RE_SCISSORS_TL, 1 ) );
 101                 OUT_RING( 0 );
 102                 OUT_RING( R300_SCISSORS_X_MASK | R300_SCISSORS_Y_MASK );
 103                 ADVANCE_RING();
 104                 } else {
 105                 /* Why we allow zero cliprect rendering:
 106                  * There are some commands in a command buffer that must be submitted
 107                  * even when there are no cliprects, e.g. DMA buffer discard
 108                  * or state setting (though state setting could be avoided by
 109                  * simulating a loss of context).
 110                  *
 111                  * Now since the cmdbuf interface is so chaotic right now (and is
 112                  * bound to remain that way for a bit until things settle down),
 113                  * it is basically impossible to filter out the commands that are
 114                  * necessary and those that aren't.
 115                  *
 116                  * So I choose the safe way and don't do any filtering at all;
 117                  * instead, I simply set up the engine so that all rendering
 118                  * can't produce any fragments.
 119                  */
 120                 BEGIN_RING(2);
 121                 OUT_RING_REG( R300_RE_CLIPRECT_CNTL, 0 );
 122                 ADVANCE_RING();
 123                 }
 124
 125         return 0;
 126 }
 127
 128 static u8 r300_reg_flags[0x10000>>2];
 129
 130
 131 void r300_init_reg_flags(void)
 132 {
 133         int i;
 134         memset(r300_reg_flags, 0, 0x10000>>2);
 135         #define ADD_RANGE_MARK(reg, count,mark) \
 136                 for(i=((reg)>>2);i<((reg)>>2)+(count);i++)\
 137                         r300_reg_flags[i]|=(mark);
 138
 139         #define MARK_SAFE               1
 140         #define MARK_CHECK_OFFSET       2
 141
 142         #define ADD_RANGE(reg, count)   ADD_RANGE_MARK(reg, count, MARK_SAFE)
 143
 144         /* these match cmducs() command in r300_driver/r300/r300_cmdbuf.c */
 145         ADD_RANGE(R300_SE_VPORT_XSCALE, 6);
 146         ADD_RANGE(0x2080, 1);
 147         ADD_RANGE(R300_SE_VTE_CNTL, 2);
 148         ADD_RANGE(0x2134, 2);
 149         ADD_RANGE(0x2140, 1);
 150         ADD_RANGE(R300_VAP_INPUT_CNTL_0, 2);
 151         ADD_RANGE(0x21DC, 1);
 152         ADD_RANGE(0x221C, 1);
 153         ADD_RANGE(0x2220, 4);
 154         ADD_RANGE(0x2288, 1);
 155         ADD_RANGE(R300_VAP_OUTPUT_VTX_FMT_0, 2);
 156         ADD_RANGE(R300_VAP_PVS_CNTL_1, 3);
 157         ADD_RANGE(R300_GB_ENABLE, 1);
 158         ADD_RANGE(R300_GB_MSPOS0, 5);
 159         ADD_RANGE(R300_TX_ENABLE, 1);
 160         ADD_RANGE(0x4200, 4);
 161         ADD_RANGE(0x4214, 1);
 162         ADD_RANGE(R300_RE_POINTSIZE, 1);
 163         ADD_RANGE(0x4230, 3);
 164         ADD_RANGE(R300_RE_LINE_CNT, 1);
 165         ADD_RANGE(0x4238, 1);
 166         ADD_RANGE(0x4260, 3);
 167         ADD_RANGE(0x4274, 4);
 168         ADD_RANGE(0x4288, 5);
 169         ADD_RANGE(0x42A0, 1);
 170         ADD_RANGE(R300_RE_ZBIAS_T_FACTOR, 4);
 171         ADD_RANGE(0x42B4, 1);
 172         ADD_RANGE(R300_RE_CULL_CNTL, 1);
 173         ADD_RANGE(0x42C0, 2);
 174         ADD_RANGE(R300_RS_CNTL_0, 2);
 175         ADD_RANGE(R300_RS_INTERP_0, 8);
 176         ADD_RANGE(R300_RS_ROUTE_0, 8);
 177         ADD_RANGE(0x43A4, 2);
 178         ADD_RANGE(0x43E8, 1);
 179         ADD_RANGE(R300_PFS_CNTL_0, 3);
 180         ADD_RANGE(R300_PFS_NODE_0, 4);
 181         ADD_RANGE(R300_PFS_TEXI_0, 64);
 182         ADD_RANGE(0x46A4, 5);
 183         ADD_RANGE(R300_PFS_INSTR0_0, 64);
 184         ADD_RANGE(R300_PFS_INSTR1_0, 64);
 185         ADD_RANGE(R300_PFS_INSTR2_0, 64);
 186         ADD_RANGE(R300_PFS_INSTR3_0, 64);
 187         ADD_RANGE(0x4BC0, 1);
 188         ADD_RANGE(0x4BC8, 3);
 189         ADD_RANGE(R300_PP_ALPHA_TEST, 2);
 190         ADD_RANGE(0x4BD8, 1);
 191         ADD_RANGE(R300_PFS_PARAM_0_X, 64);
 192         ADD_RANGE(0x4E00, 1);
 193         ADD_RANGE(R300_RB3D_CBLEND, 2);
 194         ADD_RANGE(R300_RB3D_COLORMASK, 1);
 195         ADD_RANGE(0x4E10, 3);
 196         ADD_RANGE_MARK(R300_RB3D_COLOROFFSET0, 1, MARK_CHECK_OFFSET); /* check offset */
 197         ADD_RANGE(R300_RB3D_COLORPITCH0, 1);
 198         ADD_RANGE(0x4E50, 9);
 199         ADD_RANGE(0x4E88, 1);
 200         ADD_RANGE(0x4EA0, 2);
 201         ADD_RANGE(R300_RB3D_ZSTENCIL_CNTL_0, 3);
 202         ADD_RANGE(0x4F10, 4);
 203         ADD_RANGE_MARK(R300_RB3D_DEPTHOFFSET, 1, MARK_CHECK_OFFSET); /* check offset */
 204         ADD_RANGE(R300_RB3D_DEPTHPITCH, 1);
 205         ADD_RANGE(0x4F28, 1);
 206         ADD_RANGE(0x4F30, 2);
 207         ADD_RANGE(0x4F44, 1);
 208         ADD_RANGE(0x4F54, 1);
 209
 210         ADD_RANGE(R300_TX_FILTER_0, 16);
 211         ADD_RANGE(R300_TX_UNK1_0, 16);
 212         ADD_RANGE(R300_TX_SIZE_0, 16);
 213         ADD_RANGE(R300_TX_FORMAT_0, 16);
 214         ADD_RANGE(R300_TX_PITCH_0, 16);
 215                 /* Texture offset is dangerous and needs more checking */
 216         ADD_RANGE_MARK(R300_TX_OFFSET_0, 16, MARK_CHECK_OFFSET);
 217         ADD_RANGE(R300_TX_UNK4_0, 16);
 218         ADD_RANGE(R300_TX_BORDER_COLOR_0, 16);
 219
 220         /* Sporadic registers used as primitives are emitted */
 221         ADD_RANGE(0x4f18, 1);
 222         ADD_RANGE(R300_RB3D_DSTCACHE_CTLSTAT, 1);
 223         ADD_RANGE(R300_VAP_INPUT_ROUTE_0_0, 8);
 224         ADD_RANGE(R300_VAP_INPUT_ROUTE_1_0, 8);
 225
 226 }
 227
 228 static __inline__ int r300_check_range(unsigned  reg, int count)
 229 {
 230         int i;
 231         if(reg & ~0xffff)return -1;
 232         for(i=(reg>>2);i<(reg>>2)+count;i++)
 233                 if(r300_reg_flags[i]!=MARK_SAFE)return 1;
 234         return 0;
 235 }
 236
 237   /* we expect offsets passed to the framebuffer to be either within video memory or
 238       within AGP space */
 239 static __inline__ int r300_check_offset(drm_radeon_private_t* dev_priv, u32 offset)
 240 {
 241         /* we realy want to check against end of video aperture
 242                 but this value is not being kept.
 243                 This code is correct for now (does the same thing as the
 244                 code that sets MC_FB_LOCATION) in radeon_cp.c */
 245         if((offset>=dev_priv->fb_location) &&
 246                 (offset<dev_priv->gart_vm_start))return 0;
 247         if((offset>=dev_priv->gart_vm_start) &&
 248                  (offset<dev_priv->gart_vm_start+dev_priv->gart_size))return 0;
 249         return 1;
 250 }
 251
 252 static __inline__ int r300_emit_carefully_checked_packet0(drm_radeon_private_t *dev_priv,
 253                                                 drm_radeon_kcmd_buffer_t *cmdbuf,
 254                                                 drm_r300_cmd_header_t header)
 255 {
 256         int reg;
 257         int sz;
 258         int i;
 259         int values[64];
 260         RING_LOCALS;
 261
 262         sz = header.packet0.count;
 263         reg = (header.packet0.reghi << 8) | header.packet0.reglo;
 264
 265         if((sz>64)||(sz<0)){
 266                 DRM_ERROR("Cannot emit more than 64 values at a time (reg=%04x sz=%d)\n", reg, sz);
 267                 return DRM_ERR(EINVAL);
 268                 }
 269         for(i=0;i<sz;i++){
 270                 values[i]=((int *)cmdbuf->buf)[i];
 271                 switch(r300_reg_flags[(reg>>2)+i]){
 272                 case MARK_SAFE:
 273                         break;
 274                 case MARK_CHECK_OFFSET:
 275                         if(r300_check_offset(dev_priv, (u32)values[i])){
 276                                 DRM_ERROR("Offset failed range check (reg=%04x sz=%d)\n", reg, sz);
 277                                 return DRM_ERR(EINVAL);
 278                                 }
 279                         break;
 280                 default:
 281                         DRM_ERROR("Register %04x failed check as flag=%02x\n", reg+i*4, r300_reg_flags[(reg>>2)+i]);
 282                         return DRM_ERR(EINVAL);
 283                         }
 284                 }
 285
 286         BEGIN_RING(1+sz);
 287         OUT_RING( CP_PACKET0( reg, sz-1 ) );
 288         OUT_RING_TABLE( values, sz );
 289         ADVANCE_RING();
 290
 291         cmdbuf->buf += sz*4;
 292         cmdbuf->bufsz -= sz*4;
 293
 294         return 0;
 295 }
 296
 297 /**
 298  * Emits a packet0 setting arbitrary registers.
 299  * Called by r300_do_cp_cmdbuf.
 300  *
 301  * Note that checks are performed on contents and addresses of the registers
 302  */
 303 static __inline__ int r300_emit_packet0(drm_radeon_private_t *dev_priv,
 304                                         drm_radeon_kcmd_buffer_t *cmdbuf,
 305                                         drm_r300_cmd_header_t header)
 306 {
 307         int reg;
 308         int sz;
 309         RING_LOCALS;
 310
 311         sz = header.packet0.count;
 312         reg = (header.packet0.reghi << 8) | header.packet0.reglo;
 313
 314         if (!sz)
 315                 return 0;
 316
 317         if (sz*4 > cmdbuf->bufsz)
 318                 return DRM_ERR(EINVAL);
 319
 320         if (reg+sz*4 >= 0x10000){
 321                 DRM_ERROR("No such registers in hardware reg=%04x sz=%d\n", reg, sz);
 322                 return DRM_ERR(EINVAL);
 323                 }
 324
 325         if(r300_check_range(reg, sz)){
 326                 /* go and check everything */
 327                 return r300_emit_carefully_checked_packet0(dev_priv, cmdbuf, header);
 328                 }
 329         /* the rest of the data is safe to emit, whatever the values the user passed */
 330
 331         BEGIN_RING(1+sz);
 332         OUT_RING( CP_PACKET0( reg, sz-1 ) );
 333         OUT_RING_TABLE( (int *)cmdbuf->buf, sz );
 334         ADVANCE_RING();
 335
 336         cmdbuf->buf += sz*4;
 337         cmdbuf->bufsz -= sz*4;
 338
 339         return 0;
 340 }
 341
 342
 343 /**
 344  * Uploads user-supplied vertex program instructions or parameters onto
 345  * the graphics card.
 346  * Called by r300_do_cp_cmdbuf.
 347  */
 348 static __inline__ int r300_emit_vpu(drm_radeon_private_t *dev_priv,
 349                                     drm_radeon_kcmd_buffer_t *cmdbuf,
 350                                     drm_r300_cmd_header_t header)
 351 {
 352         int sz;
 353         int addr;
 354         RING_LOCALS;
 355
 356         sz = header.vpu.count;
 357         addr = (header.vpu.adrhi << 8) | header.vpu.adrlo;
 358
 359         if (!sz)
 360                 return 0;
 361         if (sz*16 > cmdbuf->bufsz)
 362                 return DRM_ERR(EINVAL);
 363
 364         BEGIN_RING(5+sz*4);
 365         /* Wait for VAP to come to senses.. */
 366         /* there is no need to emit it multiple times, (only once before VAP is programmed,
 367            but this optimization is for later */
 368         OUT_RING_REG( R300_VAP_PVS_WAITIDLE, 0 );
 369         OUT_RING_REG( R300_VAP_PVS_UPLOAD_ADDRESS, addr );
 370         OUT_RING( CP_PACKET0_TABLE( R300_VAP_PVS_UPLOAD_DATA, sz*4 - 1 ) );
 371         OUT_RING_TABLE((int *)cmdbuf->buf, sz*4);
 372
 373         ADVANCE_RING();
 374
 375         cmdbuf->buf += sz*16;
 376         cmdbuf->bufsz -= sz*16;
 377
 378         return 0;
 379 }
 380
 381
 382 /**
 383  * Emit a clear packet from userspace.
 384  * Called by r300_emit_packet3.
 385  */
 386 static __inline__ int r300_emit_clear(drm_radeon_private_t *dev_priv,
 387                                       drm_radeon_kcmd_buffer_t *cmdbuf)
 388 {
 389         RING_LOCALS;
 390
 391         if (8*4 > cmdbuf->bufsz)
 392                 return DRM_ERR(EINVAL);
 393
 394         BEGIN_RING(10);
 395         OUT_RING( CP_PACKET3( R200_3D_DRAW_IMMD_2, 8 ) );
 396         OUT_RING( R300_PRIM_TYPE_POINT|R300_PRIM_WALK_RING|
 397                   (1<<R300_PRIM_NUM_VERTICES_SHIFT) );
 398         OUT_RING_TABLE((int *)cmdbuf->buf, 8);
 399         ADVANCE_RING();
 400
 401         cmdbuf->buf += 8*4;
 402         cmdbuf->bufsz -= 8*4;
 403
 404         return 0;
 405 }
 406
 407 static __inline__ int r300_emit_3d_load_vbpntr(drm_radeon_private_t *dev_priv,
 408                                                drm_radeon_kcmd_buffer_t *cmdbuf,
 409                                                u32 header)
 410 {
 411         int count, i,k;
 412         #define MAX_ARRAY_PACKET  64
 413         u32 payload[MAX_ARRAY_PACKET];
 414         u32 narrays;
 415         RING_LOCALS;
 416
 417         count=(header>>16) & 0x3fff;
 418
 419         if((count+1)>MAX_ARRAY_PACKET){
 420                 DRM_ERROR("Too large payload in 3D_LOAD_VBPNTR (count=%d)\n", count);
 421                 return DRM_ERR(EINVAL);
 422                 }
 423         memset(payload, 0, MAX_ARRAY_PACKET*4);
 424         memcpy(payload, cmdbuf->buf+4, (count+1)*4);
 425
 426         /* carefully check packet contents */
 427
 428         narrays=payload[0];
 429         k=0;
 430         i=1;
 431         while((k<narrays) && (i<(count+1))){
 432                 i++; /* skip attribute field */
 433                 if(r300_check_offset(dev_priv, payload[i])){
 434                         DRM_ERROR("Offset failed range check (k=%d i=%d) while processing 3D_LOAD_VBPNTR packet.\n", k, i);
 435                         return DRM_ERR(EINVAL);
 436                         }
 437                 k++;
 438                 i++;
 439                 if(k==narrays)break;
 440                 /* have one more to process, they come in pairs */
 441                 if(r300_check_offset(dev_priv, payload[i])){
 442                         DRM_ERROR("Offset failed range check (k=%d i=%d) while processing 3D_LOAD_VBPNTR packet.\n", k, i);
 443                         return DRM_ERR(EINVAL);
 444                         }
 445                 k++;
 446                 i++;
 447                 }
 448         /* do the counts match what we expect ? */
 449         if((k!=narrays) || (i!=(count+1))){
 450                 DRM_ERROR("Malformed 3D_LOAD_VBPNTR packet (k=%d i=%d narrays=%d count+1=%d).\n", k, i, narrays, count+1);
 451                 return DRM_ERR(EINVAL);
 452                 }
 453
 454         /* all clear, output packet */
 455
 456         BEGIN_RING(count+2);
 457         OUT_RING(header);
 458         OUT_RING_TABLE(payload, count+1);
 459         ADVANCE_RING();
 460
 461         cmdbuf->buf += (count+2)*4;
 462         cmdbuf->bufsz -= (count+2)*4;
 463
 464         return 0;
 465 }
 466
 467 static __inline__ int r300_emit_raw_packet3(drm_radeon_private_t *dev_priv,
 468                                       drm_radeon_kcmd_buffer_t *cmdbuf)
 469 {
 470         u32 header;
 471         int count;
 472         RING_LOCALS;
 473
 474         if (4 > cmdbuf->bufsz)
 475                 return DRM_ERR(EINVAL);
 476
 477         /* Fixme !! This simply emits a packet without much checking.
 478            We need to be smarter. */
 479
 480         /* obtain first word - actual packet3 header */
 481         header = *(u32 *)cmdbuf->buf;
 482
 483         /* Is it packet 3 ? */
 484         if( (header>>30)!=0x3 ) {
 485                 DRM_ERROR("Not a packet3 header (0x%08x)\n", header);
 486                 return DRM_ERR(EINVAL);
 487                 }
 488
 489         count=(header>>16) & 0x3fff;
 490
 491         /* Check again now that we know how much data to expect */
 492         if ((count+2)*4 > cmdbuf->bufsz){
 493                 DRM_ERROR("Expected packet3 of length %d but have only %d bytes left\n",
 494                         (count+2)*4, cmdbuf->bufsz);
 495                 return DRM_ERR(EINVAL);
 496                 }
 497
 498         /* Is it a packet type we know about ? */
 499         switch(header & 0xff00){
 500         case RADEON_3D_LOAD_VBPNTR: /* load vertex array pointers */
 501                 return r300_emit_3d_load_vbpntr(dev_priv, cmdbuf, header);
 502
 503         case RADEON_CP_3D_DRAW_IMMD_2: /* triggers drawing using in-packet vertex data */
 504         case RADEON_CP_3D_DRAW_VBUF_2: /* triggers drawing of vertex buffers setup elsewhere */
 505         case RADEON_CP_3D_DRAW_INDX_2: /* triggers drawing using indices to vertex buffer */
 506         case RADEON_CP_INDX_BUFFER: /* DRAW_INDX_2 without INDX_BUFFER seems to lock up the gpu */
 507         case RADEON_WAIT_FOR_IDLE:
 508         case RADEON_CP_NOP:
 509                 /* these packets are safe */
 510                 break;
 511         default:
 512                 DRM_ERROR("Unknown packet3 header (0x%08x)\n", header);
 513                 return DRM_ERR(EINVAL);
 514                 }
 515
 516
 517         BEGIN_RING(count+2);
 518         OUT_RING(header);
 519         OUT_RING_TABLE((int *)(cmdbuf->buf + 4), count + 1);
 520         ADVANCE_RING();
 521
 522         cmdbuf->buf += (count+2)*4;
 523         cmdbuf->bufsz -= (count+2)*4;
 524
 525         return 0;
 526 }
 527
 528
 529 /**
 530  * Emit a rendering packet3 from userspace.
 531  * Called by r300_do_cp_cmdbuf.
 532  */
 533 static __inline__ int r300_emit_packet3(drm_radeon_private_t *dev_priv,
 534                                         drm_radeon_kcmd_buffer_t *cmdbuf,
 535                                         drm_r300_cmd_header_t header)
 536 {
 537         int n;
 538         int ret;
 539         char *orig_buf = cmdbuf->buf;
 540         int orig_bufsz = cmdbuf->bufsz;
 541
 542         /* This is a do-while-loop so that we run the interior at least once,
 543          * even if cmdbuf->nbox is 0. Compare r300_emit_cliprects for rationale.
 544          */
 545         n = 0;
 546         do {
 547                 if (cmdbuf->nbox > R300_SIMULTANEOUS_CLIPRECTS) {
 548                         ret = r300_emit_cliprects(dev_priv, cmdbuf, n);
 549                         if (ret)
 550                                 return ret;
 551
 552                         cmdbuf->buf = orig_buf;
 553                         cmdbuf->bufsz = orig_bufsz;
 554                         }
 555
 556                 switch(header.packet3.packet) {
 557                 case R300_CMD_PACKET3_CLEAR:
 558                         DRM_DEBUG("R300_CMD_PACKET3_CLEAR\n");
 559                         ret = r300_emit_clear(dev_priv, cmdbuf);
 560                         if (ret) {
 561                                 DRM_ERROR("r300_emit_clear failed\n");
 562                                 return ret;
 563                                 }
 564                         break;
 565
 566                 case R300_CMD_PACKET3_RAW:
 567                         DRM_DEBUG("R300_CMD_PACKET3_RAW\n");
 568                         ret = r300_emit_raw_packet3(dev_priv, cmdbuf);
 569                         if (ret) {
 570                                 DRM_ERROR("r300_emit_raw_packet3 failed\n");
 571                                 return ret;
 572                                 }
 573                         break;
 574
 575                 default:
 576                         DRM_ERROR("bad packet3 type %i at %p\n",
 577                                 header.packet3.packet,
 578                                 cmdbuf->buf - sizeof(header));
 579                         return DRM_ERR(EINVAL);
 580                         }
 581
 582                 n += R300_SIMULTANEOUS_CLIPRECTS;
 583         } while(n < cmdbuf->nbox);
 584
 585         return 0;
 586 }
 587
 588 /* Some of the R300 chips seem to be extremely touchy about the two registers
 589  * that are configured in r300_pacify.
 590  * Among the worst offenders seems to be the R300 ND (0x4E44): When userspace
 591  * sends a command buffer that contains only state setting commands and a
 592  * vertex program/parameter upload sequence, this will eventually lead to a
 593  * lockup, unless the sequence is bracketed by calls to r300_pacify.
 594  * So we should take great care to *always* call r300_pacify before
 595  * *anything* 3D related, and again afterwards. This is what the
 596  * call bracket in r300_do_cp_cmdbuf is for.
 597  */
 598
 599 /**
 600  * Emit the sequence to pacify R300.
 601  */
 602 static __inline__ void r300_pacify(drm_radeon_private_t* dev_priv)
 603 {
 604         RING_LOCALS;
 605
 606         BEGIN_RING(6);
 607         OUT_RING( CP_PACKET0( R300_RB3D_DSTCACHE_CTLSTAT, 0 ) );
 608         OUT_RING( 0xa );
 609         OUT_RING( CP_PACKET0( 0x4f18, 0 ) );
 610         OUT_RING( 0x3 );
 611         OUT_RING( CP_PACKET3( RADEON_CP_NOP, 0 ) );
 612         OUT_RING( 0x0 );
 613         ADVANCE_RING();
 614 }
 615
 616
 617 /**
 618  * Called by r300_do_cp_cmdbuf to update the internal buffer age and state.
 619  * The actual age emit is done by r300_do_cp_cmdbuf, which is why you must
 620  * be careful about how this function is called.
 621  */
 622 static void r300_discard_buffer(drm_device_t * dev, drm_buf_t * buf)
 623 {
 624         drm_radeon_private_t *dev_priv = dev->dev_private;
 625         drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
 626
 627         buf_priv->age = ++dev_priv->sarea_priv->last_dispatch;
 628         buf->pending = 1;
 629         buf->used = 0;
 630 }
 631
 632
 633 /**
 634  * Parses and validates a user-supplied command buffer and emits appropriate
 635  * commands on the DMA ring buffer.
 636  * Called by the ioctl handler function radeon_cp_cmdbuf.
 637  */
 638 int r300_do_cp_cmdbuf(drm_device_t* dev,
 639                       DRMFILE filp,
 640                       drm_file_t* filp_priv,
 641                       drm_radeon_kcmd_buffer_t* cmdbuf)
 642 {
 643         drm_radeon_private_t *dev_priv = dev->dev_private;
 644         drm_device_dma_t *dma = dev->dma;
 645         drm_buf_t *buf = NULL;
 646         int emit_dispatch_age = 0;
 647         int ret = 0;
 648
 649         DRM_DEBUG("\n");
 650
 651         /* See the comment above r300_emit_begin3d for why this call must be here,
 652          * and what the cleanup gotos are for. */
 653         r300_pacify(dev_priv);
 654
 655         if (cmdbuf->nbox <= R300_SIMULTANEOUS_CLIPRECTS) {
 656                 ret = r300_emit_cliprects(dev_priv, cmdbuf, 0);
 657                 if (ret)
 658                         goto cleanup;
 659                 }
 660
 661         while(cmdbuf->bufsz >= sizeof(drm_r300_cmd_header_t)) {
 662                 int idx;
 663                 drm_r300_cmd_header_t header;
 664
 665                 header.u = *(unsigned int *)cmdbuf->buf;
 666
 667                 cmdbuf->buf += sizeof(header);
 668                 cmdbuf->bufsz -= sizeof(header);
 669
 670                 switch(header.header.cmd_type) {
 671                 case R300_CMD_PACKET0:
 672                         DRM_DEBUG("R300_CMD_PACKET0\n");
 673                         ret = r300_emit_packet0(dev_priv, cmdbuf, header);
 674                         if (ret) {
 675                                 DRM_ERROR("r300_emit_packet0 failed\n");
 676                                 goto cleanup;
 677                                 }
 678                         break;
 679
 680                 case R300_CMD_VPU:
 681                         DRM_DEBUG("R300_CMD_VPU\n");
 682                         ret = r300_emit_vpu(dev_priv, cmdbuf, header);
 683                         if (ret) {
 684                                 DRM_ERROR("r300_emit_vpu failed\n");
 685                                 goto cleanup;
 686                                 }
 687                         break;
 688
 689                 case R300_CMD_PACKET3:
 690                         DRM_DEBUG("R300_CMD_PACKET3\n");
 691                         ret = r300_emit_packet3(dev_priv, cmdbuf, header);
 692                         if (ret) {
 693                                 DRM_ERROR("r300_emit_packet3 failed\n");
 694                                 goto cleanup;
 695                                 }
 696                         break;
 697
 698                 case R300_CMD_END3D:
 699                         DRM_DEBUG("R300_CMD_END3D\n");
 700                         /* TODO:
 701                                 Ideally userspace driver should not need to issue this call,
 702                                 i.e. the drm driver should issue it automatically and prevent
 703                                 lockups.
 704
 705                                 In practice, we do not understand why this call is needed and what
 706                                 it does (except for some vague guesses that it has to do with cache
 707                                 coherence) and so the user space driver does it.
 708
 709                                 Once we are sure which uses prevent lockups the code could be moved
 710                                 into the kernel and the userspace driver will not
 711                                 need to use this command.
 712
 713                                 Note that issuing this command does not hurt anything
 714                                 except, possibly, performance */
 715                         r300_pacify(dev_priv);
 716                         break;
 717
 718                 case R300_CMD_CP_DELAY:
 719                         /* simple enough, we can do it here */
 720                         DRM_DEBUG("R300_CMD_CP_DELAY\n");
 721                         {
 722                                 int i;
 723                                 RING_LOCALS;
 724
 725                                 BEGIN_RING(header.delay.count);
 726                                 for(i=0;i<header.delay.count;i++)
 727                                         OUT_RING(RADEON_CP_PACKET2);
 728                                 ADVANCE_RING();
 729                         }
 730                         break;
 731
 732                 case R300_CMD_DMA_DISCARD:
 733                         DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n");
 734                         idx = header.dma.buf_idx;
 735                         if (idx < 0 || idx >= dma->buf_count) {
 736                                 DRM_ERROR("buffer index %d (of %d max)\n",
 737                                         idx, dma->buf_count - 1);
 738                                 ret = DRM_ERR(EINVAL);
 739                                 goto cleanup;
 740                                 }
 741
 742                         buf = dma->buflist[idx];
 743                         if (buf->filp != filp || buf->pending) {
 744                                 DRM_ERROR("bad buffer %p %p %d\n",
 745                                 buf->filp, filp, buf->pending);
 746                                 ret = DRM_ERR(EINVAL);
 747                                 goto cleanup;
 748                                 }
 749
 750                         emit_dispatch_age = 1;
 751                         r300_discard_buffer(dev, buf);
 752                         break;
 753
 754                 case R300_CMD_WAIT:
 755                         /* simple enough, we can do it here */
 756                         DRM_DEBUG("R300_CMD_WAIT\n");
 757                         if(header.wait.flags==0)break; /* nothing to do */
 758
 759                         {
 760                                 RING_LOCALS;
 761
 762                                 BEGIN_RING(2);
 763                                 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) );
 764                                 OUT_RING( (header.wait.flags & 0xf)<<14 );
 765                                 ADVANCE_RING();
 766                         }
 767                         break;
 768
 769                 default:
 770                         DRM_ERROR("bad cmd_type %i at %p\n",
 771                                   header.header.cmd_type,
 772                                   cmdbuf->buf - sizeof(header));
 773                         ret = DRM_ERR(EINVAL);
 774                         goto cleanup;
 775                         }
 776         }
 777
 778         DRM_DEBUG("END\n");
 779
 780 cleanup:
 781         r300_pacify(dev_priv);
 782
 783         /* We emit the vertex buffer age here, outside the pacifier "brackets"
 784          * for two reasons:
 785          *  (1) This may coalesce multiple age emissions into a single one and
 786          *  (2) more importantly, some chips lock up hard when scratch registers
 787          *      are written inside the pacifier bracket.
 788          */
 789         if (emit_dispatch_age) {
 790                 RING_LOCALS;
 791
 792                 /* Emit the vertex buffer age */
 793                 BEGIN_RING(2);
 794                 RADEON_DISPATCH_AGE(dev_priv->sarea_priv->last_dispatch);
 795                 ADVANCE_RING();
 796                 }
 797
 798         COMMIT_RING();
 799
 800         return ret;
 801 }
 802