shared-core/r300_cmdbuf.c

   1 /* r300_cmdbuf.c -- Command buffer emission for R300 -*- linux-c -*-
   2  *
   3  * Copyright (C) The Weather Channel, Inc.  2002.
   4  * Copyright (C) 2004 Nicolai Haehnle.
   5  * All Rights Reserved.
   6  *
   7  * The Weather Channel (TM) funded Tungsten Graphics to develop the
   8  * initial release of the Radeon 8500 driver under the XFree86 license.
   9  * This notice must be preserved.
  10  *
  11  * Permission is hereby granted, free of charge, to any person obtaining a
  12  * copy of this software and associated documentation files (the "Software"),
  13  * to deal in the Software without restriction, including without limitation
  14  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  15  * and/or sell copies of the Software, and to permit persons to whom the
  16  * Software is furnished to do so, subject to the following conditions:
  17  *
  18  * The above copyright notice and this permission notice (including the next
  19  * paragraph) shall be included in all copies or substantial portions of the
  20  * Software.
  21  *
  22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  25  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  26  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  27  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  28  * DEALINGS IN THE SOFTWARE.
  29  *
  30  * Authors:
  31  *    Nicolai Haehnle <prefect_@gmx.net>
  32  */
  33
  34 #include "drmP.h"
  35 #include "drm.h"
  36 #include "radeon_drm.h"
  37 #include "radeon_drv.h"
  38 #include "r300_reg.h"
  39
  40 #define R300_SIMULTANEOUS_CLIPRECTS             4
  41
  42 /* Values for R300_RE_CLIPRECT_CNTL depending on the number of cliprects
  43  */
  44 static const int r300_cliprect_cntl[4] = {
  45         0xAAAA,
  46         0xEEEE,
  47         0xFEFE,
  48         0xFFFE
  49 };
  50
  51 /**
  52  * Emit up to R300_SIMULTANEOUS_CLIPRECTS cliprects from the given command
  53  * buffer, starting with index n.
  54  */
  55 static int r300_emit_cliprects(drm_radeon_private_t *dev_priv,
  56                                drm_radeon_kcmd_buffer_t *cmdbuf, int n)
  57 {
  58         struct drm_clip_rect box;
  59         int nr;
  60         int i;
  61         RING_LOCALS;
  62
  63         nr = cmdbuf->nbox - n;
  64         if (nr > R300_SIMULTANEOUS_CLIPRECTS)
  65                 nr = R300_SIMULTANEOUS_CLIPRECTS;
  66
  67         DRM_DEBUG("%i cliprects\n", nr);
  68
  69         if (nr) {
  70                 BEGIN_RING(6 + nr * 2);
  71                 OUT_RING(CP_PACKET0(R300_RE_CLIPRECT_TL_0, nr * 2 - 1));
  72
  73                 for (i = 0; i < nr; ++i) {
  74                         if (DRM_COPY_FROM_USER_UNCHECKED
  75                             (&box, &cmdbuf->boxes[n + i], sizeof(box))) {
  76                                 DRM_ERROR("copy cliprect faulted\n");
  77                                 return -EFAULT;
  78                         }
  79
  80                         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
  81                                 box.x1 = (box.x1) &
  82                                         R300_CLIPRECT_MASK;
  83                                 box.y1 = (box.y1) &
  84                                         R300_CLIPRECT_MASK;
  85                                 box.x2 = (box.x2) &
  86                                         R300_CLIPRECT_MASK;
  87                                 box.y2 = (box.y2) &
  88                                         R300_CLIPRECT_MASK;
  89                         } else {
  90                                 box.x1 = (box.x1 + R300_CLIPRECT_OFFSET) &
  91                                         R300_CLIPRECT_MASK;
  92                                 box.y1 = (box.y1 + R300_CLIPRECT_OFFSET) &
  93                                         R300_CLIPRECT_MASK;
  94                                 box.x2 = (box.x2 + R300_CLIPRECT_OFFSET) &
  95                                         R300_CLIPRECT_MASK;
  96                                 box.y2 = (box.y2 + R300_CLIPRECT_OFFSET) &
  97                                         R300_CLIPRECT_MASK;
  98
  99                         }
 100                         OUT_RING((box.x1 << R300_CLIPRECT_X_SHIFT) |
 101                                  (box.y1 << R300_CLIPRECT_Y_SHIFT));
 102                         OUT_RING((box.x2 << R300_CLIPRECT_X_SHIFT) |
 103                                  (box.y2 << R300_CLIPRECT_Y_SHIFT));
 104
 105                 }
 106
 107                 OUT_RING_REG(R300_RE_CLIPRECT_CNTL, r300_cliprect_cntl[nr - 1]);
 108
 109                 /* TODO/SECURITY: Force scissors to a safe value, otherwise the
 110                  * client might be able to trample over memory.
 111                  * The impact should be very limited, but I'd rather be safe than
 112                  * sorry.
 113                  */
 114                 OUT_RING(CP_PACKET0(R300_RE_SCISSORS_TL, 1));
 115                 OUT_RING(0);
 116                 OUT_RING(R300_SCISSORS_X_MASK | R300_SCISSORS_Y_MASK);
 117                 ADVANCE_RING();
 118         } else {
 119                 /* Why we allow zero cliprect rendering:
 120                  * There are some commands in a command buffer that must be submitted
 121                  * even when there are no cliprects, e.g. DMA buffer discard
 122                  * or state setting (though state setting could be avoided by
 123                  * simulating a loss of context).
 124                  *
 125                  * Now since the cmdbuf interface is so chaotic right now (and is
 126                  * bound to remain that way for a bit until things settle down),
 127                  * it is basically impossible to filter out the commands that are
 128                  * necessary and those that aren't.
 129                  *
 130                  * So I choose the safe way and don't do any filtering at all;
 131                  * instead, I simply set up the engine so that all rendering
 132                  * can't produce any fragments.
 133                  */
 134                 BEGIN_RING(2);
 135                 OUT_RING_REG(R300_RE_CLIPRECT_CNTL, 0);
 136                 ADVANCE_RING();
 137         }
 138
 139         return 0;
 140 }
 141
 142 static u8 r300_reg_flags[0x10000 >> 2];
 143
 144 void r300_init_reg_flags(struct drm_device *dev)
 145 {
 146         int i;
 147         drm_radeon_private_t *dev_priv = dev->dev_private;
 148
 149         memset(r300_reg_flags, 0, 0x10000 >> 2);
 150 #define ADD_RANGE_MARK(reg, count,mark) \
 151                 for(i=((reg)>>2);i<((reg)>>2)+(count);i++)\
 152                         r300_reg_flags[i]|=(mark);
 153
 154
 155 #define ADD_RANGE(reg, count)   ADD_RANGE_MARK(reg, count, MARK_SAFE)
 156
 157         /* these match cmducs() command in r300_driver/r300/r300_cmdbuf.c */
 158         ADD_RANGE(R300_SE_VPORT_XSCALE, 6);
 159         ADD_RANGE(R300_VAP_CNTL, 1);
 160         ADD_RANGE(R300_SE_VTE_CNTL, 2);
 161         ADD_RANGE(0x2134, 2);
 162         ADD_RANGE(R300_VAP_CNTL_STATUS, 1);
 163         ADD_RANGE(R300_VAP_INPUT_CNTL_0, 2);
 164         ADD_RANGE(0x21DC, 1);
 165         ADD_RANGE(R300_VAP_UNKNOWN_221C, 1);
 166         ADD_RANGE(R300_VAP_CLIP_X_0, 4);
 167         ADD_RANGE(R300_VAP_PVS_WAITIDLE, 1);
 168         ADD_RANGE(R300_VAP_UNKNOWN_2288, 1);
 169         ADD_RANGE(R300_VAP_OUTPUT_VTX_FMT_0, 2);
 170         ADD_RANGE(R300_VAP_PVS_CNTL_1, 3);
 171         ADD_RANGE(R300_GB_ENABLE, 1);
 172         ADD_RANGE(R300_GB_MSPOS0, 5);
 173         ADD_RANGE(R300_TX_CNTL, 1);
 174         ADD_RANGE(R300_TX_ENABLE, 1);
 175         ADD_RANGE(0x4200, 4);
 176         ADD_RANGE(0x4214, 1);
 177         ADD_RANGE(R300_RE_POINTSIZE, 1);
 178         ADD_RANGE(0x4230, 3);
 179         ADD_RANGE(R300_RE_LINE_CNT, 1);
 180         ADD_RANGE(R300_RE_UNK4238, 1);
 181         ADD_RANGE(0x4260, 3);
 182         ADD_RANGE(R300_RE_SHADE, 4);
 183         ADD_RANGE(R300_RE_POLYGON_MODE, 5);
 184         ADD_RANGE(R300_RE_ZBIAS_CNTL, 1);
 185         ADD_RANGE(R300_RE_ZBIAS_T_FACTOR, 4);
 186         ADD_RANGE(R300_RE_OCCLUSION_CNTL, 1);
 187         ADD_RANGE(R300_RE_CULL_CNTL, 1);
 188         ADD_RANGE(0x42C0, 2);
 189         ADD_RANGE(R300_RS_CNTL_0, 2);
 190
 191         ADD_RANGE(0x43A4, 2);
 192         ADD_RANGE(0x43E8, 1);
 193
 194         ADD_RANGE(0x46A4, 5);
 195
 196         ADD_RANGE(R300_RE_FOG_STATE, 1);
 197         ADD_RANGE(R300_FOG_COLOR_R, 3);
 198         ADD_RANGE(R300_PP_ALPHA_TEST, 2);
 199         ADD_RANGE(0x4BD8, 1);
 200         ADD_RANGE(R300_PFS_PARAM_0_X, 64);
 201         ADD_RANGE(0x4E00, 1);
 202         ADD_RANGE(R300_RB3D_CBLEND, 2);
 203         ADD_RANGE(R300_RB3D_COLORMASK, 1);
 204         ADD_RANGE(R300_RB3D_BLEND_COLOR, 3);
 205         ADD_RANGE_MARK(R300_RB3D_COLOROFFSET0, 1, MARK_CHECK_OFFSET);   /* check offset */
 206         ADD_RANGE(R300_RB3D_COLORPITCH0, 1);
 207         ADD_RANGE(0x4E50, 9);
 208         ADD_RANGE(0x4E88, 1);
 209         ADD_RANGE(0x4EA0, 2);
 210         ADD_RANGE(R300_RB3D_ZSTENCIL_CNTL_0, 3);
 211         ADD_RANGE(R300_RB3D_ZSTENCIL_FORMAT, 4);
 212         ADD_RANGE_MARK(R300_RB3D_DEPTHOFFSET, 1, MARK_CHECK_OFFSET);    /* check offset */
 213         ADD_RANGE(R300_RB3D_DEPTHPITCH, 1);
 214         ADD_RANGE(0x4F28, 1);
 215         ADD_RANGE(0x4F30, 2);
 216         ADD_RANGE(0x4F44, 1);
 217         ADD_RANGE(0x4F54, 1);
 218
 219         ADD_RANGE(R300_TX_FILTER_0, 16);
 220         ADD_RANGE(R300_TX_FILTER1_0, 16);
 221         ADD_RANGE(R300_TX_SIZE_0, 16);
 222         ADD_RANGE(R300_TX_FORMAT_0, 16);
 223         ADD_RANGE(R300_TX_PITCH_0, 16);
 224         /* Texture offset is dangerous and needs more checking */
 225         ADD_RANGE_MARK(R300_TX_OFFSET_0, 16, MARK_CHECK_OFFSET);
 226         ADD_RANGE(R300_TX_CHROMA_KEY_0, 16);
 227         ADD_RANGE(R300_TX_BORDER_COLOR_0, 16);
 228
 229         /* Sporadic registers used as primitives are emitted */
 230         ADD_RANGE(R300_RB3D_ZCACHE_CTLSTAT, 1);
 231         ADD_RANGE(R300_RB3D_DSTCACHE_CTLSTAT, 1);
 232         ADD_RANGE(R300_VAP_INPUT_ROUTE_0_0, 8);
 233         ADD_RANGE(R300_VAP_INPUT_ROUTE_1_0, 8);
 234
 235         ADD_RANGE(R500_SU_REG_DEST, 1);
 236         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV410) {
 237                 ADD_RANGE(R300_DST_PIPE_CONFIG, 1);
 238         }
 239
 240         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
 241                 ADD_RANGE(R500_VAP_INDEX_OFFSET, 1);
 242                 ADD_RANGE(R500_US_CONFIG, 2);
 243                 ADD_RANGE(R500_US_CODE_ADDR, 3);
 244                 ADD_RANGE(R500_US_FC_CTRL, 1);
 245                 ADD_RANGE(R500_RS_IP_0, 16);
 246                 ADD_RANGE(R500_RS_INST_0, 16);
 247                 ADD_RANGE(R500_RB3D_COLOR_CLEAR_VALUE_AR, 2);
 248                 ADD_RANGE(R500_RB3D_CONSTANT_COLOR_AR, 2);
 249
 250                 ADD_RANGE(R500_GA_US_VECTOR_INDEX, 2);
 251         } else {
 252                 ADD_RANGE(R300_PFS_CNTL_0, 3);
 253                 ADD_RANGE(R300_PFS_NODE_0, 4);
 254                 ADD_RANGE(R300_PFS_TEXI_0, 64);
 255                 ADD_RANGE(R300_PFS_INSTR0_0, 64);
 256                 ADD_RANGE(R300_PFS_INSTR1_0, 64);
 257                 ADD_RANGE(R300_PFS_INSTR2_0, 64);
 258                 ADD_RANGE(R300_PFS_INSTR3_0, 64);
 259                 ADD_RANGE(R300_RS_INTERP_0, 8);
 260                 ADD_RANGE(R300_RS_ROUTE_0, 8);
 261
 262         }
 263
 264         /* add 2d blit engine registers for DDX */
 265         ADD_RANGE(RADEON_SRC_Y_X, 3); /* 1434, 1438, 143c,
 266                                          SRC_Y_X, DST_Y_X, DST_HEIGHT_WIDTH
 267                                        */
 268         ADD_RANGE(RADEON_DP_GUI_MASTER_CNTL, 1); /* 146c */
 269         ADD_RANGE(RADEON_DP_BRUSH_BKGD_CLR, 2); /* 1478, 147c */
 270         ADD_RANGE(RADEON_DP_SRC_FRGD_CLR, 2); /* 15d8, 15dc */
 271         ADD_RANGE(RADEON_DP_CNTL, 1); /* 16c0 */
 272         ADD_RANGE(RADEON_DP_WRITE_MASK, 1); /* 16cc */
 273         ADD_RANGE(RADEON_DEFAULT_SC_BOTTOM_RIGHT, 1); /* 16e8 */
 274
 275         ADD_RANGE(RADEON_DSTCACHE_CTLSTAT, 1);
 276         ADD_RANGE(RADEON_WAIT_UNTIL, 1);
 277
 278         ADD_RANGE_MARK(RADEON_DST_OFFSET, 1, MARK_CHECK_OFFSET);
 279         ADD_RANGE_MARK(RADEON_SRC_OFFSET, 1, MARK_CHECK_OFFSET);
 280
 281         ADD_RANGE_MARK(RADEON_DST_PITCH_OFFSET, 1, MARK_CHECK_OFFSET);
 282         ADD_RANGE_MARK(RADEON_SRC_PITCH_OFFSET, 1, MARK_CHECK_OFFSET);
 283
 284         /* TODO SCISSOR */
 285         ADD_RANGE_MARK(R300_SC_SCISSOR0, 2, MARK_CHECK_SCISSOR);
 286
 287         ADD_RANGE(R300_SC_CLIP_0_A, 2);
 288         ADD_RANGE(R300_SC_CLIP_RULE, 1);
 289         ADD_RANGE(R300_SC_SCREENDOOR, 1);
 290
 291         ADD_RANGE(R300_VAP_PVS_CODE_CNTL_0, 4);
 292         ADD_RANGE(R300_VAP_PVS_VECTOR_INDX_REG, 2);
 293 }
 294
 295 int r300_check_range(unsigned reg, int count)
 296 {
 297         int i;
 298         if (reg & ~0xffff)
 299                 return -1;
 300         for (i = (reg >> 2); i < (reg >> 2) + count; i++)
 301                 if (r300_reg_flags[i] != MARK_SAFE)
 302                         return 1;
 303         return 0;
 304 }
 305
 306 int r300_get_reg_flags(unsigned reg)
 307 {
 308         if (reg & ~0xffff)
 309                 return -1;
 310         return r300_reg_flags[(reg >> 2)];
 311 }
 312
 313 static __inline__ int r300_emit_carefully_checked_packet0(drm_radeon_private_t *
 314                                                           dev_priv,
 315                                                           drm_radeon_kcmd_buffer_t
 316                                                           * cmdbuf,
 317                                                           drm_r300_cmd_header_t
 318                                                           header)
 319 {
 320         int reg;
 321         int sz;
 322         int i;
 323         int values[64];
 324         RING_LOCALS;
 325
 326         sz = header.packet0.count;
 327         reg = (header.packet0.reghi << 8) | header.packet0.reglo;
 328
 329         if ((sz > 64) || (sz < 0)) {
 330                 DRM_ERROR
 331                     ("Cannot emit more than 64 values at a time (reg=%04x sz=%d)\n",
 332                      reg, sz);
 333                 return -EINVAL;
 334         }
 335         for (i = 0; i < sz; i++) {
 336                 values[i] = ((int *)cmdbuf->buf)[i];
 337                 switch (r300_reg_flags[(reg >> 2) + i]) {
 338                 case MARK_SAFE:
 339                         break;
 340                 case MARK_CHECK_OFFSET:
 341                         if (!radeon_check_offset(dev_priv, (u32) values[i])) {
 342                                 DRM_ERROR
 343                                     ("Offset failed range check (reg=%04x sz=%d)\n",
 344                                      reg, sz);
 345                                 return -EINVAL;
 346                         }
 347                         break;
 348                 default:
 349                         DRM_ERROR("Register %04x failed check as flag=%02x\n",
 350                                   reg + i * 4, r300_reg_flags[(reg >> 2) + i]);
 351                         return -EINVAL;
 352                 }
 353         }
 354
 355         BEGIN_RING(1 + sz);
 356         OUT_RING(CP_PACKET0(reg, sz - 1));
 357         OUT_RING_TABLE(values, sz);
 358         ADVANCE_RING();
 359
 360         cmdbuf->buf += sz * 4;
 361         cmdbuf->bufsz -= sz * 4;
 362
 363         return 0;
 364 }
 365
 366 /**
 367  * Emits a packet0 setting arbitrary registers.
 368  * Called by r300_do_cp_cmdbuf.
 369  *
 370  * Note that checks are performed on contents and addresses of the registers
 371  */
 372 static __inline__ int r300_emit_packet0(drm_radeon_private_t *dev_priv,
 373                                         drm_radeon_kcmd_buffer_t *cmdbuf,
 374                                         drm_r300_cmd_header_t header)
 375 {
 376         int reg;
 377         int sz;
 378         RING_LOCALS;
 379
 380         sz = header.packet0.count;
 381         reg = (header.packet0.reghi << 8) | header.packet0.reglo;
 382
 383         DRM_DEBUG("R300_CMD_PACKET0: reg %04x, sz %d\n", reg, sz);
 384         if (!sz)
 385                 return 0;
 386
 387         if (sz * 4 > cmdbuf->bufsz)
 388                 return -EINVAL;
 389
 390         if (reg + sz * 4 >= 0x10000) {
 391                 DRM_ERROR("No such registers in hardware reg=%04x sz=%d\n", reg,
 392                           sz);
 393                 return -EINVAL;
 394         }
 395
 396         if (r300_check_range(reg, sz)) {
 397                 /* go and check everything */
 398                 return r300_emit_carefully_checked_packet0(dev_priv, cmdbuf,
 399                                                            header);
 400         }
 401         /* the rest of the data is safe to emit, whatever the values the user passed */
 402
 403         BEGIN_RING(1 + sz);
 404         OUT_RING(CP_PACKET0(reg, sz - 1));
 405         OUT_RING_TABLE((int *)cmdbuf->buf, sz);
 406         ADVANCE_RING();
 407
 408         cmdbuf->buf += sz * 4;
 409         cmdbuf->bufsz -= sz * 4;
 410
 411         return 0;
 412 }
 413
 414 /**
 415  * Uploads user-supplied vertex program instructions or parameters onto
 416  * the graphics card.
 417  * Called by r300_do_cp_cmdbuf.
 418  */
 419 static __inline__ int r300_emit_vpu(drm_radeon_private_t *dev_priv,
 420                                     drm_radeon_kcmd_buffer_t *cmdbuf,
 421                                     drm_r300_cmd_header_t header)
 422 {
 423         int sz;
 424         int addr;
 425         RING_LOCALS;
 426
 427         sz = header.vpu.count;
 428         addr = (header.vpu.adrhi << 8) | header.vpu.adrlo;
 429
 430         if (!sz)
 431                 return 0;
 432         if (sz * 16 > cmdbuf->bufsz)
 433                 return -EINVAL;
 434
 435         BEGIN_RING(5 + sz * 4);
 436         /* Wait for VAP to come to senses.. */
 437         /* there is no need to emit it multiple times, (only once before VAP is programmed,
 438            but this optimization is for later */
 439         OUT_RING_REG(R300_VAP_PVS_WAITIDLE, 0);
 440         OUT_RING_REG(R300_VAP_PVS_UPLOAD_ADDRESS, addr);
 441         OUT_RING(CP_PACKET0_TABLE(R300_VAP_PVS_UPLOAD_DATA, sz * 4 - 1));
 442         OUT_RING_TABLE((int *)cmdbuf->buf, sz * 4);
 443
 444         ADVANCE_RING();
 445
 446         cmdbuf->buf += sz * 16;
 447         cmdbuf->bufsz -= sz * 16;
 448
 449         return 0;
 450 }
 451
 452 /**
 453  * Emit a clear packet from userspace.
 454  * Called by r300_emit_packet3.
 455  */
 456 static __inline__ int r300_emit_clear(drm_radeon_private_t *dev_priv,
 457                                       drm_radeon_kcmd_buffer_t *cmdbuf)
 458 {
 459         RING_LOCALS;
 460
 461         if (8 * 4 > cmdbuf->bufsz)
 462                 return -EINVAL;
 463
 464         BEGIN_RING(10);
 465         OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8));
 466         OUT_RING(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING |
 467                  (1 << R300_PRIM_NUM_VERTICES_SHIFT));
 468         OUT_RING_TABLE((int *)cmdbuf->buf, 8);
 469         ADVANCE_RING();
 470
 471         cmdbuf->buf += 8 * 4;
 472         cmdbuf->bufsz -= 8 * 4;
 473
 474         return 0;
 475 }
 476
 477 static __inline__ int r300_emit_3d_load_vbpntr(drm_radeon_private_t *dev_priv,
 478                                                drm_radeon_kcmd_buffer_t *cmdbuf,
 479                                                u32 header)
 480 {
 481         int count, i, k;
 482 #define MAX_ARRAY_PACKET  64
 483         u32 payload[MAX_ARRAY_PACKET];
 484         u32 narrays;
 485         RING_LOCALS;
 486
 487         count = (header >> 16) & 0x3fff;
 488
 489         if ((count + 1) > MAX_ARRAY_PACKET) {
 490                 DRM_ERROR("Too large payload in 3D_LOAD_VBPNTR (count=%d)\n",
 491                           count);
 492                 return -EINVAL;
 493         }
 494         memset(payload, 0, MAX_ARRAY_PACKET * 4);
 495         memcpy(payload, cmdbuf->buf + 4, (count + 1) * 4);
 496
 497         /* carefully check packet contents */
 498
 499         narrays = payload[0];
 500         k = 0;
 501         i = 1;
 502         while ((k < narrays) && (i < (count + 1))) {
 503                 i++;            /* skip attribute field */
 504                 if (!radeon_check_offset(dev_priv, payload[i])) {
 505                         DRM_ERROR
 506                             ("Offset failed range check (k=%d i=%d) while processing 3D_LOAD_VBPNTR packet.\n",
 507                              k, i);
 508                         return -EINVAL;
 509                 }
 510                 k++;
 511                 i++;
 512                 if (k == narrays)
 513                         break;
 514                 /* have one more to process, they come in pairs */
 515                 if (!radeon_check_offset(dev_priv, payload[i])) {
 516                         DRM_ERROR
 517                             ("Offset failed range check (k=%d i=%d) while processing 3D_LOAD_VBPNTR packet.\n",
 518                              k, i);
 519                         return -EINVAL;
 520                 }
 521                 k++;
 522                 i++;
 523         }
 524         /* do the counts match what we expect ? */
 525         if ((k != narrays) || (i != (count + 1))) {
 526                 DRM_ERROR
 527                     ("Malformed 3D_LOAD_VBPNTR packet (k=%d i=%d narrays=%d count+1=%d).\n",
 528                      k, i, narrays, count + 1);
 529                 return -EINVAL;
 530         }
 531
 532         /* all clear, output packet */
 533
 534         BEGIN_RING(count + 2);
 535         OUT_RING(header);
 536         OUT_RING_TABLE(payload, count + 1);
 537         ADVANCE_RING();
 538
 539         cmdbuf->buf += (count + 2) * 4;
 540         cmdbuf->bufsz -= (count + 2) * 4;
 541
 542         return 0;
 543 }
 544
 545 static __inline__ int r300_emit_bitblt_multi(drm_radeon_private_t *dev_priv,
 546                                              drm_radeon_kcmd_buffer_t *cmdbuf)
 547 {
 548         u32 *cmd = (u32 *) cmdbuf->buf;
 549         int count, ret;
 550         RING_LOCALS;
 551
 552         count=(cmd[0]>>16) & 0x3fff;
 553
 554         if (cmd[0] & 0x8000) {
 555                 u32 offset;
 556
 557                 if (cmd[1] & (RADEON_GMC_SRC_PITCH_OFFSET_CNTL
 558                               | RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
 559                         offset = cmd[2] << 10;
 560                         ret = !radeon_check_offset(dev_priv, offset);
 561                         if (ret) {
 562                                 DRM_ERROR("Invalid bitblt first offset is %08X\n", offset);
 563                                 return -EINVAL;
 564                         }
 565                 }
 566
 567                 if ((cmd[1] & RADEON_GMC_SRC_PITCH_OFFSET_CNTL) &&
 568                     (cmd[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
 569                         offset = cmd[3] << 10;
 570                         ret = !radeon_check_offset(dev_priv, offset);
 571                         if (ret) {
 572                                 DRM_ERROR("Invalid bitblt second offset is %08X\n", offset);
 573                                 return -EINVAL;
 574                         }
 575
 576                 }
 577         }
 578
 579         BEGIN_RING(count+2);
 580         OUT_RING(cmd[0]);
 581         OUT_RING_TABLE((int *)(cmdbuf->buf + 4), count + 1);
 582         ADVANCE_RING();
 583
 584         cmdbuf->buf += (count+2)*4;
 585         cmdbuf->bufsz -= (count+2)*4;
 586
 587         return 0;
 588 }
 589
 590 static __inline__ int r300_emit_indx_buffer(drm_radeon_private_t *dev_priv,
 591                                              drm_radeon_kcmd_buffer_t *cmdbuf)
 592 {
 593         u32 *cmd = (u32 *) cmdbuf->buf;
 594         int count, ret;
 595         RING_LOCALS;
 596
 597         count=(cmd[0]>>16) & 0x3fff;
 598
 599         if ((cmd[1] & 0x8000ffff) != 0x80000810) {
 600                 DRM_ERROR("Invalid indx_buffer reg address %08X\n", cmd[1]);
 601                 return -EINVAL;
 602         }
 603         ret = !radeon_check_offset(dev_priv, cmd[2]);
 604         if (ret) {
 605                 DRM_ERROR("Invalid indx_buffer offset is %08X\n", cmd[2]);
 606                 return -EINVAL;
 607         }
 608
 609         BEGIN_RING(count+2);
 610         OUT_RING(cmd[0]);
 611         OUT_RING_TABLE((int *)(cmdbuf->buf + 4), count + 1);
 612         ADVANCE_RING();
 613
 614         cmdbuf->buf += (count+2)*4;
 615         cmdbuf->bufsz -= (count+2)*4;
 616
 617         return 0;
 618 }
 619
 620 static __inline__ int r300_emit_raw_packet3(drm_radeon_private_t *dev_priv,
 621                                             drm_radeon_kcmd_buffer_t *cmdbuf)
 622 {
 623         u32 header;
 624         int count;
 625         RING_LOCALS;
 626
 627         if (4 > cmdbuf->bufsz)
 628                 return -EINVAL;
 629
 630         /* Fixme !! This simply emits a packet without much checking.
 631            We need to be smarter. */
 632
 633         /* obtain first word - actual packet3 header */
 634         header = *(u32 *) cmdbuf->buf;
 635
 636         /* Is it packet 3 ? */
 637         if ((header >> 30) != 0x3) {
 638                 DRM_ERROR("Not a packet3 header (0x%08x)\n", header);
 639                 return -EINVAL;
 640         }
 641
 642         count = (header >> 16) & 0x3fff;
 643
 644         /* Check again now that we know how much data to expect */
 645         if ((count + 2) * 4 > cmdbuf->bufsz) {
 646                 DRM_ERROR
 647                     ("Expected packet3 of length %d but have only %d bytes left\n",
 648                      (count + 2) * 4, cmdbuf->bufsz);
 649                 return -EINVAL;
 650         }
 651
 652         /* Is it a packet type we know about ? */
 653         switch (header & 0xff00) {
 654         case RADEON_3D_LOAD_VBPNTR:     /* load vertex array pointers */
 655                 return r300_emit_3d_load_vbpntr(dev_priv, cmdbuf, header);
 656
 657         case RADEON_CNTL_BITBLT_MULTI:
 658                 return r300_emit_bitblt_multi(dev_priv, cmdbuf);
 659
 660         case RADEON_CP_INDX_BUFFER:     /* DRAW_INDX_2 without INDX_BUFFER seems to lock up the gpu */
 661                 return r300_emit_indx_buffer(dev_priv, cmdbuf);
 662         case RADEON_CP_3D_DRAW_IMMD_2:  /* triggers drawing using in-packet vertex data */
 663         case RADEON_CP_3D_DRAW_VBUF_2:  /* triggers drawing of vertex buffers setup elsewhere */
 664         case RADEON_CP_3D_DRAW_INDX_2:  /* triggers drawing using indices to vertex buffer */
 665         case RADEON_WAIT_FOR_IDLE:
 666         case RADEON_CP_NOP:
 667                 /* these packets are safe */
 668                 break;
 669         default:
 670                 DRM_ERROR("Unknown packet3 header (0x%08x)\n", header);
 671                 return -EINVAL;
 672         }
 673
 674         BEGIN_RING(count + 2);
 675         OUT_RING(header);
 676         OUT_RING_TABLE((int *)(cmdbuf->buf + 4), count + 1);
 677         ADVANCE_RING();
 678
 679         cmdbuf->buf += (count + 2) * 4;
 680         cmdbuf->bufsz -= (count + 2) * 4;
 681
 682         return 0;
 683 }
 684
 685 /**
 686  * Emit a rendering packet3 from userspace.
 687  * Called by r300_do_cp_cmdbuf.
 688  */
 689 static __inline__ int r300_emit_packet3(drm_radeon_private_t *dev_priv,
 690                                         drm_radeon_kcmd_buffer_t *cmdbuf,
 691                                         drm_r300_cmd_header_t header)
 692 {
 693         int n;
 694         int ret;
 695         char *orig_buf = cmdbuf->buf;
 696         int orig_bufsz = cmdbuf->bufsz;
 697
 698         /* This is a do-while-loop so that we run the interior at least once,
 699          * even if cmdbuf->nbox is 0. Compare r300_emit_cliprects for rationale.
 700          */
 701         n = 0;
 702         do {
 703                 if (cmdbuf->nbox > R300_SIMULTANEOUS_CLIPRECTS) {
 704                         ret = r300_emit_cliprects(dev_priv, cmdbuf, n);
 705                         if (ret)
 706                                 return ret;
 707
 708                         cmdbuf->buf = orig_buf;
 709                         cmdbuf->bufsz = orig_bufsz;
 710                 }
 711
 712                 switch (header.packet3.packet) {
 713                 case R300_CMD_PACKET3_CLEAR:
 714                         DRM_DEBUG("R300_CMD_PACKET3_CLEAR\n");
 715                         ret = r300_emit_clear(dev_priv, cmdbuf);
 716                         if (ret) {
 717                                 DRM_ERROR("r300_emit_clear failed\n");
 718                                 return ret;
 719                         }
 720                         break;
 721
 722                 case R300_CMD_PACKET3_RAW:
 723                         DRM_DEBUG("R300_CMD_PACKET3_RAW\n");
 724                         ret = r300_emit_raw_packet3(dev_priv, cmdbuf);
 725                         if (ret) {
 726                                 DRM_ERROR("r300_emit_raw_packet3 failed\n");
 727                                 return ret;
 728                         }
 729                         break;
 730
 731                 default:
 732                         DRM_ERROR("bad packet3 type %i at %p\n",
 733                                   header.packet3.packet,
 734                                   cmdbuf->buf - sizeof(header));
 735                         return -EINVAL;
 736                 }
 737
 738                 n += R300_SIMULTANEOUS_CLIPRECTS;
 739         } while (n < cmdbuf->nbox);
 740
 741         return 0;
 742 }
 743
 744 /* Some of the R300 chips seem to be extremely touchy about the two registers
 745  * that are configured in r300_pacify.
 746  * Among the worst offenders seems to be the R300 ND (0x4E44): When userspace
 747  * sends a command buffer that contains only state setting commands and a
 748  * vertex program/parameter upload sequence, this will eventually lead to a
 749  * lockup, unless the sequence is bracketed by calls to r300_pacify.
 750  * So we should take great care to *always* call r300_pacify before
 751  * *anything* 3D related, and again afterwards. This is what the
 752  * call bracket in r300_do_cp_cmdbuf is for.
 753  */
 754
 755 /**
 756  * Emit the sequence to pacify R300.
 757  */
 758 static __inline__ void r300_pacify(drm_radeon_private_t *dev_priv)
 759 {
 760         RING_LOCALS;
 761
 762         BEGIN_RING(6);
 763         OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 764         OUT_RING(R300_RB3D_DSTCACHE_UNKNOWN_0A);
 765         OUT_RING(CP_PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
 766         OUT_RING(R300_RB3D_ZCACHE_UNKNOWN_03);
 767         OUT_RING(CP_PACKET3(RADEON_CP_NOP, 0));
 768         OUT_RING(0x0);
 769         ADVANCE_RING();
 770 }
 771
 772 /**
 773  * Called by r300_do_cp_cmdbuf to update the internal buffer age and state.
 774  * The actual age emit is done by r300_do_cp_cmdbuf, which is why you must
 775  * be careful about how this function is called.
 776  */
 777 static void r300_discard_buffer(struct drm_device * dev, struct drm_master *master, struct drm_buf * buf)
 778 {
 779         drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
 780         struct drm_radeon_master_private *master_priv = master->driver_priv;
 781
 782         buf_priv->age = ++master_priv->sarea_priv->last_dispatch;
 783         buf->pending = 1;
 784         buf->used = 0;
 785 }
 786
 787 static void r300_cmd_wait(drm_radeon_private_t * dev_priv,
 788                           drm_r300_cmd_header_t header)
 789 {
 790         u32 wait_until;
 791         RING_LOCALS;
 792
 793         if (!header.wait.flags)
 794                 return;
 795
 796         wait_until = 0;
 797
 798         switch(header.wait.flags) {
 799         case R300_WAIT_2D:
 800                 wait_until = RADEON_WAIT_2D_IDLE;
 801                 break;
 802         case R300_WAIT_3D:
 803                 wait_until = RADEON_WAIT_3D_IDLE;
 804                 break;
 805         case R300_NEW_WAIT_2D_3D:
 806                 wait_until = RADEON_WAIT_2D_IDLE|RADEON_WAIT_3D_IDLE;
 807                 break;
 808         case R300_NEW_WAIT_2D_2D_CLEAN:
 809                 wait_until = RADEON_WAIT_2D_IDLE|RADEON_WAIT_2D_IDLECLEAN;
 810                 break;
 811         case R300_NEW_WAIT_3D_3D_CLEAN:
 812                 wait_until = RADEON_WAIT_3D_IDLE|RADEON_WAIT_3D_IDLECLEAN;
 813                 break;
 814         case R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN:
 815                 wait_until = RADEON_WAIT_2D_IDLE|RADEON_WAIT_2D_IDLECLEAN;
 816                 wait_until |= RADEON_WAIT_3D_IDLE|RADEON_WAIT_3D_IDLECLEAN;
 817                 break;
 818         default:
 819                 return;
 820         }
 821
 822         BEGIN_RING(2);
 823         OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
 824         OUT_RING(wait_until);
 825         ADVANCE_RING();
 826 }
 827
 828 static int r300_scratch(drm_radeon_private_t *dev_priv,
 829                         drm_radeon_kcmd_buffer_t *cmdbuf,
 830                         drm_r300_cmd_header_t header)
 831 {
 832         u32 *ref_age_base;
 833         u32 i, buf_idx, h_pending;
 834         RING_LOCALS;
 835
 836         if (cmdbuf->bufsz < sizeof(uint64_t) + header.scratch.n_bufs * sizeof(buf_idx) ) {
 837                 return -EINVAL;
 838         }
 839
 840         if (header.scratch.reg >= 5) {
 841                 return -EINVAL;
 842         }
 843
 844         dev_priv->scratch_ages[header.scratch.reg] ++;
 845
 846         ref_age_base = (u32 *)(unsigned long)*((uint64_t *)cmdbuf->buf);
 847
 848         cmdbuf->buf += sizeof(uint64_t);
 849         cmdbuf->bufsz -= sizeof(uint64_t);
 850
 851         for (i=0; i < header.scratch.n_bufs; i++) {
 852                 buf_idx = *(u32 *)cmdbuf->buf;
 853                 buf_idx *= 2; /* 8 bytes per buf */
 854
 855                 if (DRM_COPY_TO_USER(ref_age_base + buf_idx, &dev_priv->scratch_ages[header.scratch.reg], sizeof(u32))) {
 856                         return -EINVAL;
 857                 }
 858
 859                 if (DRM_COPY_FROM_USER(&h_pending, ref_age_base + buf_idx + 1, sizeof(u32))) {
 860                         return -EINVAL;
 861                 }
 862
 863                 if (h_pending == 0) {
 864                         return -EINVAL;
 865                 }
 866
 867                 h_pending--;
 868
 869                 if (DRM_COPY_TO_USER(ref_age_base + buf_idx + 1, &h_pending, sizeof(u32))) {
 870                         return -EINVAL;
 871                 }
 872
 873                 cmdbuf->buf += sizeof(buf_idx);
 874                 cmdbuf->bufsz -= sizeof(buf_idx);
 875         }
 876
 877         BEGIN_RING(2);
 878         OUT_RING( CP_PACKET0( RADEON_SCRATCH_REG0 + header.scratch.reg * 4, 0 ) );
 879         OUT_RING( dev_priv->scratch_ages[header.scratch.reg] );
 880         ADVANCE_RING();
 881
 882         return 0;
 883 }
 884
 885 /**
 886  * Uploads user-supplied vertex program instructions or parameters onto
 887  * the graphics card.
 888  * Called by r300_do_cp_cmdbuf.
 889  */
 890 static __inline__ int r300_emit_r500fp(drm_radeon_private_t *dev_priv,
 891                                        drm_radeon_kcmd_buffer_t *cmdbuf,
 892                                        drm_r300_cmd_header_t header)
 893 {
 894         int sz;
 895         int addr;
 896         int type;
 897         int clamp;
 898         int stride;
 899         RING_LOCALS;
 900
 901         sz = header.r500fp.count;
 902         /* address is 9 bits 0 - 8, bit 1 of flags is part of address */
 903         addr = ((header.r500fp.adrhi_flags & 1) << 8) | header.r500fp.adrlo;
 904
 905         type = !!(header.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE);
 906         clamp = !!(header.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP);
 907
 908         addr |= (type << 16);
 909         addr |= (clamp << 17);
 910
 911         stride = type ? 4 : 6;
 912
 913         DRM_DEBUG("r500fp %d %d type: %d\n", sz, addr, type);
 914         if (!sz)
 915                 return 0;
 916         if (sz * stride * 4 > cmdbuf->bufsz)
 917                 return -EINVAL;
 918
 919         BEGIN_RING(3 + sz * stride);
 920         OUT_RING_REG(R500_GA_US_VECTOR_INDEX, addr);
 921         OUT_RING(CP_PACKET0_TABLE(R500_GA_US_VECTOR_DATA, sz * stride - 1));
 922         OUT_RING_TABLE((int *)cmdbuf->buf, sz * stride);
 923
 924         ADVANCE_RING();
 925
 926         cmdbuf->buf += sz * stride * 4;
 927         cmdbuf->bufsz -= sz * stride * 4;
 928
 929         return 0;
 930 }
 931
 932
 933 /**
 934  * Parses and validates a user-supplied command buffer and emits appropriate
 935  * commands on the DMA ring buffer.
 936  * Called by the ioctl handler function radeon_cp_cmdbuf.
 937  */
 938 int r300_do_cp_cmdbuf(struct drm_device *dev,
 939                       struct drm_file *file_priv,
 940                       drm_radeon_kcmd_buffer_t *cmdbuf)
 941 {
 942         drm_radeon_private_t *dev_priv = dev->dev_private;
 943         struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
 944         struct drm_device_dma *dma = dev->dma;
 945         struct drm_buf *buf = NULL;
 946         int emit_dispatch_age = 0;
 947         int ret = 0;
 948
 949         DRM_DEBUG("\n");
 950
 951         /* See the comment above r300_emit_begin3d for why this call must be here,
 952          * and what the cleanup gotos are for. */
 953         r300_pacify(dev_priv);
 954
 955         if (cmdbuf->nbox <= R300_SIMULTANEOUS_CLIPRECTS) {
 956                 ret = r300_emit_cliprects(dev_priv, cmdbuf, 0);
 957                 if (ret)
 958                         goto cleanup;
 959         }
 960
 961         while (cmdbuf->bufsz >= sizeof(drm_r300_cmd_header_t)) {
 962                 int idx;
 963                 drm_r300_cmd_header_t header;
 964
 965                 header.u = *(unsigned int *)cmdbuf->buf;
 966
 967                 cmdbuf->buf += sizeof(header);
 968                 cmdbuf->bufsz -= sizeof(header);
 969
 970                 switch (header.header.cmd_type) {
 971                 case R300_CMD_PACKET0:
 972                         ret = r300_emit_packet0(dev_priv, cmdbuf, header);
 973                         if (ret) {
 974                                 DRM_ERROR("r300_emit_packet0 failed\n");
 975                                 goto cleanup;
 976                         }
 977                         break;
 978
 979                 case R300_CMD_VPU:
 980                         DRM_DEBUG("R300_CMD_VPU\n");
 981                         ret = r300_emit_vpu(dev_priv, cmdbuf, header);
 982                         if (ret) {
 983                                 DRM_ERROR("r300_emit_vpu failed\n");
 984                                 goto cleanup;
 985                         }
 986                         break;
 987
 988                 case R300_CMD_PACKET3:
 989                         DRM_DEBUG("R300_CMD_PACKET3\n");
 990                         ret = r300_emit_packet3(dev_priv, cmdbuf, header);
 991                         if (ret) {
 992                                 DRM_ERROR("r300_emit_packet3 failed\n");
 993                                 goto cleanup;
 994                         }
 995                         break;
 996
 997                 case R300_CMD_END3D:
 998                         DRM_DEBUG("R300_CMD_END3D\n");
 999                         /* TODO:
1000                            Ideally userspace driver should not need to issue this call,
1001                            i.e. the drm driver should issue it automatically and prevent
1002                            lockups.
1003
1004                            In practice, we do not understand why this call is needed and what
1005                            it does (except for some vague guesses that it has to do with cache
1006                            coherence) and so the user space driver does it.
1007
1008                            Once we are sure which uses prevent lockups the code could be moved
1009                            into the kernel and the userspace driver will not
1010                            need to use this command.
1011
1012                            Note that issuing this command does not hurt anything
1013                            except, possibly, performance */
1014                         r300_pacify(dev_priv);
1015                         break;
1016
1017                 case R300_CMD_CP_DELAY:
1018                         /* simple enough, we can do it here */
1019                         DRM_DEBUG("R300_CMD_CP_DELAY\n");
1020                         {
1021                                 int i;
1022                                 RING_LOCALS;
1023
1024                                 BEGIN_RING(header.delay.count);
1025                                 for (i = 0; i < header.delay.count; i++)
1026                                         OUT_RING(RADEON_CP_PACKET2);
1027                                 ADVANCE_RING();
1028                         }
1029                         break;
1030
1031                 case R300_CMD_DMA_DISCARD:
1032                         DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n");
1033                         idx = header.dma.buf_idx;
1034                         if (idx < 0 || idx >= dma->buf_count) {
1035                                 DRM_ERROR("buffer index %d (of %d max)\n",
1036                                           idx, dma->buf_count - 1);
1037                                 ret = -EINVAL;
1038                                 goto cleanup;
1039                         }
1040
1041                         buf = dma->buflist[idx];
1042                         if (buf->file_priv != file_priv || buf->pending) {
1043                                 DRM_ERROR("bad buffer %p %p %d\n",
1044                                           buf->file_priv, file_priv,
1045                                           buf->pending);
1046                                 ret = -EINVAL;
1047                                 goto cleanup;
1048                         }
1049
1050                         emit_dispatch_age = 1;
1051                         r300_discard_buffer(dev, file_priv->master, buf);
1052                         break;
1053
1054                 case R300_CMD_WAIT:
1055                         DRM_DEBUG("R300_CMD_WAIT\n");
1056                         r300_cmd_wait(dev_priv, header);
1057                         break;
1058
1059                 case R300_CMD_SCRATCH:
1060                         DRM_DEBUG("R300_CMD_SCRATCH\n");
1061                         ret = r300_scratch(dev_priv, cmdbuf, header);
1062                         if (ret) {
1063                                 DRM_ERROR("r300_scratch failed\n");
1064                                 goto cleanup;
1065                         }
1066                         break;
1067
1068                 case R300_CMD_R500FP:
1069                         if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) {
1070                                 DRM_ERROR("Calling r500 command on r300 card\n");
1071                                 ret = -EINVAL;
1072                                 goto cleanup;
1073                         }
1074                         DRM_DEBUG("R300_CMD_R500FP\n");
1075                         ret = r300_emit_r500fp(dev_priv, cmdbuf, header);
1076                         if (ret) {
1077                                 DRM_ERROR("r300_emit_r500fp failed\n");
1078                                 goto cleanup;
1079                         }
1080                         break;
1081                 default:
1082                         DRM_ERROR("bad cmd_type %i at %p\n",
1083                                   header.header.cmd_type,
1084                                   cmdbuf->buf - sizeof(header));
1085                         ret = -EINVAL;
1086                         goto cleanup;
1087                 }
1088         }
1089
1090         DRM_DEBUG("END\n");
1091
1092       cleanup:
1093         r300_pacify(dev_priv);
1094
1095         /* We emit the vertex buffer age here, outside the pacifier "brackets"
1096          * for two reasons:
1097          *  (1) This may coalesce multiple age emissions into a single one and
1098          *  (2) more importantly, some chips lock up hard when scratch registers
1099          *      are written inside the pacifier bracket.
1100          */
1101         if (emit_dispatch_age) {
1102                 RING_LOCALS;
1103
1104                 /* Emit the vertex buffer age */
1105                 BEGIN_RING(2);
1106                 RADEON_DISPATCH_AGE(master_priv->sarea_priv->last_dispatch);
1107                 ADVANCE_RING();
1108         }
1109
1110         COMMIT_RING();
1111
1112         return ret;
1113 }