shared-core/r300_cmdbuf.c

   1 /* r300_cmdbuf.c -- Command buffer emission for R300 -*- linux-c -*-
   2  *
   3  * Copyright (C) The Weather Channel, Inc.  2002.
   4  * Copyright (C) 2004 Nicolai Haehnle.
   5  * All Rights Reserved.
   6  *
   7  * The Weather Channel (TM) funded Tungsten Graphics to develop the
   8  * initial release of the Radeon 8500 driver under the XFree86 license.
   9  * This notice must be preserved.
  10  *
  11  * Permission is hereby granted, free of charge, to any person obtaining a
  12  * copy of this software and associated documentation files (the "Software"),
  13  * to deal in the Software without restriction, including without limitation
  14  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  15  * and/or sell copies of the Software, and to permit persons to whom the
  16  * Software is furnished to do so, subject to the following conditions:
  17  *
  18  * The above copyright notice and this permission notice (including the next
  19  * paragraph) shall be included in all copies or substantial portions of the
  20  * Software.
  21  *
  22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  25  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  26  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  27  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  28  * DEALINGS IN THE SOFTWARE.
  29  *
  30  * Authors:
  31  *    Nicolai Haehnle <prefect_@gmx.net>
  32  */
  33
  34 #include "drmP.h"
  35 #include "drm.h"
  36 #include "radeon_drm.h"
  37 #include "radeon_drv.h"
  38 #include "r300_reg.h"
  39
  40 #define R300_SIMULTANEOUS_CLIPRECTS             4
  41
  42 /* Values for R300_RE_CLIPRECT_CNTL depending on the number of cliprects
  43  */
  44 static const int r300_cliprect_cntl[4] = {
  45         0xAAAA,
  46         0xEEEE,
  47         0xFEFE,
  48         0xFFFE
  49 };
  50
  51 /**
  52  * Emit up to R300_SIMULTANEOUS_CLIPRECTS cliprects from the given command
  53  * buffer, starting with index n.
  54  */
  55 static int r300_emit_cliprects(drm_radeon_private_t *dev_priv,
  56                                drm_radeon_kcmd_buffer_t *cmdbuf, int n)
  57 {
  58         struct drm_clip_rect box;
  59         int nr;
  60         int i;
  61         RING_LOCALS;
  62
  63         nr = cmdbuf->nbox - n;
  64         if (nr > R300_SIMULTANEOUS_CLIPRECTS)
  65                 nr = R300_SIMULTANEOUS_CLIPRECTS;
  66
  67         DRM_DEBUG("%i cliprects\n", nr);
  68
  69         if (nr) {
  70                 BEGIN_RING(6 + nr * 2);
  71                 OUT_RING(CP_PACKET0(R300_RE_CLIPRECT_TL_0, nr * 2 - 1));
  72
  73                 for (i = 0; i < nr; ++i) {
  74                         if (DRM_COPY_FROM_USER_UNCHECKED
  75                             (&box, &cmdbuf->boxes[n + i], sizeof(box))) {
  76                                 DRM_ERROR("copy cliprect faulted\n");
  77                                 return -EFAULT;
  78                         }
  79
  80                         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
  81                                 box.x1 = (box.x1) &
  82                                         R300_CLIPRECT_MASK;
  83                                 box.y1 = (box.y1) &
  84                                         R300_CLIPRECT_MASK;
  85                                 box.x2 = (box.x2) &
  86                                         R300_CLIPRECT_MASK;
  87                                 box.y2 = (box.y2) &
  88                                         R300_CLIPRECT_MASK;
  89                         } else {
  90                                 box.x1 = (box.x1 + R300_CLIPRECT_OFFSET) &
  91                                         R300_CLIPRECT_MASK;
  92                                 box.y1 = (box.y1 + R300_CLIPRECT_OFFSET) &
  93                                         R300_CLIPRECT_MASK;
  94                                 box.x2 = (box.x2 + R300_CLIPRECT_OFFSET) &
  95                                         R300_CLIPRECT_MASK;
  96                                 box.y2 = (box.y2 + R300_CLIPRECT_OFFSET) &
  97                                         R300_CLIPRECT_MASK;
  98
  99                         }
 100                         OUT_RING((box.x1 << R300_CLIPRECT_X_SHIFT) |
 101                                  (box.y1 << R300_CLIPRECT_Y_SHIFT));
 102                         OUT_RING((box.x2 << R300_CLIPRECT_X_SHIFT) |
 103                                  (box.y2 << R300_CLIPRECT_Y_SHIFT));
 104
 105                 }
 106
 107                 OUT_RING_REG(R300_RE_CLIPRECT_CNTL, r300_cliprect_cntl[nr - 1]);
 108
 109                 /* TODO/SECURITY: Force scissors to a safe value, otherwise the
 110                  * client might be able to trample over memory.
 111                  * The impact should be very limited, but I'd rather be safe than
 112                  * sorry.
 113                  */
 114                 OUT_RING(CP_PACKET0(R300_RE_SCISSORS_TL, 1));
 115                 OUT_RING(0);
 116                 OUT_RING(R300_SCISSORS_X_MASK | R300_SCISSORS_Y_MASK);
 117                 ADVANCE_RING();
 118         } else {
 119                 /* Why we allow zero cliprect rendering:
 120                  * There are some commands in a command buffer that must be submitted
 121                  * even when there are no cliprects, e.g. DMA buffer discard
 122                  * or state setting (though state setting could be avoided by
 123                  * simulating a loss of context).
 124                  *
 125                  * Now since the cmdbuf interface is so chaotic right now (and is
 126                  * bound to remain that way for a bit until things settle down),
 127                  * it is basically impossible to filter out the commands that are
 128                  * necessary and those that aren't.
 129                  *
 130                  * So I choose the safe way and don't do any filtering at all;
 131                  * instead, I simply set up the engine so that all rendering
 132                  * can't produce any fragments.
 133                  */
 134                 BEGIN_RING(2);
 135                 OUT_RING_REG(R300_RE_CLIPRECT_CNTL, 0);
 136                 ADVANCE_RING();
 137         }
 138
 139         return 0;
 140 }
 141
 142 static u8 r300_reg_flags[0x10000 >> 2];
 143
 144 void r300_init_reg_flags(struct drm_device *dev)
 145 {
 146         int i;
 147         drm_radeon_private_t *dev_priv = dev->dev_private;
 148
 149         memset(r300_reg_flags, 0, 0x10000 >> 2);
 150 #define ADD_RANGE_MARK(reg, count,mark) \
 151                 for(i=((reg)>>2);i<((reg)>>2)+(count);i++)\
 152                         r300_reg_flags[i]|=(mark);
 153
 154 #define MARK_SAFE               1
 155 #define MARK_CHECK_OFFSET       2
 156
 157 #define ADD_RANGE(reg, count)   ADD_RANGE_MARK(reg, count, MARK_SAFE)
 158
 159         /* these match cmducs() command in r300_driver/r300/r300_cmdbuf.c */
 160         ADD_RANGE(R300_SE_VPORT_XSCALE, 6);
 161         ADD_RANGE(R300_VAP_CNTL, 1);
 162         ADD_RANGE(R300_SE_VTE_CNTL, 2);
 163         ADD_RANGE(0x2134, 2);
 164         ADD_RANGE(R300_VAP_CNTL_STATUS, 1);
 165         ADD_RANGE(R300_VAP_INPUT_CNTL_0, 2);
 166         ADD_RANGE(0x21DC, 1);
 167         ADD_RANGE(R300_VAP_UNKNOWN_221C, 1);
 168         ADD_RANGE(R300_VAP_CLIP_X_0, 4);
 169         ADD_RANGE(R300_VAP_PVS_WAITIDLE, 1);
 170         ADD_RANGE(R300_VAP_UNKNOWN_2288, 1);
 171         ADD_RANGE(R300_VAP_OUTPUT_VTX_FMT_0, 2);
 172         ADD_RANGE(R300_VAP_PVS_CNTL_1, 3);
 173         ADD_RANGE(R300_GB_ENABLE, 1);
 174         ADD_RANGE(R300_GB_MSPOS0, 5);
 175         ADD_RANGE(R300_TX_CNTL, 1);
 176         ADD_RANGE(R300_TX_ENABLE, 1);
 177         ADD_RANGE(0x4200, 4);
 178         ADD_RANGE(0x4214, 1);
 179         ADD_RANGE(R300_RE_POINTSIZE, 1);
 180         ADD_RANGE(0x4230, 3);
 181         ADD_RANGE(R300_RE_LINE_CNT, 1);
 182         ADD_RANGE(R300_RE_UNK4238, 1);
 183         ADD_RANGE(0x4260, 3);
 184         ADD_RANGE(R300_RE_SHADE, 4);
 185         ADD_RANGE(R300_RE_POLYGON_MODE, 5);
 186         ADD_RANGE(R300_RE_ZBIAS_CNTL, 1);
 187         ADD_RANGE(R300_RE_ZBIAS_T_FACTOR, 4);
 188         ADD_RANGE(R300_RE_OCCLUSION_CNTL, 1);
 189         ADD_RANGE(R300_RE_CULL_CNTL, 1);
 190         ADD_RANGE(0x42C0, 2);
 191         ADD_RANGE(R300_RS_CNTL_0, 2);
 192
 193         ADD_RANGE(0x43A4, 2);
 194         ADD_RANGE(0x43E8, 1);
 195
 196         ADD_RANGE(0x46A4, 5);
 197
 198         ADD_RANGE(R300_RE_FOG_STATE, 1);
 199         ADD_RANGE(R300_FOG_COLOR_R, 3);
 200         ADD_RANGE(R300_PP_ALPHA_TEST, 2);
 201         ADD_RANGE(0x4BD8, 1);
 202         ADD_RANGE(R300_PFS_PARAM_0_X, 64);
 203         ADD_RANGE(0x4E00, 1);
 204         ADD_RANGE(R300_RB3D_CBLEND, 2);
 205         ADD_RANGE(R300_RB3D_COLORMASK, 1);
 206         ADD_RANGE(R300_RB3D_BLEND_COLOR, 3);
 207         ADD_RANGE_MARK(R300_RB3D_COLOROFFSET0, 1, MARK_CHECK_OFFSET);   /* check offset */
 208         ADD_RANGE(R300_RB3D_COLORPITCH0, 1);
 209         ADD_RANGE(0x4E50, 9);
 210         ADD_RANGE(0x4E88, 1);
 211         ADD_RANGE(0x4EA0, 2);
 212         ADD_RANGE(R300_RB3D_ZSTENCIL_CNTL_0, 3);
 213         ADD_RANGE(R300_RB3D_ZSTENCIL_FORMAT, 4);
 214         ADD_RANGE_MARK(R300_RB3D_DEPTHOFFSET, 1, MARK_CHECK_OFFSET);    /* check offset */
 215         ADD_RANGE(R300_RB3D_DEPTHPITCH, 1);
 216         ADD_RANGE(0x4F28, 1);
 217         ADD_RANGE(0x4F30, 2);
 218         ADD_RANGE(0x4F44, 1);
 219         ADD_RANGE(0x4F54, 1);
 220
 221         ADD_RANGE(R300_TX_FILTER_0, 16);
 222         ADD_RANGE(R300_TX_FILTER1_0, 16);
 223         ADD_RANGE(R300_TX_SIZE_0, 16);
 224         ADD_RANGE(R300_TX_FORMAT_0, 16);
 225         ADD_RANGE(R300_TX_PITCH_0, 16);
 226         /* Texture offset is dangerous and needs more checking */
 227         ADD_RANGE_MARK(R300_TX_OFFSET_0, 16, MARK_CHECK_OFFSET);
 228         ADD_RANGE(R300_TX_CHROMA_KEY_0, 16);
 229         ADD_RANGE(R300_TX_BORDER_COLOR_0, 16);
 230
 231         /* Sporadic registers used as primitives are emitted */
 232         ADD_RANGE(R300_RB3D_ZCACHE_CTLSTAT, 1);
 233         ADD_RANGE(R300_RB3D_DSTCACHE_CTLSTAT, 1);
 234         ADD_RANGE(R300_VAP_INPUT_ROUTE_0_0, 8);
 235         ADD_RANGE(R300_VAP_INPUT_ROUTE_1_0, 8);
 236
 237         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
 238                 ADD_RANGE(R500_RS_IP_0, 16);
 239                 ADD_RANGE(R500_RS_INST_0, 16);
 240         } else {
 241                 ADD_RANGE(R300_PFS_CNTL_0, 3);
 242                 ADD_RANGE(R300_PFS_NODE_0, 4);
 243                 ADD_RANGE(R300_PFS_TEXI_0, 64);
 244                 ADD_RANGE(R300_PFS_INSTR0_0, 64);
 245                 ADD_RANGE(R300_PFS_INSTR1_0, 64);
 246                 ADD_RANGE(R300_PFS_INSTR2_0, 64);
 247                 ADD_RANGE(R300_PFS_INSTR3_0, 64);
 248                 ADD_RANGE(R300_RS_INTERP_0, 8);
 249                 ADD_RANGE(R300_RS_ROUTE_0, 8);
 250
 251         }
 252 }
 253
 254 static __inline__ int r300_check_range(unsigned reg, int count)
 255 {
 256         int i;
 257         if (reg & ~0xffff)
 258                 return -1;
 259         for (i = (reg >> 2); i < (reg >> 2) + count; i++)
 260                 if (r300_reg_flags[i] != MARK_SAFE)
 261                         return 1;
 262         return 0;
 263 }
 264
 265 static __inline__ int r300_emit_carefully_checked_packet0(drm_radeon_private_t *
 266                                                           dev_priv,
 267                                                           drm_radeon_kcmd_buffer_t
 268                                                           * cmdbuf,
 269                                                           drm_r300_cmd_header_t
 270                                                           header)
 271 {
 272         int reg;
 273         int sz;
 274         int i;
 275         int values[64];
 276         RING_LOCALS;
 277
 278         sz = header.packet0.count;
 279         reg = (header.packet0.reghi << 8) | header.packet0.reglo;
 280
 281         if ((sz > 64) || (sz < 0)) {
 282                 DRM_ERROR
 283                     ("Cannot emit more than 64 values at a time (reg=%04x sz=%d)\n",
 284                      reg, sz);
 285                 return -EINVAL;
 286         }
 287         for (i = 0; i < sz; i++) {
 288                 values[i] = ((int *)cmdbuf->buf)[i];
 289                 switch (r300_reg_flags[(reg >> 2) + i]) {
 290                 case MARK_SAFE:
 291                         break;
 292                 case MARK_CHECK_OFFSET:
 293                         if (!radeon_check_offset(dev_priv, (u32) values[i])) {
 294                                 DRM_ERROR
 295                                     ("Offset failed range check (reg=%04x sz=%d)\n",
 296                                      reg, sz);
 297                                 return -EINVAL;
 298                         }
 299                         break;
 300                 default:
 301                         DRM_ERROR("Register %04x failed check as flag=%02x\n",
 302                                   reg + i * 4, r300_reg_flags[(reg >> 2) + i]);
 303                         return -EINVAL;
 304                 }
 305         }
 306
 307         BEGIN_RING(1 + sz);
 308         OUT_RING(CP_PACKET0(reg, sz - 1));
 309         OUT_RING_TABLE(values, sz);
 310         ADVANCE_RING();
 311
 312         cmdbuf->buf += sz * 4;
 313         cmdbuf->bufsz -= sz * 4;
 314
 315         return 0;
 316 }
 317
 318 /**
 319  * Emits a packet0 setting arbitrary registers.
 320  * Called by r300_do_cp_cmdbuf.
 321  *
 322  * Note that checks are performed on contents and addresses of the registers
 323  */
 324 static __inline__ int r300_emit_packet0(drm_radeon_private_t *dev_priv,
 325                                         drm_radeon_kcmd_buffer_t *cmdbuf,
 326                                         drm_r300_cmd_header_t header)
 327 {
 328         int reg;
 329         int sz;
 330         RING_LOCALS;
 331
 332         sz = header.packet0.count;
 333         reg = (header.packet0.reghi << 8) | header.packet0.reglo;
 334
 335         if (!sz)
 336                 return 0;
 337
 338         if (sz * 4 > cmdbuf->bufsz)
 339                 return -EINVAL;
 340
 341         if (reg + sz * 4 >= 0x10000) {
 342                 DRM_ERROR("No such registers in hardware reg=%04x sz=%d\n", reg,
 343                           sz);
 344                 return -EINVAL;
 345         }
 346
 347         if (r300_check_range(reg, sz)) {
 348                 /* go and check everything */
 349                 return r300_emit_carefully_checked_packet0(dev_priv, cmdbuf,
 350                                                            header);
 351         }
 352         /* the rest of the data is safe to emit, whatever the values the user passed */
 353
 354         BEGIN_RING(1 + sz);
 355         OUT_RING(CP_PACKET0(reg, sz - 1));
 356         OUT_RING_TABLE((int *)cmdbuf->buf, sz);
 357         ADVANCE_RING();
 358
 359         cmdbuf->buf += sz * 4;
 360         cmdbuf->bufsz -= sz * 4;
 361
 362         return 0;
 363 }
 364
 365 /**
 366  * Uploads user-supplied vertex program instructions or parameters onto
 367  * the graphics card.
 368  * Called by r300_do_cp_cmdbuf.
 369  */
 370 static __inline__ int r300_emit_vpu(drm_radeon_private_t *dev_priv,
 371                                     drm_radeon_kcmd_buffer_t *cmdbuf,
 372                                     drm_r300_cmd_header_t header)
 373 {
 374         int sz;
 375         int addr;
 376         RING_LOCALS;
 377
 378         sz = header.vpu.count;
 379         addr = (header.vpu.adrhi << 8) | header.vpu.adrlo;
 380
 381         if (!sz)
 382                 return 0;
 383         if (sz * 16 > cmdbuf->bufsz)
 384                 return -EINVAL;
 385
 386         BEGIN_RING(5 + sz * 4);
 387         /* Wait for VAP to come to senses.. */
 388         /* there is no need to emit it multiple times, (only once before VAP is programmed,
 389            but this optimization is for later */
 390         OUT_RING_REG(R300_VAP_PVS_WAITIDLE, 0);
 391         OUT_RING_REG(R300_VAP_PVS_UPLOAD_ADDRESS, addr);
 392         OUT_RING(CP_PACKET0_TABLE(R300_VAP_PVS_UPLOAD_DATA, sz * 4 - 1));
 393         OUT_RING_TABLE((int *)cmdbuf->buf, sz * 4);
 394
 395         ADVANCE_RING();
 396
 397         cmdbuf->buf += sz * 16;
 398         cmdbuf->bufsz -= sz * 16;
 399
 400         return 0;
 401 }
 402
 403 /**
 404  * Emit a clear packet from userspace.
 405  * Called by r300_emit_packet3.
 406  */
 407 static __inline__ int r300_emit_clear(drm_radeon_private_t *dev_priv,
 408                                       drm_radeon_kcmd_buffer_t *cmdbuf)
 409 {
 410         RING_LOCALS;
 411
 412         if (8 * 4 > cmdbuf->bufsz)
 413                 return -EINVAL;
 414
 415         BEGIN_RING(10);
 416         OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8));
 417         OUT_RING(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING |
 418                  (1 << R300_PRIM_NUM_VERTICES_SHIFT));
 419         OUT_RING_TABLE((int *)cmdbuf->buf, 8);
 420         ADVANCE_RING();
 421
 422         cmdbuf->buf += 8 * 4;
 423         cmdbuf->bufsz -= 8 * 4;
 424
 425         return 0;
 426 }
 427
 428 static __inline__ int r300_emit_3d_load_vbpntr(drm_radeon_private_t *dev_priv,
 429                                                drm_radeon_kcmd_buffer_t *cmdbuf,
 430                                                u32 header)
 431 {
 432         int count, i, k;
 433 #define MAX_ARRAY_PACKET  64
 434         u32 payload[MAX_ARRAY_PACKET];
 435         u32 narrays;
 436         RING_LOCALS;
 437
 438         count = (header >> 16) & 0x3fff;
 439
 440         if ((count + 1) > MAX_ARRAY_PACKET) {
 441                 DRM_ERROR("Too large payload in 3D_LOAD_VBPNTR (count=%d)\n",
 442                           count);
 443                 return -EINVAL;
 444         }
 445         memset(payload, 0, MAX_ARRAY_PACKET * 4);
 446         memcpy(payload, cmdbuf->buf + 4, (count + 1) * 4);
 447
 448         /* carefully check packet contents */
 449
 450         narrays = payload[0];
 451         k = 0;
 452         i = 1;
 453         while ((k < narrays) && (i < (count + 1))) {
 454                 i++;            /* skip attribute field */
 455                 if (!radeon_check_offset(dev_priv, payload[i])) {
 456                         DRM_ERROR
 457                             ("Offset failed range check (k=%d i=%d) while processing 3D_LOAD_VBPNTR packet.\n",
 458                              k, i);
 459                         return -EINVAL;
 460                 }
 461                 k++;
 462                 i++;
 463                 if (k == narrays)
 464                         break;
 465                 /* have one more to process, they come in pairs */
 466                 if (!radeon_check_offset(dev_priv, payload[i])) {
 467                         DRM_ERROR
 468                             ("Offset failed range check (k=%d i=%d) while processing 3D_LOAD_VBPNTR packet.\n",
 469                              k, i);
 470                         return -EINVAL;
 471                 }
 472                 k++;
 473                 i++;
 474         }
 475         /* do the counts match what we expect ? */
 476         if ((k != narrays) || (i != (count + 1))) {
 477                 DRM_ERROR
 478                     ("Malformed 3D_LOAD_VBPNTR packet (k=%d i=%d narrays=%d count+1=%d).\n",
 479                      k, i, narrays, count + 1);
 480                 return -EINVAL;
 481         }
 482
 483         /* all clear, output packet */
 484
 485         BEGIN_RING(count + 2);
 486         OUT_RING(header);
 487         OUT_RING_TABLE(payload, count + 1);
 488         ADVANCE_RING();
 489
 490         cmdbuf->buf += (count + 2) * 4;
 491         cmdbuf->bufsz -= (count + 2) * 4;
 492
 493         return 0;
 494 }
 495
 496 static __inline__ int r300_emit_bitblt_multi(drm_radeon_private_t *dev_priv,
 497                                              drm_radeon_kcmd_buffer_t *cmdbuf)
 498 {
 499         u32 *cmd = (u32 *) cmdbuf->buf;
 500         int count, ret;
 501         RING_LOCALS;
 502
 503         count=(cmd[0]>>16) & 0x3fff;
 504
 505         if (cmd[0] & 0x8000) {
 506                 u32 offset;
 507
 508                 if (cmd[1] & (RADEON_GMC_SRC_PITCH_OFFSET_CNTL
 509                               | RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
 510                         offset = cmd[2] << 10;
 511                         ret = !radeon_check_offset(dev_priv, offset);
 512                         if (ret) {
 513                                 DRM_ERROR("Invalid bitblt first offset is %08X\n", offset);
 514                                 return -EINVAL;
 515                         }
 516                 }
 517
 518                 if ((cmd[1] & RADEON_GMC_SRC_PITCH_OFFSET_CNTL) &&
 519                     (cmd[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
 520                         offset = cmd[3] << 10;
 521                         ret = !radeon_check_offset(dev_priv, offset);
 522                         if (ret) {
 523                                 DRM_ERROR("Invalid bitblt second offset is %08X\n", offset);
 524                                 return -EINVAL;
 525                         }
 526
 527                 }
 528         }
 529
 530         BEGIN_RING(count+2);
 531         OUT_RING(cmd[0]);
 532         OUT_RING_TABLE((int *)(cmdbuf->buf + 4), count + 1);
 533         ADVANCE_RING();
 534
 535         cmdbuf->buf += (count+2)*4;
 536         cmdbuf->bufsz -= (count+2)*4;
 537
 538         return 0;
 539 }
 540
 541 static __inline__ int r300_emit_indx_buffer(drm_radeon_private_t *dev_priv,
 542                                              drm_radeon_kcmd_buffer_t *cmdbuf)
 543 {
 544         u32 *cmd = (u32 *) cmdbuf->buf;
 545         int count, ret;
 546         RING_LOCALS;
 547
 548         count=(cmd[0]>>16) & 0x3fff;
 549
 550         if ((cmd[1] & 0x8000ffff) != 0x80000810) {
 551                 DRM_ERROR("Invalid indx_buffer reg address %08X\n", cmd[1]);
 552                 return -EINVAL;
 553         }
 554         ret = !radeon_check_offset(dev_priv, cmd[2]);
 555         if (ret) {
 556                 DRM_ERROR("Invalid indx_buffer offset is %08X\n", cmd[2]);
 557                 return -EINVAL;
 558         }
 559
 560         BEGIN_RING(count+2);
 561         OUT_RING(cmd[0]);
 562         OUT_RING_TABLE((int *)(cmdbuf->buf + 4), count + 1);
 563         ADVANCE_RING();
 564
 565         cmdbuf->buf += (count+2)*4;
 566         cmdbuf->bufsz -= (count+2)*4;
 567
 568         return 0;
 569 }
 570
 571 static __inline__ int r300_emit_raw_packet3(drm_radeon_private_t *dev_priv,
 572                                             drm_radeon_kcmd_buffer_t *cmdbuf)
 573 {
 574         u32 header;
 575         int count;
 576         RING_LOCALS;
 577
 578         if (4 > cmdbuf->bufsz)
 579                 return -EINVAL;
 580
 581         /* Fixme !! This simply emits a packet without much checking.
 582            We need to be smarter. */
 583
 584         /* obtain first word - actual packet3 header */
 585         header = *(u32 *) cmdbuf->buf;
 586
 587         /* Is it packet 3 ? */
 588         if ((header >> 30) != 0x3) {
 589                 DRM_ERROR("Not a packet3 header (0x%08x)\n", header);
 590                 return -EINVAL;
 591         }
 592
 593         count = (header >> 16) & 0x3fff;
 594
 595         /* Check again now that we know how much data to expect */
 596         if ((count + 2) * 4 > cmdbuf->bufsz) {
 597                 DRM_ERROR
 598                     ("Expected packet3 of length %d but have only %d bytes left\n",
 599                      (count + 2) * 4, cmdbuf->bufsz);
 600                 return -EINVAL;
 601         }
 602
 603         /* Is it a packet type we know about ? */
 604         switch (header & 0xff00) {
 605         case RADEON_3D_LOAD_VBPNTR:     /* load vertex array pointers */
 606                 return r300_emit_3d_load_vbpntr(dev_priv, cmdbuf, header);
 607
 608         case RADEON_CNTL_BITBLT_MULTI:
 609                 return r300_emit_bitblt_multi(dev_priv, cmdbuf);
 610
 611         case RADEON_CP_INDX_BUFFER:     /* DRAW_INDX_2 without INDX_BUFFER seems to lock up the gpu */
 612                 return r300_emit_indx_buffer(dev_priv, cmdbuf);
 613         case RADEON_CP_3D_DRAW_IMMD_2:  /* triggers drawing using in-packet vertex data */
 614         case RADEON_CP_3D_DRAW_VBUF_2:  /* triggers drawing of vertex buffers setup elsewhere */
 615         case RADEON_CP_3D_DRAW_INDX_2:  /* triggers drawing using indices to vertex buffer */
 616         case RADEON_WAIT_FOR_IDLE:
 617         case RADEON_CP_NOP:
 618                 /* these packets are safe */
 619                 break;
 620         default:
 621                 DRM_ERROR("Unknown packet3 header (0x%08x)\n", header);
 622                 return -EINVAL;
 623         }
 624
 625         BEGIN_RING(count + 2);
 626         OUT_RING(header);
 627         OUT_RING_TABLE((int *)(cmdbuf->buf + 4), count + 1);
 628         ADVANCE_RING();
 629
 630         cmdbuf->buf += (count + 2) * 4;
 631         cmdbuf->bufsz -= (count + 2) * 4;
 632
 633         return 0;
 634 }
 635
 636 /**
 637  * Emit a rendering packet3 from userspace.
 638  * Called by r300_do_cp_cmdbuf.
 639  */
 640 static __inline__ int r300_emit_packet3(drm_radeon_private_t *dev_priv,
 641                                         drm_radeon_kcmd_buffer_t *cmdbuf,
 642                                         drm_r300_cmd_header_t header)
 643 {
 644         int n;
 645         int ret;
 646         char *orig_buf = cmdbuf->buf;
 647         int orig_bufsz = cmdbuf->bufsz;
 648
 649         /* This is a do-while-loop so that we run the interior at least once,
 650          * even if cmdbuf->nbox is 0. Compare r300_emit_cliprects for rationale.
 651          */
 652         n = 0;
 653         do {
 654                 if (cmdbuf->nbox > R300_SIMULTANEOUS_CLIPRECTS) {
 655                         ret = r300_emit_cliprects(dev_priv, cmdbuf, n);
 656                         if (ret)
 657                                 return ret;
 658
 659                         cmdbuf->buf = orig_buf;
 660                         cmdbuf->bufsz = orig_bufsz;
 661                 }
 662
 663                 switch (header.packet3.packet) {
 664                 case R300_CMD_PACKET3_CLEAR:
 665                         DRM_DEBUG("R300_CMD_PACKET3_CLEAR\n");
 666                         ret = r300_emit_clear(dev_priv, cmdbuf);
 667                         if (ret) {
 668                                 DRM_ERROR("r300_emit_clear failed\n");
 669                                 return ret;
 670                         }
 671                         break;
 672
 673                 case R300_CMD_PACKET3_RAW:
 674                         DRM_DEBUG("R300_CMD_PACKET3_RAW\n");
 675                         ret = r300_emit_raw_packet3(dev_priv, cmdbuf);
 676                         if (ret) {
 677                                 DRM_ERROR("r300_emit_raw_packet3 failed\n");
 678                                 return ret;
 679                         }
 680                         break;
 681
 682                 default:
 683                         DRM_ERROR("bad packet3 type %i at %p\n",
 684                                   header.packet3.packet,
 685                                   cmdbuf->buf - sizeof(header));
 686                         return -EINVAL;
 687                 }
 688
 689                 n += R300_SIMULTANEOUS_CLIPRECTS;
 690         } while (n < cmdbuf->nbox);
 691
 692         return 0;
 693 }
 694
 695 /* Some of the R300 chips seem to be extremely touchy about the two registers
 696  * that are configured in r300_pacify.
 697  * Among the worst offenders seems to be the R300 ND (0x4E44): When userspace
 698  * sends a command buffer that contains only state setting commands and a
 699  * vertex program/parameter upload sequence, this will eventually lead to a
 700  * lockup, unless the sequence is bracketed by calls to r300_pacify.
 701  * So we should take great care to *always* call r300_pacify before
 702  * *anything* 3D related, and again afterwards. This is what the
 703  * call bracket in r300_do_cp_cmdbuf is for.
 704  */
 705
 706 /**
 707  * Emit the sequence to pacify R300.
 708  */
 709 static __inline__ void r300_pacify(drm_radeon_private_t *dev_priv)
 710 {
 711         RING_LOCALS;
 712
 713         BEGIN_RING(6);
 714         OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 715         OUT_RING(R300_RB3D_DSTCACHE_UNKNOWN_0A);
 716         OUT_RING(CP_PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
 717         OUT_RING(R300_RB3D_ZCACHE_UNKNOWN_03);
 718         OUT_RING(CP_PACKET3(RADEON_CP_NOP, 0));
 719         OUT_RING(0x0);
 720         ADVANCE_RING();
 721 }
 722
 723 /**
 724  * Called by r300_do_cp_cmdbuf to update the internal buffer age and state.
 725  * The actual age emit is done by r300_do_cp_cmdbuf, which is why you must
 726  * be careful about how this function is called.
 727  */
 728 static void r300_discard_buffer(struct drm_device * dev, struct drm_buf * buf)
 729 {
 730         drm_radeon_private_t *dev_priv = dev->dev_private;
 731         drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
 732
 733         buf_priv->age = ++dev_priv->sarea_priv->last_dispatch;
 734         buf->pending = 1;
 735         buf->used = 0;
 736 }
 737
 738 static int r300_scratch(drm_radeon_private_t *dev_priv,
 739                         drm_radeon_kcmd_buffer_t *cmdbuf,
 740                         drm_r300_cmd_header_t header)
 741 {
 742         u32 *ref_age_base;
 743         u32 i, buf_idx, h_pending;
 744         RING_LOCALS;
 745
 746         if (cmdbuf->bufsz < sizeof(uint64_t) + header.scratch.n_bufs * sizeof(buf_idx) ) {
 747                 return -EINVAL;
 748         }
 749
 750         if (header.scratch.reg >= 5) {
 751                 return -EINVAL;
 752         }
 753
 754         dev_priv->scratch_ages[header.scratch.reg] ++;
 755
 756         ref_age_base = (u32 *)(unsigned long)*((uint64_t *)cmdbuf->buf);
 757
 758         cmdbuf->buf += sizeof(uint64_t);
 759         cmdbuf->bufsz -= sizeof(uint64_t);
 760
 761         for (i=0; i < header.scratch.n_bufs; i++) {
 762                 buf_idx = *(u32 *)cmdbuf->buf;
 763                 buf_idx *= 2; /* 8 bytes per buf */
 764
 765                 if (DRM_COPY_TO_USER(ref_age_base + buf_idx, &dev_priv->scratch_ages[header.scratch.reg], sizeof(u32))) {
 766                         return -EINVAL;
 767                 }
 768
 769                 if (DRM_COPY_FROM_USER(&h_pending, ref_age_base + buf_idx + 1, sizeof(u32))) {
 770                         return -EINVAL;
 771                 }
 772
 773                 if (h_pending == 0) {
 774                         return -EINVAL;
 775                 }
 776
 777                 h_pending--;
 778
 779                 if (DRM_COPY_TO_USER(ref_age_base + buf_idx + 1, &h_pending, sizeof(u32))) {
 780                         return -EINVAL;
 781                 }
 782
 783                 cmdbuf->buf += sizeof(buf_idx);
 784                 cmdbuf->bufsz -= sizeof(buf_idx);
 785         }
 786
 787         BEGIN_RING(2);
 788         OUT_RING( CP_PACKET0( RADEON_SCRATCH_REG0 + header.scratch.reg * 4, 0 ) );
 789         OUT_RING( dev_priv->scratch_ages[header.scratch.reg] );
 790         ADVANCE_RING();
 791
 792         return 0;
 793 }
 794
 795 /**
 796  * Uploads user-supplied vertex program instructions or parameters onto
 797  * the graphics card.
 798  * Called by r300_do_cp_cmdbuf.
 799  */
 800 static __inline__ int r300_emit_r500fp(drm_radeon_private_t *dev_priv,
 801                                        drm_radeon_kcmd_buffer_t *cmdbuf,
 802                                        drm_r300_cmd_header_t header)
 803 {
 804         int sz;
 805         int addr;
 806         RING_LOCALS;
 807
 808         sz = header.r500fp.count;
 809         addr = (header.r500fp.adrhi << 8) | header.r500fp.adrlo;
 810
 811         if (!sz)
 812                 return 0;
 813         if (sz * 16 > cmdbuf->bufsz)
 814                 return -EINVAL;
 815
 816         BEGIN_RING(4 + sz * 4);
 817         /* Wait for VAP to come to senses.. */
 818         /* there is no need to emit it multiple times, (only once before VAP is programmed,
 819            but this optimization is for later */
 820         OUT_RING_REG(R500_GA_US_VECTOR_INDEX, addr);
 821         OUT_RING(CP_PACKET0_TABLE(R500_GA_US_VECTOR_DATA, sz * 4 - 1));
 822         OUT_RING_TABLE((int *)cmdbuf->buf, sz * 4);
 823
 824         ADVANCE_RING();
 825
 826         cmdbuf->buf += sz * 16;
 827         cmdbuf->bufsz -= sz * 16;
 828
 829         return 0;
 830 }
 831
 832
 833 /**
 834  * Parses and validates a user-supplied command buffer and emits appropriate
 835  * commands on the DMA ring buffer.
 836  * Called by the ioctl handler function radeon_cp_cmdbuf.
 837  */
 838 int r300_do_cp_cmdbuf(struct drm_device *dev,
 839                       struct drm_file *file_priv,
 840                       drm_radeon_kcmd_buffer_t *cmdbuf)
 841 {
 842         drm_radeon_private_t *dev_priv = dev->dev_private;
 843         struct drm_device_dma *dma = dev->dma;
 844         struct drm_buf *buf = NULL;
 845         int emit_dispatch_age = 0;
 846         int ret = 0;
 847
 848         DRM_DEBUG("\n");
 849
 850         /* See the comment above r300_emit_begin3d for why this call must be here,
 851          * and what the cleanup gotos are for. */
 852         r300_pacify(dev_priv);
 853
 854         if (cmdbuf->nbox <= R300_SIMULTANEOUS_CLIPRECTS) {
 855                 ret = r300_emit_cliprects(dev_priv, cmdbuf, 0);
 856                 if (ret)
 857                         goto cleanup;
 858         }
 859
 860         while (cmdbuf->bufsz >= sizeof(drm_r300_cmd_header_t)) {
 861                 int idx;
 862                 drm_r300_cmd_header_t header;
 863
 864                 header.u = *(unsigned int *)cmdbuf->buf;
 865
 866                 cmdbuf->buf += sizeof(header);
 867                 cmdbuf->bufsz -= sizeof(header);
 868
 869                 switch (header.header.cmd_type) {
 870                 case R300_CMD_PACKET0:
 871                         DRM_DEBUG("R300_CMD_PACKET0\n");
 872                         ret = r300_emit_packet0(dev_priv, cmdbuf, header);
 873                         if (ret) {
 874                                 DRM_ERROR("r300_emit_packet0 failed\n");
 875                                 goto cleanup;
 876                         }
 877                         break;
 878
 879                 case R300_CMD_VPU:
 880                         DRM_DEBUG("R300_CMD_VPU\n");
 881                         ret = r300_emit_vpu(dev_priv, cmdbuf, header);
 882                         if (ret) {
 883                                 DRM_ERROR("r300_emit_vpu failed\n");
 884                                 goto cleanup;
 885                         }
 886                         break;
 887
 888                 case R300_CMD_PACKET3:
 889                         DRM_DEBUG("R300_CMD_PACKET3\n");
 890                         ret = r300_emit_packet3(dev_priv, cmdbuf, header);
 891                         if (ret) {
 892                                 DRM_ERROR("r300_emit_packet3 failed\n");
 893                                 goto cleanup;
 894                         }
 895                         break;
 896
 897                 case R300_CMD_END3D:
 898                         DRM_DEBUG("R300_CMD_END3D\n");
 899                         /* TODO:
 900                            Ideally userspace driver should not need to issue this call,
 901                            i.e. the drm driver should issue it automatically and prevent
 902                            lockups.
 903
 904                            In practice, we do not understand why this call is needed and what
 905                            it does (except for some vague guesses that it has to do with cache
 906                            coherence) and so the user space driver does it.
 907
 908                            Once we are sure which uses prevent lockups the code could be moved
 909                            into the kernel and the userspace driver will not
 910                            need to use this command.
 911
 912                            Note that issuing this command does not hurt anything
 913                            except, possibly, performance */
 914                         r300_pacify(dev_priv);
 915                         break;
 916
 917                 case R300_CMD_CP_DELAY:
 918                         /* simple enough, we can do it here */
 919                         DRM_DEBUG("R300_CMD_CP_DELAY\n");
 920                         {
 921                                 int i;
 922                                 RING_LOCALS;
 923
 924                                 BEGIN_RING(header.delay.count);
 925                                 for (i = 0; i < header.delay.count; i++)
 926                                         OUT_RING(RADEON_CP_PACKET2);
 927                                 ADVANCE_RING();
 928                         }
 929                         break;
 930
 931                 case R300_CMD_DMA_DISCARD:
 932                         DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n");
 933                         idx = header.dma.buf_idx;
 934                         if (idx < 0 || idx >= dma->buf_count) {
 935                                 DRM_ERROR("buffer index %d (of %d max)\n",
 936                                           idx, dma->buf_count - 1);
 937                                 ret = -EINVAL;
 938                                 goto cleanup;
 939                         }
 940
 941                         buf = dma->buflist[idx];
 942                         if (buf->file_priv != file_priv || buf->pending) {
 943                                 DRM_ERROR("bad buffer %p %p %d\n",
 944                                           buf->file_priv, file_priv,
 945                                           buf->pending);
 946                                 ret = -EINVAL;
 947                                 goto cleanup;
 948                         }
 949
 950                         emit_dispatch_age = 1;
 951                         r300_discard_buffer(dev, buf);
 952                         break;
 953
 954                 case R300_CMD_WAIT:
 955                         /* simple enough, we can do it here */
 956                         DRM_DEBUG("R300_CMD_WAIT\n");
 957                         if (header.wait.flags == 0)
 958                                 break;  /* nothing to do */
 959
 960                         {
 961                                 RING_LOCALS;
 962
 963                                 BEGIN_RING(2);
 964                                 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
 965                                 OUT_RING((header.wait.flags & 0xf) << 14);
 966                                 ADVANCE_RING();
 967                         }
 968                         break;
 969
 970                 case R300_CMD_SCRATCH:
 971                         DRM_DEBUG("R300_CMD_SCRATCH\n");
 972                         ret = r300_scratch(dev_priv, cmdbuf, header);
 973                         if (ret) {
 974                                 DRM_ERROR("r300_scratch failed\n");
 975                                 goto cleanup;
 976                         }
 977                         break;
 978
 979                 case R300_CMD_R500FP:
 980                         if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) {
 981                                 DRM_ERROR("Calling r500 command on r300 card\n");
 982                                 ret = -EINVAL;
 983                                 goto cleanup;
 984                         }
 985                         DRM_DEBUG("R300_CMD_R500FP\n");
 986                         ret = r300_emit_r500fp(dev_priv, cmdbuf, header);
 987                         if (ret) {
 988                                 DRM_ERROR("r300_emit_r500fp failed\n");
 989                                 goto cleanup;
 990                         }
 991                         break;
 992                 default:
 993                         DRM_ERROR("bad cmd_type %i at %p\n",
 994                                   header.header.cmd_type,
 995                                   cmdbuf->buf - sizeof(header));
 996                         ret = -EINVAL;
 997                         goto cleanup;
 998                 }
 999         }
1000
1001         DRM_DEBUG("END\n");
1002
1003       cleanup:
1004         r300_pacify(dev_priv);
1005
1006         /* We emit the vertex buffer age here, outside the pacifier "brackets"
1007          * for two reasons:
1008          *  (1) This may coalesce multiple age emissions into a single one and
1009          *  (2) more importantly, some chips lock up hard when scratch registers
1010          *      are written inside the pacifier bracket.
1011          */
1012         if (emit_dispatch_age) {
1013                 RING_LOCALS;
1014
1015                 /* Emit the vertex buffer age */
1016                 BEGIN_RING(2);
1017                 RADEON_DISPATCH_AGE(dev_priv->sarea_priv->last_dispatch);
1018                 ADVANCE_RING();
1019         }
1020
1021         COMMIT_RING();
1022
1023         return ret;
1024 }