1 /* r128_state.c -- State support for r128 -*- linux-c -*-
2 * Created: Thu Jan 27 02:53:43 2000 by gareth@valinux.com
4 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
27 * Gareth Hughes <gareth@valinux.com>
38 * 2.4 - Add support for ycbcr textures (no new ioctls)
39 * 2.5 - Add FLIP ioctl, disable FULLSCREEN.
41 drm_ioctl_desc_t r128_ioctls[] = {
42 [DRM_IOCTL_NR(DRM_R128_INIT)] = {r128_cce_init, 1, 1},
43 [DRM_IOCTL_NR(DRM_R128_CCE_START)] = {r128_cce_start, 1, 1},
44 [DRM_IOCTL_NR(DRM_R128_CCE_STOP)] = {r128_cce_stop, 1, 1},
45 [DRM_IOCTL_NR(DRM_R128_CCE_RESET)] = {r128_cce_reset, 1, 1},
46 [DRM_IOCTL_NR(DRM_R128_CCE_IDLE)] = {r128_cce_idle, 1, 0},
47 [DRM_IOCTL_NR(DRM_R128_RESET)] = {r128_engine_reset, 1, 0},
48 [DRM_IOCTL_NR(DRM_R128_FULLSCREEN)] = {r128_fullscreen, 1, 0},
49 [DRM_IOCTL_NR(DRM_R128_SWAP)] = {r128_cce_swap, 1, 0},
50 [DRM_IOCTL_NR(DRM_R128_FLIP)] = {r128_cce_flip, 1, 0},
51 [DRM_IOCTL_NR(DRM_R128_CLEAR)] = {r128_cce_clear, 1, 0},
52 [DRM_IOCTL_NR(DRM_R128_VERTEX)] = {r128_cce_vertex, 1, 0},
53 [DRM_IOCTL_NR(DRM_R128_INDICES)] = {r128_cce_indices, 1, 0},
54 [DRM_IOCTL_NR(DRM_R128_BLIT)] = {r128_cce_blit, 1, 0},
55 [DRM_IOCTL_NR(DRM_R128_DEPTH)] = {r128_cce_depth, 1, 0},
56 [DRM_IOCTL_NR(DRM_R128_STIPPLE)] = {r128_cce_stipple, 1, 0},
57 [DRM_IOCTL_NR(DRM_R128_INDIRECT)] = {r128_cce_indirect, 1, 1},
58 [DRM_IOCTL_NR(DRM_R128_GETPARAM)] = {r128_getparam, 1, 0},
61 int r128_max_ioctl = DRM_ARRAY_SIZE(r128_ioctls);
63 /* ================================================================
64 * CCE hardware state programming functions
67 static void r128_emit_clip_rects(drm_r128_private_t * dev_priv,
68 drm_clip_rect_t * boxes, int count)
70 u32 aux_sc_cntl = 0x00000000;
72 DRM_DEBUG(" %s\n", __FUNCTION__);
74 BEGIN_RING((count < 3 ? count : 3) * 5 + 2);
77 OUT_RING(CCE_PACKET0(R128_AUX1_SC_LEFT, 3));
78 OUT_RING(boxes[0].x1);
79 OUT_RING(boxes[0].x2 - 1);
80 OUT_RING(boxes[0].y1);
81 OUT_RING(boxes[0].y2 - 1);
83 aux_sc_cntl |= (R128_AUX1_SC_EN | R128_AUX1_SC_MODE_OR);
86 OUT_RING(CCE_PACKET0(R128_AUX2_SC_LEFT, 3));
87 OUT_RING(boxes[1].x1);
88 OUT_RING(boxes[1].x2 - 1);
89 OUT_RING(boxes[1].y1);
90 OUT_RING(boxes[1].y2 - 1);
92 aux_sc_cntl |= (R128_AUX2_SC_EN | R128_AUX2_SC_MODE_OR);
95 OUT_RING(CCE_PACKET0(R128_AUX3_SC_LEFT, 3));
96 OUT_RING(boxes[2].x1);
97 OUT_RING(boxes[2].x2 - 1);
98 OUT_RING(boxes[2].y1);
99 OUT_RING(boxes[2].y2 - 1);
101 aux_sc_cntl |= (R128_AUX3_SC_EN | R128_AUX3_SC_MODE_OR);
104 OUT_RING(CCE_PACKET0(R128_AUX_SC_CNTL, 0));
105 OUT_RING(aux_sc_cntl);
110 static __inline__ void r128_emit_core(drm_r128_private_t * dev_priv)
112 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
113 drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
115 DRM_DEBUG(" %s\n", __FUNCTION__);
119 OUT_RING(CCE_PACKET0(R128_SCALE_3D_CNTL, 0));
120 OUT_RING(ctx->scale_3d_cntl);
125 static __inline__ void r128_emit_context(drm_r128_private_t * dev_priv)
127 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
128 drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
130 DRM_DEBUG(" %s\n", __FUNCTION__);
134 OUT_RING(CCE_PACKET0(R128_DST_PITCH_OFFSET_C, 11));
135 OUT_RING(ctx->dst_pitch_offset_c);
136 OUT_RING(ctx->dp_gui_master_cntl_c);
137 OUT_RING(ctx->sc_top_left_c);
138 OUT_RING(ctx->sc_bottom_right_c);
139 OUT_RING(ctx->z_offset_c);
140 OUT_RING(ctx->z_pitch_c);
141 OUT_RING(ctx->z_sten_cntl_c);
142 OUT_RING(ctx->tex_cntl_c);
143 OUT_RING(ctx->misc_3d_state_cntl_reg);
144 OUT_RING(ctx->texture_clr_cmp_clr_c);
145 OUT_RING(ctx->texture_clr_cmp_msk_c);
146 OUT_RING(ctx->fog_color_c);
151 static __inline__ void r128_emit_setup(drm_r128_private_t * dev_priv)
153 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
154 drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
156 DRM_DEBUG(" %s\n", __FUNCTION__);
160 OUT_RING(CCE_PACKET1(R128_SETUP_CNTL, R128_PM4_VC_FPU_SETUP));
161 OUT_RING(ctx->setup_cntl);
162 OUT_RING(ctx->pm4_vc_fpu_setup);
167 static __inline__ void r128_emit_masks(drm_r128_private_t * dev_priv)
169 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
170 drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
172 DRM_DEBUG(" %s\n", __FUNCTION__);
176 OUT_RING(CCE_PACKET0(R128_DP_WRITE_MASK, 0));
177 OUT_RING(ctx->dp_write_mask);
179 OUT_RING(CCE_PACKET0(R128_STEN_REF_MASK_C, 1));
180 OUT_RING(ctx->sten_ref_mask_c);
181 OUT_RING(ctx->plane_3d_mask_c);
186 static __inline__ void r128_emit_window(drm_r128_private_t * dev_priv)
188 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
189 drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
191 DRM_DEBUG(" %s\n", __FUNCTION__);
195 OUT_RING(CCE_PACKET0(R128_WINDOW_XY_OFFSET, 0));
196 OUT_RING(ctx->window_xy_offset);
201 static __inline__ void r128_emit_tex0(drm_r128_private_t * dev_priv)
203 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
204 drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
205 drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[0];
208 DRM_DEBUG(" %s\n", __FUNCTION__);
210 BEGIN_RING(7 + R128_MAX_TEXTURE_LEVELS);
212 OUT_RING(CCE_PACKET0(R128_PRIM_TEX_CNTL_C,
213 2 + R128_MAX_TEXTURE_LEVELS));
214 OUT_RING(tex->tex_cntl);
215 OUT_RING(tex->tex_combine_cntl);
216 OUT_RING(ctx->tex_size_pitch_c);
217 for (i = 0; i < R128_MAX_TEXTURE_LEVELS; i++) {
218 OUT_RING(tex->tex_offset[i]);
221 OUT_RING(CCE_PACKET0(R128_CONSTANT_COLOR_C, 1));
222 OUT_RING(ctx->constant_color_c);
223 OUT_RING(tex->tex_border_color);
228 static __inline__ void r128_emit_tex1(drm_r128_private_t * dev_priv)
230 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
231 drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[1];
234 DRM_DEBUG(" %s\n", __FUNCTION__);
236 BEGIN_RING(5 + R128_MAX_TEXTURE_LEVELS);
238 OUT_RING(CCE_PACKET0(R128_SEC_TEX_CNTL_C, 1 + R128_MAX_TEXTURE_LEVELS));
239 OUT_RING(tex->tex_cntl);
240 OUT_RING(tex->tex_combine_cntl);
241 for (i = 0; i < R128_MAX_TEXTURE_LEVELS; i++) {
242 OUT_RING(tex->tex_offset[i]);
245 OUT_RING(CCE_PACKET0(R128_SEC_TEXTURE_BORDER_COLOR_C, 0));
246 OUT_RING(tex->tex_border_color);
251 static __inline__ void r128_emit_state(drm_r128_private_t * dev_priv)
253 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
254 unsigned int dirty = sarea_priv->dirty;
256 DRM_DEBUG("%s: dirty=0x%08x\n", __FUNCTION__, dirty);
258 if (dirty & R128_UPLOAD_CORE) {
259 r128_emit_core(dev_priv);
260 sarea_priv->dirty &= ~R128_UPLOAD_CORE;
263 if (dirty & R128_UPLOAD_CONTEXT) {
264 r128_emit_context(dev_priv);
265 sarea_priv->dirty &= ~R128_UPLOAD_CONTEXT;
268 if (dirty & R128_UPLOAD_SETUP) {
269 r128_emit_setup(dev_priv);
270 sarea_priv->dirty &= ~R128_UPLOAD_SETUP;
273 if (dirty & R128_UPLOAD_MASKS) {
274 r128_emit_masks(dev_priv);
275 sarea_priv->dirty &= ~R128_UPLOAD_MASKS;
278 if (dirty & R128_UPLOAD_WINDOW) {
279 r128_emit_window(dev_priv);
280 sarea_priv->dirty &= ~R128_UPLOAD_WINDOW;
283 if (dirty & R128_UPLOAD_TEX0) {
284 r128_emit_tex0(dev_priv);
285 sarea_priv->dirty &= ~R128_UPLOAD_TEX0;
288 if (dirty & R128_UPLOAD_TEX1) {
289 r128_emit_tex1(dev_priv);
290 sarea_priv->dirty &= ~R128_UPLOAD_TEX1;
293 /* Turn off the texture cache flushing */
294 sarea_priv->context_state.tex_cntl_c &= ~R128_TEX_CACHE_FLUSH;
296 sarea_priv->dirty &= ~R128_REQUIRE_QUIESCENCE;
299 #if R128_PERFORMANCE_BOXES
300 /* ================================================================
301 * Performance monitoring functions
304 static void r128_clear_box(drm_r128_private_t * dev_priv,
305 int x, int y, int w, int h, int r, int g, int b)
311 switch (dev_priv->fb_bpp) {
313 fb_bpp = R128_GMC_DST_16BPP;
314 color = (((r & 0xf8) << 8) |
315 ((g & 0xfc) << 3) | ((b & 0xf8) >> 3));
318 fb_bpp = R128_GMC_DST_24BPP;
319 color = ((r << 16) | (g << 8) | b);
322 fb_bpp = R128_GMC_DST_32BPP;
323 color = (((0xff) << 24) | (r << 16) | (g << 8) | b);
329 offset = dev_priv->back_offset;
330 pitch = dev_priv->back_pitch >> 3;
334 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
335 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
336 R128_GMC_BRUSH_SOLID_COLOR |
338 R128_GMC_SRC_DATATYPE_COLOR |
340 R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_AUX_CLIP_DIS);
342 OUT_RING((pitch << 21) | (offset >> 5));
345 OUT_RING((x << 16) | y);
346 OUT_RING((w << 16) | h);
351 static void r128_cce_performance_boxes(drm_r128_private_t * dev_priv)
353 if (atomic_read(&dev_priv->idle_count) == 0) {
354 r128_clear_box(dev_priv, 64, 4, 8, 8, 0, 255, 0);
356 atomic_set(&dev_priv->idle_count, 0);
362 /* ================================================================
363 * CCE command dispatch functions
366 static void r128_print_dirty(const char *msg, unsigned int flags)
368 DRM_INFO("%s: (0x%x) %s%s%s%s%s%s%s%s%s\n",
371 (flags & R128_UPLOAD_CORE) ? "core, " : "",
372 (flags & R128_UPLOAD_CONTEXT) ? "context, " : "",
373 (flags & R128_UPLOAD_SETUP) ? "setup, " : "",
374 (flags & R128_UPLOAD_TEX0) ? "tex0, " : "",
375 (flags & R128_UPLOAD_TEX1) ? "tex1, " : "",
376 (flags & R128_UPLOAD_MASKS) ? "masks, " : "",
377 (flags & R128_UPLOAD_WINDOW) ? "window, " : "",
378 (flags & R128_UPLOAD_CLIPRECTS) ? "cliprects, " : "",
379 (flags & R128_REQUIRE_QUIESCENCE) ? "quiescence, " : "");
382 static void r128_cce_dispatch_clear(drm_device_t * dev,
383 drm_r128_clear_t * clear)
385 drm_r128_private_t *dev_priv = dev->dev_private;
386 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
387 int nbox = sarea_priv->nbox;
388 drm_clip_rect_t *pbox = sarea_priv->boxes;
389 unsigned int flags = clear->flags;
392 DRM_DEBUG("%s\n", __FUNCTION__);
394 if (dev_priv->page_flipping && dev_priv->current_page == 1) {
395 unsigned int tmp = flags;
397 flags &= ~(R128_FRONT | R128_BACK);
398 if (tmp & R128_FRONT)
404 for (i = 0; i < nbox; i++) {
407 int w = pbox[i].x2 - x;
408 int h = pbox[i].y2 - y;
410 DRM_DEBUG("dispatch clear %d,%d-%d,%d flags 0x%x\n",
411 pbox[i].x1, pbox[i].y1, pbox[i].x2,
414 if (flags & (R128_FRONT | R128_BACK)) {
417 OUT_RING(CCE_PACKET0(R128_DP_WRITE_MASK, 0));
418 OUT_RING(clear->color_mask);
423 if (flags & R128_FRONT) {
426 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
427 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
428 R128_GMC_BRUSH_SOLID_COLOR |
429 (dev_priv->color_fmt << 8) |
430 R128_GMC_SRC_DATATYPE_COLOR |
432 R128_GMC_CLR_CMP_CNTL_DIS |
433 R128_GMC_AUX_CLIP_DIS);
435 OUT_RING(dev_priv->front_pitch_offset_c);
436 OUT_RING(clear->clear_color);
438 OUT_RING((x << 16) | y);
439 OUT_RING((w << 16) | h);
444 if (flags & R128_BACK) {
447 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
448 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
449 R128_GMC_BRUSH_SOLID_COLOR |
450 (dev_priv->color_fmt << 8) |
451 R128_GMC_SRC_DATATYPE_COLOR |
453 R128_GMC_CLR_CMP_CNTL_DIS |
454 R128_GMC_AUX_CLIP_DIS);
456 OUT_RING(dev_priv->back_pitch_offset_c);
457 OUT_RING(clear->clear_color);
459 OUT_RING((x << 16) | y);
460 OUT_RING((w << 16) | h);
465 if (flags & R128_DEPTH) {
468 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
469 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
470 R128_GMC_BRUSH_SOLID_COLOR |
471 (dev_priv->depth_fmt << 8) |
472 R128_GMC_SRC_DATATYPE_COLOR |
474 R128_GMC_CLR_CMP_CNTL_DIS |
475 R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS);
477 OUT_RING(dev_priv->depth_pitch_offset_c);
478 OUT_RING(clear->clear_depth);
480 OUT_RING((x << 16) | y);
481 OUT_RING((w << 16) | h);
488 static void r128_cce_dispatch_swap(drm_device_t * dev)
490 drm_r128_private_t *dev_priv = dev->dev_private;
491 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
492 int nbox = sarea_priv->nbox;
493 drm_clip_rect_t *pbox = sarea_priv->boxes;
496 DRM_DEBUG("%s\n", __FUNCTION__);
498 #if R128_PERFORMANCE_BOXES
499 /* Do some trivial performance monitoring...
501 r128_cce_performance_boxes(dev_priv);
504 for (i = 0; i < nbox; i++) {
507 int w = pbox[i].x2 - x;
508 int h = pbox[i].y2 - y;
512 OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5));
513 OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL |
514 R128_GMC_DST_PITCH_OFFSET_CNTL |
515 R128_GMC_BRUSH_NONE |
516 (dev_priv->color_fmt << 8) |
517 R128_GMC_SRC_DATATYPE_COLOR |
519 R128_DP_SRC_SOURCE_MEMORY |
520 R128_GMC_CLR_CMP_CNTL_DIS |
521 R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS);
523 /* Make this work even if front & back are flipped:
525 if (dev_priv->current_page == 0) {
526 OUT_RING(dev_priv->back_pitch_offset_c);
527 OUT_RING(dev_priv->front_pitch_offset_c);
529 OUT_RING(dev_priv->front_pitch_offset_c);
530 OUT_RING(dev_priv->back_pitch_offset_c);
533 OUT_RING((x << 16) | y);
534 OUT_RING((x << 16) | y);
535 OUT_RING((w << 16) | h);
540 /* Increment the frame counter. The client-side 3D driver must
541 * throttle the framerate by waiting for this value before
542 * performing the swapbuffer ioctl.
544 dev_priv->sarea_priv->last_frame++;
548 OUT_RING(CCE_PACKET0(R128_LAST_FRAME_REG, 0));
549 OUT_RING(dev_priv->sarea_priv->last_frame);
554 static void r128_cce_dispatch_flip(drm_device_t * dev)
556 drm_r128_private_t *dev_priv = dev->dev_private;
558 DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
560 dev_priv->current_page, dev_priv->sarea_priv->pfCurrentPage);
562 #if R128_PERFORMANCE_BOXES
563 /* Do some trivial performance monitoring...
565 r128_cce_performance_boxes(dev_priv);
570 R128_WAIT_UNTIL_PAGE_FLIPPED();
571 OUT_RING(CCE_PACKET0(R128_CRTC_OFFSET, 0));
573 if (dev_priv->current_page == 0) {
574 OUT_RING(dev_priv->back_offset);
576 OUT_RING(dev_priv->front_offset);
581 /* Increment the frame counter. The client-side 3D driver must
582 * throttle the framerate by waiting for this value before
583 * performing the swapbuffer ioctl.
585 dev_priv->sarea_priv->last_frame++;
586 dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page =
587 1 - dev_priv->current_page;
591 OUT_RING(CCE_PACKET0(R128_LAST_FRAME_REG, 0));
592 OUT_RING(dev_priv->sarea_priv->last_frame);
597 static void r128_cce_dispatch_vertex(drm_device_t * dev, drm_buf_t * buf)
599 drm_r128_private_t *dev_priv = dev->dev_private;
600 drm_r128_buf_priv_t *buf_priv = buf->dev_private;
601 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
602 int format = sarea_priv->vc_format;
603 int offset = buf->bus_address;
604 int size = buf->used;
605 int prim = buf_priv->prim;
608 DRM_DEBUG("buf=%d nbox=%d\n", buf->idx, sarea_priv->nbox);
611 r128_print_dirty("dispatch_vertex", sarea_priv->dirty);
614 buf_priv->dispatched = 1;
616 if (sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS) {
617 r128_emit_state(dev_priv);
621 /* Emit the next set of up to three cliprects */
622 if (i < sarea_priv->nbox) {
623 r128_emit_clip_rects(dev_priv,
624 &sarea_priv->boxes[i],
625 sarea_priv->nbox - i);
628 /* Emit the vertex buffer rendering commands */
631 OUT_RING(CCE_PACKET3(R128_3D_RNDR_GEN_INDX_PRIM, 3));
635 OUT_RING(prim | R128_CCE_VC_CNTL_PRIM_WALK_LIST |
636 (size << R128_CCE_VC_CNTL_NUM_SHIFT));
641 } while (i < sarea_priv->nbox);
644 if (buf_priv->discard) {
645 buf_priv->age = dev_priv->sarea_priv->last_dispatch;
647 /* Emit the vertex buffer age */
650 OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0));
651 OUT_RING(buf_priv->age);
657 /* FIXME: Check dispatched field */
658 buf_priv->dispatched = 0;
661 dev_priv->sarea_priv->last_dispatch++;
663 sarea_priv->dirty &= ~R128_UPLOAD_CLIPRECTS;
664 sarea_priv->nbox = 0;
667 static void r128_cce_dispatch_indirect(drm_device_t * dev,
668 drm_buf_t * buf, int start, int end)
670 drm_r128_private_t *dev_priv = dev->dev_private;
671 drm_r128_buf_priv_t *buf_priv = buf->dev_private;
673 DRM_DEBUG("indirect: buf=%d s=0x%x e=0x%x\n", buf->idx, start, end);
676 int offset = buf->bus_address + start;
677 int dwords = (end - start + 3) / sizeof(u32);
679 /* Indirect buffer data must be an even number of
680 * dwords, so if we've been given an odd number we must
681 * pad the data with a Type-2 CCE packet.
685 ((char *)dev->agp_buffer_map->handle
686 + buf->offset + start);
687 data[dwords++] = cpu_to_le32(R128_CCE_PACKET2);
690 buf_priv->dispatched = 1;
692 /* Fire off the indirect buffer */
695 OUT_RING(CCE_PACKET0(R128_PM4_IW_INDOFF, 1));
702 if (buf_priv->discard) {
703 buf_priv->age = dev_priv->sarea_priv->last_dispatch;
705 /* Emit the indirect buffer age */
708 OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0));
709 OUT_RING(buf_priv->age);
715 /* FIXME: Check dispatched field */
716 buf_priv->dispatched = 0;
719 dev_priv->sarea_priv->last_dispatch++;
722 static void r128_cce_dispatch_indices(drm_device_t * dev,
724 int start, int end, int count)
726 drm_r128_private_t *dev_priv = dev->dev_private;
727 drm_r128_buf_priv_t *buf_priv = buf->dev_private;
728 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
729 int format = sarea_priv->vc_format;
730 int offset = dev->agp_buffer_map->offset - dev_priv->cce_buffers_offset;
731 int prim = buf_priv->prim;
736 DRM_DEBUG("indices: s=%d e=%d c=%d\n", start, end, count);
739 r128_print_dirty("dispatch_indices", sarea_priv->dirty);
742 buf_priv->dispatched = 1;
744 if (sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS) {
745 r128_emit_state(dev_priv);
748 dwords = (end - start + 3) / sizeof(u32);
750 data = (u32 *) ((char *)dev->agp_buffer_map->handle
751 + buf->offset + start);
753 data[0] = cpu_to_le32(CCE_PACKET3(R128_3D_RNDR_GEN_INDX_PRIM,
756 data[1] = cpu_to_le32(offset);
757 data[2] = cpu_to_le32(R128_MAX_VB_VERTS);
758 data[3] = cpu_to_le32(format);
759 data[4] = cpu_to_le32((prim | R128_CCE_VC_CNTL_PRIM_WALK_IND |
763 #ifdef __LITTLE_ENDIAN
764 data[dwords - 1] &= 0x0000ffff;
766 data[dwords - 1] &= 0xffff0000;
771 /* Emit the next set of up to three cliprects */
772 if (i < sarea_priv->nbox) {
773 r128_emit_clip_rects(dev_priv,
774 &sarea_priv->boxes[i],
775 sarea_priv->nbox - i);
778 r128_cce_dispatch_indirect(dev, buf, start, end);
781 } while (i < sarea_priv->nbox);
784 if (buf_priv->discard) {
785 buf_priv->age = dev_priv->sarea_priv->last_dispatch;
787 /* Emit the vertex buffer age */
790 OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0));
791 OUT_RING(buf_priv->age);
796 /* FIXME: Check dispatched field */
797 buf_priv->dispatched = 0;
800 dev_priv->sarea_priv->last_dispatch++;
802 sarea_priv->dirty &= ~R128_UPLOAD_CLIPRECTS;
803 sarea_priv->nbox = 0;
806 static int r128_cce_dispatch_blit(DRMFILE filp,
807 drm_device_t * dev, drm_r128_blit_t * blit)
809 drm_r128_private_t *dev_priv = dev->dev_private;
810 drm_device_dma_t *dma = dev->dma;
812 drm_r128_buf_priv_t *buf_priv;
814 int dword_shift, dwords;
818 /* The compiler won't optimize away a division by a variable,
819 * even if the only legal values are powers of two. Thus, we'll
820 * use a shift instead.
822 switch (blit->format) {
823 case R128_DATATYPE_ARGB8888:
826 case R128_DATATYPE_ARGB1555:
827 case R128_DATATYPE_RGB565:
828 case R128_DATATYPE_ARGB4444:
829 case R128_DATATYPE_YVYU422:
830 case R128_DATATYPE_VYUY422:
833 case R128_DATATYPE_CI8:
834 case R128_DATATYPE_RGB8:
838 DRM_ERROR("invalid blit format %d\n", blit->format);
839 return DRM_ERR(EINVAL);
842 /* Flush the pixel cache, and mark the contents as Read Invalid.
843 * This ensures no pixel data gets mixed up with the texture
844 * data from the host data blit, otherwise part of the texture
845 * image may be corrupted.
849 OUT_RING(CCE_PACKET0(R128_PC_GUI_CTLSTAT, 0));
850 OUT_RING(R128_PC_RI_GUI | R128_PC_FLUSH_GUI);
854 /* Dispatch the indirect buffer.
856 buf = dma->buflist[blit->idx];
857 buf_priv = buf->dev_private;
859 if (buf->filp != filp) {
860 DRM_ERROR("process %d using buffer owned by %p\n",
861 DRM_CURRENTPID, buf->filp);
862 return DRM_ERR(EINVAL);
865 DRM_ERROR("sending pending buffer %d\n", blit->idx);
866 return DRM_ERR(EINVAL);
869 buf_priv->discard = 1;
871 dwords = (blit->width * blit->height) >> dword_shift;
873 data = (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset);
875 data[0] = cpu_to_le32(CCE_PACKET3(R128_CNTL_HOSTDATA_BLT, dwords + 6));
876 data[1] = cpu_to_le32((R128_GMC_DST_PITCH_OFFSET_CNTL |
877 R128_GMC_BRUSH_NONE |
878 (blit->format << 8) |
879 R128_GMC_SRC_DATATYPE_COLOR |
881 R128_DP_SRC_SOURCE_HOST_DATA |
882 R128_GMC_CLR_CMP_CNTL_DIS |
883 R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS));
885 data[2] = cpu_to_le32((blit->pitch << 21) | (blit->offset >> 5));
886 data[3] = cpu_to_le32(0xffffffff);
887 data[4] = cpu_to_le32(0xffffffff);
888 data[5] = cpu_to_le32((blit->y << 16) | blit->x);
889 data[6] = cpu_to_le32((blit->height << 16) | blit->width);
890 data[7] = cpu_to_le32(dwords);
892 buf->used = (dwords + 8) * sizeof(u32);
894 r128_cce_dispatch_indirect(dev, buf, 0, buf->used);
896 /* Flush the pixel cache after the blit completes. This ensures
897 * the texture data is written out to memory before rendering
902 OUT_RING(CCE_PACKET0(R128_PC_GUI_CTLSTAT, 0));
903 OUT_RING(R128_PC_FLUSH_GUI);
910 /* ================================================================
911 * Tiled depth buffer management
913 * FIXME: These should all set the destination write mask for when we
914 * have hardware stencil support.
917 static int r128_cce_dispatch_write_span(drm_device_t * dev,
918 drm_r128_depth_t * depth)
920 drm_r128_private_t *dev_priv = dev->dev_private;
924 int i, buffer_size, mask_size;
929 if (count > 4096 || count <= 0)
930 return DRM_ERR(EMSGSIZE);
932 if (DRM_COPY_FROM_USER(&x, depth->x, sizeof(x))) {
933 return DRM_ERR(EFAULT);
935 if (DRM_COPY_FROM_USER(&y, depth->y, sizeof(y))) {
936 return DRM_ERR(EFAULT);
939 buffer_size = depth->n * sizeof(u32);
940 buffer = drm_alloc(buffer_size, DRM_MEM_BUFS);
942 return DRM_ERR(ENOMEM);
943 if (DRM_COPY_FROM_USER(buffer, depth->buffer, buffer_size)) {
944 drm_free(buffer, buffer_size, DRM_MEM_BUFS);
945 return DRM_ERR(EFAULT);
948 mask_size = depth->n * sizeof(u8);
950 mask = drm_alloc(mask_size, DRM_MEM_BUFS);
952 drm_free(buffer, buffer_size, DRM_MEM_BUFS);
953 return DRM_ERR(ENOMEM);
955 if (DRM_COPY_FROM_USER(mask, depth->mask, mask_size)) {
956 drm_free(buffer, buffer_size, DRM_MEM_BUFS);
957 drm_free(mask, mask_size, DRM_MEM_BUFS);
958 return DRM_ERR(EFAULT);
961 for (i = 0; i < count; i++, x++) {
965 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
966 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
967 R128_GMC_BRUSH_SOLID_COLOR |
968 (dev_priv->depth_fmt << 8) |
969 R128_GMC_SRC_DATATYPE_COLOR |
971 R128_GMC_CLR_CMP_CNTL_DIS |
972 R128_GMC_WR_MSK_DIS);
974 OUT_RING(dev_priv->depth_pitch_offset_c);
977 OUT_RING((x << 16) | y);
978 OUT_RING((1 << 16) | 1);
984 drm_free(mask, mask_size, DRM_MEM_BUFS);
986 for (i = 0; i < count; i++, x++) {
989 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
990 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
991 R128_GMC_BRUSH_SOLID_COLOR |
992 (dev_priv->depth_fmt << 8) |
993 R128_GMC_SRC_DATATYPE_COLOR |
995 R128_GMC_CLR_CMP_CNTL_DIS |
996 R128_GMC_WR_MSK_DIS);
998 OUT_RING(dev_priv->depth_pitch_offset_c);
1001 OUT_RING((x << 16) | y);
1002 OUT_RING((1 << 16) | 1);
1008 drm_free(buffer, buffer_size, DRM_MEM_BUFS);
1013 static int r128_cce_dispatch_write_pixels(drm_device_t * dev,
1014 drm_r128_depth_t * depth)
1016 drm_r128_private_t *dev_priv = dev->dev_private;
1020 int i, xbuf_size, ybuf_size, buffer_size, mask_size;
1025 if (count > 4096 || count <= 0)
1026 return DRM_ERR(EMSGSIZE);
1028 xbuf_size = count * sizeof(*x);
1029 ybuf_size = count * sizeof(*y);
1030 x = drm_alloc(xbuf_size, DRM_MEM_BUFS);
1032 return DRM_ERR(ENOMEM);
1034 y = drm_alloc(ybuf_size, DRM_MEM_BUFS);
1036 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1037 return DRM_ERR(ENOMEM);
1039 if (DRM_COPY_FROM_USER(x, depth->x, xbuf_size)) {
1040 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1041 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1042 return DRM_ERR(EFAULT);
1044 if (DRM_COPY_FROM_USER(y, depth->y, xbuf_size)) {
1045 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1046 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1047 return DRM_ERR(EFAULT);
1050 buffer_size = depth->n * sizeof(u32);
1051 buffer = drm_alloc(buffer_size, DRM_MEM_BUFS);
1052 if (buffer == NULL) {
1053 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1054 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1055 return DRM_ERR(ENOMEM);
1057 if (DRM_COPY_FROM_USER(buffer, depth->buffer, buffer_size)) {
1058 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1059 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1060 drm_free(buffer, buffer_size, DRM_MEM_BUFS);
1061 return DRM_ERR(EFAULT);
1065 mask_size = depth->n * sizeof(u8);
1066 mask = drm_alloc(mask_size, DRM_MEM_BUFS);
1068 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1069 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1070 drm_free(buffer, buffer_size, DRM_MEM_BUFS);
1071 return DRM_ERR(ENOMEM);
1073 if (DRM_COPY_FROM_USER(mask, depth->mask, mask_size)) {
1074 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1075 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1076 drm_free(buffer, buffer_size, DRM_MEM_BUFS);
1077 drm_free(mask, mask_size, DRM_MEM_BUFS);
1078 return DRM_ERR(EFAULT);
1081 for (i = 0; i < count; i++) {
1085 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
1086 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
1087 R128_GMC_BRUSH_SOLID_COLOR |
1088 (dev_priv->depth_fmt << 8) |
1089 R128_GMC_SRC_DATATYPE_COLOR |
1091 R128_GMC_CLR_CMP_CNTL_DIS |
1092 R128_GMC_WR_MSK_DIS);
1094 OUT_RING(dev_priv->depth_pitch_offset_c);
1095 OUT_RING(buffer[i]);
1097 OUT_RING((x[i] << 16) | y[i]);
1098 OUT_RING((1 << 16) | 1);
1104 drm_free(mask, mask_size, DRM_MEM_BUFS);
1106 for (i = 0; i < count; i++) {
1109 OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4));
1110 OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL |
1111 R128_GMC_BRUSH_SOLID_COLOR |
1112 (dev_priv->depth_fmt << 8) |
1113 R128_GMC_SRC_DATATYPE_COLOR |
1115 R128_GMC_CLR_CMP_CNTL_DIS |
1116 R128_GMC_WR_MSK_DIS);
1118 OUT_RING(dev_priv->depth_pitch_offset_c);
1119 OUT_RING(buffer[i]);
1121 OUT_RING((x[i] << 16) | y[i]);
1122 OUT_RING((1 << 16) | 1);
1128 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1129 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1130 drm_free(buffer, buffer_size, DRM_MEM_BUFS);
1135 static int r128_cce_dispatch_read_span(drm_device_t * dev,
1136 drm_r128_depth_t * depth)
1138 drm_r128_private_t *dev_priv = dev->dev_private;
1144 if (count > 4096 || count <= 0)
1145 return DRM_ERR(EMSGSIZE);
1147 if (DRM_COPY_FROM_USER(&x, depth->x, sizeof(x))) {
1148 return DRM_ERR(EFAULT);
1150 if (DRM_COPY_FROM_USER(&y, depth->y, sizeof(y))) {
1151 return DRM_ERR(EFAULT);
1156 OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5));
1157 OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL |
1158 R128_GMC_DST_PITCH_OFFSET_CNTL |
1159 R128_GMC_BRUSH_NONE |
1160 (dev_priv->depth_fmt << 8) |
1161 R128_GMC_SRC_DATATYPE_COLOR |
1163 R128_DP_SRC_SOURCE_MEMORY |
1164 R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_WR_MSK_DIS);
1166 OUT_RING(dev_priv->depth_pitch_offset_c);
1167 OUT_RING(dev_priv->span_pitch_offset_c);
1169 OUT_RING((x << 16) | y);
1170 OUT_RING((0 << 16) | 0);
1171 OUT_RING((count << 16) | 1);
1178 static int r128_cce_dispatch_read_pixels(drm_device_t * dev,
1179 drm_r128_depth_t * depth)
1181 drm_r128_private_t *dev_priv = dev->dev_private;
1183 int i, xbuf_size, ybuf_size;
1185 DRM_DEBUG("%s\n", __FUNCTION__);
1188 if (count > 4096 || count <= 0)
1189 return DRM_ERR(EMSGSIZE);
1191 if (count > dev_priv->depth_pitch) {
1192 count = dev_priv->depth_pitch;
1195 xbuf_size = count * sizeof(*x);
1196 ybuf_size = count * sizeof(*y);
1197 x = drm_alloc(xbuf_size, DRM_MEM_BUFS);
1199 return DRM_ERR(ENOMEM);
1201 y = drm_alloc(ybuf_size, DRM_MEM_BUFS);
1203 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1204 return DRM_ERR(ENOMEM);
1206 if (DRM_COPY_FROM_USER(x, depth->x, xbuf_size)) {
1207 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1208 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1209 return DRM_ERR(EFAULT);
1211 if (DRM_COPY_FROM_USER(y, depth->y, ybuf_size)) {
1212 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1213 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1214 return DRM_ERR(EFAULT);
1217 for (i = 0; i < count; i++) {
1220 OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5));
1221 OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL |
1222 R128_GMC_DST_PITCH_OFFSET_CNTL |
1223 R128_GMC_BRUSH_NONE |
1224 (dev_priv->depth_fmt << 8) |
1225 R128_GMC_SRC_DATATYPE_COLOR |
1227 R128_DP_SRC_SOURCE_MEMORY |
1228 R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_WR_MSK_DIS);
1230 OUT_RING(dev_priv->depth_pitch_offset_c);
1231 OUT_RING(dev_priv->span_pitch_offset_c);
1233 OUT_RING((x[i] << 16) | y[i]);
1234 OUT_RING((i << 16) | 0);
1235 OUT_RING((1 << 16) | 1);
1240 drm_free(x, xbuf_size, DRM_MEM_BUFS);
1241 drm_free(y, ybuf_size, DRM_MEM_BUFS);
1246 /* ================================================================
1250 static void r128_cce_dispatch_stipple(drm_device_t * dev, u32 * stipple)
1252 drm_r128_private_t *dev_priv = dev->dev_private;
1255 DRM_DEBUG("%s\n", __FUNCTION__);
1259 OUT_RING(CCE_PACKET0(R128_BRUSH_DATA0, 31));
1260 for (i = 0; i < 32; i++) {
1261 OUT_RING(stipple[i]);
1267 /* ================================================================
1271 int r128_cce_clear(DRM_IOCTL_ARGS)
1274 drm_r128_private_t *dev_priv = dev->dev_private;
1275 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
1276 drm_r128_clear_t clear;
1279 LOCK_TEST_WITH_RETURN(dev, filp);
1281 DRM_COPY_FROM_USER_IOCTL(clear, (drm_r128_clear_t __user *) data,
1284 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1286 if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS)
1287 sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS;
1289 r128_cce_dispatch_clear(dev, &clear);
1292 /* Make sure we restore the 3D state next time.
1294 dev_priv->sarea_priv->dirty |= R128_UPLOAD_CONTEXT | R128_UPLOAD_MASKS;
1299 static int r128_do_init_pageflip(drm_device_t * dev)
1301 drm_r128_private_t *dev_priv = dev->dev_private;
1304 dev_priv->crtc_offset = R128_READ(R128_CRTC_OFFSET);
1305 dev_priv->crtc_offset_cntl = R128_READ(R128_CRTC_OFFSET_CNTL);
1307 R128_WRITE(R128_CRTC_OFFSET, dev_priv->front_offset);
1308 R128_WRITE(R128_CRTC_OFFSET_CNTL,
1309 dev_priv->crtc_offset_cntl | R128_CRTC_OFFSET_FLIP_CNTL);
1311 dev_priv->page_flipping = 1;
1312 dev_priv->current_page = 0;
1313 dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page;
1318 int r128_do_cleanup_pageflip(drm_device_t * dev)
1320 drm_r128_private_t *dev_priv = dev->dev_private;
1323 R128_WRITE(R128_CRTC_OFFSET, dev_priv->crtc_offset);
1324 R128_WRITE(R128_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl);
1326 if (dev_priv->current_page != 0) {
1327 r128_cce_dispatch_flip(dev);
1331 dev_priv->page_flipping = 0;
1335 /* Swapping and flipping are different operations, need different ioctls.
1336 * They can & should be intermixed to support multiple 3d windows.
1339 int r128_cce_flip(DRM_IOCTL_ARGS)
1342 drm_r128_private_t *dev_priv = dev->dev_private;
1343 DRM_DEBUG("%s\n", __FUNCTION__);
1345 LOCK_TEST_WITH_RETURN(dev, filp);
1347 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1349 if (!dev_priv->page_flipping)
1350 r128_do_init_pageflip(dev);
1352 r128_cce_dispatch_flip(dev);
1358 int r128_cce_swap(DRM_IOCTL_ARGS)
1361 drm_r128_private_t *dev_priv = dev->dev_private;
1362 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
1363 DRM_DEBUG("%s\n", __FUNCTION__);
1365 LOCK_TEST_WITH_RETURN(dev, filp);
1367 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1369 if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS)
1370 sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS;
1372 r128_cce_dispatch_swap(dev);
1373 dev_priv->sarea_priv->dirty |= (R128_UPLOAD_CONTEXT |
1380 int r128_cce_vertex(DRM_IOCTL_ARGS)
1383 drm_r128_private_t *dev_priv = dev->dev_private;
1384 drm_device_dma_t *dma = dev->dma;
1386 drm_r128_buf_priv_t *buf_priv;
1387 drm_r128_vertex_t vertex;
1389 LOCK_TEST_WITH_RETURN(dev, filp);
1392 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1393 return DRM_ERR(EINVAL);
1396 DRM_COPY_FROM_USER_IOCTL(vertex, (drm_r128_vertex_t __user *) data,
1399 DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n",
1400 DRM_CURRENTPID, vertex.idx, vertex.count, vertex.discard);
1402 if (vertex.idx < 0 || vertex.idx >= dma->buf_count) {
1403 DRM_ERROR("buffer index %d (of %d max)\n",
1404 vertex.idx, dma->buf_count - 1);
1405 return DRM_ERR(EINVAL);
1407 if (vertex.prim < 0 ||
1408 vertex.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2) {
1409 DRM_ERROR("buffer prim %d\n", vertex.prim);
1410 return DRM_ERR(EINVAL);
1413 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1414 VB_AGE_TEST_WITH_RETURN(dev_priv);
1416 buf = dma->buflist[vertex.idx];
1417 buf_priv = buf->dev_private;
1419 if (buf->filp != filp) {
1420 DRM_ERROR("process %d using buffer owned by %p\n",
1421 DRM_CURRENTPID, buf->filp);
1422 return DRM_ERR(EINVAL);
1425 DRM_ERROR("sending pending buffer %d\n", vertex.idx);
1426 return DRM_ERR(EINVAL);
1429 buf->used = vertex.count;
1430 buf_priv->prim = vertex.prim;
1431 buf_priv->discard = vertex.discard;
1433 r128_cce_dispatch_vertex(dev, buf);
1439 int r128_cce_indices(DRM_IOCTL_ARGS)
1442 drm_r128_private_t *dev_priv = dev->dev_private;
1443 drm_device_dma_t *dma = dev->dma;
1445 drm_r128_buf_priv_t *buf_priv;
1446 drm_r128_indices_t elts;
1449 LOCK_TEST_WITH_RETURN(dev, filp);
1452 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1453 return DRM_ERR(EINVAL);
1456 DRM_COPY_FROM_USER_IOCTL(elts, (drm_r128_indices_t __user *) data,
1459 DRM_DEBUG("pid=%d buf=%d s=%d e=%d d=%d\n", DRM_CURRENTPID,
1460 elts.idx, elts.start, elts.end, elts.discard);
1462 if (elts.idx < 0 || elts.idx >= dma->buf_count) {
1463 DRM_ERROR("buffer index %d (of %d max)\n",
1464 elts.idx, dma->buf_count - 1);
1465 return DRM_ERR(EINVAL);
1467 if (elts.prim < 0 || elts.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2) {
1468 DRM_ERROR("buffer prim %d\n", elts.prim);
1469 return DRM_ERR(EINVAL);
1472 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1473 VB_AGE_TEST_WITH_RETURN(dev_priv);
1475 buf = dma->buflist[elts.idx];
1476 buf_priv = buf->dev_private;
1478 if (buf->filp != filp) {
1479 DRM_ERROR("process %d using buffer owned by %p\n",
1480 DRM_CURRENTPID, buf->filp);
1481 return DRM_ERR(EINVAL);
1484 DRM_ERROR("sending pending buffer %d\n", elts.idx);
1485 return DRM_ERR(EINVAL);
1488 count = (elts.end - elts.start) / sizeof(u16);
1489 elts.start -= R128_INDEX_PRIM_OFFSET;
1491 if (elts.start & 0x7) {
1492 DRM_ERROR("misaligned buffer 0x%x\n", elts.start);
1493 return DRM_ERR(EINVAL);
1495 if (elts.start < buf->used) {
1496 DRM_ERROR("no header 0x%x - 0x%x\n", elts.start, buf->used);
1497 return DRM_ERR(EINVAL);
1500 buf->used = elts.end;
1501 buf_priv->prim = elts.prim;
1502 buf_priv->discard = elts.discard;
1504 r128_cce_dispatch_indices(dev, buf, elts.start, elts.end, count);
1510 int r128_cce_blit(DRM_IOCTL_ARGS)
1513 drm_device_dma_t *dma = dev->dma;
1514 drm_r128_private_t *dev_priv = dev->dev_private;
1515 drm_r128_blit_t blit;
1518 LOCK_TEST_WITH_RETURN(dev, filp);
1520 DRM_COPY_FROM_USER_IOCTL(blit, (drm_r128_blit_t __user *) data,
1523 DRM_DEBUG("pid=%d index=%d\n", DRM_CURRENTPID, blit.idx);
1525 if (blit.idx < 0 || blit.idx >= dma->buf_count) {
1526 DRM_ERROR("buffer index %d (of %d max)\n",
1527 blit.idx, dma->buf_count - 1);
1528 return DRM_ERR(EINVAL);
1531 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1532 VB_AGE_TEST_WITH_RETURN(dev_priv);
1534 ret = r128_cce_dispatch_blit(filp, dev, &blit);
1540 int r128_cce_depth(DRM_IOCTL_ARGS)
1543 drm_r128_private_t *dev_priv = dev->dev_private;
1544 drm_r128_depth_t depth;
1547 LOCK_TEST_WITH_RETURN(dev, filp);
1549 DRM_COPY_FROM_USER_IOCTL(depth, (drm_r128_depth_t __user *) data,
1552 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1554 ret = DRM_ERR(EINVAL);
1555 switch (depth.func) {
1556 case R128_WRITE_SPAN:
1557 ret = r128_cce_dispatch_write_span(dev, &depth);
1558 case R128_WRITE_PIXELS:
1559 ret = r128_cce_dispatch_write_pixels(dev, &depth);
1560 case R128_READ_SPAN:
1561 ret = r128_cce_dispatch_read_span(dev, &depth);
1562 case R128_READ_PIXELS:
1563 ret = r128_cce_dispatch_read_pixels(dev, &depth);
1570 int r128_cce_stipple(DRM_IOCTL_ARGS)
1573 drm_r128_private_t *dev_priv = dev->dev_private;
1574 drm_r128_stipple_t stipple;
1577 LOCK_TEST_WITH_RETURN(dev, filp);
1579 DRM_COPY_FROM_USER_IOCTL(stipple, (drm_r128_stipple_t __user *) data,
1582 if (DRM_COPY_FROM_USER(&mask, stipple.mask, 32 * sizeof(u32)))
1583 return DRM_ERR(EFAULT);
1585 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1587 r128_cce_dispatch_stipple(dev, mask);
1593 int r128_cce_indirect(DRM_IOCTL_ARGS)
1596 drm_r128_private_t *dev_priv = dev->dev_private;
1597 drm_device_dma_t *dma = dev->dma;
1599 drm_r128_buf_priv_t *buf_priv;
1600 drm_r128_indirect_t indirect;
1605 LOCK_TEST_WITH_RETURN(dev, filp);
1608 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1609 return DRM_ERR(EINVAL);
1612 DRM_COPY_FROM_USER_IOCTL(indirect, (drm_r128_indirect_t __user *) data,
1615 DRM_DEBUG("indirect: idx=%d s=%d e=%d d=%d\n",
1616 indirect.idx, indirect.start, indirect.end, indirect.discard);
1618 if (indirect.idx < 0 || indirect.idx >= dma->buf_count) {
1619 DRM_ERROR("buffer index %d (of %d max)\n",
1620 indirect.idx, dma->buf_count - 1);
1621 return DRM_ERR(EINVAL);
1624 buf = dma->buflist[indirect.idx];
1625 buf_priv = buf->dev_private;
1627 if (buf->filp != filp) {
1628 DRM_ERROR("process %d using buffer owned by %p\n",
1629 DRM_CURRENTPID, buf->filp);
1630 return DRM_ERR(EINVAL);
1633 DRM_ERROR("sending pending buffer %d\n", indirect.idx);
1634 return DRM_ERR(EINVAL);
1637 if (indirect.start < buf->used) {
1638 DRM_ERROR("reusing indirect: start=0x%x actual=0x%x\n",
1639 indirect.start, buf->used);
1640 return DRM_ERR(EINVAL);
1643 RING_SPACE_TEST_WITH_RETURN(dev_priv);
1644 VB_AGE_TEST_WITH_RETURN(dev_priv);
1646 buf->used = indirect.end;
1647 buf_priv->discard = indirect.discard;
1650 /* Wait for the 3D stream to idle before the indirect buffer
1651 * containing 2D acceleration commands is processed.
1654 RADEON_WAIT_UNTIL_3D_IDLE();
1658 /* Dispatch the indirect buffer full of commands from the
1659 * X server. This is insecure and is thus only available to
1660 * privileged clients.
1662 r128_cce_dispatch_indirect(dev, buf, indirect.start, indirect.end);
1668 int r128_getparam(DRM_IOCTL_ARGS)
1671 drm_r128_private_t *dev_priv = dev->dev_private;
1672 drm_r128_getparam_t param;
1676 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1677 return DRM_ERR(EINVAL);
1680 DRM_COPY_FROM_USER_IOCTL(param, (drm_r128_getparam_t __user *) data,
1683 DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
1685 switch (param.param) {
1686 case R128_PARAM_IRQ_NR:
1690 return DRM_ERR(EINVAL);
1693 if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) {
1694 DRM_ERROR("copy_to_user\n");
1695 return DRM_ERR(EFAULT);
1701 void r128_driver_prerelease(drm_device_t * dev, DRMFILE filp)
1703 if (dev->dev_private) {
1704 drm_r128_private_t *dev_priv = dev->dev_private;
1705 if (dev_priv->page_flipping) {
1706 r128_do_cleanup_pageflip(dev);
1711 void r128_driver_pretakedown(drm_device_t * dev)
1713 r128_do_cleanup_cce(dev);