2 * Copyright (C) 2007 Ben Skeggs.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include "nouveau_drv.h"
33 uint32_t save1700[5]; /* 0x1700->0x1710 */
36 #define NV50_INSTMEM_PAGE_SHIFT 12
37 #define NV50_INSTMEM_PAGE_SIZE (1 << NV50_INSTMEM_PAGE_SHIFT)
38 #define NV50_INSTMEM_RSVD_SIZE (64 * 1024)
39 #define NV50_INSTMEM_PT_SIZE(a) (((a) >> 12) << 3)
42 nv50_instmem_init(drm_device_t *dev)
44 drm_nouveau_private_t *dev_priv = dev->dev_private;
45 nv50_instmem_priv *priv;
46 uint32_t rv, pt, pts, cb, cb0, cb1, unk, as;
50 priv = drm_calloc(1, sizeof(*priv), DRM_MEM_DRIVER);
52 return DRM_ERR(ENOMEM);
53 dev_priv->Engine.instmem.priv = priv;
55 /* Save current state */
56 for (i = 0x1700; i <= 0x1710; i+=4)
57 priv->save1700[(i-0x1700)/4] = NV_READ(i);
59 as = dev_priv->ramin->size;
60 rv = nouveau_mem_fb_amount(dev) - (1*1024*1024);
62 pts = NV50_INSTMEM_PT_SIZE(as);
64 if ((dev_priv->chipset & 0xf0) != 0x50) {
74 DRM_DEBUG("PRAMIN config:\n");
75 DRM_DEBUG(" Rsvd VRAM base: 0x%08x\n", rv);
76 DRM_DEBUG(" Aperture size: %i MiB\n", as >> 20);
77 DRM_DEBUG(" PT base: 0x%08x\n", pt);
78 DRM_DEBUG(" PT size: %d KiB\n", pts >> 10);
79 DRM_DEBUG(" BIOS image: 0x%08x\n", (NV_READ(0x619f04)&~0xff)<<8);
80 DRM_DEBUG(" Config base: 0x%08x\n", cb);
81 DRM_DEBUG(" ctxdma Config0: 0x%08x\n", cb0);
82 DRM_DEBUG(" Config1: 0x%08x\n", cb1);
84 /* Map first MiB of reserved vram into BAR0 PRAMIN aperture */
85 NV_WRITE(0x1700, (rv>>16));
86 /* Poke some regs.. */
87 NV_WRITE(0x1704, (cb>>12));
88 NV_WRITE(0x1710, (((unk-cb)>>4))|(1<<31));
89 NV_WRITE(0x1704, (cb>>12)|(1<<30));
91 /* CB0, some DMA object, NFI what it points at... Needed however,
92 * or the PRAMIN aperture doesn't operate as expected.
94 NV_WRITE(NV_RAMIN + (cb0 - rv) + 0x00, 0x7fc00000);
95 NV_WRITE(NV_RAMIN + (cb0 - rv) + 0x04, 0xe1ffffff);
96 NV_WRITE(NV_RAMIN + (cb0 - rv) + 0x08, 0xe0000000);
97 NV_WRITE(NV_RAMIN + (cb0 - rv) + 0x0c, 0x01000001);
98 NV_WRITE(NV_RAMIN + (cb0 - rv) + 0x10, 0x00000000);
99 NV_WRITE(NV_RAMIN + (cb0 - rv) + 0x14, 0x00000000);
101 /* CB1, points at PRAMIN PT */
102 NV_WRITE(NV_RAMIN + (cb1 - rv) + 0, pt | 0x63);
103 NV_WRITE(NV_RAMIN + (cb1 - rv) + 4, 0x00000000);
105 /* Zero PRAMIN page table */
106 v = NV_RAMIN + (pt - rv);
107 for (i = v; i < v + pts; i += 8) {
108 NV_WRITE(i + 0x00, 0x00000009);
109 NV_WRITE(i + 0x04, 0x00000000);
112 /* Map page table into PRAMIN aperture */
113 for (i = pt; i < pt + pts; i += 0x1000) {
114 uint32_t pte = NV_RAMIN + (pt-rv) + (((i-pt) >> 12) << 3);
115 DRM_DEBUG("PRAMIN PTE = 0x%08x @ 0x%08x\n", i, pte);
116 NV_WRITE(pte + 0x00, i | 1);
117 NV_WRITE(pte + 0x04, 0x00000000);
121 NV_WRITE(0x170c, (((cb0 - cb)>>4)|(1<<31)));
123 /* Confirm it all worked, should be able to read back the page table's
124 * PTEs from the PRAMIN BAR
126 NV_WRITE(0x1700, pt >> 16);
127 if (NV_READ(0x700000) != NV_RI32(0)) {
128 DRM_ERROR("Failed to init PRAMIN page table\n");
129 return DRM_ERR(EINVAL);
132 /* Create a heap to manage PRAMIN aperture allocations */
133 ret = nouveau_mem_init_heap(&dev_priv->ramin_heap, pts, as-pts);
135 DRM_ERROR("Failed to init PRAMIN heap\n");
136 return DRM_ERR(ENOMEM);
138 DRM_DEBUG("NV50: PRAMIN setup ok\n");
140 /* Don't alloc the last MiB of VRAM, probably too much, but be safe
143 dev_priv->ramin_rsvd_vram = 1*1024*1024;
145 /*XXX: probably incorrect, but needed to make hash func "work" */
146 dev_priv->ramht_offset = 0x10000;
147 dev_priv->ramht_bits = 9;
148 dev_priv->ramht_size = (1 << dev_priv->ramht_bits);
153 nv50_instmem_takedown(drm_device_t *dev)
155 drm_nouveau_private_t *dev_priv = dev->dev_private;
156 nv50_instmem_priv *priv = dev_priv->Engine.instmem.priv;
162 /* Restore state from before init */
163 for (i = 0x1700; i <= 0x1710; i+=4)
164 NV_WRITE(i, priv->save1700[(i-0x1700)/4]);
166 dev_priv->Engine.instmem.priv = NULL;
167 drm_free(priv, sizeof(*priv), DRM_MEM_DRIVER);
171 nv50_instmem_populate(drm_device_t *dev, nouveau_gpuobj_t *gpuobj, uint32_t *sz)
173 if (gpuobj->im_backing)
174 return DRM_ERR(EINVAL);
176 *sz = (*sz + (NV50_INSTMEM_PAGE_SIZE-1)) & ~(NV50_INSTMEM_PAGE_SIZE-1);
178 return DRM_ERR(EINVAL);
180 gpuobj->im_backing = nouveau_mem_alloc(dev, NV50_INSTMEM_PAGE_SIZE,
183 if (!gpuobj->im_backing) {
184 DRM_ERROR("Couldn't allocate vram to back PRAMIN pages\n");
185 return DRM_ERR(ENOMEM);
192 nv50_instmem_clear(drm_device_t *dev, nouveau_gpuobj_t *gpuobj)
194 drm_nouveau_private_t *dev_priv = dev->dev_private;
196 if (gpuobj && gpuobj->im_backing) {
197 if (gpuobj->im_bound)
198 dev_priv->Engine.instmem.unbind(dev, gpuobj);
199 nouveau_mem_free(dev, gpuobj->im_backing);
200 gpuobj->im_backing = NULL;
205 nv50_instmem_bind(drm_device_t *dev, nouveau_gpuobj_t *gpuobj)
207 drm_nouveau_private_t *dev_priv = dev->dev_private;
208 uint32_t pte, pte_end, vram;
210 if (!gpuobj->im_backing || !gpuobj->im_pramin || gpuobj->im_bound)
211 return DRM_ERR(EINVAL);
213 DRM_DEBUG("st=0x%0llx sz=0x%0llx\n",
214 gpuobj->im_pramin->start, gpuobj->im_pramin->size);
216 pte = (gpuobj->im_pramin->start >> 12) << 3;
217 pte_end = ((gpuobj->im_pramin->size >> 12) << 3) + pte;
218 vram = gpuobj->im_backing->start - dev_priv->fb_phys;
220 if (pte == pte_end) {
221 DRM_ERROR("WARNING: badness in bind() pte calc\n");
225 DRM_DEBUG("pramin=0x%llx, pte=%d, pte_end=%d\n",
226 gpuobj->im_pramin->start, pte, pte_end);
227 DRM_DEBUG("first vram page: 0x%llx\n",
228 gpuobj->im_backing->start);
230 while (pte < pte_end) {
231 NV_WI32(pte + 0, vram | 1);
232 NV_WI32(pte + 4, 0x00000000);
235 vram += NV50_INSTMEM_PAGE_SIZE;
238 gpuobj->im_bound = 1;
243 nv50_instmem_unbind(drm_device_t *dev, nouveau_gpuobj_t *gpuobj)
245 drm_nouveau_private_t *dev_priv = dev->dev_private;
246 uint32_t pte, pte_end;
248 if (gpuobj->im_bound == 0)
249 return DRM_ERR(EINVAL);
251 pte = (gpuobj->im_pramin->start >> 12) << 3;
252 pte_end = ((gpuobj->im_pramin->size >> 12) << 3) + pte;
253 while (pte < pte_end) {
254 NV_WI32(pte + 0, 0x00000000);
255 NV_WI32(pte + 4, 0x00000000);
259 gpuobj->im_bound = 0;