2 * Copyright (C) 2007 Ben Skeggs.
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include "nouveau_drv.h"
33 uint32_t save1700[5]; /* 0x1700->0x1710 */
35 struct nouveau_gpuobj_ref *pramin_pt;
36 struct nouveau_gpuobj_ref *pramin_bar;
39 #define NV50_INSTMEM_PAGE_SHIFT 12
40 #define NV50_INSTMEM_PAGE_SIZE (1 << NV50_INSTMEM_PAGE_SHIFT)
41 #define NV50_INSTMEM_PT_SIZE(a) (((a) >> 12) << 3)
43 /*NOTE: - Assumes 0x1700 already covers the correct MiB of PRAMIN
45 #define BAR0_WI32(g,o,v) do { \
47 if ((g)->im_backing) { \
48 offset = (g)->im_backing->start; \
50 offset = chan->ramin->gpuobj->im_backing->start; \
51 offset += (g)->im_pramin->start; \
54 NV_WRITE(NV_RAMIN + (offset & 0xfffff), (v)); \
58 nv50_instmem_init(struct drm_device *dev)
60 struct drm_nouveau_private *dev_priv = dev->dev_private;
61 struct nouveau_channel *chan;
62 uint32_t c_offset, c_size, c_ramfc, c_vmpd, c_base, pt_size;
63 nv50_instmem_priv *priv;
67 priv = drm_calloc(1, sizeof(*priv), DRM_MEM_DRIVER);
70 dev_priv->Engine.instmem.priv = priv;
72 /* Reserve the last MiB of VRAM, we should probably try to avoid
73 * setting up the below tables over the top of the VBIOS image at
76 dev_priv->ramin_rsvd_vram = 1 << 20;
77 c_offset = nouveau_mem_fb_amount(dev) - dev_priv->ramin_rsvd_vram;
79 c_vmpd = ((dev_priv->chipset & 0xf0) == 0x50) ? 0x1400 : 0x200;
80 c_ramfc = ((dev_priv->chipset & 0xf0) == 0x50) ? 0x0 : 0x20;
81 c_base = c_vmpd + 0x4000;
82 pt_size = NV50_INSTMEM_PT_SIZE(dev_priv->ramin->size);
84 DRM_DEBUG(" Rsvd VRAM base: 0x%08x\n", c_offset);
85 DRM_DEBUG(" VBIOS image: 0x%08x\n", (NV_READ(0x619f04)&~0xff)<<8);
86 DRM_DEBUG(" Aperture size: %d MiB\n",
87 (uint32_t)dev_priv->ramin->size >> 20);
88 DRM_DEBUG(" PT size: %d KiB\n", pt_size >> 10);
90 NV_WRITE(NV50_PUNK_BAR0_PRAMIN, (c_offset >> 16));
92 /* Create a fake channel, and use it as our "dummy" channels 0/127.
93 * The main reason for creating a channel is so we can use the gpuobj
94 * code. However, it's probably worth noting that NVIDIA also setup
95 * their channels 0/127 with the same values they configure here.
96 * So, there may be some other reason for doing this.
98 * Have to create the entire channel manually, as the real channel
99 * creation code assumes we have PRAMIN access, and we don't until
102 chan = drm_calloc(1, sizeof(*chan), DRM_MEM_DRIVER);
107 chan->file_priv = (struct drm_file *)-2;
108 dev_priv->fifos[0] = dev_priv->fifos[127] = chan;
110 /* Channel's PRAMIN object + heap */
111 if ((ret = nouveau_gpuobj_new_fake(dev, 0, c_offset, 128<<10, 0,
112 NULL, &chan->ramin)))
115 if (nouveau_mem_init_heap(&chan->ramin_heap, c_base, c_size - c_base))
118 /* RAMFC + zero channel's PRAMIN up to start of VM pagedir */
119 if ((ret = nouveau_gpuobj_new_fake(dev, c_ramfc, c_offset + c_ramfc,
120 0x4000, 0, NULL, &chan->ramfc)))
123 for (i = 0; i < c_vmpd; i += 4)
124 BAR0_WI32(chan->ramin->gpuobj, i, 0);
126 /* VM page directory */
127 if ((ret = nouveau_gpuobj_new_fake(dev, c_vmpd, c_offset + c_vmpd,
128 0x4000, 0, &chan->vm_pd, NULL)))
130 for (i = 0; i < 0x4000; i += 8) {
131 BAR0_WI32(chan->vm_pd, i + 0x00, 0x00000000);
132 BAR0_WI32(chan->vm_pd, i + 0x04, 0x00000000);
135 /* PRAMIN page table, cheat and map into VM at 0x0000000000.
136 * We map the entire fake channel into the start of the PRAMIN BAR
138 if ((ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, pt_size, 0x1000,
139 0, &priv->pramin_pt)))
142 for (i = 0, v = c_offset; i < pt_size; i+=8, v+=0x1000) {
143 if (v < (c_offset + c_size))
144 BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, v | 1);
146 BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, 0x00000009);
147 BAR0_WI32(priv->pramin_pt->gpuobj, i + 4, 0x00000000);
150 BAR0_WI32(chan->vm_pd, 0x00, priv->pramin_pt->instance | 0x63);
151 BAR0_WI32(chan->vm_pd, 0x04, 0x00000000);
153 /* DMA object for PRAMIN BAR */
154 if ((ret = nouveau_gpuobj_new_ref(dev, chan, chan, 0, 6*4, 16, 0,
157 BAR0_WI32(priv->pramin_bar->gpuobj, 0x00, 0x7fc00000);
158 BAR0_WI32(priv->pramin_bar->gpuobj, 0x04, dev_priv->ramin->size - 1);
159 BAR0_WI32(priv->pramin_bar->gpuobj, 0x08, 0x00000000);
160 BAR0_WI32(priv->pramin_bar->gpuobj, 0x0c, 0x00000000);
161 BAR0_WI32(priv->pramin_bar->gpuobj, 0x10, 0x00000000);
162 BAR0_WI32(priv->pramin_bar->gpuobj, 0x14, 0x00000000);
164 /* Poke the relevant regs, and pray it works :) */
165 NV_WRITE(NV50_PUNK_BAR_CFG_BASE, (chan->ramin->instance >> 12));
166 NV_WRITE(NV50_PUNK_UNK1710, 0);
167 NV_WRITE(NV50_PUNK_BAR_CFG_BASE, (chan->ramin->instance >> 12) |
168 NV50_PUNK_BAR_CFG_BASE_VALID);
169 NV_WRITE(NV50_PUNK_BAR1_CTXDMA, 0);
170 NV_WRITE(NV50_PUNK_BAR3_CTXDMA, (priv->pramin_bar->instance >> 4) |
171 NV50_PUNK_BAR3_CTXDMA_VALID);
173 /* Assume that praying isn't enough, check that we can re-read the
174 * entire fake channel back from the PRAMIN BAR */
175 for (i = 0; i < c_size; i+=4) {
176 if (NV_READ(NV_RAMIN + i) != NV_RI32(i)) {
177 DRM_ERROR("Error reading back PRAMIN at 0x%08x\n", i);
182 /* Global PRAMIN heap */
183 if (nouveau_mem_init_heap(&dev_priv->ramin_heap,
184 c_size, dev_priv->ramin->size - c_size)) {
185 dev_priv->ramin_heap = NULL;
186 DRM_ERROR("Failed to init RAMIN heap\n");
189 /*XXX: incorrect, but needed to make hash func "work" */
190 dev_priv->ramht_offset = 0x10000;
191 dev_priv->ramht_bits = 9;
192 dev_priv->ramht_size = (1 << dev_priv->ramht_bits);
197 nv50_instmem_takedown(struct drm_device *dev)
199 struct drm_nouveau_private *dev_priv = dev->dev_private;
200 nv50_instmem_priv *priv = dev_priv->Engine.instmem.priv;
201 struct nouveau_channel *chan = dev_priv->fifos[0];
209 /* Restore state from before init */
210 for (i = 0x1700; i <= 0x1710; i+=4)
211 NV_WRITE(i, priv->save1700[(i-0x1700)/4]);
213 nouveau_gpuobj_ref_del(dev, &priv->pramin_bar);
214 nouveau_gpuobj_ref_del(dev, &priv->pramin_pt);
216 /* Destroy dummy channel */
218 nouveau_gpuobj_del(dev, &chan->vm_pd);
219 nouveau_gpuobj_ref_del(dev, &chan->ramfc);
220 nouveau_gpuobj_ref_del(dev, &chan->ramin);
221 nouveau_mem_takedown(&chan->ramin_heap);
223 dev_priv->fifos[0] = dev_priv->fifos[127] = NULL;
224 drm_free(chan, sizeof(*chan), DRM_MEM_DRIVER);
227 dev_priv->Engine.instmem.priv = NULL;
228 drm_free(priv, sizeof(*priv), DRM_MEM_DRIVER);
232 nv50_instmem_populate(struct drm_device *dev, struct nouveau_gpuobj *gpuobj, uint32_t *sz)
234 if (gpuobj->im_backing)
237 *sz = (*sz + (NV50_INSTMEM_PAGE_SIZE-1)) & ~(NV50_INSTMEM_PAGE_SIZE-1);
241 gpuobj->im_backing = nouveau_mem_alloc(dev, NV50_INSTMEM_PAGE_SIZE,
243 (struct drm_file *)-2);
244 if (!gpuobj->im_backing) {
245 DRM_ERROR("Couldn't allocate vram to back PRAMIN pages\n");
253 nv50_instmem_clear(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
255 struct drm_nouveau_private *dev_priv = dev->dev_private;
257 if (gpuobj && gpuobj->im_backing) {
258 if (gpuobj->im_bound)
259 dev_priv->Engine.instmem.unbind(dev, gpuobj);
260 nouveau_mem_free(dev, gpuobj->im_backing);
261 gpuobj->im_backing = NULL;
266 nv50_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
268 struct drm_nouveau_private *dev_priv = dev->dev_private;
269 nv50_instmem_priv *priv = dev_priv->Engine.instmem.priv;
270 uint32_t pte, pte_end, vram;
272 if (!gpuobj->im_backing || !gpuobj->im_pramin || gpuobj->im_bound)
275 DRM_DEBUG("st=0x%0llx sz=0x%0llx\n",
276 gpuobj->im_pramin->start, gpuobj->im_pramin->size);
278 pte = (gpuobj->im_pramin->start >> 12) << 3;
279 pte_end = ((gpuobj->im_pramin->size >> 12) << 3) + pte;
280 vram = gpuobj->im_backing->start;
282 DRM_DEBUG("pramin=0x%llx, pte=%d, pte_end=%d\n",
283 gpuobj->im_pramin->start, pte, pte_end);
284 DRM_DEBUG("first vram page: 0x%llx\n",
285 gpuobj->im_backing->start);
287 while (pte < pte_end) {
288 INSTANCE_WR(priv->pramin_pt->gpuobj, (pte + 0)/4, vram | 1);
289 INSTANCE_WR(priv->pramin_pt->gpuobj, (pte + 4)/4, 0x00000000);
292 vram += NV50_INSTMEM_PAGE_SIZE;
295 gpuobj->im_bound = 1;
300 nv50_instmem_unbind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
302 struct drm_nouveau_private *dev_priv = dev->dev_private;
303 nv50_instmem_priv *priv = dev_priv->Engine.instmem.priv;
304 uint32_t pte, pte_end;
306 if (gpuobj->im_bound == 0)
309 pte = (gpuobj->im_pramin->start >> 12) << 3;
310 pte_end = ((gpuobj->im_pramin->size >> 12) << 3) + pte;
311 while (pte < pte_end) {
312 INSTANCE_WR(priv->pramin_pt->gpuobj, (pte + 0)/4, 0x00000009);
313 INSTANCE_WR(priv->pramin_pt->gpuobj, (pte + 4)/4, 0x00000000);
317 gpuobj->im_bound = 0;