3 #include "nouveau_drv.h"
4 #include "nouveau_drm.h"
9 * There are 3 families :
10 * NV20 is 0x10de:0x020*
11 * NV25/28 is 0x10de:0x025* / 0x10de:0x028*
12 * NV2A is 0x10de:0x02A0
16 * There are 3 families :
17 * NV30/31 is 0x10de:0x030* / 0x10de:0x031*
18 * NV34 is 0x10de:0x032*
19 * NV35/36 is 0x10de:0x033* / 0x10de:0x034*
21 * Not seen in the wild, no dumps (probably NV35) :
22 * NV37 is 0x10de:0x00fc, 0x10de:0x00fd
23 * NV38 is 0x10de:0x0333, 0x10de:0x00fe
27 #define NV20_GRCTX_SIZE (3580*4)
28 #define NV25_GRCTX_SIZE (3529*4)
29 #define NV2A_GRCTX_SIZE (3500*4)
31 #define NV30_31_GRCTX_SIZE (24392)
32 #define NV34_GRCTX_SIZE (18140)
33 #define NV35_36_GRCTX_SIZE (22396)
35 static void nv20_graph_context_init(struct drm_device *dev,
36 struct nouveau_gpuobj *ctx)
38 struct drm_nouveau_private *dev_priv = dev->dev_private;
41 write32 #1 block at +0x00740adc NV_PRAMIN+0x40adc of 3369 (0xd29) elements:
42 +0x00740adc: ffff0000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
43 +0x00740afc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
44 +0x00740b1c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
45 +0x00740b3c: 00000000 0fff0000 0fff0000 00000000 00000000 00000000 00000000 00000000
46 +0x00740b5c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
47 +0x00740b7c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
48 +0x00740b9c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
49 +0x00740bbc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
50 +0x00740bdc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
51 +0x00740bfc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
53 +0x00740c1c: 00000101 00000000 00000000 00000000 00000000 00000111 00000000 00000000
54 +0x00740c3c: 00000000 00000000 00000000 44400000 00000000 00000000 00000000 00000000
55 +0x00740c5c: 00000000 00000000 00000000 00000000 00000000 00000000 00030303 00030303
56 +0x00740c7c: 00030303 00030303 00000000 00000000 00000000 00000000 00080000 00080000
57 +0x00740c9c: 00080000 00080000 00000000 00000000 01012000 01012000 01012000 01012000
58 +0x00740cbc: 000105b8 000105b8 000105b8 000105b8 00080008 00080008 00080008 00080008
59 +0x00740cdc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
60 +0x00740cfc: 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000
61 +0x00740d1c: 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000
62 +0x00740d3c: 00000000 00000000 4b7fffff 00000000 00000000 00000000 00000000 00000000
64 +0x00740d5c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
65 +0x00740d7c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
66 +0x00740d9c: 00000001 00000000 00004000 00000000 00000000 00000001 00000000 00040000
67 +0x00740dbc: 00010000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
68 +0x00740ddc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
71 INSTANCE_WR(ctx, (0x33c/4)+0, 0xffff0000);
72 INSTANCE_WR(ctx, (0x33c/4)+25, 0x0fff0000);
73 INSTANCE_WR(ctx, (0x33c/4)+26, 0x0fff0000);
74 INSTANCE_WR(ctx, (0x33c/4)+80, 0x00000101);
75 INSTANCE_WR(ctx, (0x33c/4)+85, 0x00000111);
76 INSTANCE_WR(ctx, (0x33c/4)+91, 0x44400000);
77 for (i = 0; i < 4; ++i)
78 INSTANCE_WR(ctx, (0x33c/4)+102+i, 0x00030303);
79 for (i = 0; i < 4; ++i)
80 INSTANCE_WR(ctx, (0x33c/4)+110+i, 0x00080000);
81 for (i = 0; i < 4; ++i)
82 INSTANCE_WR(ctx, (0x33c/4)+116+i, 0x01012000);
83 for (i = 0; i < 4; ++i)
84 INSTANCE_WR(ctx, (0x33c/4)+120+i, 0x000105b8);
85 for (i = 0; i < 4; ++i)
86 INSTANCE_WR(ctx, (0x33c/4)+124+i, 0x00080008);
87 for (i = 0; i < 16; ++i)
88 INSTANCE_WR(ctx, (0x33c/4)+136+i, 0x07ff0000);
89 INSTANCE_WR(ctx, (0x33c/4)+154, 0x4b7fffff);
90 INSTANCE_WR(ctx, (0x33c/4)+176, 0x00000001);
91 INSTANCE_WR(ctx, (0x33c/4)+178, 0x00004000);
92 INSTANCE_WR(ctx, (0x33c/4)+181, 0x00000001);
93 INSTANCE_WR(ctx, (0x33c/4)+183, 0x00040000);
94 INSTANCE_WR(ctx, (0x33c/4)+184, 0x00010000);
98 +0x0074239c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
99 +0x007423bc: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
100 +0x007423dc: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
101 +0x007423fc: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
103 +0x00742bdc: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
104 +0x00742bfc: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
105 +0x00742c1c: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
106 +0x00742c3c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
109 for (i = 0; i < 0x880; i += 0x10) {
110 INSTANCE_WR(ctx, ((0x1c1c + i)/4)+0, 0x10700ff9);
111 INSTANCE_WR(ctx, ((0x1c1c + i)/4)+1, 0x0436086c);
112 INSTANCE_WR(ctx, ((0x1c1c + i)/4)+2, 0x000c001b);
116 write32 #1 block at +0x00742fbc NV_PRAMIN+0x42fbc of 4 (0x4) elements:
117 +0x00742fbc: 3f800000 00000000 00000000 00000000
119 INSTANCE_WR(ctx, (0x281c/4), 0x3f800000);
122 write32 #1 block at +0x00742ffc NV_PRAMIN+0x42ffc of 12 (0xc) elements:
123 +0x00742ffc: 40000000 3f800000 3f000000 00000000 40000000 3f800000 00000000 bf800000
124 +0x0074301c: 00000000 bf800000 00000000 00000000
126 INSTANCE_WR(ctx, (0x285c/4)+0, 0x40000000);
127 INSTANCE_WR(ctx, (0x285c/4)+1, 0x3f800000);
128 INSTANCE_WR(ctx, (0x285c/4)+2, 0x3f000000);
129 INSTANCE_WR(ctx, (0x285c/4)+4, 0x40000000);
130 INSTANCE_WR(ctx, (0x285c/4)+5, 0x3f800000);
131 INSTANCE_WR(ctx, (0x285c/4)+7, 0xbf800000);
132 INSTANCE_WR(ctx, (0x285c/4)+9, 0xbf800000);
135 write32 #1 block at +0x00742fcc NV_PRAMIN+0x42fcc of 4 (0x4) elements:
136 +0x00742fcc: 00000000 3f800000 00000000 00000000
138 INSTANCE_WR(ctx, (0x282c/4)+1, 0x3f800000);
141 write32 #1 block at +0x0074302c NV_PRAMIN+0x4302c of 4 (0x4) elements:
142 +0x0074302c: 00000000 00000000 00000000 00000000
143 write32 #1 block at +0x00743c9c NV_PRAMIN+0x43c9c of 4 (0x4) elements:
144 +0x00743c9c: 00000000 00000000 00000000 00000000
145 write32 #1 block at +0x00743c3c NV_PRAMIN+0x43c3c of 8 (0x8) elements:
146 +0x00743c3c: 00000000 00000000 000fe000 00000000 00000000 00000000 00000000 00000000
148 INSTANCE_WR(ctx, (0x349c/4)+2, 0x000fe000);
151 write32 #1 block at +0x00743c6c NV_PRAMIN+0x43c6c of 4 (0x4) elements:
152 +0x00743c6c: 00000000 00000000 00000000 00000000
153 write32 #1 block at +0x00743ccc NV_PRAMIN+0x43ccc of 4 (0x4) elements:
154 +0x00743ccc: 00000000 000003f8 00000000 00000000
156 INSTANCE_WR(ctx, (0x352c/4)+1, 0x000003f8);
158 /* write32 #1 NV_PRAMIN+0x43ce0 <- 0x002fe000 */
159 INSTANCE_WR(ctx, 0x3540/4, 0x002fe000);
162 write32 #1 block at +0x00743cfc NV_PRAMIN+0x43cfc of 8 (0x8) elements:
163 +0x00743cfc: 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c
165 for (i = 0; i < 8; ++i)
166 INSTANCE_WR(ctx, (0x355c/4)+i, 0x001c527c);
169 static void nv2a_graph_context_init(struct drm_device *dev,
170 struct nouveau_gpuobj *ctx)
172 struct drm_nouveau_private *dev_priv = dev->dev_private;
175 INSTANCE_WR(ctx, 0x33c/4, 0xffff0000);
176 for(i = 0x3a0; i< 0x3a8; i += 4)
177 INSTANCE_WR(ctx, i/4, 0x0fff0000);
178 INSTANCE_WR(ctx, 0x47c/4, 0x00000101);
179 INSTANCE_WR(ctx, 0x490/4, 0x00000111);
180 INSTANCE_WR(ctx, 0x4a8/4, 0x44400000);
181 for(i = 0x4d4; i< 0x4e4; i += 4)
182 INSTANCE_WR(ctx, i/4, 0x00030303);
183 for(i = 0x4f4; i< 0x504; i += 4)
184 INSTANCE_WR(ctx, i/4, 0x00080000);
185 for(i = 0x50c; i< 0x51c; i += 4)
186 INSTANCE_WR(ctx, i/4, 0x01012000);
187 for(i = 0x51c; i< 0x52c; i += 4)
188 INSTANCE_WR(ctx, i/4, 0x000105b8);
189 for(i = 0x52c; i< 0x53c; i += 4)
190 INSTANCE_WR(ctx, i/4, 0x00080008);
191 for(i = 0x55c; i< 0x59c; i += 4)
192 INSTANCE_WR(ctx, i/4, 0x07ff0000);
193 INSTANCE_WR(ctx, 0x5a4/4, 0x4b7fffff);
194 INSTANCE_WR(ctx, 0x5fc/4, 0x00000001);
195 INSTANCE_WR(ctx, 0x604/4, 0x00004000);
196 INSTANCE_WR(ctx, 0x610/4, 0x00000001);
197 INSTANCE_WR(ctx, 0x618/4, 0x00040000);
198 INSTANCE_WR(ctx, 0x61c/4, 0x00010000);
200 for (i=0x1a9c; i <= 0x22fc/4; i += 32) {
201 INSTANCE_WR(ctx, i/4 , 0x10700ff9);
202 INSTANCE_WR(ctx, i/4 + 1, 0x0436086c);
203 INSTANCE_WR(ctx, i/4 + 2, 0x000c001b);
206 INSTANCE_WR(ctx, 0x269c/4, 0x3f800000);
207 INSTANCE_WR(ctx, 0x26b0/4, 0x3f800000);
208 INSTANCE_WR(ctx, 0x26dc/4, 0x40000000);
209 INSTANCE_WR(ctx, 0x26e0/4, 0x3f800000);
210 INSTANCE_WR(ctx, 0x26e4/4, 0x3f000000);
211 INSTANCE_WR(ctx, 0x26ec/4, 0x40000000);
212 INSTANCE_WR(ctx, 0x26f0/4, 0x3f800000);
213 INSTANCE_WR(ctx, 0x26f8/4, 0xbf800000);
214 INSTANCE_WR(ctx, 0x2700/4, 0xbf800000);
215 INSTANCE_WR(ctx, 0x3024/4, 0x000fe000);
216 INSTANCE_WR(ctx, 0x30a0/4, 0x000003f8);
217 INSTANCE_WR(ctx, 0x33fc/4, 0x002fe000);
218 for(i = 0x341c; i< 0x343c; i += 4)
219 INSTANCE_WR(ctx, i/4, 0x001c527c);
222 static void nv25_graph_context_init(struct drm_device *dev,
223 struct nouveau_gpuobj *ctx)
225 struct drm_nouveau_private *dev_priv = dev->dev_private;
228 write32 #1 block at +0x00740a7c NV_PRAMIN.GRCTX0+0x35c of 173 (0xad) elements:
229 +0x00740a7c: ffff0000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
230 +0x00740a9c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
231 +0x00740abc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
232 +0x00740adc: 00000000 0fff0000 0fff0000 00000000 00000000 00000000 00000000 00000000
233 +0x00740afc: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
234 +0x00740b1c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
235 +0x00740b3c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
236 +0x00740b5c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
238 +0x00740b7c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
239 +0x00740b9c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
240 +0x00740bbc: 00000101 00000000 00000000 00000000 00000000 00000111 00000000 00000000
241 +0x00740bdc: 00000000 00000000 00000000 00000080 ffff0000 00000001 00000000 00000000
242 +0x00740bfc: 00000000 00000000 44400000 00000000 00000000 00000000 00000000 00000000
243 +0x00740c1c: 4b800000 00000000 00000000 00000000 00000000 00030303 00030303 00030303
244 +0x00740c3c: 00030303 00000000 00000000 00000000 00000000 00080000 00080000 00080000
245 +0x00740c5c: 00080000 00000000 00000000 01012000 01012000 01012000 01012000 000105b8
247 +0x00740c7c: 000105b8 000105b8 000105b8 00080008 00080008 00080008 00080008 00000000
248 +0x00740c9c: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 07ff0000
249 +0x00740cbc: 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000
250 +0x00740cdc: 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 07ff0000 00000000
251 +0x00740cfc: 00000000 4b7fffff 00000000 00000000 00000000 00000000 00000000 00000000
252 +0x00740d1c: 00000000 00000000 00000000 00000000 00000000
254 INSTANCE_WR(ctx, (0x35c/4)+0, 0xffff0000);
255 INSTANCE_WR(ctx, (0x35c/4)+25, 0x0fff0000);
256 INSTANCE_WR(ctx, (0x35c/4)+26, 0x0fff0000);
257 INSTANCE_WR(ctx, (0x35c/4)+80, 0x00000101);
258 INSTANCE_WR(ctx, (0x35c/4)+85, 0x00000111);
259 INSTANCE_WR(ctx, (0x35c/4)+91, 0x00000080);
260 INSTANCE_WR(ctx, (0x35c/4)+92, 0xffff0000);
261 INSTANCE_WR(ctx, (0x35c/4)+93, 0x00000001);
262 INSTANCE_WR(ctx, (0x35c/4)+98, 0x44400000);
263 INSTANCE_WR(ctx, (0x35c/4)+104, 0x4b800000);
264 INSTANCE_WR(ctx, (0x35c/4)+109, 0x00030303);
265 INSTANCE_WR(ctx, (0x35c/4)+110, 0x00030303);
266 INSTANCE_WR(ctx, (0x35c/4)+111, 0x00030303);
267 INSTANCE_WR(ctx, (0x35c/4)+112, 0x00030303);
268 INSTANCE_WR(ctx, (0x35c/4)+117, 0x00080000);
269 INSTANCE_WR(ctx, (0x35c/4)+118, 0x00080000);
270 INSTANCE_WR(ctx, (0x35c/4)+119, 0x00080000);
271 INSTANCE_WR(ctx, (0x35c/4)+120, 0x00080000);
272 INSTANCE_WR(ctx, (0x35c/4)+123, 0x01012000);
273 INSTANCE_WR(ctx, (0x35c/4)+124, 0x01012000);
274 INSTANCE_WR(ctx, (0x35c/4)+125, 0x01012000);
275 INSTANCE_WR(ctx, (0x35c/4)+126, 0x01012000);
276 INSTANCE_WR(ctx, (0x35c/4)+127, 0x000105b8);
277 INSTANCE_WR(ctx, (0x35c/4)+128, 0x000105b8);
278 INSTANCE_WR(ctx, (0x35c/4)+129, 0x000105b8);
279 INSTANCE_WR(ctx, (0x35c/4)+130, 0x000105b8);
280 INSTANCE_WR(ctx, (0x35c/4)+131, 0x00080008);
281 INSTANCE_WR(ctx, (0x35c/4)+132, 0x00080008);
282 INSTANCE_WR(ctx, (0x35c/4)+133, 0x00080008);
283 INSTANCE_WR(ctx, (0x35c/4)+134, 0x00080008);
285 INSTANCE_WR(ctx, (0x35c/4)+143+i, 0x07ff0000);
286 INSTANCE_WR(ctx, (0x35c/4)+161, 0x4b7fffff);
289 write32 #1 block at +0x00740d34 NV_PRAMIN.GRCTX0+0x614 of 3136 (0xc40) elements:
290 +0x00740d34: 00000000 00000000 00000000 00000080 30201000 70605040 b0a09080 f0e0d0c0
291 +0x00740d54: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
292 +0x00740d74: 00000000 00000000 00000000 00000000 00000001 00000000 00004000 00000000
293 +0x00740d94: 00000000 00000001 00000000 00040000 00010000 00000000 00000000 00000000
294 +0x00740db4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
296 +0x00742214: 00000000 00000000 00000000 00000000 10700ff9 0436086c 000c001b 00000000
297 +0x00742234: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
298 +0x00742254: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
299 +0x00742274: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
301 +0x00742a34: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
302 +0x00742a54: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
303 +0x00742a74: 10700ff9 0436086c 000c001b 00000000 10700ff9 0436086c 000c001b 00000000
304 +0x00742a94: 10700ff9 0436086c 000c001b 00000000 00000000 00000000 00000000 00000000
305 +0x00742ab4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
306 +0x00742ad4: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
308 INSTANCE_WR(ctx, (0x614/4)+3, 0x00000080);
309 INSTANCE_WR(ctx, (0x614/4)+4, 0x30201000);
310 INSTANCE_WR(ctx, (0x614/4)+5, 0x70605040);
311 INSTANCE_WR(ctx, (0x614/4)+6, 0xb0a09080);
312 INSTANCE_WR(ctx, (0x614/4)+7, 0xf0e0d0c0);
313 INSTANCE_WR(ctx, (0x614/4)+20, 0x00000001);
314 INSTANCE_WR(ctx, (0x614/4)+22, 0x00004000);
315 INSTANCE_WR(ctx, (0x614/4)+25, 0x00000001);
316 INSTANCE_WR(ctx, (0x614/4)+27, 0x00040000);
317 INSTANCE_WR(ctx, (0x614/4)+28, 0x00010000);
318 for (i=0; i < 0x880/4; i+=4) {
319 INSTANCE_WR(ctx, (0x1b04/4)+i+0, 0x10700ff9);
320 INSTANCE_WR(ctx, (0x1b04/4)+i+1, 0x0436086c);
321 INSTANCE_WR(ctx, (0x1b04/4)+i+2, 0x000c001b);
325 write32 #1 block at +0x00742e24 NV_PRAMIN.GRCTX0+0x2704 of 4 (0x4) elements:
326 +0x00742e24: 3f800000 00000000 00000000 00000000
328 INSTANCE_WR(ctx, (0x2704/4), 0x3f800000);
331 write32 #1 block at +0x00742e64 NV_PRAMIN.GRCTX0+0x2744 of 12 (0xc) elements:
332 +0x00742e64: 40000000 3f800000 3f000000 00000000 40000000 3f800000 00000000 bf800000
333 +0x00742e84: 00000000 bf800000 00000000 00000000
335 INSTANCE_WR(ctx, (0x2744/4)+0, 0x40000000);
336 INSTANCE_WR(ctx, (0x2744/4)+1, 0x3f800000);
337 INSTANCE_WR(ctx, (0x2744/4)+2, 0x3f000000);
338 INSTANCE_WR(ctx, (0x2744/4)+4, 0x40000000);
339 INSTANCE_WR(ctx, (0x2744/4)+5, 0x3f800000);
340 INSTANCE_WR(ctx, (0x2744/4)+7, 0xbf800000);
341 INSTANCE_WR(ctx, (0x2744/4)+9, 0xbf800000);
344 write32 #1 block at +0x00742e34 NV_PRAMIN.GRCTX0+0x2714 of 4 (0x4) elements:
345 +0x00742e34: 00000000 3f800000 00000000 00000000
347 INSTANCE_WR(ctx, (0x2714/4)+1, 0x3f800000);
350 write32 #1 block at +0x00742e94 NV_PRAMIN.GRCTX0+0x2774 of 4 (0x4) elements:
351 +0x00742e94: 00000000 00000000 00000000 00000000
352 write32 #1 block at +0x00743804 NV_PRAMIN.GRCTX0+0x30e4 of 4 (0x4) elements:
353 +0x00743804: 00000000 00000000 00000000 00000000
354 write32 #1 block at +0x007437a4 NV_PRAMIN.GRCTX0+0x3084 of 8 (0x8) elements:
355 +0x007437a4: 00000000 00000000 000fe000 00000000 00000000 00000000 00000000 00000000
357 INSTANCE_WR(ctx, (0x3084/4)+2, 0x000fe000);
360 write32 #1 block at +0x007437d4 NV_PRAMIN.GRCTX0+0x30b4 of 4 (0x4) elements:
361 +0x007437d4: 00000000 00000000 00000000 00000000
362 write32 #1 block at +0x00743824 NV_PRAMIN.GRCTX0+0x3104 of 4 (0x4) elements:
363 +0x00743824: 00000000 000003f8 00000000 00000000
365 INSTANCE_WR(ctx, (0x3104/4)+1, 0x000003f8);
367 /* write32 #1 NV_PRAMIN.GRCTX0+0x3468 <- 0x002fe000 */
368 INSTANCE_WR(ctx, 0x3468/4, 0x002fe000);
371 write32 #1 block at +0x00743ba4 NV_PRAMIN.GRCTX0+0x3484 of 8 (0x8) elements:
372 +0x00743ba4: 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c 001c527c
375 INSTANCE_WR(ctx, (0x3484/4)+i, 0x001c527c);
378 static void nv30_31_graph_context_init(struct drm_device *dev,
379 struct nouveau_gpuobj *ctx)
381 struct drm_nouveau_private *dev_priv = dev->dev_private;
384 INSTANCE_WR(ctx, 0x410/4, 0x00000101);
385 INSTANCE_WR(ctx, 0x424/4, 0x00000111);
386 INSTANCE_WR(ctx, 0x428/4, 0x00000060);
387 INSTANCE_WR(ctx, 0x444/4, 0x00000080);
388 INSTANCE_WR(ctx, 0x448/4, 0xffff0000);
389 INSTANCE_WR(ctx, 0x44c/4, 0x00000001);
390 INSTANCE_WR(ctx, 0x460/4, 0x44400000);
391 INSTANCE_WR(ctx, 0x48c/4, 0xffff0000);
392 for(i = 0x4e0; i< 0x4e8; i += 4)
393 INSTANCE_WR(ctx, i/4, 0x0fff0000);
394 INSTANCE_WR(ctx, 0x4ec/4, 0x00011100);
395 for(i = 0x508; i< 0x548; i += 4)
396 INSTANCE_WR(ctx, i/4, 0x07ff0000);
397 INSTANCE_WR(ctx, 0x550/4, 0x4b7fffff);
398 INSTANCE_WR(ctx, 0x58c/4, 0x00000080);
399 INSTANCE_WR(ctx, 0x590/4, 0x30201000);
400 INSTANCE_WR(ctx, 0x594/4, 0x70605040);
401 INSTANCE_WR(ctx, 0x598/4, 0xb8a89888);
402 INSTANCE_WR(ctx, 0x59c/4, 0xf8e8d8c8);
403 INSTANCE_WR(ctx, 0x5b0/4, 0xb0000000);
404 for(i = 0x600; i< 0x640; i += 4)
405 INSTANCE_WR(ctx, i/4, 0x00010588);
406 for(i = 0x640; i< 0x680; i += 4)
407 INSTANCE_WR(ctx, i/4, 0x00030303);
408 for(i = 0x6c0; i< 0x700; i += 4)
409 INSTANCE_WR(ctx, i/4, 0x0008aae4);
410 for(i = 0x700; i< 0x740; i += 4)
411 INSTANCE_WR(ctx, i/4, 0x01012000);
412 for(i = 0x740; i< 0x780; i += 4)
413 INSTANCE_WR(ctx, i/4, 0x00080008);
414 INSTANCE_WR(ctx, 0x85c/4, 0x00040000);
415 INSTANCE_WR(ctx, 0x860/4, 0x00010000);
416 for(i = 0x864; i< 0x874; i += 4)
417 INSTANCE_WR(ctx, i/4, 0x00040004);
418 for(i = 0x1f18; i<= 0x3088 ; i+= 16) {
419 INSTANCE_WR(ctx, i/4 + 0, 0x10700ff9);
420 INSTANCE_WR(ctx, i/4 + 1, 0x0436086c);
421 INSTANCE_WR(ctx, i/4 + 2, 0x000c001b);
423 for(i = 0x30b8; i< 0x30c8; i += 4)
424 INSTANCE_WR(ctx, i/4, 0x0000ffff);
425 INSTANCE_WR(ctx, 0x344c/4, 0x3f800000);
426 INSTANCE_WR(ctx, 0x3808/4, 0x3f800000);
427 INSTANCE_WR(ctx, 0x381c/4, 0x3f800000);
428 INSTANCE_WR(ctx, 0x3848/4, 0x40000000);
429 INSTANCE_WR(ctx, 0x384c/4, 0x3f800000);
430 INSTANCE_WR(ctx, 0x3850/4, 0x3f000000);
431 INSTANCE_WR(ctx, 0x3858/4, 0x40000000);
432 INSTANCE_WR(ctx, 0x385c/4, 0x3f800000);
433 INSTANCE_WR(ctx, 0x3864/4, 0xbf800000);
434 INSTANCE_WR(ctx, 0x386c/4, 0xbf800000);
437 static void nv34_graph_context_init(struct drm_device *dev,
438 struct nouveau_gpuobj *ctx)
440 struct drm_nouveau_private *dev_priv = dev->dev_private;
443 INSTANCE_WR(ctx, 0x40c/4, 0x01000101);
444 INSTANCE_WR(ctx, 0x420/4, 0x00000111);
445 INSTANCE_WR(ctx, 0x424/4, 0x00000060);
446 INSTANCE_WR(ctx, 0x440/4, 0x00000080);
447 INSTANCE_WR(ctx, 0x444/4, 0xffff0000);
448 INSTANCE_WR(ctx, 0x448/4, 0x00000001);
449 INSTANCE_WR(ctx, 0x45c/4, 0x44400000);
450 INSTANCE_WR(ctx, 0x480/4, 0xffff0000);
451 for(i = 0x4d4; i< 0x4dc; i += 4)
452 INSTANCE_WR(ctx, i/4, 0x0fff0000);
453 INSTANCE_WR(ctx, 0x4e0/4, 0x00011100);
454 for(i = 0x4fc; i< 0x53c; i += 4)
455 INSTANCE_WR(ctx, i/4, 0x07ff0000);
456 INSTANCE_WR(ctx, 0x544/4, 0x4b7fffff);
457 INSTANCE_WR(ctx, 0x57c/4, 0x00000080);
458 INSTANCE_WR(ctx, 0x580/4, 0x30201000);
459 INSTANCE_WR(ctx, 0x584/4, 0x70605040);
460 INSTANCE_WR(ctx, 0x588/4, 0xb8a89888);
461 INSTANCE_WR(ctx, 0x58c/4, 0xf8e8d8c8);
462 INSTANCE_WR(ctx, 0x5a0/4, 0xb0000000);
463 for(i = 0x5f0; i< 0x630; i += 4)
464 INSTANCE_WR(ctx, i/4, 0x00010588);
465 for(i = 0x630; i< 0x670; i += 4)
466 INSTANCE_WR(ctx, i/4, 0x00030303);
467 for(i = 0x6b0; i< 0x6f0; i += 4)
468 INSTANCE_WR(ctx, i/4, 0x0008aae4);
469 for(i = 0x6f0; i< 0x730; i += 4)
470 INSTANCE_WR(ctx, i/4, 0x01012000);
471 for(i = 0x730; i< 0x770; i += 4)
472 INSTANCE_WR(ctx, i/4, 0x00080008);
473 INSTANCE_WR(ctx, 0x850/4, 0x00040000);
474 INSTANCE_WR(ctx, 0x854/4, 0x00010000);
475 for(i = 0x858; i< 0x868; i += 4)
476 INSTANCE_WR(ctx, i/4, 0x00040004);
477 for(i = 0x15ac; i<= 0x271c ; i+= 16) {
478 INSTANCE_WR(ctx, i/4 + 0, 0x10700ff9);
479 INSTANCE_WR(ctx, i/4 + 1, 0x0436086c);
480 INSTANCE_WR(ctx, i/4 + 2, 0x000c001b);
482 for(i = 0x274c; i< 0x275c; i += 4)
483 INSTANCE_WR(ctx, i/4, 0x0000ffff);
484 INSTANCE_WR(ctx, 0x2ae0/4, 0x3f800000);
485 INSTANCE_WR(ctx, 0x2e9c/4, 0x3f800000);
486 INSTANCE_WR(ctx, 0x2eb0/4, 0x3f800000);
487 INSTANCE_WR(ctx, 0x2edc/4, 0x40000000);
488 INSTANCE_WR(ctx, 0x2ee0/4, 0x3f800000);
489 INSTANCE_WR(ctx, 0x2ee4/4, 0x3f000000);
490 INSTANCE_WR(ctx, 0x2eec/4, 0x40000000);
491 INSTANCE_WR(ctx, 0x2ef0/4, 0x3f800000);
492 INSTANCE_WR(ctx, 0x2ef8/4, 0xbf800000);
493 INSTANCE_WR(ctx, 0x2f00/4, 0xbf800000);
496 static void nv35_36_graph_context_init(struct drm_device *dev,
497 struct nouveau_gpuobj *ctx)
499 struct drm_nouveau_private *dev_priv = dev->dev_private;
502 INSTANCE_WR(ctx, 0x40c/4, 0x00000101);
503 INSTANCE_WR(ctx, 0x420/4, 0x00000111);
504 INSTANCE_WR(ctx, 0x424/4, 0x00000060);
505 INSTANCE_WR(ctx, 0x440/4, 0x00000080);
506 INSTANCE_WR(ctx, 0x444/4, 0xffff0000);
507 INSTANCE_WR(ctx, 0x448/4, 0x00000001);
508 INSTANCE_WR(ctx, 0x45c/4, 0x44400000);
509 INSTANCE_WR(ctx, 0x488/4, 0xffff0000);
510 for(i = 0x4dc; i< 0x4e4; i += 4)
511 INSTANCE_WR(ctx, i/4, 0x0fff0000);
512 INSTANCE_WR(ctx, 0x4e8/4, 0x00011100);
513 for(i = 0x504; i< 0x544; i += 4)
514 INSTANCE_WR(ctx, i/4, 0x07ff0000);
515 INSTANCE_WR(ctx, 0x54c/4, 0x4b7fffff);
516 INSTANCE_WR(ctx, 0x588/4, 0x00000080);
517 INSTANCE_WR(ctx, 0x58c/4, 0x30201000);
518 INSTANCE_WR(ctx, 0x590/4, 0x70605040);
519 INSTANCE_WR(ctx, 0x594/4, 0xb8a89888);
520 INSTANCE_WR(ctx, 0x598/4, 0xf8e8d8c8);
521 INSTANCE_WR(ctx, 0x5ac/4, 0xb0000000);
522 for(i = 0x604; i< 0x644; i += 4)
523 INSTANCE_WR(ctx, i/4, 0x00010588);
524 for(i = 0x644; i< 0x684; i += 4)
525 INSTANCE_WR(ctx, i/4, 0x00030303);
526 for(i = 0x6c4; i< 0x704; i += 4)
527 INSTANCE_WR(ctx, i/4, 0x0008aae4);
528 for(i = 0x704; i< 0x744; i += 4)
529 INSTANCE_WR(ctx, i/4, 0x01012000);
530 for(i = 0x744; i< 0x784; i += 4)
531 INSTANCE_WR(ctx, i/4, 0x00080008);
532 INSTANCE_WR(ctx, 0x860/4, 0x00040000);
533 INSTANCE_WR(ctx, 0x864/4, 0x00010000);
534 for(i = 0x868; i< 0x878; i += 4)
535 INSTANCE_WR(ctx, i/4, 0x00040004);
536 for(i = 0x1f1c; i<= 0x308c ; i+= 16) {
537 INSTANCE_WR(ctx, i/4 + 0, 0x10700ff9);
538 INSTANCE_WR(ctx, i/4 + 1, 0x0436086c);
539 INSTANCE_WR(ctx, i/4 + 2, 0x000c001b);
541 for(i = 0x30bc; i< 0x30cc; i += 4)
542 INSTANCE_WR(ctx, i/4, 0x0000ffff);
543 INSTANCE_WR(ctx, 0x3450/4, 0x3f800000);
544 INSTANCE_WR(ctx, 0x380c/4, 0x3f800000);
545 INSTANCE_WR(ctx, 0x3820/4, 0x3f800000);
546 INSTANCE_WR(ctx, 0x384c/4, 0x40000000);
547 INSTANCE_WR(ctx, 0x3850/4, 0x3f800000);
548 INSTANCE_WR(ctx, 0x3854/4, 0x3f000000);
549 INSTANCE_WR(ctx, 0x385c/4, 0x40000000);
550 INSTANCE_WR(ctx, 0x3860/4, 0x3f800000);
551 INSTANCE_WR(ctx, 0x3868/4, 0xbf800000);
552 INSTANCE_WR(ctx, 0x3870/4, 0xbf800000);
555 int nv20_graph_create_context(struct nouveau_channel *chan)
557 struct drm_device *dev = chan->dev;
558 struct drm_nouveau_private *dev_priv = dev->dev_private;
559 void (*ctx_init)(struct drm_device *, struct nouveau_gpuobj *);
560 unsigned int ctx_size;
561 unsigned int idoffs = 0x28/4;
564 switch (dev_priv->chipset) {
566 ctx_size = NV20_GRCTX_SIZE;
567 ctx_init = nv20_graph_context_init;
572 ctx_size = NV25_GRCTX_SIZE;
573 ctx_init = nv25_graph_context_init;
576 ctx_size = NV2A_GRCTX_SIZE;
577 ctx_init = nv2a_graph_context_init;
582 ctx_size = NV30_31_GRCTX_SIZE;
583 ctx_init = nv30_31_graph_context_init;
586 ctx_size = NV34_GRCTX_SIZE;
587 ctx_init = nv34_graph_context_init;
591 ctx_size = NV35_36_GRCTX_SIZE;
592 ctx_init = nv35_36_graph_context_init;
596 ctx_init = nv35_36_graph_context_init;
597 DRM_ERROR("Please contact the devs if you want your NV%x"
598 " card to work\n", dev_priv->chipset);
603 if ((ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, ctx_size, 16,
604 NVOBJ_FLAG_ZERO_ALLOC,
605 &chan->ramin_grctx)))
608 /* Initialise default context values */
609 ctx_init(dev, chan->ramin_grctx->gpuobj);
611 /* nv20: INSTANCE_WR(chan->ramin_grctx->gpuobj, 10, chan->id<<24); */
612 INSTANCE_WR(chan->ramin_grctx->gpuobj, idoffs, (chan->id<<24)|0x1);
615 INSTANCE_WR(dev_priv->ctx_table->gpuobj, chan->id,
616 chan->ramin_grctx->instance >> 4);
621 void nv20_graph_destroy_context(struct nouveau_channel *chan)
623 struct drm_device *dev = chan->dev;
624 struct drm_nouveau_private *dev_priv = dev->dev_private;
626 if (chan->ramin_grctx)
627 nouveau_gpuobj_ref_del(dev, &chan->ramin_grctx);
629 INSTANCE_WR(dev_priv->ctx_table->gpuobj, chan->id, 0);
632 int nv20_graph_load_context(struct nouveau_channel *chan)
634 struct drm_device *dev = chan->dev;
635 struct drm_nouveau_private *dev_priv = dev->dev_private;
638 if (!chan->ramin_grctx)
640 inst = chan->ramin_grctx->instance >> 4;
642 NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
643 NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_XFER,
644 NV20_PGRAPH_CHANNEL_CTX_XFER_LOAD);
645 NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10010100);
647 nouveau_wait_for_idle(dev);
651 int nv20_graph_save_context(struct nouveau_channel *chan)
653 struct drm_device *dev = chan->dev;
654 struct drm_nouveau_private *dev_priv = dev->dev_private;
657 if (!chan->ramin_grctx)
659 inst = chan->ramin_grctx->instance >> 4;
661 NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
662 NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_XFER,
663 NV20_PGRAPH_CHANNEL_CTX_XFER_SAVE);
665 nouveau_wait_for_idle(dev);
669 static void nv20_graph_rdi(struct drm_device *dev) {
670 struct drm_nouveau_private *dev_priv = dev->dev_private;
671 int i, writecount = 32;
672 uint32_t rdi_index = 0x2c80000;
674 if (dev_priv->chipset == 0x20) {
675 rdi_index = 0x3d0000;
679 NV_WRITE(NV10_PGRAPH_RDI_INDEX, rdi_index);
680 for (i = 0; i < writecount; i++)
681 NV_WRITE(NV10_PGRAPH_RDI_DATA, 0);
683 nouveau_wait_for_idle(dev);
686 int nv20_graph_init(struct drm_device *dev) {
687 struct drm_nouveau_private *dev_priv =
688 (struct drm_nouveau_private *)dev->dev_private;
689 uint32_t tmp, vramsz;
692 NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) &
693 ~NV_PMC_ENABLE_PGRAPH);
694 NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) |
695 NV_PMC_ENABLE_PGRAPH);
697 /* Create Context Pointer Table */
698 dev_priv->ctx_table_size = 32 * 4;
699 if ((ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0,
700 dev_priv->ctx_table_size, 16,
701 NVOBJ_FLAG_ZERO_ALLOC,
702 &dev_priv->ctx_table)))
705 NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_TABLE,
706 dev_priv->ctx_table->instance >> 4);
710 NV_WRITE(NV03_PGRAPH_INTR , 0xFFFFFFFF);
711 NV_WRITE(NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
713 NV_WRITE(NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
714 NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x00000000);
715 NV_WRITE(NV04_PGRAPH_DEBUG_1, 0x00118700);
716 NV_WRITE(NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */
717 NV_WRITE(NV10_PGRAPH_DEBUG_4, 0x00000000);
718 NV_WRITE(0x40009C , 0x00000040);
720 if (dev_priv->chipset >= 0x25) {
721 NV_WRITE(0x400890, 0x00080000);
722 NV_WRITE(0x400610, 0x304B1FB6);
723 NV_WRITE(0x400B80, 0x18B82880);
724 NV_WRITE(0x400B84, 0x44000000);
725 NV_WRITE(0x400098, 0x40000080);
726 NV_WRITE(0x400B88, 0x000000ff);
728 NV_WRITE(0x400880, 0x00080000); /* 0x0008c7df */
729 NV_WRITE(0x400094, 0x00000005);
730 NV_WRITE(0x400B80, 0x45CAA208); /* 0x45eae20e */
731 NV_WRITE(0x400B84, 0x24000000);
732 NV_WRITE(0x400098, 0x00000040);
733 NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00E00038);
734 NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00000030);
735 NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00E10038);
736 NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00000030);
739 /* copy tile info from PFB */
740 for (i = 0; i < NV10_PFB_TILE__SIZE; i++) {
741 NV_WRITE(0x00400904 + i*0x10, NV_READ(NV10_PFB_TLIMIT(i)));
742 /* which is NV40_PGRAPH_TLIMIT0(i) ?? */
743 NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0030+i*4);
744 NV_WRITE(NV10_PGRAPH_RDI_DATA, NV_READ(NV10_PFB_TLIMIT(i)));
745 NV_WRITE(0x00400908 + i*0x10, NV_READ(NV10_PFB_TSIZE(i)));
746 /* which is NV40_PGRAPH_TSIZE0(i) ?? */
747 NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0050+i*4);
748 NV_WRITE(NV10_PGRAPH_RDI_DATA, NV_READ(NV10_PFB_TSIZE(i)));
749 NV_WRITE(0x00400900 + i*0x10, NV_READ(NV10_PFB_TILE(i)));
750 /* which is NV40_PGRAPH_TILE0(i) ?? */
751 NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0010+i*4);
752 NV_WRITE(NV10_PGRAPH_RDI_DATA, NV_READ(NV10_PFB_TILE(i)));
754 for (i = 0; i < 8; i++) {
755 NV_WRITE(0x400980+i*4, NV_READ(0x100300+i*4));
756 NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0090+i*4);
757 NV_WRITE(NV10_PGRAPH_RDI_DATA, NV_READ(0x100300+i*4));
759 NV_WRITE(0x4009a0, NV_READ(0x100324));
760 NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA000C);
761 NV_WRITE(NV10_PGRAPH_RDI_DATA, NV_READ(0x100324));
763 NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10000100);
764 NV_WRITE(NV10_PGRAPH_STATE , 0xFFFFFFFF);
765 NV_WRITE(NV04_PGRAPH_FIFO , 0x00000001);
767 tmp = NV_READ(NV10_PGRAPH_SURFACE) & 0x0007ff00;
768 NV_WRITE(NV10_PGRAPH_SURFACE, tmp);
769 tmp = NV_READ(NV10_PGRAPH_SURFACE) | 0x00020100;
770 NV_WRITE(NV10_PGRAPH_SURFACE, tmp);
772 /* begin RAM config */
773 vramsz = drm_get_resource_len(dev, 0) - 1;
774 NV_WRITE(0x4009A4, NV_READ(NV04_PFB_CFG0));
775 NV_WRITE(0x4009A8, NV_READ(NV04_PFB_CFG1));
776 NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
777 NV_WRITE(NV10_PGRAPH_RDI_DATA , NV_READ(NV04_PFB_CFG0));
778 NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
779 NV_WRITE(NV10_PGRAPH_RDI_DATA , NV_READ(NV04_PFB_CFG1));
780 NV_WRITE(0x400820, 0);
781 NV_WRITE(0x400824, 0);
782 NV_WRITE(0x400864, vramsz-1);
783 NV_WRITE(0x400868, vramsz-1);
785 /* interesting.. the below overwrites some of the tile setup above.. */
786 NV_WRITE(0x400B20, 0x00000000);
787 NV_WRITE(0x400B04, 0xFFFFFFFF);
789 NV_WRITE(NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
790 NV_WRITE(NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
791 NV_WRITE(NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
792 NV_WRITE(NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
797 void nv20_graph_takedown(struct drm_device *dev)
799 struct drm_nouveau_private *dev_priv = dev->dev_private;
801 nouveau_gpuobj_ref_del(dev, &dev_priv->ctx_table);
804 int nv30_graph_init(struct drm_device *dev)
806 struct drm_nouveau_private *dev_priv = dev->dev_private;
807 // uint32_t vramsz, tmp;
810 NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) &
811 ~NV_PMC_ENABLE_PGRAPH);
812 NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) |
813 NV_PMC_ENABLE_PGRAPH);
815 /* Create Context Pointer Table */
816 dev_priv->ctx_table_size = 32 * 4;
817 if ((ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0,
818 dev_priv->ctx_table_size, 16,
819 NVOBJ_FLAG_ZERO_ALLOC,
820 &dev_priv->ctx_table)))
823 NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_TABLE,
824 dev_priv->ctx_table->instance >> 4);
826 NV_WRITE(NV03_PGRAPH_INTR , 0xFFFFFFFF);
827 NV_WRITE(NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
829 NV_WRITE(NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
830 NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x00000000);
831 NV_WRITE(NV04_PGRAPH_DEBUG_1, 0x401287c0);
832 NV_WRITE(0x400890, 0x01b463ff);
833 NV_WRITE(NV04_PGRAPH_DEBUG_3, 0xf2de0475);
834 NV_WRITE(NV10_PGRAPH_DEBUG_4, 0x00008000);
835 NV_WRITE(NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6);
836 NV_WRITE(0x400B80, 0x1003d888);
837 NV_WRITE(0x400B84, 0x0c000000);
838 NV_WRITE(0x400098, 0x00000000);
839 NV_WRITE(0x40009C, 0x0005ad00);
840 NV_WRITE(0x400B88, 0x62ff00ff); // suspiciously like PGRAPH_DEBUG_2
841 NV_WRITE(0x4000a0, 0x00000000);
842 NV_WRITE(0x4000a4, 0x00000008);
843 NV_WRITE(0x4008a8, 0xb784a400);
844 NV_WRITE(0x400ba0, 0x002f8685);
845 NV_WRITE(0x400ba4, 0x00231f3f);
846 NV_WRITE(0x4008a4, 0x40000020);
848 if (dev_priv->chipset == 0x34) {
849 NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
850 NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00200201);
851 NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0008);
852 NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00000008);
853 NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
854 NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00000032);
855 NV_WRITE(NV10_PGRAPH_RDI_INDEX, 0x00E00004);
856 NV_WRITE(NV10_PGRAPH_RDI_DATA , 0x00000002);
859 NV_WRITE(0x4000c0, 0x00000016);
861 /* copy tile info from PFB */
862 for (i = 0; i < NV10_PFB_TILE__SIZE; i++) {
863 NV_WRITE(0x00400904 + i*0x10, NV_READ(NV10_PFB_TLIMIT(i)));
864 /* which is NV40_PGRAPH_TLIMIT0(i) ?? */
865 NV_WRITE(0x00400908 + i*0x10, NV_READ(NV10_PFB_TSIZE(i)));
866 /* which is NV40_PGRAPH_TSIZE0(i) ?? */
867 NV_WRITE(0x00400900 + i*0x10, NV_READ(NV10_PFB_TILE(i)));
868 /* which is NV40_PGRAPH_TILE0(i) ?? */
871 NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10000100);
872 NV_WRITE(NV10_PGRAPH_STATE , 0xFFFFFFFF);
873 NV_WRITE(0x0040075c , 0x00000001);
874 NV_WRITE(NV04_PGRAPH_FIFO , 0x00000001);
876 /* begin RAM config */
877 // vramsz = drm_get_resource_len(dev, 0) - 1;
878 NV_WRITE(0x4009A4, NV_READ(NV04_PFB_CFG0));
879 NV_WRITE(0x4009A8, NV_READ(NV04_PFB_CFG1));
880 if (dev_priv->chipset != 0x34) {
881 NV_WRITE(0x400750, 0x00EA0000);
882 NV_WRITE(0x400754, NV_READ(NV04_PFB_CFG0));
883 NV_WRITE(0x400750, 0x00EA0004);
884 NV_WRITE(0x400754, NV_READ(NV04_PFB_CFG1));
888 NV_WRITE(0x400820, 0);
889 NV_WRITE(0x400824, 0);
890 NV_WRITE(0x400864, vramsz-1);
891 NV_WRITE(0x400868, vramsz-1);
893 NV_WRITE(0x400B20, 0x00000000);
894 NV_WRITE(0x400B04, 0xFFFFFFFF);
896 /* per-context state, doesn't belong here */
897 tmp = NV_READ(NV10_PGRAPH_SURFACE) & 0x0007ff00;
898 NV_WRITE(NV10_PGRAPH_SURFACE, tmp);
899 tmp = NV_READ(NV10_PGRAPH_SURFACE) | 0x00020100;
900 NV_WRITE(NV10_PGRAPH_SURFACE, tmp);
902 NV_WRITE(NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
903 NV_WRITE(NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
904 NV_WRITE(NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
905 NV_WRITE(NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);