shared-core/nv04_instmem.c

   1 #include "drmP.h"
   2 #include "drm.h"
   3 #include "nouveau_drv.h"
   4
   5 static void
   6 nv04_instmem_determine_amount(struct drm_device *dev)
   7 {
   8         struct drm_nouveau_private *dev_priv = dev->dev_private;
   9         int i;
  10
  11         /* Figure out how much instance memory we need */
  12         if (dev_priv->card_type >= NV_40) {
  13                 /* We'll want more instance memory than this on some NV4x cards.
  14                  * There's a 16MB aperture to play with that maps onto the end
  15                  * of vram.  For now, only reserve a small piece until we know
  16                  * more about what each chipset requires.
  17                  */
  18                 dev_priv->ramin_rsvd_vram = (1*1024* 1024);
  19         } else {
  20                 /*XXX: what *are* the limits on <NV40 cards?, and does RAMIN
  21                  *     exist in vram on those cards as well?
  22                  */
  23                 dev_priv->ramin_rsvd_vram = (512*1024);
  24         }
  25         DRM_DEBUG("RAMIN size: %dKiB\n", dev_priv->ramin_rsvd_vram>>10);
  26
  27         /* Clear all of it, except the BIOS image that's in the first 64KiB */
  28         for (i=(64*1024); i<dev_priv->ramin_rsvd_vram; i+=4)
  29                 NV_WI32(i, 0x00000000);
  30 }
  31
  32 static void
  33 nv04_instmem_configure_fixed_tables(struct drm_device *dev)
  34 {
  35         struct drm_nouveau_private *dev_priv = dev->dev_private;
  36         struct nouveau_engine *engine = &dev_priv->Engine;
  37
  38         /* FIFO hash table (RAMHT)
  39          *   use 4k hash table at RAMIN+0x10000
  40          *   TODO: extend the hash table
  41          */
  42         dev_priv->ramht_offset = 0x10000;
  43         dev_priv->ramht_bits   = 9;
  44         dev_priv->ramht_size   = (1 << dev_priv->ramht_bits);
  45         DRM_DEBUG("RAMHT offset=0x%x, size=%d\n", dev_priv->ramht_offset,
  46                                                   dev_priv->ramht_size);
  47
  48         /* FIFO runout table (RAMRO) - 512k at 0x11200 */
  49         dev_priv->ramro_offset = 0x11200;
  50         dev_priv->ramro_size   = 512;
  51         DRM_DEBUG("RAMRO offset=0x%x, size=%d\n", dev_priv->ramro_offset,
  52                                                   dev_priv->ramro_size);
  53
  54         /* FIFO context table (RAMFC)
  55          *   NV40  : Not sure exactly how to position RAMFC on some cards,
  56          *           0x30002 seems to position it at RAMIN+0x20000 on these
  57          *           cards.  RAMFC is 4kb (32 fifos, 128byte entries).
  58          *   Others: Position RAMFC at RAMIN+0x11400
  59          */
  60         switch(dev_priv->card_type)
  61         {
  62                 case NV_40:
  63                 case NV_44:
  64                         dev_priv->ramfc_offset = 0x20000;
  65                         dev_priv->ramfc_size   = engine->fifo.channels *
  66                                                  nouveau_fifo_ctx_size(dev);
  67                         break;
  68                 case NV_30:
  69                 case NV_20:
  70                 case NV_17:
  71                 case NV_11:
  72                 case NV_10:
  73                 case NV_04:
  74                 default:
  75                         dev_priv->ramfc_offset = 0x11400;
  76                         dev_priv->ramfc_size   = engine->fifo.channels *
  77                                                  nouveau_fifo_ctx_size(dev);
  78                         break;
  79         }
  80         DRM_DEBUG("RAMFC offset=0x%x, size=%d\n", dev_priv->ramfc_offset,
  81                                                   dev_priv->ramfc_size);
  82 }
  83
  84 int nv04_instmem_init(struct drm_device *dev)
  85 {
  86         struct drm_nouveau_private *dev_priv = dev->dev_private;
  87         uint32_t offset;
  88         int ret = 0;
  89
  90         nv04_instmem_determine_amount(dev);
  91         nv04_instmem_configure_fixed_tables(dev);
  92
  93         /* Create a heap to manage RAMIN allocations, we don't allocate
  94          * the space that was reserved for RAMHT/FC/RO.
  95          */
  96         offset = dev_priv->ramfc_offset + dev_priv->ramfc_size;
  97
  98         /* On my NV4E, there's *something* clobbering the 16KiB just after
  99          * where we setup these fixed tables.  No idea what it is just yet,
 100          * so reserve this space on all NV4X cards for now.
 101          */
 102         if (dev_priv->card_type >= NV_40)
 103                 offset += 16*1024;
 104
 105         ret = nouveau_mem_init_heap(&dev_priv->ramin_heap,
 106                                     offset, dev_priv->ramin_rsvd_vram - offset);
 107         if (ret) {
 108                 dev_priv->ramin_heap = NULL;
 109                 DRM_ERROR("Failed to init RAMIN heap\n");
 110         }
 111
 112         return ret;
 113 }
 114
 115 void
 116 nv04_instmem_takedown(struct drm_device *dev)
 117 {
 118 }
 119
 120 int
 121 nv04_instmem_populate(struct drm_device *dev, struct nouveau_gpuobj *gpuobj, uint32_t *sz)
 122 {
 123         if (gpuobj->im_backing)
 124                 return -EINVAL;
 125
 126         return 0;
 127 }
 128
 129 void
 130 nv04_instmem_clear(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
 131 {
 132         struct drm_nouveau_private *dev_priv = dev->dev_private;
 133
 134         if (gpuobj && gpuobj->im_backing) {
 135                 if (gpuobj->im_bound)
 136                         dev_priv->Engine.instmem.unbind(dev, gpuobj);
 137                 gpuobj->im_backing = NULL;
 138         }
 139 }
 140
 141 int
 142 nv04_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
 143 {
 144         if (!gpuobj->im_pramin || gpuobj->im_bound)
 145                 return -EINVAL;
 146
 147         gpuobj->im_bound = 1;
 148         return 0;
 149 }
 150
 151 int
 152 nv04_instmem_unbind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
 153 {
 154         if (gpuobj->im_bound == 0)
 155                 return -EINVAL;
 156
 157         gpuobj->im_bound = 0;
 158         return 0;
 159 }