shared-core/nv04_fifo.c

   1 /*
   2  * Copyright (C) 2007 Ben Skeggs.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm.h"
  29 #include "nouveau_drv.h"
  30
  31 #define NV04_RAMFC (NV_RAMIN + dev_priv->ramfc_offset)
  32 #define RAMFC_WR(offset, val) NV_WRITE(fifoctx + NV04_RAMFC_##offset, (val))
  33 #define RAMFC_RD(offset)      NV_READ(fifoctx + NV04_RAMFC_##offset)
  34 #define NV04_FIFO_CONTEXT_SIZE 32
  35
  36 int
  37 nv04_fifo_create_context(drm_device_t *dev, int channel)
  38 {
  39         drm_nouveau_private_t *dev_priv = dev->dev_private;
  40         struct nouveau_fifo *chan = &dev_priv->fifos[channel];
  41         struct nouveau_object *pb = chan->cmdbuf_obj;
  42         int fifoctx = NV04_RAMFC + (channel * NV04_FIFO_CONTEXT_SIZE);
  43         int i;
  44
  45         if (!pb || !pb->instance)
  46                 return DRM_ERR(EINVAL);
  47
  48         /* Clear RAMFC */
  49         for (i=0; i<NV04_FIFO_CONTEXT_SIZE; i+=4)
  50                 NV_WRITE(fifoctx + i, 0);
  51
  52         /* Setup initial state */
  53         RAMFC_WR(DMA_PUT, chan->pushbuf_base);
  54         RAMFC_WR(DMA_GET, chan->pushbuf_base);
  55         RAMFC_WR(DMA_INSTANCE, nouveau_chip_instance_get(dev, pb->instance));
  56         /* NOTE: nvidia use TRIG_128/SIZE_128/MAX_REQS_8 */
  57         RAMFC_WR(DMA_FETCH, (NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES |
  58                              NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
  59                              NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 |
  60 #ifdef __BIG_ENDIAN
  61                              NV_PFIFO_CACHE1_BIG_ENDIAN |
  62 #endif
  63                              0));
  64         return 0;
  65 }
  66
  67 void
  68 nv04_fifo_destroy_context(drm_device_t *dev, int channel)
  69 {
  70         drm_nouveau_private_t *dev_priv = dev->dev_private;
  71         uint32_t fifoctx;
  72         int i;
  73
  74         fifoctx = NV04_RAMFC + (channel * NV04_FIFO_CONTEXT_SIZE);
  75         for (i=0; i<NV04_FIFO_CONTEXT_SIZE; i+=4)
  76                 NV_WRITE(fifoctx + i, 0);
  77 }
  78
  79 int
  80 nv04_fifo_load_context(drm_device_t *dev, int channel)
  81 {
  82         drm_nouveau_private_t *dev_priv = dev->dev_private;
  83         int fifoctx = NV04_RAMFC + (channel * NV04_FIFO_CONTEXT_SIZE);
  84         uint32_t tmp;
  85
  86         NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT, RAMFC_RD(DMA_PUT));
  87         NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET, RAMFC_RD(DMA_GET));
  88
  89         tmp = RAMFC_RD(DMA_INSTANCE);
  90         NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE, tmp & 0xFFFF);
  91         NV_WRITE(NV04_PFIFO_CACHE1_DMA_DCOUNT, tmp >> 16);
  92
  93         NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE, RAMFC_RD(DMA_STATE));
  94         NV_WRITE(NV04_PFIFO_CACHE1_DMA_FETCH, RAMFC_RD(DMA_FETCH));
  95         NV_WRITE(NV04_PFIFO_CACHE1_ENGINE, RAMFC_RD(ENGINE));
  96         NV_WRITE(NV04_PFIFO_CACHE1_PULL1, RAMFC_RD(PULL1_ENGINE));
  97
  98         /* Reset NV04_PFIFO_CACHE1_DMA_CTL_AT_INFO to INVALID */
  99         tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_CTL) & ~(1<<31);
 100         NV_WRITE(NV04_PFIFO_CACHE1_DMA_CTL, tmp);
 101
 102         return 0;
 103 }
 104
 105 int
 106 nv04_fifo_save_context(drm_device_t *dev, int channel)
 107 {
 108         drm_nouveau_private_t *dev_priv = dev->dev_private;
 109         int fifoctx = NV04_RAMFC + (channel * NV04_FIFO_CONTEXT_SIZE);
 110         uint32_t tmp;
 111
 112         RAMFC_WR(DMA_PUT, NV04_PFIFO_CACHE1_DMA_PUT);
 113         RAMFC_WR(DMA_GET, NV04_PFIFO_CACHE1_DMA_GET);
 114
 115         tmp  = NV_READ(NV04_PFIFO_CACHE1_DMA_DCOUNT) << 16;
 116         tmp |= NV_READ(NV04_PFIFO_CACHE1_DMA_INSTANCE);
 117         RAMFC_WR(DMA_INSTANCE, tmp);
 118
 119         RAMFC_WR(DMA_STATE, NV_READ(NV04_PFIFO_CACHE1_DMA_STATE));
 120         RAMFC_WR(DMA_FETCH, NV_READ(NV04_PFIFO_CACHE1_DMA_FETCH));
 121         RAMFC_WR(ENGINE, NV_READ(NV04_PFIFO_CACHE1_ENGINE));
 122         RAMFC_WR(PULL1_ENGINE, NV_READ(NV04_PFIFO_CACHE1_PULL1));
 123
 124         return 0;
 125 }
 126