3 #define NV03_BOOT_0 0x00100000
4 # define NV03_BOOT_0_RAM_AMOUNT 0x00000003
5 # define NV03_BOOT_0_RAM_AMOUNT_8MB 0x00000000
6 # define NV03_BOOT_0_RAM_AMOUNT_2MB 0x00000001
7 # define NV03_BOOT_0_RAM_AMOUNT_4MB 0x00000002
8 # define NV03_BOOT_0_RAM_AMOUNT_8MB_SDRAM 0x00000003
9 # define NV04_BOOT_0_RAM_AMOUNT_32MB 0x00000000
10 # define NV04_BOOT_0_RAM_AMOUNT_4MB 0x00000001
11 # define NV04_BOOT_0_RAM_AMOUNT_8MB 0x00000002
12 # define NV04_BOOT_0_RAM_AMOUNT_16MB 0x00000003
14 #define NV04_FIFO_DATA 0x0010020c
15 # define NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK 0xfff00000
16 # define NV10_FIFO_DATA_RAM_AMOUNT_MB_SHIFT 20
18 #define NV03_PGRAPH_STATUS 0x004006b0
19 #define NV04_PGRAPH_STATUS 0x00400700
21 #define NV_RAMIN 0x00700000
23 #define NV_RAMHT_HANDLE_OFFSET 0
24 #define NV_RAMHT_CONTEXT_OFFSET 4
25 # define NV_RAMHT_CONTEXT_VALID (1<<31)
26 # define NV_RAMHT_CONTEXT_CHANNEL_SHIFT 24
27 # define NV_RAMHT_CONTEXT_ENGINE_SHIFT 16
28 # define NV_RAMHT_CONTEXT_ENGINE_SOFTWARE 0
29 # define NV_RAMHT_CONTEXT_ENGINE_GRAPHICS 1
30 # define NV_RAMHT_CONTEXT_INSTANCE_SHIFT 0
31 # define NV40_RAMHT_CONTEXT_CHANNEL_SHIFT 23
32 # define NV40_RAMHT_CONTEXT_ENGINE_SHIFT 20
33 # define NV40_RAMHT_CONTEXT_INSTANCE_SHIFT 0
35 /* DMA object defines */
36 #define NV_DMA_ACCESS_RW 0
37 #define NV_DMA_ACCESS_RO 1
38 #define NV_DMA_ACCESS_WO 2
39 #define NV_DMA_TARGET_VIDMEM 0
40 #define NV_DMA_TARGET_PCI 2
41 #define NV_DMA_TARGET_AGP 3
43 /* Some object classes we care about in the drm */
44 #define NV_CLASS_DMA_FROM_MEMORY 0x00000002
45 #define NV_CLASS_DMA_TO_MEMORY 0x00000003
46 #define NV_CLASS_NULL 0x00000030
47 #define NV_CLASS_DMA_IN_MEMORY 0x0000003D
49 #define NV03_FIFO_SIZE 0x8000UL
50 #define NV_MAX_FIFO_NUMBER 32
51 #define NV03_FIFO_REGS_SIZE 0x10000
52 #define NV03_FIFO_REGS(i) (0x00800000+i*NV03_FIFO_REGS_SIZE)
53 # define NV03_FIFO_REGS_DMAPUT(i) (NV03_FIFO_REGS(i)+0x40)
54 # define NV03_FIFO_REGS_DMAGET(i) (NV03_FIFO_REGS(i)+0x44)
56 #define NV03_PMC_BOOT_0 0x00000000
57 #define NV03_PMC_INTR_0 0x00000100
58 # define NV_PMC_INTR_0_PFIFO_PENDING (1<< 8)
59 # define NV_PMC_INTR_0_PGRAPH_PENDING (1<<12)
60 # define NV_PMC_INTR_0_CRTC0_PENDING (1<<24)
61 # define NV_PMC_INTR_0_CRTC1_PENDING (1<<25)
62 # define NV_PMC_INTR_0_CRTCn_PENDING (3<<24)
63 #define NV03_PMC_INTR_EN_0 0x00000140
64 # define NV_PMC_INTR_EN_0_MASTER_ENABLE (1<< 0)
65 #define NV03_PMC_ENABLE 0x00000200
66 # define NV_PMC_ENABLE_PFIFO (1<< 8)
67 # define NV_PMC_ENABLE_PGRAPH (1<<12)
68 /* Disabling the below bit breaks newer (G7X only?) mobile chipsets,
69 * the card will hang early on in the X init process.
71 # define NV_PMC_ENABLE_UNK13 (1<<13)
72 #define NV40_PMC_1700 0x00001700
73 #define NV40_PMC_1704 0x00001704
74 #define NV40_PMC_1708 0x00001708
75 #define NV40_PMC_170C 0x0000170C
77 #define NV04_PTIMER_INTR_0 0x00009100
78 #define NV04_PTIMER_INTR_EN_0 0x00009140
79 #define NV04_PTIMER_NUMERATOR 0x00009200
80 #define NV04_PTIMER_DENOMINATOR 0x00009210
81 #define NV04_PTIMER_TIME_0 0x00009400
82 #define NV04_PTIMER_TIME_1 0x00009410
83 #define NV04_PTIMER_ALARM_0 0x00009420
85 #define NV04_PFB_CFG0 0x00100200
86 #define NV04_PFB_CFG1 0x00100204
87 #define NV40_PFB_020C 0x0010020C
88 #define NV10_PFB_TILE(i) (0x00100240 + (i*16))
89 #define NV10_PFB_TILE__SIZE 8
90 #define NV10_PFB_TLIMIT(i) (0x00100244 + (i*16))
91 #define NV10_PFB_TSIZE(i) (0x00100248 + (i*16))
92 #define NV10_PFB_TSTATUS(i) (0x0010024C + (i*16))
93 #define NV10_PFB_CLOSE_PAGE2 0x0010033C
94 #define NV40_PFB_TILE(i) (0x00100600 + (i*16))
95 #define NV40_PFB_TILE__SIZE_0 12
96 #define NV40_PFB_TILE__SIZE_1 15
97 #define NV40_PFB_TLIMIT(i) (0x00100604 + (i*16))
98 #define NV40_PFB_TSIZE(i) (0x00100608 + (i*16))
99 #define NV40_PFB_TSTATUS(i) (0x0010060C + (i*16))
101 #define NV04_PGRAPH_DEBUG_0 0x00400080
102 #define NV04_PGRAPH_DEBUG_1 0x00400084
103 #define NV04_PGRAPH_DEBUG_2 0x00400088
104 #define NV04_PGRAPH_DEBUG_3 0x0040008c
105 #define NV10_PGRAPH_DEBUG_4 0x00400090
106 #define NV03_PGRAPH_INTR 0x00400100
107 #define NV03_PGRAPH_INTR_EN 0x00400140
108 #define NV40_PGRAPH_INTR_EN 0x0040013C
109 # define NV_PGRAPH_INTR_NOTIFY (1<< 0)
110 # define NV_PGRAPH_INTR_MISSING_HW (1<< 4)
111 # define NV_PGRAPH_INTR_CONTEXT_SWITCH (1<<12)
112 # define NV_PGRAPH_INTR_BUFFER_NOTIFY (1<<16)
113 # define NV_PGRAPH_INTR_ERROR (1<<20)
114 #define NV10_PGRAPH_CTX_CONTROL 0x00400144
115 #define NV10_PGRAPH_CTX_USER 0x00400148
116 #define NV10_PGRAPH_CTX_SWITCH1 0x0040014C
117 #define NV10_PGRAPH_CTX_SWITCH2 0x00400150
118 #define NV10_PGRAPH_CTX_SWITCH3 0x00400154
119 #define NV10_PGRAPH_CTX_SWITCH4 0x00400158
120 #define NV10_PGRAPH_CTX_SWITCH5 0x0040015C
121 #define NV04_PGRAPH_CTX_SWITCH1 0x00400160
122 #define NV10_PGRAPH_CTX_CACHE1 0x00400160
123 #define NV04_PGRAPH_CTX_SWITCH2 0x00400164
124 #define NV04_PGRAPH_CTX_SWITCH3 0x00400168
125 #define NV04_PGRAPH_CTX_SWITCH4 0x0040016C
126 #define NV04_PGRAPH_CTX_CONTROL 0x00400170
127 #define NV04_PGRAPH_CTX_USER 0x00400174
128 #define NV04_PGRAPH_CTX_CACHE1 0x00400180
129 #define NV10_PGRAPH_CTX_CACHE2 0x00400180
130 #define NV03_PGRAPH_CTX_CONTROL 0x00400190
131 #define NV03_PGRAPH_CTX_USER 0x00400194
132 #define NV04_PGRAPH_CTX_CACHE2 0x004001A0
133 #define NV10_PGRAPH_CTX_CACHE3 0x004001A0
134 #define NV04_PGRAPH_CTX_CACHE3 0x004001C0
135 #define NV10_PGRAPH_CTX_CACHE4 0x004001C0
136 #define NV04_PGRAPH_CTX_CACHE4 0x004001E0
137 #define NV10_PGRAPH_CTX_CACHE5 0x004001E0
138 #define NV03_PGRAPH_ABS_X_RAM 0x00400400
139 #define NV03_PGRAPH_ABS_Y_RAM 0x00400480
140 #define NV03_PGRAPH_X_MISC 0x00400500
141 #define NV03_PGRAPH_Y_MISC 0x00400504
142 #define NV04_PGRAPH_VALID1 0x00400508
143 #define NV04_PGRAPH_SOURCE_COLOR 0x0040050C
144 #define NV04_PGRAPH_MISC24_0 0x00400510
145 #define NV03_PGRAPH_XY_LOGIC_MISC0 0x00400514
146 #define NV03_PGRAPH_XY_LOGIC_MISC1 0x00400518
147 #define NV03_PGRAPH_XY_LOGIC_MISC2 0x0040051C
148 #define NV03_PGRAPH_XY_LOGIC_MISC3 0x00400520
149 #define NV03_PGRAPH_CLIPX_0 0x00400524
150 #define NV03_PGRAPH_CLIPX_1 0x00400528
151 #define NV03_PGRAPH_CLIPY_0 0x0040052C
152 #define NV03_PGRAPH_CLIPY_1 0x00400530
153 #define NV03_PGRAPH_ABS_ICLIP_XMAX 0x00400534
154 #define NV03_PGRAPH_ABS_ICLIP_YMAX 0x00400538
155 #define NV03_PGRAPH_ABS_UCLIP_XMIN 0x0040053C
156 #define NV03_PGRAPH_ABS_UCLIP_YMIN 0x00400540
157 #define NV03_PGRAPH_ABS_UCLIP_XMAX 0x00400544
158 #define NV03_PGRAPH_ABS_UCLIP_YMAX 0x00400548
159 #define NV03_PGRAPH_ABS_UCLIPA_XMIN 0x00400560
160 #define NV03_PGRAPH_ABS_UCLIPA_YMIN 0x00400564
161 #define NV03_PGRAPH_ABS_UCLIPA_XMAX 0x00400568
162 #define NV03_PGRAPH_ABS_UCLIPA_YMAX 0x0040056C
163 #define NV04_PGRAPH_MISC24_1 0x00400570
164 #define NV04_PGRAPH_MISC24_2 0x00400574
165 #define NV04_PGRAPH_VALID2 0x00400578
166 #define NV04_PGRAPH_PASSTHRU_0 0x0040057C
167 #define NV04_PGRAPH_PASSTHRU_1 0x00400580
168 #define NV04_PGRAPH_PASSTHRU_2 0x00400584
169 #define NV10_PGRAPH_DIMX_TEXTURE 0x00400588
170 #define NV10_PGRAPH_WDIMX_TEXTURE 0x0040058C
171 #define NV04_PGRAPH_COMBINE_0_ALPHA 0x00400590
172 #define NV04_PGRAPH_COMBINE_0_COLOR 0x00400594
173 #define NV04_PGRAPH_COMBINE_1_ALPHA 0x00400598
174 #define NV04_PGRAPH_COMBINE_1_COLOR 0x0040059C
175 #define NV04_PGRAPH_FORMAT_0 0x004005A8
176 #define NV04_PGRAPH_FORMAT_1 0x004005AC
177 #define NV04_PGRAPH_FILTER_0 0x004005B0
178 #define NV04_PGRAPH_FILTER_1 0x004005B4
179 #define NV03_PGRAPH_MONO_COLOR0 0x00400600
180 #define NV04_PGRAPH_ROP3 0x00400604
181 #define NV04_PGRAPH_BETA_AND 0x00400608
182 #define NV04_PGRAPH_BETA_PREMULT 0x0040060C
183 #define NV04_PGRAPH_LIMIT_VIOL_PIX 0x00400610
184 #define NV04_PGRAPH_FORMATS 0x00400618
185 #define NV10_PGRAPH_DEBUG_2 0x00400620
186 #define NV04_PGRAPH_BOFFSET0 0x00400640
187 #define NV04_PGRAPH_BOFFSET1 0x00400644
188 #define NV04_PGRAPH_BOFFSET2 0x00400648
189 #define NV04_PGRAPH_BOFFSET3 0x0040064C
190 #define NV04_PGRAPH_BOFFSET4 0x00400650
191 #define NV04_PGRAPH_BOFFSET5 0x00400654
192 #define NV04_PGRAPH_BBASE0 0x00400658
193 #define NV04_PGRAPH_BBASE1 0x0040065C
194 #define NV04_PGRAPH_BBASE2 0x00400660
195 #define NV04_PGRAPH_BBASE3 0x00400664
196 #define NV04_PGRAPH_BBASE4 0x00400668
197 #define NV04_PGRAPH_BBASE5 0x0040066C
198 #define NV04_PGRAPH_BPITCH0 0x00400670
199 #define NV04_PGRAPH_BPITCH1 0x00400674
200 #define NV04_PGRAPH_BPITCH2 0x00400678
201 #define NV04_PGRAPH_BPITCH3 0x0040067C
202 #define NV04_PGRAPH_BPITCH4 0x00400680
203 #define NV04_PGRAPH_BLIMIT0 0x00400684
204 #define NV04_PGRAPH_BLIMIT1 0x00400688
205 #define NV04_PGRAPH_BLIMIT2 0x0040068C
206 #define NV04_PGRAPH_BLIMIT3 0x00400690
207 #define NV04_PGRAPH_BLIMIT4 0x00400694
208 #define NV04_PGRAPH_BLIMIT5 0x00400698
209 #define NV04_PGRAPH_BSWIZZLE2 0x0040069C
210 #define NV04_PGRAPH_BSWIZZLE5 0x004006A0
211 #define NV04_PGRAPH_SURFACE 0x0040070C
212 #define NV04_PGRAPH_STATE 0x00400710
213 #define NV10_PGRAPH_SURFACE 0x00400710
214 #define NV04_PGRAPH_NOTIFY 0x00400714
215 #define NV10_PGRAPH_STATE 0x00400714
216 #define NV10_PGRAPH_NOTIFY 0x00400718
218 #define NV04_PGRAPH_FIFO 0x00400720
220 #define NV04_PGRAPH_BPIXEL 0x00400724
221 #define NV10_PGRAPH_RDI_INDEX 0x00400750
222 #define NV04_PGRAPH_FFINTFC_ST2 0x00400754
223 #define NV10_PGRAPH_RDI_DATA 0x00400754
224 #define NV04_PGRAPH_DMA_PITCH 0x00400760
225 #define NV10_PGRAPH_FFINTFC_ST2 0x00400764
226 #define NV04_PGRAPH_DVD_COLORFMT 0x00400764
227 #define NV04_PGRAPH_SCALED_FORMAT 0x00400768
228 #define NV10_PGRAPH_DMA_PITCH 0x00400770
229 #define NV10_PGRAPH_DVD_COLORFMT 0x00400774
230 #define NV10_PGRAPH_SCALED_FORMAT 0x00400778
231 #define NV10_PGRAPH_CHANNEL_CTX_TABLE 0x00400780
232 #define NV10_PGRAPH_CHANNEL_CTX_SIZE 0x00400784
233 #define NV10_PGRAPH_CHANNEL_CTX_POINTER 0x00400788
234 #define NV04_PGRAPH_PATT_COLOR0 0x00400800
235 #define NV04_PGRAPH_PATT_COLOR1 0x00400804
236 #define NV04_PGRAPH_PATTERN 0x00400808
237 #define NV04_PGRAPH_PATTERN_SHAPE 0x00400810
238 #define NV04_PGRAPH_CHROMA 0x00400814
239 #define NV04_PGRAPH_CONTROL0 0x00400818
240 #define NV04_PGRAPH_CONTROL1 0x0040081C
241 #define NV04_PGRAPH_CONTROL2 0x00400820
242 #define NV04_PGRAPH_BLEND 0x00400824
243 #define NV04_PGRAPH_STORED_FMT 0x00400830
244 #define NV04_PGRAPH_PATT_COLORRAM 0x00400900
245 #define NV40_PGRAPH_TILE0(i) 0x00400900
246 #define NV40_PGRAPH_TLIMIT0(i) 0x00400904
247 #define NV40_PGRAPH_TSIZE0(i) 0x00400908
248 #define NV40_PGRAPH_TSTATUS0(i) 0x0040090C
249 #define NV10_PGRAPH_TILE(i) (0x00400B00 + (i*16))
250 #define NV10_PGRAPH_TLIMIT(i) (0x00400B04 + (i*16))
251 #define NV10_PGRAPH_TSIZE(i) (0x00400B08 + (i*16))
252 #define NV10_PGRAPH_TSTATUS(i) (0x00400B0C + (i*16))
253 #define NV04_PGRAPH_U_RAM 0x00400D00
254 #define NV47_PGRAPH_TILE0(i) 0x00400D00
255 #define NV47_PGRAPH_TLIMIT0(i) 0x00400D04
256 #define NV47_PGRAPH_TSIZE0(i) 0x00400D08
257 #define NV47_PGRAPH_TSTATUS0(i) 0x00400D0C
258 #define NV04_PGRAPH_V_RAM 0x00400D40
259 #define NV04_PGRAPH_W_RAM 0x00400D80
260 #define NV10_PGRAPH_WINDOWCLIP_HORIZONTAL 0x00400F00
261 #define NV10_PGRAPH_WINDOWCLIP_VERTICAL 0x00400F20
262 #define NV10_PGRAPH_XFMODE0 0x00400F40
263 #define NV10_PGRAPH_XFMODE1 0x00400F44
264 #define NV10_PGRAPH_GLOBALSTATE0 0x00400F48
265 #define NV10_PGRAPH_GLOBALSTATE1 0x00400F4C
266 #define NV10_PGRAPH_PIPE_ADDRESS 0x00400F50
267 #define NV10_PGRAPH_PIPE_DATA 0x00400F54
268 #define NV04_PGRAPH_DMA_START_0 0x00401000
269 #define NV04_PGRAPH_DMA_START_1 0x00401004
270 #define NV04_PGRAPH_DMA_LENGTH 0x00401008
271 #define NV04_PGRAPH_DMA_MISC 0x0040100C
272 #define NV04_PGRAPH_DMA_DATA_0 0x00401020
273 #define NV04_PGRAPH_DMA_DATA_1 0x00401024
274 #define NV04_PGRAPH_DMA_RM 0x00401030
275 #define NV04_PGRAPH_DMA_A_XLATE_INST 0x00401040
276 #define NV04_PGRAPH_DMA_A_CONTROL 0x00401044
277 #define NV04_PGRAPH_DMA_A_LIMIT 0x00401048
278 #define NV04_PGRAPH_DMA_A_TLB_PTE 0x0040104C
279 #define NV04_PGRAPH_DMA_A_TLB_TAG 0x00401050
280 #define NV04_PGRAPH_DMA_A_ADJ_OFFSET 0x00401054
281 #define NV04_PGRAPH_DMA_A_OFFSET 0x00401058
282 #define NV04_PGRAPH_DMA_A_SIZE 0x0040105C
283 #define NV04_PGRAPH_DMA_A_Y_SIZE 0x00401060
284 #define NV04_PGRAPH_DMA_B_XLATE_INST 0x00401080
285 #define NV04_PGRAPH_DMA_B_CONTROL 0x00401084
286 #define NV04_PGRAPH_DMA_B_LIMIT 0x00401088
287 #define NV04_PGRAPH_DMA_B_TLB_PTE 0x0040108C
288 #define NV04_PGRAPH_DMA_B_TLB_TAG 0x00401090
289 #define NV04_PGRAPH_DMA_B_ADJ_OFFSET 0x00401094
290 #define NV04_PGRAPH_DMA_B_OFFSET 0x00401098
291 #define NV04_PGRAPH_DMA_B_SIZE 0x0040109C
292 #define NV04_PGRAPH_DMA_B_Y_SIZE 0x004010A0
293 #define NV40_PGRAPH_TILE1(i) 0x00406900
294 #define NV40_PGRAPH_TLIMIT1(i) 0x00406904
295 #define NV40_PGRAPH_TSIZE1(i) 0x00406908
296 #define NV40_PGRAPH_TSTATUS1(i) 0x0040690C
299 /* It's a guess that this works on NV03. Confirmed on NV04, though */
300 #define NV04_PFIFO_DELAY_0 0x00002040
301 #define NV04_PFIFO_DMA_TIMESLICE 0x00002044
302 #define NV04_PFIFO_NEXT_CHANNEL 0x00002050
303 #define NV03_PFIFO_INTR_0 0x00002100
304 #define NV03_PFIFO_INTR_EN_0 0x00002140
305 # define NV_PFIFO_INTR_CACHE_ERROR (1<< 0)
306 # define NV_PFIFO_INTR_RUNOUT (1<< 4)
307 # define NV_PFIFO_INTR_RUNOUT_OVERFLOW (1<< 8)
308 # define NV_PFIFO_INTR_DMA_PUSHER (1<<12)
309 # define NV_PFIFO_INTR_DMA_PT (1<<16)
310 # define NV_PFIFO_INTR_SEMAPHORE (1<<20)
311 # define NV_PFIFO_INTR_ACQUIRE_TIMEOUT (1<<24)
312 #define NV03_PFIFO_RAMHT 0x00002210
313 #define NV03_PFIFO_RAMFC 0x00002214
314 #define NV03_PFIFO_RAMRO 0x00002218
315 #define NV40_PFIFO_RAMFC 0x00002220
316 #define NV03_PFIFO_CACHES 0x00002500
317 #define NV04_PFIFO_MODE 0x00002504
318 #define NV04_PFIFO_DMA 0x00002508
319 #define NV04_PFIFO_SIZE 0x0000250c
320 #define NV03_PFIFO_CACHE0_PUSH0 0x00003000
321 #define NV03_PFIFO_CACHE0_PULL0 0x00003040
322 #define NV04_PFIFO_CACHE0_PULL0 0x00003050
323 #define NV04_PFIFO_CACHE0_PULL1 0x00003054
324 #define NV03_PFIFO_CACHE1_PUSH0 0x00003200
325 #define NV03_PFIFO_CACHE1_PUSH1 0x00003204
326 #define NV04_PFIFO_CACHE1_DMA_PUSH 0x00003220
327 #define NV04_PFIFO_CACHE1_DMA_FETCH 0x00003224
328 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_8_BYTES 0x00000000
329 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_16_BYTES 0x00000008
330 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_24_BYTES 0x00000010
331 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_32_BYTES 0x00000018
332 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_40_BYTES 0x00000020
333 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_48_BYTES 0x00000028
334 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_56_BYTES 0x00000030
335 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_64_BYTES 0x00000038
336 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_72_BYTES 0x00000040
337 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_80_BYTES 0x00000048
338 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_88_BYTES 0x00000050
339 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_96_BYTES 0x00000058
340 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_104_BYTES 0x00000060
341 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES 0x00000068
342 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_120_BYTES 0x00000070
343 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES 0x00000078
344 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_136_BYTES 0x00000080
345 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_144_BYTES 0x00000088
346 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_152_BYTES 0x00000090
347 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_160_BYTES 0x00000098
348 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_168_BYTES 0x000000A0
349 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_176_BYTES 0x000000A8
350 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_184_BYTES 0x000000B0
351 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_192_BYTES 0x000000B8
352 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_200_BYTES 0x000000C0
353 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_208_BYTES 0x000000C8
354 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_216_BYTES 0x000000D0
355 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_224_BYTES 0x000000D8
356 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_232_BYTES 0x000000E0
357 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_240_BYTES 0x000000E8
358 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_248_BYTES 0x000000F0
359 # define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_256_BYTES 0x000000F8
360 # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE 0x0000E000
361 # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_32_BYTES 0x00000000
362 # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_64_BYTES 0x00002000
363 # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_96_BYTES 0x00004000
364 # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES 0x00006000
365 # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_160_BYTES 0x00008000
366 # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_192_BYTES 0x0000A000
367 # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_224_BYTES 0x0000C000
368 # define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_256_BYTES 0x0000E000
369 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS 0x001F0000
370 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_0 0x00000000
371 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_1 0x00010000
372 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_2 0x00020000
373 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_3 0x00030000
374 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 0x00040000
375 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_5 0x00050000
376 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_6 0x00060000
377 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_7 0x00070000
378 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 0x00080000
379 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_9 0x00090000
380 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_10 0x000A0000
381 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_11 0x000B0000
382 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_12 0x000C0000
383 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_13 0x000D0000
384 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_14 0x000E0000
385 # define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_15 0x000F0000
386 # define NV_PFIFO_CACHE1_ENDIAN 0x80000000
387 # define NV_PFIFO_CACHE1_LITTLE_ENDIAN 0x7FFFFFFF
388 # define NV_PFIFO_CACHE1_BIG_ENDIAN 0x80000000
389 #define NV04_PFIFO_CACHE1_DMA_STATE 0x00003228
390 #define NV04_PFIFO_CACHE1_DMA_INSTANCE 0x0000322c
391 #define NV04_PFIFO_CACHE1_DMA_CTL 0x00003230
392 #define NV04_PFIFO_CACHE1_DMA_PUT 0x00003240
393 #define NV04_PFIFO_CACHE1_DMA_GET 0x00003244
394 #define NV10_PFIFO_CACHE1_REF_CNT 0x00003248
395 #define NV10_PFIFO_CACHE1_DMA_SUBROUTINE 0x0000324C
396 #define NV03_PFIFO_CACHE1_PULL0 0x00003240
397 #define NV04_PFIFO_CACHE1_PULL0 0x00003250
398 #define NV03_PFIFO_CACHE1_PULL1 0x00003250
399 #define NV04_PFIFO_CACHE1_PULL1 0x00003254
400 #define NV04_PFIFO_CACHE1_HASH 0x00003258
401 #define NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT 0x00003260
402 #define NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP 0x00003264
403 #define NV10_PFIFO_CACHE1_ACQUIRE_VALUE 0x00003268
404 #define NV10_PFIFO_CACHE1_SEMAPHORE 0x0000326C
405 #define NV03_PFIFO_CACHE1_GET 0x00003270
406 #define NV04_PFIFO_CACHE1_ENGINE 0x00003280
407 #define NV04_PFIFO_CACHE1_DMA_DCOUNT 0x000032A0
408 #define NV40_PFIFO_GRCTX_INSTANCE 0x000032E0
409 #define NV40_PFIFO_UNK32E4 0x000032E4
410 #define NV04_PFIFO_CACHE1_METHOD(i) (0x00003800+(i*8))
411 #define NV04_PFIFO_CACHE1_DATA(i) (0x00003804+(i*8))
412 #define NV40_PFIFO_CACHE1_METHOD(i) (0x00090000+(i*8))
413 #define NV40_PFIFO_CACHE1_DATA(i) (0x00090004+(i*8))
415 #define NV_CRTC0_INTSTAT 0x00600100
416 #define NV_CRTC0_INTEN 0x00600140
417 #define NV_CRTC1_INTSTAT 0x00602100
418 #define NV_CRTC1_INTEN 0x00602140
419 # define NV_CRTC_INTR_VBLANK (1<<0)
421 /* Fifo commands. These are not regs, neither masks */
422 #define NV03_FIFO_CMD_JUMP 0x20000000
423 #define NV03_FIFO_CMD_JUMP_OFFSET_MASK 0x1ffffffc
424 #define NV03_FIFO_CMD_REWIND (NV03_FIFO_CMD_JUMP | (0 & NV03_FIFO_CMD_JUMP_OFFSET_MASK))
427 #define NV04_RAMFC_DMA_PUT 0x00
428 #define NV04_RAMFC_DMA_GET 0x04
429 #define NV04_RAMFC_DMA_INSTANCE 0x08
430 #define NV04_RAMFC_DMA_STATE 0x0C
431 #define NV04_RAMFC_DMA_FETCH 0x10
432 #define NV04_RAMFC_ENGINE 0x14
433 #define NV04_RAMFC_PULL1_ENGINE 0x18
435 #define NV10_RAMFC_DMA_PUT 0x00
436 #define NV10_RAMFC_DMA_GET 0x04
437 #define NV10_RAMFC_REF_CNT 0x08
438 #define NV10_RAMFC_DMA_INSTANCE 0x0C
439 #define NV10_RAMFC_DMA_STATE 0x10
440 #define NV10_RAMFC_DMA_FETCH 0x14
441 #define NV10_RAMFC_ENGINE 0x18
442 #define NV10_RAMFC_PULL1_ENGINE 0x1C
443 #define NV10_RAMFC_ACQUIRE_VALUE 0x20
444 #define NV10_RAMFC_ACQUIRE_TIMESTAMP 0x24
445 #define NV10_RAMFC_ACQUIRE_TIMEOUT 0x28
446 #define NV10_RAMFC_SEMAPHORE 0x2C
447 #define NV10_RAMFC_DMA_SUBROUTINE 0x30
449 #define NV40_RAMFC_DMA_PUT 0x00
450 #define NV40_RAMFC_DMA_GET 0x04
451 #define NV40_RAMFC_REF_CNT 0x08
452 #define NV40_RAMFC_DMA_INSTANCE 0x0C
453 #define NV40_RAMFC_DMA_DCOUNT /* ? */ 0x10
454 #define NV40_RAMFC_DMA_STATE 0x14
455 #define NV40_RAMFC_DMA_FETCH 0x18
456 #define NV40_RAMFC_ENGINE 0x1C
457 #define NV40_RAMFC_PULL1_ENGINE 0x20
458 #define NV40_RAMFC_ACQUIRE_VALUE 0x24
459 #define NV40_RAMFC_ACQUIRE_TIMESTAMP 0x28
460 #define NV40_RAMFC_ACQUIRE_TIMEOUT 0x2C
461 #define NV40_RAMFC_SEMAPHORE 0x30
462 #define NV40_RAMFC_DMA_SUBROUTINE 0x34
463 #define NV40_RAMFC_GRCTX_INSTANCE /* guess */ 0x38
464 #define NV40_RAMFC_DMA_TIMESLICE 0x3C
465 #define NV40_RAMFC_UNK_40 0x40
466 #define NV40_RAMFC_UNK_44 0x44
467 #define NV40_RAMFC_UNK_48 0x48
468 #define NV40_RAMFC_UNK_4C 0x4C
469 #define NV40_RAMFC_UNK_50 0x50