shared-core/nouveau_reg.h

   1
   2
   3 #define NV03_BOOT_0                                        0x00100000
   4 #    define NV03_BOOT_0_RAM_AMOUNT                         0x00000003
   5 #    define NV03_BOOT_0_RAM_AMOUNT_8MB                     0x00000000
   6 #    define NV03_BOOT_0_RAM_AMOUNT_2MB                     0x00000001
   7 #    define NV03_BOOT_0_RAM_AMOUNT_4MB                     0x00000002
   8 #    define NV03_BOOT_0_RAM_AMOUNT_8MB_SDRAM               0x00000003
   9 #    define NV04_BOOT_0_RAM_AMOUNT_32MB                    0x00000000
  10 #    define NV04_BOOT_0_RAM_AMOUNT_4MB                     0x00000001
  11 #    define NV04_BOOT_0_RAM_AMOUNT_8MB                     0x00000002
  12 #    define NV04_BOOT_0_RAM_AMOUNT_16MB                    0x00000003
  13
  14 #define NV04_FIFO_DATA                                     0x0010020c
  15 #    define NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK              0xfff00000
  16 #    define NV10_FIFO_DATA_RAM_AMOUNT_MB_SHIFT             20
  17
  18 #define NV_RAMIN                                           0x00700000
  19
  20 #define NV_RAMHT_HANDLE_OFFSET                             0
  21 #define NV_RAMHT_CONTEXT_OFFSET                            4
  22 #    define NV_RAMHT_CONTEXT_VALID                         (1<<31)
  23 #    define NV_RAMHT_CONTEXT_CHANNEL_SHIFT                 24
  24 #    define NV_RAMHT_CONTEXT_ENGINE_SHIFT                  16
  25 #        define NV_RAMHT_CONTEXT_ENGINE_SOFTWARE           0
  26 #        define NV_RAMHT_CONTEXT_ENGINE_GRAPHICS           1
  27 #    define NV_RAMHT_CONTEXT_INSTANCE_SHIFT                0
  28 #    define NV40_RAMHT_CONTEXT_CHANNEL_SHIFT               23
  29 #    define NV40_RAMHT_CONTEXT_ENGINE_SHIFT                20
  30 #    define NV40_RAMHT_CONTEXT_INSTANCE_SHIFT              0
  31
  32 /* DMA object defines */
  33 #define NV_DMA_ACCESS_RW 0
  34 #define NV_DMA_ACCESS_RO 1
  35 #define NV_DMA_ACCESS_WO 2
  36 #define NV_DMA_TARGET_VIDMEM 0
  37 #define NV_DMA_TARGET_PCI    2
  38 #define NV_DMA_TARGET_AGP    3
  39 /*The following is not a real value used by nvidia cards, it's changed by nouveau_object_dma_create*/
  40 #define NV_DMA_TARGET_PCI_NONLINEAR   8
  41
  42 /* Some object classes we care about in the drm */
  43 #define NV_CLASS_DMA_FROM_MEMORY                           0x00000002
  44 #define NV_CLASS_DMA_TO_MEMORY                             0x00000003
  45 #define NV_CLASS_NULL                                      0x00000030
  46 #define NV_CLASS_DMA_IN_MEMORY                             0x0000003D
  47
  48 #define NV03_USER(i)                             (0x00800000+(i*NV03_USER_SIZE))
  49 #define NV03_USER__SIZE                                                       16
  50 #define NV10_USER__SIZE                                                       32
  51 #define NV03_USER_SIZE                                                0x00010000
  52 #define NV03_USER_DMA_PUT(i)                     (0x00800040+(i*NV03_USER_SIZE))
  53 #define NV03_USER_DMA_PUT__SIZE                                               16
  54 #define NV10_USER_DMA_PUT__SIZE                                               32
  55 #define NV03_USER_DMA_GET(i)                     (0x00800044+(i*NV03_USER_SIZE))
  56 #define NV03_USER_DMA_GET__SIZE                                               16
  57 #define NV10_USER_DMA_GET__SIZE                                               32
  58 #define NV03_USER_REF_CNT(i)                     (0x00800048+(i*NV03_USER_SIZE))
  59 #define NV03_USER_REF_CNT__SIZE                                               16
  60 #define NV10_USER_REF_CNT__SIZE                                               32
  61
  62 #define NV40_USER(i)                             (0x00c00000+(i*NV40_USER_SIZE))
  63 #define NV40_USER_SIZE                                                0x00001000
  64 #define NV40_USER_DMA_PUT(i)                     (0x00c00040+(i*NV40_USER_SIZE))
  65 #define NV40_USER_DMA_PUT__SIZE                                               32
  66 #define NV40_USER_DMA_GET(i)                     (0x00c00044+(i*NV40_USER_SIZE))
  67 #define NV40_USER_DMA_GET__SIZE                                               32
  68 #define NV40_USER_REF_CNT(i)                     (0x00c00048+(i*NV40_USER_SIZE))
  69 #define NV40_USER_REF_CNT__SIZE                                               32
  70
  71 #define NV50_USER(i)                             (0x00c00000+(i*NV50_USER_SIZE))
  72 #define NV50_USER_SIZE                                                0x00002000
  73 #define NV50_USER_DMA_PUT(i)                     (0x00c00040+(i*NV50_USER_SIZE))
  74 #define NV50_USER_DMA_PUT__SIZE                                              128
  75 #define NV50_USER_DMA_GET(i)                     (0x00c00044+(i*NV50_USER_SIZE))
  76 #define NV50_USER_DMA_GET__SIZE                                              128
  77 /*XXX: I don't think this actually exists.. */
  78 #define NV50_USER_REF_CNT(i)                     (0x00c00048+(i*NV50_USER_SIZE))
  79 #define NV50_USER_REF_CNT__SIZE                                              128
  80
  81 #define NV03_FIFO_SIZE                                     0x8000UL
  82
  83 #define NV03_PMC_BOOT_0                                    0x00000000
  84 #define NV03_PMC_BOOT_1                                    0x00000004
  85 #define NV03_PMC_INTR_0                                    0x00000100
  86 #    define NV_PMC_INTR_0_PFIFO_PENDING                       (1<< 8)
  87 #    define NV_PMC_INTR_0_PGRAPH_PENDING                      (1<<12)
  88 #    define NV_PMC_INTR_0_NV50_I2C_PENDING                  (1<<21)
  89 #    define NV_PMC_INTR_0_CRTC0_PENDING                       (1<<24)
  90 #    define NV_PMC_INTR_0_CRTC1_PENDING                       (1<<25)
  91 #    define NV_PMC_INTR_0_NV50_DISPLAY_PENDING           (1<<26)
  92 #    define NV_PMC_INTR_0_CRTCn_PENDING                       (3<<24)
  93 #define NV03_PMC_INTR_EN_0                                 0x00000140
  94 #    define NV_PMC_INTR_EN_0_MASTER_ENABLE                    (1<< 0)
  95 #define NV03_PMC_ENABLE                                    0x00000200
  96 #    define NV_PMC_ENABLE_PFIFO                               (1<< 8)
  97 #    define NV_PMC_ENABLE_PGRAPH                              (1<<12)
  98 /* Disabling the below bit breaks newer (G7X only?) mobile chipsets,
  99  * the card will hang early on in the X init process.
 100  */
 101 #    define NV_PMC_ENABLE_UNK13                               (1<<13)
 102 #define NV40_PMC_1700                                      0x00001700
 103 #define NV40_PMC_1704                                      0x00001704
 104 #define NV40_PMC_1708                                      0x00001708
 105 #define NV40_PMC_170C                                      0x0000170C
 106
 107 /* probably PMC ? */
 108 #define NV50_PUNK_BAR0_PRAMIN                              0x00001700
 109 #define NV50_PUNK_BAR_CFG_BASE                             0x00001704
 110 #define NV50_PUNK_BAR_CFG_BASE_VALID                          (1<<30)
 111 #define NV50_PUNK_BAR1_CTXDMA                              0x00001708
 112 #define NV50_PUNK_BAR1_CTXDMA_VALID                           (1<<31)
 113 #define NV50_PUNK_BAR3_CTXDMA                              0x0000170C
 114 #define NV50_PUNK_BAR3_CTXDMA_VALID                           (1<<31)
 115 #define NV50_PUNK_UNK1710                                  0x00001710
 116
 117 #define NV04_PBUS_PCI_NV_1                                 0x00001804
 118 #define NV04_PBUS_PCI_NV_19                                0x0000184C
 119 #define NV04_PBUS_PCI_NV_20                             0x00001850
 120 #       define NV04_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED          (0 << 0)
 121 #       define NV04_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED           (1 << 0)
 122
 123 #define NV04_PTIMER_INTR_0                                 0x00009100
 124 #define NV04_PTIMER_INTR_EN_0                              0x00009140
 125 #define NV04_PTIMER_NUMERATOR                              0x00009200
 126 #define NV04_PTIMER_DENOMINATOR                            0x00009210
 127 #define NV04_PTIMER_TIME_0                                 0x00009400
 128 #define NV04_PTIMER_TIME_1                                 0x00009410
 129 #define NV04_PTIMER_ALARM_0                                0x00009420
 130
 131 #define NV50_I2C_CONTROLLER                           0x0000E054
 132
 133 #define NV04_PFB_CFG0                                      0x00100200
 134 #define NV04_PFB_CFG1                                      0x00100204
 135 #define NV40_PFB_020C                                      0x0010020C
 136 #define NV10_PFB_TILE(i)                                   (0x00100240 + (i*16))
 137 #define NV10_PFB_TILE__SIZE                                8
 138 #define NV10_PFB_TLIMIT(i)                                 (0x00100244 + (i*16))
 139 #define NV10_PFB_TSIZE(i)                                  (0x00100248 + (i*16))
 140 #define NV10_PFB_TSTATUS(i)                                (0x0010024C + (i*16))
 141 #define NV10_PFB_CLOSE_PAGE2                               0x0010033C
 142 #define NV40_PFB_TILE(i)                                   (0x00100600 + (i*16))
 143 #define NV40_PFB_TILE__SIZE_0                              12
 144 #define NV40_PFB_TILE__SIZE_1                              15
 145 #define NV40_PFB_TLIMIT(i)                                 (0x00100604 + (i*16))
 146 #define NV40_PFB_TSIZE(i)                                  (0x00100608 + (i*16))
 147 #define NV40_PFB_TSTATUS(i)                                (0x0010060C + (i*16))
 148 #define NV40_PFB_UNK_800                                        0x00100800
 149
 150 #define NV04_PGRAPH_DEBUG_0                                0x00400080
 151 #define NV04_PGRAPH_DEBUG_1                                0x00400084
 152 #define NV04_PGRAPH_DEBUG_2                                0x00400088
 153 #define NV04_PGRAPH_DEBUG_3                                0x0040008c
 154 #define NV10_PGRAPH_DEBUG_4                                0x00400090
 155 #define NV03_PGRAPH_INTR                                   0x00400100
 156 #define NV03_PGRAPH_NSTATUS                                0x00400104
 157 #    define NV04_PGRAPH_NSTATUS_STATE_IN_USE                  (1<<11)
 158 #    define NV04_PGRAPH_NSTATUS_INVALID_STATE                 (1<<12)
 159 #    define NV04_PGRAPH_NSTATUS_BAD_ARGUMENT                  (1<<13)
 160 #    define NV04_PGRAPH_NSTATUS_PROTECTION_FAULT              (1<<14)
 161 #    define NV10_PGRAPH_NSTATUS_STATE_IN_USE                  (1<<23)
 162 #    define NV10_PGRAPH_NSTATUS_INVALID_STATE                 (1<<24)
 163 #    define NV10_PGRAPH_NSTATUS_BAD_ARGUMENT                  (1<<25)
 164 #    define NV10_PGRAPH_NSTATUS_PROTECTION_FAULT              (1<<26)
 165 #define NV03_PGRAPH_NSOURCE                                0x00400108
 166 #    define NV03_PGRAPH_NSOURCE_NOTIFICATION                  (1<< 0)
 167 #    define NV03_PGRAPH_NSOURCE_DATA_ERROR                    (1<< 1)
 168 #    define NV03_PGRAPH_NSOURCE_PROTECTION_ERROR              (1<< 2)
 169 #    define NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION               (1<< 3)
 170 #    define NV03_PGRAPH_NSOURCE_LIMIT_COLOR                   (1<< 4)
 171 #    define NV03_PGRAPH_NSOURCE_LIMIT_ZETA                    (1<< 5)
 172 #    define NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD                  (1<< 6)
 173 #    define NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION              (1<< 7)
 174 #    define NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION              (1<< 8)
 175 #    define NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION              (1<< 9)
 176 #    define NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION               (1<<10)
 177 #    define NV03_PGRAPH_NSOURCE_STATE_INVALID                 (1<<11)
 178 #    define NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY                 (1<<12)
 179 #    define NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE                 (1<<13)
 180 #    define NV03_PGRAPH_NSOURCE_METHOD_CNT                    (1<<14)
 181 #    define NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION              (1<<15)
 182 #    define NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION            (1<<16)
 183 #    define NV03_PGRAPH_NSOURCE_DMA_WIDTH_A                   (1<<17)
 184 #    define NV03_PGRAPH_NSOURCE_DMA_WIDTH_B                   (1<<18)
 185 #define NV03_PGRAPH_INTR_EN                                0x00400140
 186 #define NV40_PGRAPH_INTR_EN                                0x0040013C
 187 #    define NV_PGRAPH_INTR_NOTIFY                             (1<< 0)
 188 #    define NV_PGRAPH_INTR_MISSING_HW                         (1<< 4)
 189 #    define NV_PGRAPH_INTR_CONTEXT_SWITCH                     (1<<12)
 190 #    define NV_PGRAPH_INTR_BUFFER_NOTIFY                      (1<<16)
 191 #    define NV_PGRAPH_INTR_ERROR                              (1<<20)
 192 #define NV10_PGRAPH_CTX_CONTROL                            0x00400144
 193 #define NV10_PGRAPH_CTX_USER                               0x00400148
 194 #define NV10_PGRAPH_CTX_SWITCH1                            0x0040014C
 195 #define NV10_PGRAPH_CTX_SWITCH2                            0x00400150
 196 #define NV10_PGRAPH_CTX_SWITCH3                            0x00400154
 197 #define NV10_PGRAPH_CTX_SWITCH4                            0x00400158
 198 #define NV10_PGRAPH_CTX_SWITCH5                            0x0040015C
 199 #define NV04_PGRAPH_CTX_SWITCH1                            0x00400160
 200 #define NV10_PGRAPH_CTX_CACHE1                             0x00400160
 201 #define NV04_PGRAPH_CTX_SWITCH2                            0x00400164
 202 #define NV04_PGRAPH_CTX_SWITCH3                            0x00400168
 203 #define NV04_PGRAPH_CTX_SWITCH4                            0x0040016C
 204 #define NV04_PGRAPH_CTX_CONTROL                            0x00400170
 205 #define NV04_PGRAPH_CTX_USER                               0x00400174
 206 #define NV04_PGRAPH_CTX_CACHE1                             0x00400180
 207 #define NV10_PGRAPH_CTX_CACHE2                             0x00400180
 208 #define NV03_PGRAPH_CTX_CONTROL                            0x00400190
 209 #define NV03_PGRAPH_CTX_USER                               0x00400194
 210 #define NV04_PGRAPH_CTX_CACHE2                             0x004001A0
 211 #define NV10_PGRAPH_CTX_CACHE3                             0x004001A0
 212 #define NV04_PGRAPH_CTX_CACHE3                             0x004001C0
 213 #define NV10_PGRAPH_CTX_CACHE4                             0x004001C0
 214 #define NV04_PGRAPH_CTX_CACHE4                             0x004001E0
 215 #define NV10_PGRAPH_CTX_CACHE5                             0x004001E0
 216 #define NV40_PGRAPH_CTXCTL_0304                            0x00400304
 217 #define NV40_PGRAPH_CTXCTL_0304_XFER_CTX                   0x00000001
 218 #define NV40_PGRAPH_CTXCTL_UCODE_STAT                      0x00400308
 219 #define NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_MASK              0xff000000
 220 #define NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_SHIFT                     24
 221 #define NV40_PGRAPH_CTXCTL_UCODE_STAT_OP_MASK              0x00ffffff
 222 #define NV40_PGRAPH_CTXCTL_0310                            0x00400310
 223 #define NV40_PGRAPH_CTXCTL_0310_XFER_SAVE                  0x00000020
 224 #define NV40_PGRAPH_CTXCTL_0310_XFER_LOAD                  0x00000040
 225 #define NV40_PGRAPH_CTXCTL_030C                            0x0040030c
 226 #define NV40_PGRAPH_CTXCTL_UCODE_INDEX                     0x00400324
 227 #define NV40_PGRAPH_CTXCTL_UCODE_DATA                      0x00400328
 228 #define NV40_PGRAPH_CTXCTL_CUR                             0x0040032c
 229 #define NV40_PGRAPH_CTXCTL_CUR_LOADED                      0x01000000
 230 #define NV40_PGRAPH_CTXCTL_CUR_INST_MASK                   0x000FFFFF
 231 #define NV03_PGRAPH_ABS_X_RAM                              0x00400400
 232 #define NV03_PGRAPH_ABS_Y_RAM                              0x00400480
 233 #define NV03_PGRAPH_X_MISC                                 0x00400500
 234 #define NV03_PGRAPH_Y_MISC                                 0x00400504
 235 #define NV04_PGRAPH_VALID1                                 0x00400508
 236 #define NV04_PGRAPH_SOURCE_COLOR                           0x0040050C
 237 #define NV04_PGRAPH_MISC24_0                               0x00400510
 238 #define NV03_PGRAPH_XY_LOGIC_MISC0                         0x00400514
 239 #define NV03_PGRAPH_XY_LOGIC_MISC1                         0x00400518
 240 #define NV03_PGRAPH_XY_LOGIC_MISC2                         0x0040051C
 241 #define NV03_PGRAPH_XY_LOGIC_MISC3                         0x00400520
 242 #define NV03_PGRAPH_CLIPX_0                                0x00400524
 243 #define NV03_PGRAPH_CLIPX_1                                0x00400528
 244 #define NV03_PGRAPH_CLIPY_0                                0x0040052C
 245 #define NV03_PGRAPH_CLIPY_1                                0x00400530
 246 #define NV03_PGRAPH_ABS_ICLIP_XMAX                         0x00400534
 247 #define NV03_PGRAPH_ABS_ICLIP_YMAX                         0x00400538
 248 #define NV03_PGRAPH_ABS_UCLIP_XMIN                         0x0040053C
 249 #define NV03_PGRAPH_ABS_UCLIP_YMIN                         0x00400540
 250 #define NV03_PGRAPH_ABS_UCLIP_XMAX                         0x00400544
 251 #define NV03_PGRAPH_ABS_UCLIP_YMAX                         0x00400548
 252 #define NV03_PGRAPH_ABS_UCLIPA_XMIN                        0x00400560
 253 #define NV03_PGRAPH_ABS_UCLIPA_YMIN                        0x00400564
 254 #define NV03_PGRAPH_ABS_UCLIPA_XMAX                        0x00400568
 255 #define NV03_PGRAPH_ABS_UCLIPA_YMAX                        0x0040056C
 256 #define NV04_PGRAPH_MISC24_1                               0x00400570
 257 #define NV04_PGRAPH_MISC24_2                               0x00400574
 258 #define NV04_PGRAPH_VALID2                                 0x00400578
 259 #define NV04_PGRAPH_PASSTHRU_0                             0x0040057C
 260 #define NV04_PGRAPH_PASSTHRU_1                             0x00400580
 261 #define NV04_PGRAPH_PASSTHRU_2                             0x00400584
 262 #define NV10_PGRAPH_DIMX_TEXTURE                           0x00400588
 263 #define NV10_PGRAPH_WDIMX_TEXTURE                          0x0040058C
 264 #define NV04_PGRAPH_COMBINE_0_ALPHA                        0x00400590
 265 #define NV04_PGRAPH_COMBINE_0_COLOR                        0x00400594
 266 #define NV04_PGRAPH_COMBINE_1_ALPHA                        0x00400598
 267 #define NV04_PGRAPH_COMBINE_1_COLOR                        0x0040059C
 268 #define NV04_PGRAPH_FORMAT_0                               0x004005A8
 269 #define NV04_PGRAPH_FORMAT_1                               0x004005AC
 270 #define NV04_PGRAPH_FILTER_0                               0x004005B0
 271 #define NV04_PGRAPH_FILTER_1                               0x004005B4
 272 #define NV03_PGRAPH_MONO_COLOR0                            0x00400600
 273 #define NV04_PGRAPH_ROP3                                   0x00400604
 274 #define NV04_PGRAPH_BETA_AND                               0x00400608
 275 #define NV04_PGRAPH_BETA_PREMULT                           0x0040060C
 276 #define NV04_PGRAPH_LIMIT_VIOL_PIX                         0x00400610
 277 #define NV04_PGRAPH_FORMATS                                0x00400618
 278 #define NV10_PGRAPH_DEBUG_2                                0x00400620
 279 #define NV04_PGRAPH_BOFFSET0                               0x00400640
 280 #define NV04_PGRAPH_BOFFSET1                               0x00400644
 281 #define NV04_PGRAPH_BOFFSET2                               0x00400648
 282 #define NV04_PGRAPH_BOFFSET3                               0x0040064C
 283 #define NV04_PGRAPH_BOFFSET4                               0x00400650
 284 #define NV04_PGRAPH_BOFFSET5                               0x00400654
 285 #define NV04_PGRAPH_BBASE0                                 0x00400658
 286 #define NV04_PGRAPH_BBASE1                                 0x0040065C
 287 #define NV04_PGRAPH_BBASE2                                 0x00400660
 288 #define NV04_PGRAPH_BBASE3                                 0x00400664
 289 #define NV04_PGRAPH_BBASE4                                 0x00400668
 290 #define NV04_PGRAPH_BBASE5                                 0x0040066C
 291 #define NV04_PGRAPH_BPITCH0                                0x00400670
 292 #define NV04_PGRAPH_BPITCH1                                0x00400674
 293 #define NV04_PGRAPH_BPITCH2                                0x00400678
 294 #define NV04_PGRAPH_BPITCH3                                0x0040067C
 295 #define NV04_PGRAPH_BPITCH4                                0x00400680
 296 #define NV04_PGRAPH_BLIMIT0                                0x00400684
 297 #define NV04_PGRAPH_BLIMIT1                                0x00400688
 298 #define NV04_PGRAPH_BLIMIT2                                0x0040068C
 299 #define NV04_PGRAPH_BLIMIT3                                0x00400690
 300 #define NV04_PGRAPH_BLIMIT4                                0x00400694
 301 #define NV04_PGRAPH_BLIMIT5                                0x00400698
 302 #define NV04_PGRAPH_BSWIZZLE2                              0x0040069C
 303 #define NV04_PGRAPH_BSWIZZLE5                              0x004006A0
 304 #define NV03_PGRAPH_STATUS                                 0x004006B0
 305 #define NV04_PGRAPH_STATUS                                 0x00400700
 306 #define NV04_PGRAPH_TRAPPED_ADDR                           0x00400704
 307 #define NV04_PGRAPH_TRAPPED_DATA                           0x00400708
 308 #define NV04_PGRAPH_SURFACE                                0x0040070C
 309 #define NV10_PGRAPH_TRAPPED_DATA_HIGH                      0x0040070C
 310 #define NV04_PGRAPH_STATE                                  0x00400710
 311 #define NV10_PGRAPH_SURFACE                                0x00400710
 312 #define NV04_PGRAPH_NOTIFY                                 0x00400714
 313 #define NV10_PGRAPH_STATE                                  0x00400714
 314 #define NV10_PGRAPH_NOTIFY                                 0x00400718
 315
 316 #define NV04_PGRAPH_FIFO                                   0x00400720
 317
 318 #define NV04_PGRAPH_BPIXEL                                 0x00400724
 319 #define NV10_PGRAPH_RDI_INDEX                              0x00400750
 320 #define NV04_PGRAPH_FFINTFC_ST2                            0x00400754
 321 #define NV10_PGRAPH_RDI_DATA                               0x00400754
 322 #define NV04_PGRAPH_DMA_PITCH                              0x00400760
 323 #define NV10_PGRAPH_FFINTFC_ST2                            0x00400764
 324 #define NV04_PGRAPH_DVD_COLORFMT                           0x00400764
 325 #define NV04_PGRAPH_SCALED_FORMAT                          0x00400768
 326 #define NV10_PGRAPH_DMA_PITCH                              0x00400770
 327 #define NV10_PGRAPH_DVD_COLORFMT                           0x00400774
 328 #define NV10_PGRAPH_SCALED_FORMAT                          0x00400778
 329 #define NV20_PGRAPH_CHANNEL_CTX_TABLE                      0x00400780
 330 #define NV20_PGRAPH_CHANNEL_CTX_POINTER                    0x00400784
 331 #define NV20_PGRAPH_CHANNEL_CTX_XFER                       0x00400788
 332 #define NV20_PGRAPH_CHANNEL_CTX_XFER_LOAD                  0x00000001
 333 #define NV20_PGRAPH_CHANNEL_CTX_XFER_SAVE                  0x00000002
 334 #define NV04_PGRAPH_PATT_COLOR0                            0x00400800
 335 #define NV04_PGRAPH_PATT_COLOR1                            0x00400804
 336 #define NV04_PGRAPH_PATTERN                                0x00400808
 337 #define NV04_PGRAPH_PATTERN_SHAPE                          0x00400810
 338 #define NV04_PGRAPH_CHROMA                                 0x00400814
 339 #define NV04_PGRAPH_CONTROL0                               0x00400818
 340 #define NV04_PGRAPH_CONTROL1                               0x0040081C
 341 #define NV04_PGRAPH_CONTROL2                               0x00400820
 342 #define NV04_PGRAPH_BLEND                                  0x00400824
 343 #define NV04_PGRAPH_STORED_FMT                             0x00400830
 344 #define NV04_PGRAPH_PATT_COLORRAM                          0x00400900
 345 #define NV40_PGRAPH_TILE0(i)                               (0x00400900 + (i*16))
 346 #define NV40_PGRAPH_TLIMIT0(i)                             (0x00400904 + (i*16))
 347 #define NV40_PGRAPH_TSIZE0(i)                              (0x00400908 + (i*16))
 348 #define NV40_PGRAPH_TSTATUS0(i)                            (0x0040090C + (i*16))
 349 #define NV10_PGRAPH_TILE(i)                                (0x00400B00 + (i*16))
 350 #define NV10_PGRAPH_TLIMIT(i)                              (0x00400B04 + (i*16))
 351 #define NV10_PGRAPH_TSIZE(i)                               (0x00400B08 + (i*16))
 352 #define NV10_PGRAPH_TSTATUS(i)                             (0x00400B0C + (i*16))
 353 #define NV04_PGRAPH_U_RAM                                  0x00400D00
 354 #define NV47_PGRAPH_TILE0(i)                               (0x00400D00 + (i*16))
 355 #define NV47_PGRAPH_TLIMIT0(i)                             (0x00400D04 + (i*16))
 356 #define NV47_PGRAPH_TSIZE0(i)                              (0x00400D08 + (i*16))
 357 #define NV47_PGRAPH_TSTATUS0(i)                            (0x00400D0C + (i*16))
 358 #define NV04_PGRAPH_V_RAM                                  0x00400D40
 359 #define NV04_PGRAPH_W_RAM                                  0x00400D80
 360 #define NV10_PGRAPH_COMBINER0_IN_ALPHA                     0x00400E40
 361 #define NV10_PGRAPH_COMBINER1_IN_ALPHA                     0x00400E44
 362 #define NV10_PGRAPH_COMBINER0_IN_RGB                       0x00400E48
 363 #define NV10_PGRAPH_COMBINER1_IN_RGB                       0x00400E4C
 364 #define NV10_PGRAPH_COMBINER_COLOR0                        0x00400E50
 365 #define NV10_PGRAPH_COMBINER_COLOR1                        0x00400E54
 366 #define NV10_PGRAPH_COMBINER0_OUT_ALPHA                    0x00400E58
 367 #define NV10_PGRAPH_COMBINER1_OUT_ALPHA                    0x00400E5C
 368 #define NV10_PGRAPH_COMBINER0_OUT_RGB                      0x00400E60
 369 #define NV10_PGRAPH_COMBINER1_OUT_RGB                      0x00400E64
 370 #define NV10_PGRAPH_COMBINER_FINAL0                        0x00400E68
 371 #define NV10_PGRAPH_COMBINER_FINAL1                        0x00400E6C
 372 #define NV10_PGRAPH_WINDOWCLIP_HORIZONTAL                  0x00400F00
 373 #define NV10_PGRAPH_WINDOWCLIP_VERTICAL                    0x00400F20
 374 #define NV10_PGRAPH_XFMODE0                                0x00400F40
 375 #define NV10_PGRAPH_XFMODE1                                0x00400F44
 376 #define NV10_PGRAPH_GLOBALSTATE0                           0x00400F48
 377 #define NV10_PGRAPH_GLOBALSTATE1                           0x00400F4C
 378 #define NV10_PGRAPH_PIPE_ADDRESS                           0x00400F50
 379 #define NV10_PGRAPH_PIPE_DATA                              0x00400F54
 380 #define NV04_PGRAPH_DMA_START_0                            0x00401000
 381 #define NV04_PGRAPH_DMA_START_1                            0x00401004
 382 #define NV04_PGRAPH_DMA_LENGTH                             0x00401008
 383 #define NV04_PGRAPH_DMA_MISC                               0x0040100C
 384 #define NV04_PGRAPH_DMA_DATA_0                             0x00401020
 385 #define NV04_PGRAPH_DMA_DATA_1                             0x00401024
 386 #define NV04_PGRAPH_DMA_RM                                 0x00401030
 387 #define NV04_PGRAPH_DMA_A_XLATE_INST                       0x00401040
 388 #define NV04_PGRAPH_DMA_A_CONTROL                          0x00401044
 389 #define NV04_PGRAPH_DMA_A_LIMIT                            0x00401048
 390 #define NV04_PGRAPH_DMA_A_TLB_PTE                          0x0040104C
 391 #define NV04_PGRAPH_DMA_A_TLB_TAG                          0x00401050
 392 #define NV04_PGRAPH_DMA_A_ADJ_OFFSET                       0x00401054
 393 #define NV04_PGRAPH_DMA_A_OFFSET                           0x00401058
 394 #define NV04_PGRAPH_DMA_A_SIZE                             0x0040105C
 395 #define NV04_PGRAPH_DMA_A_Y_SIZE                           0x00401060
 396 #define NV04_PGRAPH_DMA_B_XLATE_INST                       0x00401080
 397 #define NV04_PGRAPH_DMA_B_CONTROL                          0x00401084
 398 #define NV04_PGRAPH_DMA_B_LIMIT                            0x00401088
 399 #define NV04_PGRAPH_DMA_B_TLB_PTE                          0x0040108C
 400 #define NV04_PGRAPH_DMA_B_TLB_TAG                          0x00401090
 401 #define NV04_PGRAPH_DMA_B_ADJ_OFFSET                       0x00401094
 402 #define NV04_PGRAPH_DMA_B_OFFSET                           0x00401098
 403 #define NV04_PGRAPH_DMA_B_SIZE                             0x0040109C
 404 #define NV04_PGRAPH_DMA_B_Y_SIZE                           0x004010A0
 405 #define NV40_PGRAPH_TILE1(i)                               (0x00406900 + (i*16))
 406 #define NV40_PGRAPH_TLIMIT1(i)                             (0x00406904 + (i*16))
 407 #define NV40_PGRAPH_TSIZE1(i)                              (0x00406908 + (i*16))
 408 #define NV40_PGRAPH_TSTATUS1(i)                            (0x0040690C + (i*16))
 409
 410
 411 /* It's a guess that this works on NV03. Confirmed on NV04, though */
 412 #define NV04_PFIFO_DELAY_0                                 0x00002040
 413 #define NV04_PFIFO_DMA_TIMESLICE                           0x00002044
 414 #define NV04_PFIFO_NEXT_CHANNEL                            0x00002050
 415 #define NV03_PFIFO_INTR_0                                  0x00002100
 416 #define NV03_PFIFO_INTR_EN_0                               0x00002140
 417 #    define NV_PFIFO_INTR_CACHE_ERROR                         (1<< 0)
 418 #    define NV_PFIFO_INTR_RUNOUT                              (1<< 4)
 419 #    define NV_PFIFO_INTR_RUNOUT_OVERFLOW                     (1<< 8)
 420 #    define NV_PFIFO_INTR_DMA_PUSHER                          (1<<12)
 421 #    define NV_PFIFO_INTR_DMA_PT                              (1<<16)
 422 #    define NV_PFIFO_INTR_SEMAPHORE                           (1<<20)
 423 #    define NV_PFIFO_INTR_ACQUIRE_TIMEOUT                     (1<<24)
 424 #define NV03_PFIFO_RAMHT                                   0x00002210
 425 #define NV03_PFIFO_RAMFC                                   0x00002214
 426 #define NV03_PFIFO_RAMRO                                   0x00002218
 427 #define NV40_PFIFO_RAMFC                                   0x00002220
 428 #define NV03_PFIFO_CACHES                                  0x00002500
 429 #define NV04_PFIFO_MODE                                    0x00002504
 430 #define NV04_PFIFO_DMA                                     0x00002508
 431 #define NV04_PFIFO_SIZE                                    0x0000250c
 432 #define NV50_PFIFO_CTX_TABLE(c)                        (0x2600+(c)*4)
 433 #define NV50_PFIFO_CTX_TABLE__SIZE                                128
 434 #define NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED                  (1<<31)
 435 #define NV50_PFIFO_CTX_TABLE_UNK30_BAD                        (1<<30)
 436 #define NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G80             0x0FFFFFFF
 437 #define NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G84             0x00FFFFFF
 438 #define NV03_PFIFO_CACHE0_PUSH0                            0x00003000
 439 #define NV03_PFIFO_CACHE0_PULL0                            0x00003040
 440 #define NV04_PFIFO_CACHE0_PULL0                            0x00003050
 441 #define NV04_PFIFO_CACHE0_PULL1                            0x00003054
 442 #define NV03_PFIFO_CACHE1_PUSH0                            0x00003200
 443 #define NV03_PFIFO_CACHE1_PUSH1                            0x00003204
 444 #define NV03_PFIFO_CACHE1_PUSH1_DMA                            (1<<8)
 445 #define NV40_PFIFO_CACHE1_PUSH1_DMA                           (1<<16)
 446 #define NV03_PFIFO_CACHE1_PUSH1_CHID_MASK                  0x0000000f
 447 #define NV10_PFIFO_CACHE1_PUSH1_CHID_MASK                  0x0000001f
 448 #define NV50_PFIFO_CACHE1_PUSH1_CHID_MASK                  0x0000007f
 449 #define NV03_PFIFO_CACHE1_PUT                              0x00003210
 450 #define NV04_PFIFO_CACHE1_DMA_PUSH                         0x00003220
 451 #define NV04_PFIFO_CACHE1_DMA_FETCH                        0x00003224
 452 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_8_BYTES         0x00000000
 453 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_16_BYTES        0x00000008
 454 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_24_BYTES        0x00000010
 455 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_32_BYTES        0x00000018
 456 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_40_BYTES        0x00000020
 457 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_48_BYTES        0x00000028
 458 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_56_BYTES        0x00000030
 459 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_64_BYTES        0x00000038
 460 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_72_BYTES        0x00000040
 461 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_80_BYTES        0x00000048
 462 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_88_BYTES        0x00000050
 463 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_96_BYTES        0x00000058
 464 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_104_BYTES       0x00000060
 465 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES       0x00000068
 466 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_120_BYTES       0x00000070
 467 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES       0x00000078
 468 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_136_BYTES       0x00000080
 469 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_144_BYTES       0x00000088
 470 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_152_BYTES       0x00000090
 471 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_160_BYTES       0x00000098
 472 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_168_BYTES       0x000000A0
 473 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_176_BYTES       0x000000A8
 474 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_184_BYTES       0x000000B0
 475 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_192_BYTES       0x000000B8
 476 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_200_BYTES       0x000000C0
 477 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_208_BYTES       0x000000C8
 478 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_216_BYTES       0x000000D0
 479 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_224_BYTES       0x000000D8
 480 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_232_BYTES       0x000000E0
 481 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_240_BYTES       0x000000E8
 482 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_248_BYTES       0x000000F0
 483 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_256_BYTES       0x000000F8
 484 #    define NV_PFIFO_CACHE1_DMA_FETCH_SIZE                 0x0000E000
 485 #    define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_32_BYTES        0x00000000
 486 #    define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_64_BYTES        0x00002000
 487 #    define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_96_BYTES        0x00004000
 488 #    define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES       0x00006000
 489 #    define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_160_BYTES       0x00008000
 490 #    define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_192_BYTES       0x0000A000
 491 #    define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_224_BYTES       0x0000C000
 492 #    define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_256_BYTES       0x0000E000
 493 #    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS             0x001F0000
 494 #    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_0           0x00000000
 495 #    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_1           0x00010000
 496 #    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_2           0x00020000
 497 #    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_3           0x00030000
 498 #    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4           0x00040000
 499 #    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_5           0x00050000
 500 #    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_6           0x00060000
 501 #    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_7           0x00070000
 502 #    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8           0x00080000
 503 #    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_9           0x00090000
 504 #    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_10          0x000A0000
 505 #    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_11          0x000B0000
 506 #    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_12          0x000C0000
 507 #    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_13          0x000D0000
 508 #    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_14          0x000E0000
 509 #    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_15          0x000F0000
 510 #    define NV_PFIFO_CACHE1_ENDIAN                         0x80000000
 511 #    define NV_PFIFO_CACHE1_LITTLE_ENDIAN                  0x7FFFFFFF
 512 #    define NV_PFIFO_CACHE1_BIG_ENDIAN                     0x80000000
 513 #define NV04_PFIFO_CACHE1_DMA_STATE                        0x00003228
 514 #define NV04_PFIFO_CACHE1_DMA_INSTANCE                     0x0000322c
 515 #define NV04_PFIFO_CACHE1_DMA_CTL                          0x00003230
 516 #define NV04_PFIFO_CACHE1_DMA_PUT                          0x00003240
 517 #define NV04_PFIFO_CACHE1_DMA_GET                          0x00003244
 518 #define NV10_PFIFO_CACHE1_REF_CNT                          0x00003248
 519 #define NV10_PFIFO_CACHE1_DMA_SUBROUTINE                   0x0000324C
 520 #define NV03_PFIFO_CACHE1_PULL0                            0x00003240
 521 #define NV04_PFIFO_CACHE1_PULL0                            0x00003250
 522 #define NV03_PFIFO_CACHE1_PULL1                            0x00003250
 523 #define NV04_PFIFO_CACHE1_PULL1                            0x00003254
 524 #define NV04_PFIFO_CACHE1_HASH                             0x00003258
 525 #define NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT                  0x00003260
 526 #define NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP                0x00003264
 527 #define NV10_PFIFO_CACHE1_ACQUIRE_VALUE                    0x00003268
 528 #define NV10_PFIFO_CACHE1_SEMAPHORE                        0x0000326C
 529 #define NV03_PFIFO_CACHE1_GET                              0x00003270
 530 #define NV04_PFIFO_CACHE1_ENGINE                           0x00003280
 531 #define NV04_PFIFO_CACHE1_DMA_DCOUNT                       0x000032A0
 532 #define NV40_PFIFO_GRCTX_INSTANCE                          0x000032E0
 533 #define NV40_PFIFO_UNK32E4                                 0x000032E4
 534 #define NV04_PFIFO_CACHE1_METHOD(i)                (0x00003800+(i*8))
 535 #define NV04_PFIFO_CACHE1_DATA(i)                  (0x00003804+(i*8))
 536 #define NV40_PFIFO_CACHE1_METHOD(i)                (0x00090000+(i*8))
 537 #define NV40_PFIFO_CACHE1_DATA(i)                  (0x00090004+(i*8))
 538
 539 #define NV_CRTC0_INTSTAT                                   0x00600100
 540 #define NV_CRTC0_INTEN                                     0x00600140
 541 #define NV_CRTC1_INTSTAT                                   0x00602100
 542 #define NV_CRTC1_INTEN                                     0x00602140
 543 #    define NV_CRTC_INTR_VBLANK                                (1<<0)
 544
 545 /* This name is a partial guess. */
 546 #define NV50_DISPLAY_SUPERVISOR                     0x00610024
 547
 548 #define NV04_PRAMIN                                             0x00700000
 549
 550 /* Fifo commands. These are not regs, neither masks */
 551 #define NV03_FIFO_CMD_JUMP                                 0x20000000
 552 #define NV03_FIFO_CMD_JUMP_OFFSET_MASK                     0x1ffffffc
 553 #define NV03_FIFO_CMD_REWIND                               (NV03_FIFO_CMD_JUMP | (0 & NV03_FIFO_CMD_JUMP_OFFSET_MASK))
 554
 555 /* RAMFC offsets */
 556 #define NV04_RAMFC_DMA_PUT                                       0x00
 557 #define NV04_RAMFC_DMA_GET                                       0x04
 558 #define NV04_RAMFC_DMA_INSTANCE                                  0x08
 559 #define NV04_RAMFC_DMA_STATE                                     0x0C
 560 #define NV04_RAMFC_DMA_FETCH                                     0x10
 561 #define NV04_RAMFC_ENGINE                                        0x14
 562 #define NV04_RAMFC_PULL1_ENGINE                                  0x18
 563
 564 #define NV10_RAMFC_DMA_PUT                                       0x00
 565 #define NV10_RAMFC_DMA_GET                                       0x04
 566 #define NV10_RAMFC_REF_CNT                                       0x08
 567 #define NV10_RAMFC_DMA_INSTANCE                                  0x0C
 568 #define NV10_RAMFC_DMA_STATE                                     0x10
 569 #define NV10_RAMFC_DMA_FETCH                                     0x14
 570 #define NV10_RAMFC_ENGINE                                        0x18
 571 #define NV10_RAMFC_PULL1_ENGINE                                  0x1C
 572 #define NV10_RAMFC_ACQUIRE_VALUE                                 0x20
 573 #define NV10_RAMFC_ACQUIRE_TIMESTAMP                             0x24
 574 #define NV10_RAMFC_ACQUIRE_TIMEOUT                               0x28
 575 #define NV10_RAMFC_SEMAPHORE                                     0x2C
 576 #define NV10_RAMFC_DMA_SUBROUTINE                                0x30
 577
 578 #define NV40_RAMFC_DMA_PUT                                       0x00
 579 #define NV40_RAMFC_DMA_GET                                       0x04
 580 #define NV40_RAMFC_REF_CNT                                       0x08
 581 #define NV40_RAMFC_DMA_INSTANCE                                  0x0C
 582 #define NV40_RAMFC_DMA_DCOUNT /* ? */                            0x10
 583 #define NV40_RAMFC_DMA_STATE                                     0x14
 584 #define NV40_RAMFC_DMA_FETCH                                     0x18
 585 #define NV40_RAMFC_ENGINE                                        0x1C
 586 #define NV40_RAMFC_PULL1_ENGINE                                  0x20
 587 #define NV40_RAMFC_ACQUIRE_VALUE                                 0x24
 588 #define NV40_RAMFC_ACQUIRE_TIMESTAMP                             0x28
 589 #define NV40_RAMFC_ACQUIRE_TIMEOUT                               0x2C
 590 #define NV40_RAMFC_SEMAPHORE                                     0x30
 591 #define NV40_RAMFC_DMA_SUBROUTINE                                0x34
 592 #define NV40_RAMFC_GRCTX_INSTANCE /* guess */                    0x38
 593 #define NV40_RAMFC_DMA_TIMESLICE                                 0x3C
 594 #define NV40_RAMFC_UNK_40                                        0x40
 595 #define NV40_RAMFC_UNK_44                                        0x44
 596 #define NV40_RAMFC_UNK_48                                        0x48
 597 #define NV40_RAMFC_UNK_4C                                        0x4C
 598 #define NV40_RAMFC_UNK_50                                        0x50
 599
 600 /* This is a partial import from rules-ng, a few things may be duplicated.
 601  * Eventually we should completely import everything from rules-ng.
 602  * For the moment check rules-ng for docs.
 603   */
 604
 605 #define NV50_PMC                                            0x00000000
 606 #define NV50_PMC__LEN                                              0x1
 607 #define NV50_PMC__ESIZE                                         0x2000
 608 #    define NV50_PMC_BOOT_0                                 0x00000000
 609 #        define NV50_PMC_BOOT_0_REVISION                    0x000000ff
 610 #        define NV50_PMC_BOOT_0_REVISION__SHIFT                      0
 611 #        define NV50_PMC_BOOT_0_ARCH                        0x0ff00000
 612 #        define NV50_PMC_BOOT_0_ARCH__SHIFT                         20
 613 #    define NV50_PMC_INTR_0                                 0x00000100
 614 #        define NV50_PMC_INTR_0_PFIFO                           (1<<8)
 615 #        define NV50_PMC_INTR_0_PGRAPH                         (1<<12)
 616 #        define NV50_PMC_INTR_0_PTIMER                         (1<<20)
 617 #        define NV50_PMC_INTR_0_HOTPLUG                        (1<<21)
 618 #        define NV50_PMC_INTR_0_DISPLAY                        (1<<26)
 619 #    define NV50_PMC_INTR_EN_0                              0x00000140
 620 #        define NV50_PMC_INTR_EN_0_MASTER                       (1<<0)
 621 #            define NV50_PMC_INTR_EN_0_MASTER_DISABLED          (0<<0)
 622 #            define NV50_PMC_INTR_EN_0_MASTER_ENABLED           (1<<0)
 623 #    define NV50_PMC_ENABLE                                 0x00000200
 624 #        define NV50_PMC_ENABLE_PFIFO                           (1<<8)
 625 #        define NV50_PMC_ENABLE_PGRAPH                         (1<<12)
 626
 627 #define NV50_PCONNECTOR                                     0x0000e000
 628 #define NV50_PCONNECTOR__LEN                                       0x1
 629 #define NV50_PCONNECTOR__ESIZE                                  0x1000
 630 #    define NV50_PCONNECTOR_HOTPLUG_INTR                    0x0000e050
 631 #        define NV50_PCONNECTOR_HOTPLUG_INTR_PLUG_I2C0          (1<<0)
 632 #        define NV50_PCONNECTOR_HOTPLUG_INTR_PLUG_I2C1          (1<<1)
 633 #        define NV50_PCONNECTOR_HOTPLUG_INTR_PLUG_I2C2          (1<<2)
 634 #        define NV50_PCONNECTOR_HOTPLUG_INTR_PLUG_I2C3          (1<<3)
 635 #        define NV50_PCONNECTOR_HOTPLUG_INTR_UNPLUG_I2C0       (1<<16)
 636 #        define NV50_PCONNECTOR_HOTPLUG_INTR_UNPLUG_I2C1       (1<<17)
 637 #        define NV50_PCONNECTOR_HOTPLUG_INTR_UNPLUG_I2C2       (1<<18)
 638 #        define NV50_PCONNECTOR_HOTPLUG_INTR_UNPLUG_I2C3       (1<<19)
 639 #    define NV50_PCONNECTOR_HOTPLUG_CTRL                    0x0000e054
 640 #        define NV50_PCONNECTOR_HOTPLUG_CTRL_PLUG_I2C0          (1<<0)
 641 #        define NV50_PCONNECTOR_HOTPLUG_CTRL_PLUG_I2C1          (1<<1)
 642 #        define NV50_PCONNECTOR_HOTPLUG_CTRL_PLUG_I2C2          (1<<2)
 643 #        define NV50_PCONNECTOR_HOTPLUG_CTRL_PLUG_I2C3          (1<<3)
 644 #        define NV50_PCONNECTOR_HOTPLUG_CTRL_UNPLUG_I2C0       (1<<16)
 645 #        define NV50_PCONNECTOR_HOTPLUG_CTRL_UNPLUG_I2C1       (1<<17)
 646 #        define NV50_PCONNECTOR_HOTPLUG_CTRL_UNPLUG_I2C2       (1<<18)
 647 #        define NV50_PCONNECTOR_HOTPLUG_CTRL_UNPLUG_I2C3       (1<<19)
 648 #    define NV50_PCONNECTOR_HOTPLUG_STATE                   0x0000e104
 649 #        define NV50_PCONNECTOR_HOTPLUG_STATE_PIN_CONNECTED_I2C0 (1<<2)
 650 #        define NV50_PCONNECTOR_HOTPLUG_STATE_PIN_CONNECTED_I2C1 (1<<6)
 651 #        define NV50_PCONNECTOR_HOTPLUG_STATE_PIN_CONNECTED_I2C2 (1<<10)
 652 #        define NV50_PCONNECTOR_HOTPLUG_STATE_PIN_CONNECTED_I2C3 (1<<14)
 653 #    define NV50_PCONNECTOR_I2C_PORT_0                      0x0000e138
 654 #    define NV50_PCONNECTOR_I2C_PORT_1                      0x0000e150
 655 #    define NV50_PCONNECTOR_I2C_PORT_2                      0x0000e168
 656 #    define NV50_PCONNECTOR_I2C_PORT_3                      0x0000e180
 657 #    define NV50_PCONNECTOR_I2C_PORT_4                      0x0000e240
 658 #    define NV50_PCONNECTOR_I2C_PORT_5                      0x0000e258
 659
 660 #define NV50_PBUS                                           0x00088000
 661 #define NV50_PBUS__LEN                                             0x1
 662 #define NV50_PBUS__ESIZE                                        0x1000
 663 #    define NV50_PBUS_PCI_ID                                0x00088000
 664 #        define NV50_PBUS_PCI_ID_VENDOR_ID                  0x0000ffff
 665 #        define NV50_PBUS_PCI_ID_VENDOR_ID__SHIFT                    0
 666 #        define NV50_PBUS_PCI_ID_DEVICE_ID                  0xffff0000
 667 #        define NV50_PBUS_PCI_ID_DEVICE_ID__SHIFT                   16
 668
 669 #define NV50_PFB                                            0x00100000
 670 #define NV50_PFB__LEN                                              0x1
 671 #define NV50_PFB__ESIZE                                         0x1000
 672
 673 #define NV50_PEXTDEV                                        0x00101000
 674 #define NV50_PEXTDEV__LEN                                          0x1
 675 #define NV50_PEXTDEV__ESIZE                                     0x1000
 676
 677 #define NV50_PROM                                           0x00300000
 678 #define NV50_PROM__LEN                                             0x1
 679 #define NV50_PROM__ESIZE                                       0x10000
 680
 681 #define NV50_PGRAPH                                         0x00400000
 682 #define NV50_PGRAPH__LEN                                           0x1
 683 #define NV50_PGRAPH__ESIZE                                     0x10000
 684
 685 #define NV50_PDISPLAY                                       0x00610000
 686 #define NV50_PDISPLAY__LEN                                         0x1
 687 #define NV50_PDISPLAY__ESIZE                                   0x10000
 688 #    define NV50_PDISPLAY_SUPERVISOR                        0x00610024
 689 #        define NV50_PDISPLAY_SUPERVISOR_CRTCn              0x0000000c
 690 #        define NV50_PDISPLAY_SUPERVISOR_CRTCn__SHIFT                2
 691 #        define NV50_PDISPLAY_SUPERVISOR_CRTC0                  (1<<2)
 692 #        define NV50_PDISPLAY_SUPERVISOR_CRTC1                  (1<<3)
 693 #        define NV50_PDISPLAY_SUPERVISOR_CLK_MASK           0x00000070
 694 #        define NV50_PDISPLAY_SUPERVISOR_CLK_MASK__SHIFT             4
 695 #        define NV50_PDISPLAY_SUPERVISOR_CLK_UPDATE             (1<<5)
 696 #    define NV50_PDISPLAY_SUPERVISOR_INTR                   0x0061002c
 697 #        define NV50_PDISPLAY_SUPERVISOR_INTR_VBLANK_CRTC0      (1<<2)
 698 #        define NV50_PDISPLAY_SUPERVISOR_INTR_VBLANK_CRTC1      (1<<3)
 699 #        define NV50_PDISPLAY_SUPERVISOR_INTR_UNK1              (1<<4)
 700 #        define NV50_PDISPLAY_SUPERVISOR_INTR_CLK_UPDATE        (1<<5)
 701 #        define NV50_PDISPLAY_SUPERVISOR_INTR_UNK4              (1<<6)
 702 #    define NV50_PDISPLAY_UNK30_CTRL                        0x00610030
 703 #        define NV50_PDISPLAY_UNK30_CTRL_UPDATE_VCLK0           (1<<9)
 704 #        define NV50_PDISPLAY_UNK30_CTRL_UPDATE_VCLK1          (1<<10)
 705 #        define NV50_PDISPLAY_UNK30_CTRL_PENDING               (1<<31)
 706 #    define NV50_PDISPLAY_UNK50_CTRL                        0x00610050
 707 #        define NV50_PDISPLAY_UNK50_CTRL_CRTC0_ACTIVE           (1<<1)
 708 #        define NV50_PDISPLAY_UNK50_CTRL_CRTC0_ACTIVE_MASK  0x00000003
 709 #        define NV50_PDISPLAY_UNK50_CTRL_CRTC0_ACTIVE_MASK__SHIFT    0
 710 #        define NV50_PDISPLAY_UNK50_CTRL_CRTC1_ACTIVE           (1<<9)
 711 #        define NV50_PDISPLAY_UNK50_CTRL_CRTC1_ACTIVE_MASK  0x00000300
 712 #        define NV50_PDISPLAY_UNK50_CTRL_CRTC1_ACTIVE_MASK__SHIFT    8
 713 #    define NV50_PDISPLAY_UNK200_CTRL                       0x00610200
 714 #    define NV50_PDISPLAY_CURSOR                            0x00610270
 715 #    define NV50_PDISPLAY_CURSOR__LEN                              0x2
 716 #    define NV50_PDISPLAY_CURSOR__ESIZE                           0x10
 717 #        define NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i) (0x00610270+(i)*0x10)
 718 #            define NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON        (1<<0)
 719 #            define NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_MASK 0x00030000
 720 #            define NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_MASK__SHIFT 16
 721 #            define NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE (1<<16)
 722
 723 #    define NV50_PDISPLAY_CTRL_STATE                        0x00610300
 724 #        define NV50_PDISPLAY_CTRL_STATE_ENABLE                 (1<<0)
 725 #        define NV50_PDISPLAY_CTRL_STATE_PENDING               (1<<31)
 726 #    define NV50_PDISPLAY_CTRL_VAL                          0x00610304
 727 #    define NV50_PDISPLAY_UNK_380                           0x00610380
 728 #    define NV50_PDISPLAY_RAM_AMOUNT                        0x00610384
 729 #    define NV50_PDISPLAY_UNK_388                           0x00610388
 730 #    define NV50_PDISPLAY_UNK_38C                           0x0061038c
 731 #    define NV50_PDISPLAY_CRTC_VAL                          0x00610a00
 732 #    define NV50_PDISPLAY_CRTC_VAL__LEN                            0x2
 733 #            define NV50_PDISPLAY_CRTC_VAL_UNK_900(i,j) (0x00610a18+(i)*0x540+(j)*0x4)
 734 #            define NV50_PDISPLAY_CRTC_VAL_CLUT_MODE(i,j) (0x00610a24+(i)*0x540+(j)*0x4)
 735 #            define NV50_PDISPLAY_CRTC_VAL_INTERLACE(i,j) (0x00610a48+(i)*0x540+(j)*0x4)
 736 #            define NV50_PDISPLAY_CRTC_VAL_SCALE_CTRL(i,j) (0x00610a50+(i)*0x540+(j)*0x4)
 737 #            define NV50_PDISPLAY_CRTC_VAL_CURSOR_CTRL(i,j) (0x00610a58+(i)*0x540+(j)*0x4)
 738 #            define NV50_PDISPLAY_CRTC_VAL_UNK_904(i,j) (0x00610ab8+(i)*0x540+(j)*0x4)
 739 #            define NV50_PDISPLAY_CRTC_VAL_DEPTH(i,j) (0x00610ac8+(i)*0x540+(j)*0x4)
 740 #            define NV50_PDISPLAY_CRTC_VAL_CLOCK(i,j) (0x00610ad0+(i)*0x540+(j)*0x4)
 741 #            define NV50_PDISPLAY_CRTC_VAL_COLOR_CTRL(i,j) (0x00610ae0+(i)*0x540+(j)*0x4)
 742 #            define NV50_PDISPLAY_CRTC_VAL_SYNC_START_TO_BLANK_END(i,j) (0x00610ae8+(i)*0x540+(j)*0x4)
 743 #            define NV50_PDISPLAY_CRTC_VAL_MODE_UNK1(i,j) (0x00610af0+(i)*0x540+(j)*0x4)
 744 #            define NV50_PDISPLAY_CRTC_VAL_DISPLAY_TOTAL(i,j) (0x00610af8+(i)*0x540+(j)*0x4)
 745 #            define NV50_PDISPLAY_CRTC_VAL_SYNC_DURATION(i,j) (0x00610b00+(i)*0x540+(j)*0x4)
 746 #            define NV50_PDISPLAY_CRTC_VAL_MODE_UNK2(i,j) (0x00610b08+(i)*0x540+(j)*0x4)
 747 #            define NV50_PDISPLAY_CRTC_VAL_UNK_828(i,j) (0x00610b10+(i)*0x540+(j)*0x4)
 748 #            define NV50_PDISPLAY_CRTC_VAL_FB_SIZE(i,j) (0x00610b18+(i)*0x540+(j)*0x4)
 749 #            define NV50_PDISPLAY_CRTC_VAL_FB_PITCH(i,j) (0x00610b20+(i)*0x540+(j)*0x4)
 750 #                define NV50_PDISPLAY_CRTC_VAL_FB_PITCH_LINEAR_FB (1<<20)
 751 #            define NV50_PDISPLAY_CRTC_VAL_FB_POS(i,j) (0x00610b28+(i)*0x540+(j)*0x4)
 752 #            define NV50_PDISPLAY_CRTC_VAL_SCALE_CENTER_OFFSET(i,j) (0x00610b38+(i)*0x540+(j)*0x4)
 753 #            define NV50_PDISPLAY_CRTC_VAL_REAL_RES(i,j) (0x00610b40+(i)*0x540+(j)*0x4)
 754 #            define NV50_PDISPLAY_CRTC_VAL_SCALE_RES1(i,j) (0x00610b48+(i)*0x540+(j)*0x4)
 755 #            define NV50_PDISPLAY_CRTC_VAL_SCALE_RES2(i,j) (0x00610b50+(i)*0x540+(j)*0x4)
 756
 757
 758 #            define NV50_PDISPLAY_DAC_VAL_MODE_CTRL(i,j) (0x00610b58+(i)*0x8+(j)*0x4)
 759
 760
 761 #            define NV50_PDISPLAY_SOR_VAL_MODE_CTRL(i,j) (0x00610b70+(i)*0x8+(j)*0x4)
 762
 763
 764 #            define NV50_PDISPLAY_DAC_VAL_MODE_CTRL2(i,j) (0x00610bdc+(i)*0x8+(j)*0x4)
 765
 766
 767 #    define NV50_PDISPLAY_CRTC_CLK                          0x00614000
 768 #    define NV50_PDISPLAY_CRTC_CLK__LEN                            0x2
 769 #        define NV50_PDISPLAY_CRTC_CLK_CLK_CTRL1(i) (0x00614100+(i)*0x800)
 770 #            define NV50_PDISPLAY_CRTC_CLK_CLK_CTRL1_CONNECTED 0x00000600
 771 #            define NV50_PDISPLAY_CRTC_CLK_CLK_CTRL1_CONNECTED__SHIFT 9
 772 #        define NV50_PDISPLAY_CRTC_CLK_VPLL_A(i) (0x00614104+(i)*0x800)
 773 #        define NV50_PDISPLAY_CRTC_CLK_VPLL_B(i) (0x00614108+(i)*0x800)
 774 #        define NV50_PDISPLAY_CRTC_CLK_CLK_CTRL2(i) (0x00614200+(i)*0x800)
 775
 776 #    define NV50_PDISPLAY_DAC_CLK                           0x00614000
 777 #    define NV50_PDISPLAY_DAC_CLK__LEN                             0x3
 778 #        define NV50_PDISPLAY_DAC_CLK_CLK_CTRL2(i) (0x00614280+(i)*0x800)
 779
 780 #    define NV50_PDISPLAY_SOR_CLK                           0x00614000
 781 #    define NV50_PDISPLAY_SOR_CLK__LEN                             0x3
 782 #        define NV50_PDISPLAY_SOR_CLK_CLK_CTRL2(i) (0x00614300+(i)*0x800)
 783
 784 #    define NV50_PDISPLAY_DAC_REGS                          0x0061a000
 785 #    define NV50_PDISPLAY_DAC_REGS__LEN                            0x3
 786 #    define NV50_PDISPLAY_DAC_REGS__ESIZE                        0x800
 787 #        define NV50_PDISPLAY_DAC_REGS_DPMS_CTRL(i) (0x0061a004+(i)*0x800)
 788 #            define NV50_PDISPLAY_DAC_REGS_DPMS_CTRL_HSYNC_OFF  (1<<0)
 789 #            define NV50_PDISPLAY_DAC_REGS_DPMS_CTRL_VSYNC_OFF  (1<<2)
 790 #            define NV50_PDISPLAY_DAC_REGS_DPMS_CTRL_BLANKED    (1<<4)
 791 #            define NV50_PDISPLAY_DAC_REGS_DPMS_CTRL_OFF        (1<<6)
 792 #            define NV50_PDISPLAY_DAC_REGS_DPMS_CTRL_PENDING   (1<<31)
 793 #        define NV50_PDISPLAY_DAC_REGS_LOAD_CTRL(i) (0x0061a00c+(i)*0x800)
 794 #            define NV50_PDISPLAY_DAC_REGS_LOAD_CTRL_ACTIVE    (1<<20)
 795 #            define NV50_PDISPLAY_DAC_REGS_LOAD_CTRL_PRESENT 0x38000000
 796 #            define NV50_PDISPLAY_DAC_REGS_LOAD_CTRL_PRESENT__SHIFT 29
 797 #            define NV50_PDISPLAY_DAC_REGS_LOAD_CTRL_DONE      (1<<31)
 798 #        define NV50_PDISPLAY_DAC_REGS_CLK_CTRL1(i) (0x0061a010+(i)*0x800)
 799 #            define NV50_PDISPLAY_DAC_REGS_CLK_CTRL1_CONNECTED 0x00000600
 800 #            define NV50_PDISPLAY_DAC_REGS_CLK_CTRL1_CONNECTED__SHIFT 9
 801
 802 #    define NV50_PDISPLAY_SOR_REGS                          0x0061c000
 803 #    define NV50_PDISPLAY_SOR_REGS__LEN                            0x2
 804 #    define NV50_PDISPLAY_SOR_REGS__ESIZE                        0x800
 805 #        define NV50_PDISPLAY_SOR_REGS_DPMS_CTRL(i) (0x0061c004+(i)*0x800)
 806 #            define NV50_PDISPLAY_SOR_REGS_DPMS_CTRL_ON         (1<<0)
 807 #            define NV50_PDISPLAY_SOR_REGS_DPMS_CTRL_PENDING   (1<<31)
 808 #        define NV50_PDISPLAY_SOR_REGS_CLK_CTRL1(i) (0x0061c008+(i)*0x800)
 809 #            define NV50_PDISPLAY_SOR_REGS_CLK_CTRL1_CONNECTED 0x00000600
 810 #            define NV50_PDISPLAY_SOR_REGS_CLK_CTRL1_CONNECTED__SHIFT 9
 811 #        define NV50_PDISPLAY_SOR_REGS_UNK_00C(i) (0x0061c00c+(i)*0x800)
 812 #        define NV50_PDISPLAY_SOR_REGS_UNK_010(i) (0x0061c010+(i)*0x800)
 813 #        define NV50_PDISPLAY_SOR_REGS_UNK_014(i) (0x0061c014+(i)*0x800)
 814 #        define NV50_PDISPLAY_SOR_REGS_UNK_018(i) (0x0061c018+(i)*0x800)
 815 #        define NV50_PDISPLAY_SOR_REGS_DPMS_STATE(i) (0x0061c030+(i)*0x800)
 816 #            define NV50_PDISPLAY_SOR_REGS_DPMS_STATE_ACTIVE 0x00030000
 817 #            define NV50_PDISPLAY_SOR_REGS_DPMS_STATE_ACTIVE__SHIFT 16
 818 #            define NV50_PDISPLAY_SOR_REGS_DPMS_STATE_BLANKED  (1<<19)
 819 #            define NV50_PDISPLAY_SOR_REGS_DPMS_STATE_WAIT     (1<<28)
 820
 821
 822 #define NV50_UNK640000                                      0x00640000
 823 #define NV50_UNK640000__LEN                                        0x6
 824 #define NV50_UNK640000__ESIZE                                   0x1000
 825 #    define NV50_UNK640000_UNK_000(i)          (0x00640000+(i)*0x1000)
 826
 827 #define NV50_HW_CURSOR                                      0x00647000
 828 #define NV50_HW_CURSOR__LEN                                        0x2
 829 #define NV50_HW_CURSOR__ESIZE                                   0x1000
 830 #    define NV50_HW_CURSOR_POS_CTRL(i)              (0x00647080+(i)*0x1000)
 831 #    define NV50_HW_CURSOR_POS(i)         (0x00647084+(i)*0x1000)