2 * Copyright 2005 Stephane Marchesin.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 #ifndef __NOUVEAU_DRV_H__
26 #define __NOUVEAU_DRV_H__
28 #define DRIVER_AUTHOR "Stephane Marchesin"
29 #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
31 #define DRIVER_NAME "nouveau"
32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33 #define DRIVER_DATE "20060213"
35 #define DRIVER_MAJOR 0
36 #define DRIVER_MINOR 0
37 #define DRIVER_PATCHLEVEL 9
39 #define NOUVEAU_FAMILY 0x0000FFFF
40 #define NOUVEAU_FLAGS 0xFFFF0000
42 #include "nouveau_drm.h"
43 #include "nouveau_reg.h"
46 struct mem_block *next;
47 struct mem_block *prev;
50 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
53 drm_handle_t map_handle;
57 NV_NFORCE =0x10000000,
58 NV_NFORCE2 =0x20000000
61 #define NVOBJ_ENGINE_SW 0
62 #define NVOBJ_ENGINE_GR 1
63 #define NVOBJ_ENGINE_INT 0xdeadbeef
65 #define NVOBJ_FLAG_ALLOW_NO_REFS (1 << 0)
66 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
67 #define NVOBJ_FLAG_ZERO_FREE (1 << 2)
68 #define NVOBJ_FLAG_FAKE (1 << 3)
69 struct nouveau_gpuobj {
70 struct nouveau_gpuobj *next;
71 struct nouveau_gpuobj *prev;
74 struct mem_block *im_pramin;
75 struct mem_block *im_backing;
85 struct nouveau_gpuobj_ref {
86 struct nouveau_gpuobj_ref *next;
88 struct nouveau_gpuobj *gpuobj;
95 struct nouveau_channel
97 struct drm_device *dev;
100 /* owner of this fifo */
101 struct drm_file *file_priv;
102 /* mapping of the fifo itself */
103 drm_local_map_t *map;
104 /* mapping of the regs controling the fifo */
105 drm_local_map_t *regs;
107 /* DMA push buffer */
108 struct nouveau_gpuobj_ref *pushbuf;
109 struct mem_block *pushbuf_mem;
110 uint32_t pushbuf_base;
112 /* Notifier memory */
113 struct mem_block *notifier_block;
114 struct mem_block *notifier_heap;
115 drm_local_map_t *notifier_map;
118 struct nouveau_gpuobj_ref *ramfc;
121 struct nouveau_gpuobj_ref *ramin_grctx;
122 uint32_t pgraph_ctx [340]; /* XXX dynamic alloc ? */
125 struct nouveau_gpuobj *vm_pd;
126 struct nouveau_gpuobj_ref *vm_gart_pt;
129 struct nouveau_gpuobj_ref *ramin; /* Private instmem */
130 struct mem_block *ramin_heap; /* Private PRAMIN heap */
131 struct nouveau_gpuobj_ref *ramht; /* Hash table */
132 struct nouveau_gpuobj_ref *ramht_refs; /* Objects referenced by RAMHT */
135 struct nouveau_config {
142 struct nouveau_instmem_engine {
145 int (*init)(struct drm_device *dev);
146 void (*takedown)(struct drm_device *dev);
148 int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
150 void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
151 int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
152 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
155 struct nouveau_mc_engine {
156 int (*init)(struct drm_device *dev);
157 void (*takedown)(struct drm_device *dev);
160 struct nouveau_timer_engine {
161 int (*init)(struct drm_device *dev);
162 void (*takedown)(struct drm_device *dev);
163 uint64_t (*read)(struct drm_device *dev);
166 struct nouveau_fb_engine {
167 int (*init)(struct drm_device *dev);
168 void (*takedown)(struct drm_device *dev);
171 struct nouveau_fifo_engine {
174 int (*init)(struct drm_device *);
175 void (*takedown)(struct drm_device *);
177 int (*create_context)(struct nouveau_channel *);
178 void (*destroy_context)(struct nouveau_channel *);
179 int (*load_context)(struct nouveau_channel *);
180 int (*save_context)(struct nouveau_channel *);
183 struct nouveau_pgraph_engine {
184 int (*init)(struct drm_device *);
185 void (*takedown)(struct drm_device *);
187 int (*create_context)(struct nouveau_channel *);
188 void (*destroy_context)(struct nouveau_channel *);
189 int (*load_context)(struct nouveau_channel *);
190 int (*save_context)(struct nouveau_channel *);
193 struct nouveau_engine {
194 struct nouveau_instmem_engine instmem;
195 struct nouveau_mc_engine mc;
196 struct nouveau_timer_engine timer;
197 struct nouveau_fb_engine fb;
198 struct nouveau_pgraph_engine graph;
199 struct nouveau_fifo_engine fifo;
202 struct drm_nouveau_private {
204 NOUVEAU_CARD_INIT_DOWN,
205 NOUVEAU_CARD_INIT_DONE,
206 NOUVEAU_CARD_INIT_FAILED
209 /* the card type, takes NV_* as values */
211 /* exact chipset, derived from NV_PMC_BOOT_0 */
215 drm_local_map_t *mmio;
217 drm_local_map_t *ramin; /* NV40 onwards */
219 int fifo_alloc_count;
220 struct nouveau_channel *fifos[NV_MAX_FIFO_NUMBER];
222 struct nouveau_engine Engine;
224 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
225 struct nouveau_gpuobj *ramht;
226 uint32_t ramin_rsvd_vram;
227 uint32_t ramht_offset;
230 uint32_t ramfc_offset;
232 uint32_t ramro_offset;
235 /* base physical adresses */
237 uint64_t fb_available_size;
241 NOUVEAU_GART_NONE = 0,
248 struct nouveau_gpuobj *sg_ctxdma;
249 struct page *sg_dummy_page;
250 dma_addr_t sg_dummy_bus;
253 struct drm_ttm_backend *sg_be;
254 unsigned long sg_handle;
257 /* the mtrr covering the FB */
260 struct mem_block *agp_heap;
261 struct mem_block *fb_heap;
262 struct mem_block *fb_nomap_heap;
263 struct mem_block *ramin_heap;
264 struct mem_block *pci_heap;
266 /* context table pointed to be NV_PGRAPH_CHANNEL_CTX_TABLE (0x400780) */
267 uint32_t ctx_table_size;
268 struct nouveau_gpuobj_ref *ctx_table;
270 struct nouveau_config config;
272 struct nouveau_gpuobj *gpuobj_all;
275 #define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id,cl,ch) do { \
276 struct drm_nouveau_private *nv = dev->dev_private; \
277 if (!nouveau_fifo_owner(dev, (cl), (id))) { \
278 DRM_ERROR("pid %d doesn't own channel %d\n", \
279 DRM_CURRENTPID, (id)); \
282 (ch) = nv->fifos[(id)]; \
285 /* nouveau_state.c */
286 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
287 extern int nouveau_load(struct drm_device *, unsigned long flags);
288 extern int nouveau_firstopen(struct drm_device *);
289 extern void nouveau_lastclose(struct drm_device *);
290 extern int nouveau_unload(struct drm_device *);
291 extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
293 extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
295 extern void nouveau_wait_for_idle(struct drm_device *);
296 extern int nouveau_ioctl_card_init(struct drm_device *, void *data,
300 extern int nouveau_mem_init_heap(struct mem_block **, uint64_t start,
302 extern struct mem_block *nouveau_mem_alloc_block(struct mem_block *,
303 uint64_t size, int align2,
305 extern void nouveau_mem_takedown(struct mem_block **heap);
306 extern void nouveau_mem_free_block(struct mem_block *);
307 extern uint64_t nouveau_mem_fb_amount(struct drm_device *);
308 extern void nouveau_mem_release(struct drm_file *, struct mem_block *heap);
309 extern int nouveau_ioctl_mem_alloc(struct drm_device *, void *data,
311 extern int nouveau_ioctl_mem_free(struct drm_device *, void *data,
313 extern struct mem_block* nouveau_mem_alloc(struct drm_device *,
314 int alignment, uint64_t size,
315 int flags, struct drm_file *);
316 extern void nouveau_mem_free(struct drm_device *dev, struct mem_block*);
317 extern int nouveau_mem_init(struct drm_device *);
318 extern void nouveau_mem_close(struct drm_device *);
320 /* nouveau_notifier.c */
321 extern int nouveau_notifier_init_channel(struct nouveau_channel *);
322 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
323 extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
324 int cout, uint32_t *offset);
325 extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
329 extern int nouveau_fifo_init(struct drm_device *);
330 extern int nouveau_fifo_number(struct drm_device *);
331 extern int nouveau_fifo_ctx_size(struct drm_device *);
332 extern void nouveau_fifo_cleanup(struct drm_device *, struct drm_file *);
333 extern int nouveau_fifo_owner(struct drm_device *, struct drm_file *,
335 extern void nouveau_fifo_free(struct nouveau_channel *);
337 /* nouveau_object.c */
338 extern void nouveau_gpuobj_takedown(struct drm_device *);
339 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
340 uint32_t vram_h, uint32_t tt_h);
341 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
342 extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
343 int size, int align, uint32_t flags,
344 struct nouveau_gpuobj **);
345 extern int nouveau_gpuobj_del(struct drm_device *, struct nouveau_gpuobj **);
346 extern int nouveau_gpuobj_ref_add(struct drm_device *, struct nouveau_channel *,
347 uint32_t handle, struct nouveau_gpuobj *,
348 struct nouveau_gpuobj_ref **);
349 extern int nouveau_gpuobj_ref_del(struct drm_device *,
350 struct nouveau_gpuobj_ref **);
351 extern int nouveau_gpuobj_new_ref(struct drm_device *,
352 struct nouveau_channel *alloc_chan,
353 struct nouveau_channel *ref_chan,
354 uint32_t handle, int size, int align,
355 uint32_t flags, struct nouveau_gpuobj_ref **);
356 extern int nouveau_gpuobj_new_fake(struct drm_device *, uint32_t offset,
357 uint32_t size, uint32_t flags,
358 struct nouveau_gpuobj **,
359 struct nouveau_gpuobj_ref**);
360 extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
361 uint64_t offset, uint64_t size, int access,
362 int target, struct nouveau_gpuobj **);
363 extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
364 uint64_t offset, uint64_t size,
365 int access, struct nouveau_gpuobj **,
367 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
368 struct nouveau_gpuobj **);
369 extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
373 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
374 extern void nouveau_irq_preinstall(struct drm_device *);
375 extern void nouveau_irq_postinstall(struct drm_device *);
376 extern void nouveau_irq_uninstall(struct drm_device *);
378 /* nouveau_sgdma.c */
379 extern int nouveau_sgdma_init(struct drm_device *);
380 extern void nouveau_sgdma_takedown(struct drm_device *);
381 extern struct drm_ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
382 extern int nouveau_sgdma_nottm_hack_init(struct drm_device *);
383 extern void nouveau_sgdma_nottm_hack_takedown(struct drm_device *);
386 extern int nv04_fb_init(struct drm_device *);
387 extern void nv04_fb_takedown(struct drm_device *);
390 extern int nv10_fb_init(struct drm_device *);
391 extern void nv10_fb_takedown(struct drm_device *);
394 extern int nv40_fb_init(struct drm_device *);
395 extern void nv40_fb_takedown(struct drm_device *);
398 extern int nv04_fifo_create_context(struct nouveau_channel *);
399 extern void nv04_fifo_destroy_context(struct nouveau_channel *);
400 extern int nv04_fifo_load_context(struct nouveau_channel *);
401 extern int nv04_fifo_save_context(struct nouveau_channel *);
404 extern int nv10_fifo_create_context(struct nouveau_channel *);
405 extern void nv10_fifo_destroy_context(struct nouveau_channel *);
406 extern int nv10_fifo_load_context(struct nouveau_channel *);
407 extern int nv10_fifo_save_context(struct nouveau_channel *);
410 extern int nv40_fifo_create_context(struct nouveau_channel *);
411 extern void nv40_fifo_destroy_context(struct nouveau_channel *);
412 extern int nv40_fifo_load_context(struct nouveau_channel *);
413 extern int nv40_fifo_save_context(struct nouveau_channel *);
416 extern int nv50_fifo_init(struct drm_device *);
417 extern void nv50_fifo_takedown(struct drm_device *);
418 extern int nv50_fifo_create_context(struct nouveau_channel *);
419 extern void nv50_fifo_destroy_context(struct nouveau_channel *);
420 extern int nv50_fifo_load_context(struct nouveau_channel *);
421 extern int nv50_fifo_save_context(struct nouveau_channel *);
424 extern void nouveau_nv04_context_switch(struct drm_device *);
425 extern int nv04_graph_init(struct drm_device *);
426 extern void nv04_graph_takedown(struct drm_device *);
427 extern int nv04_graph_create_context(struct nouveau_channel *);
428 extern void nv04_graph_destroy_context(struct nouveau_channel *);
429 extern int nv04_graph_load_context(struct nouveau_channel *);
430 extern int nv04_graph_save_context(struct nouveau_channel *);
433 extern void nouveau_nv10_context_switch(struct drm_device *);
434 extern int nv10_graph_init(struct drm_device *);
435 extern void nv10_graph_takedown(struct drm_device *);
436 extern int nv10_graph_create_context(struct nouveau_channel *);
437 extern void nv10_graph_destroy_context(struct nouveau_channel *);
438 extern int nv10_graph_load_context(struct nouveau_channel *);
439 extern int nv10_graph_save_context(struct nouveau_channel *);
442 extern void nouveau_nv20_context_switch(struct drm_device *);
443 extern int nv20_graph_init(struct drm_device *);
444 extern void nv20_graph_takedown(struct drm_device *);
445 extern int nv20_graph_create_context(struct nouveau_channel *);
446 extern void nv20_graph_destroy_context(struct nouveau_channel *);
447 extern int nv20_graph_load_context(struct nouveau_channel *);
448 extern int nv20_graph_save_context(struct nouveau_channel *);
451 extern int nv30_graph_init(struct drm_device *);
452 extern void nv30_graph_takedown(struct drm_device *);
453 extern int nv30_graph_create_context(struct nouveau_channel *);
454 extern void nv30_graph_destroy_context(struct nouveau_channel *);
455 extern int nv30_graph_load_context(struct nouveau_channel *);
456 extern int nv30_graph_save_context(struct nouveau_channel *);
459 extern int nv40_graph_init(struct drm_device *);
460 extern void nv40_graph_takedown(struct drm_device *);
461 extern int nv40_graph_create_context(struct nouveau_channel *);
462 extern void nv40_graph_destroy_context(struct nouveau_channel *);
463 extern int nv40_graph_load_context(struct nouveau_channel *);
464 extern int nv40_graph_save_context(struct nouveau_channel *);
467 extern int nv50_graph_init(struct drm_device *);
468 extern void nv50_graph_takedown(struct drm_device *);
469 extern int nv50_graph_create_context(struct nouveau_channel *);
470 extern void nv50_graph_destroy_context(struct nouveau_channel *);
471 extern int nv50_graph_load_context(struct nouveau_channel *);
472 extern int nv50_graph_save_context(struct nouveau_channel *);
475 extern int nv04_instmem_init(struct drm_device *);
476 extern void nv04_instmem_takedown(struct drm_device *);
477 extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
479 extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
480 extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
481 extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
484 extern int nv50_instmem_init(struct drm_device *);
485 extern void nv50_instmem_takedown(struct drm_device *);
486 extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
488 extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
489 extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
490 extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
493 extern int nv04_mc_init(struct drm_device *);
494 extern void nv04_mc_takedown(struct drm_device *);
497 extern int nv40_mc_init(struct drm_device *);
498 extern void nv40_mc_takedown(struct drm_device *);
501 extern int nv50_mc_init(struct drm_device *);
502 extern void nv50_mc_takedown(struct drm_device *);
505 extern int nv04_timer_init(struct drm_device *);
506 extern uint64_t nv04_timer_read(struct drm_device *);
507 extern void nv04_timer_takedown(struct drm_device *);
509 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
512 #if defined(__powerpc__)
513 #define NV_READ(reg) in_be32((void __iomem *)(dev_priv->mmio)->handle + (reg) )
514 #define NV_WRITE(reg,val) out_be32((void __iomem *)(dev_priv->mmio)->handle + (reg) , (val) )
516 #define NV_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
517 #define NV_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
521 #if defined(__powerpc__)
522 #define NV_RI32(o) in_be32((void __iomem *)(dev_priv->ramin)->handle+(o))
523 #define NV_WI32(o,v) out_be32((void __iomem*)(dev_priv->ramin)->handle+(o), (v))
525 #define NV_RI32(o) DRM_READ32(dev_priv->ramin, (o))
526 #define NV_WI32(o,v) DRM_WRITE32(dev_priv->ramin, (o), (v))
529 #define INSTANCE_RD(o,i) NV_RI32((o)->im_pramin->start + ((i)<<2))
530 #define INSTANCE_WR(o,i,v) NV_WI32((o)->im_pramin->start + ((i)<<2), (v))
532 #endif /* __NOUVEAU_DRV_H__ */