2 * Copyright 2005 Stephane Marchesin.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 #ifndef __NOUVEAU_DRV_H__
26 #define __NOUVEAU_DRV_H__
28 #define DRIVER_AUTHOR "Stephane Marchesin"
29 #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
31 #define DRIVER_NAME "nouveau"
32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33 #define DRIVER_DATE "20060213"
35 #define DRIVER_MAJOR 0
36 #define DRIVER_MINOR 0
37 #define DRIVER_PATCHLEVEL 10
39 #define NOUVEAU_FAMILY 0x0000FFFF
40 #define NOUVEAU_FLAGS 0xFFFF0000
42 #include "nouveau_drm.h"
43 #include "nouveau_reg.h"
46 struct mem_block *next;
47 struct mem_block *prev;
50 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
53 drm_handle_t map_handle;
57 NV_NFORCE =0x10000000,
58 NV_NFORCE2 =0x20000000
61 #define NVOBJ_ENGINE_SW 0
62 #define NVOBJ_ENGINE_GR 1
63 #define NVOBJ_ENGINE_INT 0xdeadbeef
65 #define NVOBJ_FLAG_ALLOW_NO_REFS (1 << 0)
66 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
67 #define NVOBJ_FLAG_ZERO_FREE (1 << 2)
68 #define NVOBJ_FLAG_FAKE (1 << 3)
69 struct nouveau_gpuobj {
70 struct list_head list;
73 struct mem_block *im_pramin;
74 struct mem_block *im_backing;
83 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
87 struct nouveau_gpuobj_ref {
88 struct list_head list;
90 struct nouveau_gpuobj *gpuobj;
97 struct nouveau_channel
99 struct drm_device *dev;
102 /* owner of this fifo */
103 struct drm_file *file_priv;
104 /* mapping of the fifo itself */
105 drm_local_map_t *map;
106 /* mapping of the regs controling the fifo */
107 drm_local_map_t *regs;
109 /* DMA push buffer */
110 struct nouveau_gpuobj_ref *pushbuf;
111 struct mem_block *pushbuf_mem;
112 uint32_t pushbuf_base;
114 /* Notifier memory */
115 struct mem_block *notifier_block;
116 struct mem_block *notifier_heap;
117 drm_local_map_t *notifier_map;
120 struct nouveau_gpuobj_ref *ramfc;
123 struct nouveau_gpuobj_ref *ramin_grctx;
124 uint32_t pgraph_ctx [340]; /* XXX dynamic alloc ? */
127 struct nouveau_gpuobj *vm_pd;
128 struct nouveau_gpuobj_ref *vm_gart_pt;
131 struct nouveau_gpuobj_ref *ramin; /* Private instmem */
132 struct mem_block *ramin_heap; /* Private PRAMIN heap */
133 struct nouveau_gpuobj_ref *ramht; /* Hash table */
134 struct list_head ramht_refs; /* Objects referenced by RAMHT */
137 struct nouveau_config {
144 struct nouveau_instmem_engine {
147 int (*init)(struct drm_device *dev);
148 void (*takedown)(struct drm_device *dev);
150 int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
152 void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
153 int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
154 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
157 struct nouveau_mc_engine {
158 int (*init)(struct drm_device *dev);
159 void (*takedown)(struct drm_device *dev);
162 struct nouveau_timer_engine {
163 int (*init)(struct drm_device *dev);
164 void (*takedown)(struct drm_device *dev);
165 uint64_t (*read)(struct drm_device *dev);
168 struct nouveau_fb_engine {
169 int (*init)(struct drm_device *dev);
170 void (*takedown)(struct drm_device *dev);
173 struct nouveau_fifo_engine {
176 int (*init)(struct drm_device *);
177 void (*takedown)(struct drm_device *);
179 int (*create_context)(struct nouveau_channel *);
180 void (*destroy_context)(struct nouveau_channel *);
181 int (*load_context)(struct nouveau_channel *);
182 int (*save_context)(struct nouveau_channel *);
185 struct nouveau_pgraph_engine {
186 int (*init)(struct drm_device *);
187 void (*takedown)(struct drm_device *);
189 int (*create_context)(struct nouveau_channel *);
190 void (*destroy_context)(struct nouveau_channel *);
191 int (*load_context)(struct nouveau_channel *);
192 int (*save_context)(struct nouveau_channel *);
195 struct nouveau_engine {
196 struct nouveau_instmem_engine instmem;
197 struct nouveau_mc_engine mc;
198 struct nouveau_timer_engine timer;
199 struct nouveau_fb_engine fb;
200 struct nouveau_pgraph_engine graph;
201 struct nouveau_fifo_engine fifo;
204 struct drm_nouveau_private {
206 NOUVEAU_CARD_INIT_DOWN,
207 NOUVEAU_CARD_INIT_DONE,
208 NOUVEAU_CARD_INIT_FAILED
211 /* the card type, takes NV_* as values */
213 /* exact chipset, derived from NV_PMC_BOOT_0 */
217 drm_local_map_t *mmio;
219 drm_local_map_t *ramin; /* NV40 onwards */
221 int fifo_alloc_count;
222 struct nouveau_channel *fifos[NV_MAX_FIFO_NUMBER];
224 struct nouveau_engine Engine;
226 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
227 struct nouveau_gpuobj *ramht;
228 uint32_t ramin_rsvd_vram;
229 uint32_t ramht_offset;
232 uint32_t ramfc_offset;
234 uint32_t ramro_offset;
237 /* base physical adresses */
239 uint64_t fb_available_size;
243 NOUVEAU_GART_NONE = 0,
250 struct nouveau_gpuobj *sg_ctxdma;
251 struct page *sg_dummy_page;
252 dma_addr_t sg_dummy_bus;
255 struct drm_ttm_backend *sg_be;
256 unsigned long sg_handle;
259 /* the mtrr covering the FB */
262 struct mem_block *agp_heap;
263 struct mem_block *fb_heap;
264 struct mem_block *fb_nomap_heap;
265 struct mem_block *ramin_heap;
266 struct mem_block *pci_heap;
268 /* context table pointed to be NV_PGRAPH_CHANNEL_CTX_TABLE (0x400780) */
269 uint32_t ctx_table_size;
270 struct nouveau_gpuobj_ref *ctx_table;
272 struct nouveau_config config;
274 struct list_head gpuobj_list;
277 #define NOUVEAU_CHECK_INITIALISED_WITH_RETURN do { \
278 struct drm_nouveau_private *nv = dev->dev_private; \
279 if (nv->init_state != NOUVEAU_CARD_INIT_DONE) { \
280 DRM_ERROR("called without init\n"); \
285 #define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id,cl,ch) do { \
286 struct drm_nouveau_private *nv = dev->dev_private; \
287 if (!nouveau_fifo_owner(dev, (cl), (id))) { \
288 DRM_ERROR("pid %d doesn't own channel %d\n", \
289 DRM_CURRENTPID, (id)); \
292 (ch) = nv->fifos[(id)]; \
295 /* nouveau_state.c */
296 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
297 extern int nouveau_load(struct drm_device *, unsigned long flags);
298 extern int nouveau_firstopen(struct drm_device *);
299 extern void nouveau_lastclose(struct drm_device *);
300 extern int nouveau_unload(struct drm_device *);
301 extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
303 extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
305 extern void nouveau_wait_for_idle(struct drm_device *);
306 extern int nouveau_card_init(struct drm_device *);
307 extern int nouveau_ioctl_card_init(struct drm_device *, void *data,
311 extern int nouveau_mem_init_heap(struct mem_block **, uint64_t start,
313 extern struct mem_block *nouveau_mem_alloc_block(struct mem_block *,
314 uint64_t size, int align2,
316 extern void nouveau_mem_takedown(struct mem_block **heap);
317 extern void nouveau_mem_free_block(struct mem_block *);
318 extern uint64_t nouveau_mem_fb_amount(struct drm_device *);
319 extern void nouveau_mem_release(struct drm_file *, struct mem_block *heap);
320 extern int nouveau_ioctl_mem_alloc(struct drm_device *, void *data,
322 extern int nouveau_ioctl_mem_free(struct drm_device *, void *data,
324 extern struct mem_block* nouveau_mem_alloc(struct drm_device *,
325 int alignment, uint64_t size,
326 int flags, struct drm_file *);
327 extern void nouveau_mem_free(struct drm_device *dev, struct mem_block*);
328 extern int nouveau_mem_init(struct drm_device *);
329 extern void nouveau_mem_close(struct drm_device *);
331 /* nouveau_notifier.c */
332 extern int nouveau_notifier_init_channel(struct nouveau_channel *);
333 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
334 extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
335 int cout, uint32_t *offset);
336 extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
338 extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
342 extern int nouveau_fifo_init(struct drm_device *);
343 extern int nouveau_fifo_number(struct drm_device *);
344 extern int nouveau_fifo_ctx_size(struct drm_device *);
345 extern void nouveau_fifo_cleanup(struct drm_device *, struct drm_file *);
346 extern int nouveau_fifo_owner(struct drm_device *, struct drm_file *,
348 extern void nouveau_fifo_free(struct nouveau_channel *);
350 /* nouveau_object.c */
351 extern int nouveau_gpuobj_init(struct drm_device *);
352 extern void nouveau_gpuobj_takedown(struct drm_device *);
353 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
354 uint32_t vram_h, uint32_t tt_h);
355 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
356 extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
357 int size, int align, uint32_t flags,
358 struct nouveau_gpuobj **);
359 extern int nouveau_gpuobj_del(struct drm_device *, struct nouveau_gpuobj **);
360 extern int nouveau_gpuobj_ref_add(struct drm_device *, struct nouveau_channel *,
361 uint32_t handle, struct nouveau_gpuobj *,
362 struct nouveau_gpuobj_ref **);
363 extern int nouveau_gpuobj_ref_del(struct drm_device *,
364 struct nouveau_gpuobj_ref **);
365 extern int nouveau_gpuobj_ref_find(struct nouveau_channel *, uint32_t handle,
366 struct nouveau_gpuobj_ref **ref_ret);
367 extern int nouveau_gpuobj_new_ref(struct drm_device *,
368 struct nouveau_channel *alloc_chan,
369 struct nouveau_channel *ref_chan,
370 uint32_t handle, int size, int align,
371 uint32_t flags, struct nouveau_gpuobj_ref **);
372 extern int nouveau_gpuobj_new_fake(struct drm_device *, uint32_t offset,
373 uint32_t size, uint32_t flags,
374 struct nouveau_gpuobj **,
375 struct nouveau_gpuobj_ref**);
376 extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
377 uint64_t offset, uint64_t size, int access,
378 int target, struct nouveau_gpuobj **);
379 extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
380 uint64_t offset, uint64_t size,
381 int access, struct nouveau_gpuobj **,
383 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
384 struct nouveau_gpuobj **);
385 extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
387 extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
391 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
392 extern void nouveau_irq_preinstall(struct drm_device *);
393 extern void nouveau_irq_postinstall(struct drm_device *);
394 extern void nouveau_irq_uninstall(struct drm_device *);
396 /* nouveau_sgdma.c */
397 extern int nouveau_sgdma_init(struct drm_device *);
398 extern void nouveau_sgdma_takedown(struct drm_device *);
399 extern struct drm_ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
400 extern int nouveau_sgdma_nottm_hack_init(struct drm_device *);
401 extern void nouveau_sgdma_nottm_hack_takedown(struct drm_device *);
404 extern int nv04_fb_init(struct drm_device *);
405 extern void nv04_fb_takedown(struct drm_device *);
408 extern int nv10_fb_init(struct drm_device *);
409 extern void nv10_fb_takedown(struct drm_device *);
412 extern int nv40_fb_init(struct drm_device *);
413 extern void nv40_fb_takedown(struct drm_device *);
416 extern int nv04_fifo_create_context(struct nouveau_channel *);
417 extern void nv04_fifo_destroy_context(struct nouveau_channel *);
418 extern int nv04_fifo_load_context(struct nouveau_channel *);
419 extern int nv04_fifo_save_context(struct nouveau_channel *);
422 extern int nv10_fifo_create_context(struct nouveau_channel *);
423 extern void nv10_fifo_destroy_context(struct nouveau_channel *);
424 extern int nv10_fifo_load_context(struct nouveau_channel *);
425 extern int nv10_fifo_save_context(struct nouveau_channel *);
428 extern int nv40_fifo_create_context(struct nouveau_channel *);
429 extern void nv40_fifo_destroy_context(struct nouveau_channel *);
430 extern int nv40_fifo_load_context(struct nouveau_channel *);
431 extern int nv40_fifo_save_context(struct nouveau_channel *);
434 extern int nv50_fifo_init(struct drm_device *);
435 extern void nv50_fifo_takedown(struct drm_device *);
436 extern int nv50_fifo_create_context(struct nouveau_channel *);
437 extern void nv50_fifo_destroy_context(struct nouveau_channel *);
438 extern int nv50_fifo_load_context(struct nouveau_channel *);
439 extern int nv50_fifo_save_context(struct nouveau_channel *);
442 extern void nouveau_nv04_context_switch(struct drm_device *);
443 extern int nv04_graph_init(struct drm_device *);
444 extern void nv04_graph_takedown(struct drm_device *);
445 extern int nv04_graph_create_context(struct nouveau_channel *);
446 extern void nv04_graph_destroy_context(struct nouveau_channel *);
447 extern int nv04_graph_load_context(struct nouveau_channel *);
448 extern int nv04_graph_save_context(struct nouveau_channel *);
451 extern void nouveau_nv10_context_switch(struct drm_device *);
452 extern int nv10_graph_init(struct drm_device *);
453 extern void nv10_graph_takedown(struct drm_device *);
454 extern int nv10_graph_create_context(struct nouveau_channel *);
455 extern void nv10_graph_destroy_context(struct nouveau_channel *);
456 extern int nv10_graph_load_context(struct nouveau_channel *);
457 extern int nv10_graph_save_context(struct nouveau_channel *);
460 extern void nouveau_nv20_context_switch(struct drm_device *);
461 extern int nv20_graph_init(struct drm_device *);
462 extern void nv20_graph_takedown(struct drm_device *);
463 extern int nv20_graph_create_context(struct nouveau_channel *);
464 extern void nv20_graph_destroy_context(struct nouveau_channel *);
465 extern int nv20_graph_load_context(struct nouveau_channel *);
466 extern int nv20_graph_save_context(struct nouveau_channel *);
469 extern int nv30_graph_init(struct drm_device *);
470 extern void nv30_graph_takedown(struct drm_device *);
471 extern int nv30_graph_create_context(struct nouveau_channel *);
472 extern void nv30_graph_destroy_context(struct nouveau_channel *);
473 extern int nv30_graph_load_context(struct nouveau_channel *);
474 extern int nv30_graph_save_context(struct nouveau_channel *);
477 extern int nv40_graph_init(struct drm_device *);
478 extern void nv40_graph_takedown(struct drm_device *);
479 extern int nv40_graph_create_context(struct nouveau_channel *);
480 extern void nv40_graph_destroy_context(struct nouveau_channel *);
481 extern int nv40_graph_load_context(struct nouveau_channel *);
482 extern int nv40_graph_save_context(struct nouveau_channel *);
485 extern int nv50_graph_init(struct drm_device *);
486 extern void nv50_graph_takedown(struct drm_device *);
487 extern int nv50_graph_create_context(struct nouveau_channel *);
488 extern void nv50_graph_destroy_context(struct nouveau_channel *);
489 extern int nv50_graph_load_context(struct nouveau_channel *);
490 extern int nv50_graph_save_context(struct nouveau_channel *);
493 extern int nv04_instmem_init(struct drm_device *);
494 extern void nv04_instmem_takedown(struct drm_device *);
495 extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
497 extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
498 extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
499 extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
502 extern int nv50_instmem_init(struct drm_device *);
503 extern void nv50_instmem_takedown(struct drm_device *);
504 extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
506 extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
507 extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
508 extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
511 extern int nv04_mc_init(struct drm_device *);
512 extern void nv04_mc_takedown(struct drm_device *);
515 extern int nv40_mc_init(struct drm_device *);
516 extern void nv40_mc_takedown(struct drm_device *);
519 extern int nv50_mc_init(struct drm_device *);
520 extern void nv50_mc_takedown(struct drm_device *);
523 extern int nv04_timer_init(struct drm_device *);
524 extern uint64_t nv04_timer_read(struct drm_device *);
525 extern void nv04_timer_takedown(struct drm_device *);
527 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
530 #if defined(__powerpc__)
531 #define NV_READ(reg) in_be32((void __iomem *)(dev_priv->mmio)->handle + (reg) )
532 #define NV_WRITE(reg,val) out_be32((void __iomem *)(dev_priv->mmio)->handle + (reg) , (val) )
534 #define NV_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
535 #define NV_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
539 #if defined(__powerpc__)
540 #define NV_RI32(o) in_be32((void __iomem *)(dev_priv->ramin)->handle+(o))
541 #define NV_WI32(o,v) out_be32((void __iomem*)(dev_priv->ramin)->handle+(o), (v))
543 #define NV_RI32(o) DRM_READ32(dev_priv->ramin, (o))
544 #define NV_WI32(o,v) DRM_WRITE32(dev_priv->ramin, (o), (v))
547 #define INSTANCE_RD(o,i) NV_RI32((o)->im_pramin->start + ((i)<<2))
548 #define INSTANCE_WR(o,i,v) NV_WI32((o)->im_pramin->start + ((i)<<2), (v))
550 #endif /* __NOUVEAU_DRV_H__ */