2 * Copyright 2005 Stephane Marchesin.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 #ifndef __NOUVEAU_DRV_H__
26 #define __NOUVEAU_DRV_H__
28 #define DRIVER_AUTHOR "Stephane Marchesin"
29 #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
31 #define DRIVER_NAME "nouveau"
32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33 #define DRIVER_DATE "20060213"
35 #define DRIVER_MAJOR 0
36 #define DRIVER_MINOR 0
37 #define DRIVER_PATCHLEVEL 10
39 #define NOUVEAU_FAMILY 0x0000FFFF
40 #define NOUVEAU_FLAGS 0xFFFF0000
43 #if defined(__linux__)
44 #define NOUVEAU_HAVE_BUFFER
48 #include "nouveau_drm.h"
49 #include "nouveau_reg.h"
53 struct mem_block *next;
54 struct mem_block *prev;
57 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
60 drm_handle_t map_handle;
64 NV_NFORCE =0x10000000,
65 NV_NFORCE2 =0x20000000
68 #define NVOBJ_ENGINE_SW 0
69 #define NVOBJ_ENGINE_GR 1
70 #define NVOBJ_ENGINE_INT 0xdeadbeef
72 #define NVOBJ_FLAG_ALLOW_NO_REFS (1 << 0)
73 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
74 #define NVOBJ_FLAG_ZERO_FREE (1 << 2)
75 #define NVOBJ_FLAG_FAKE (1 << 3)
76 struct nouveau_gpuobj {
77 struct list_head list;
80 struct mem_block *im_pramin;
81 struct mem_block *im_backing;
90 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
94 struct nouveau_gpuobj_ref {
95 struct list_head list;
97 struct nouveau_gpuobj *gpuobj;
104 struct nouveau_channel
106 struct drm_device *dev;
109 /* owner of this fifo */
110 struct drm_file *file_priv;
111 /* mapping of the fifo itself */
112 drm_local_map_t *map;
113 /* mapping of the regs controling the fifo */
114 drm_local_map_t *regs;
116 /* DMA push buffer */
117 struct nouveau_gpuobj_ref *pushbuf;
118 struct mem_block *pushbuf_mem;
119 uint32_t pushbuf_base;
121 /* Notifier memory */
122 struct mem_block *notifier_block;
123 struct mem_block *notifier_heap;
124 drm_local_map_t *notifier_map;
127 struct nouveau_gpuobj_ref *ramfc;
130 /* XXX may be merge 2 pointers as private data ??? */
131 struct nouveau_gpuobj_ref *ramin_grctx;
135 struct nouveau_gpuobj *vm_pd;
136 struct nouveau_gpuobj_ref *vm_gart_pt;
139 struct nouveau_gpuobj_ref *ramin; /* Private instmem */
140 struct mem_block *ramin_heap; /* Private PRAMIN heap */
141 struct nouveau_gpuobj_ref *ramht; /* Hash table */
142 struct list_head ramht_refs; /* Objects referenced by RAMHT */
145 struct nouveau_drm_channel {
146 struct nouveau_channel *chan;
149 int max, put, cur, free;
151 volatile uint32_t *pushbuf;
154 uint32_t notify0_offset;
157 uint32_t m2mf_dma_source;
158 uint32_t m2mf_dma_destin;
161 struct nouveau_config {
168 struct nouveau_instmem_engine {
171 int (*init)(struct drm_device *dev);
172 void (*takedown)(struct drm_device *dev);
174 int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
176 void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
177 int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
178 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
181 struct nouveau_mc_engine {
182 int (*init)(struct drm_device *dev);
183 void (*takedown)(struct drm_device *dev);
186 struct nouveau_timer_engine {
187 int (*init)(struct drm_device *dev);
188 void (*takedown)(struct drm_device *dev);
189 uint64_t (*read)(struct drm_device *dev);
192 struct nouveau_fb_engine {
193 int (*init)(struct drm_device *dev);
194 void (*takedown)(struct drm_device *dev);
197 struct nouveau_fifo_engine {
200 int (*init)(struct drm_device *);
201 void (*takedown)(struct drm_device *);
203 int (*create_context)(struct nouveau_channel *);
204 void (*destroy_context)(struct nouveau_channel *);
205 int (*load_context)(struct nouveau_channel *);
206 int (*save_context)(struct nouveau_channel *);
209 struct nouveau_pgraph_engine {
210 int (*init)(struct drm_device *);
211 void (*takedown)(struct drm_device *);
213 int (*create_context)(struct nouveau_channel *);
214 void (*destroy_context)(struct nouveau_channel *);
215 int (*load_context)(struct nouveau_channel *);
216 int (*save_context)(struct nouveau_channel *);
219 struct nouveau_engine {
220 struct nouveau_instmem_engine instmem;
221 struct nouveau_mc_engine mc;
222 struct nouveau_timer_engine timer;
223 struct nouveau_fb_engine fb;
224 struct nouveau_pgraph_engine graph;
225 struct nouveau_fifo_engine fifo;
228 struct drm_nouveau_private {
230 NOUVEAU_CARD_INIT_DOWN,
231 NOUVEAU_CARD_INIT_DONE,
232 NOUVEAU_CARD_INIT_FAILED
235 /* the card type, takes NV_* as values */
237 /* exact chipset, derived from NV_PMC_BOOT_0 */
241 drm_local_map_t *mmio;
243 drm_local_map_t *ramin; /* NV40 onwards */
245 int fifo_alloc_count;
246 struct nouveau_channel *fifos[NV_MAX_FIFO_NUMBER];
248 struct nouveau_engine Engine;
249 struct nouveau_drm_channel channel;
251 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
252 struct nouveau_gpuobj *ramht;
253 uint32_t ramin_rsvd_vram;
254 uint32_t ramht_offset;
257 uint32_t ramfc_offset;
259 uint32_t ramro_offset;
262 /* base physical adresses */
264 uint64_t fb_available_size;
268 NOUVEAU_GART_NONE = 0,
275 struct nouveau_gpuobj *sg_ctxdma;
276 struct page *sg_dummy_page;
277 dma_addr_t sg_dummy_bus;
280 struct drm_ttm_backend *sg_be;
281 unsigned long sg_handle;
284 /* the mtrr covering the FB */
287 struct mem_block *agp_heap;
288 struct mem_block *fb_heap;
289 struct mem_block *fb_nomap_heap;
290 struct mem_block *ramin_heap;
291 struct mem_block *pci_heap;
293 /* context table pointed to be NV_PGRAPH_CHANNEL_CTX_TABLE (0x400780) */
294 uint32_t ctx_table_size;
295 struct nouveau_gpuobj_ref *ctx_table;
297 struct nouveau_config config;
299 struct list_head gpuobj_list;
302 #define NOUVEAU_CHECK_INITIALISED_WITH_RETURN do { \
303 struct drm_nouveau_private *nv = dev->dev_private; \
304 if (nv->init_state != NOUVEAU_CARD_INIT_DONE) { \
305 DRM_ERROR("called without init\n"); \
310 #define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id,cl,ch) do { \
311 struct drm_nouveau_private *nv = dev->dev_private; \
312 if (!nouveau_fifo_owner(dev, (cl), (id))) { \
313 DRM_ERROR("pid %d doesn't own channel %d\n", \
314 DRM_CURRENTPID, (id)); \
317 (ch) = nv->fifos[(id)]; \
320 /* nouveau_state.c */
321 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
322 extern int nouveau_load(struct drm_device *, unsigned long flags);
323 extern int nouveau_firstopen(struct drm_device *);
324 extern void nouveau_lastclose(struct drm_device *);
325 extern int nouveau_unload(struct drm_device *);
326 extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
328 extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
330 extern void nouveau_wait_for_idle(struct drm_device *);
331 extern int nouveau_card_init(struct drm_device *);
332 extern int nouveau_ioctl_card_init(struct drm_device *, void *data,
336 extern int nouveau_mem_init_heap(struct mem_block **, uint64_t start,
338 extern struct mem_block *nouveau_mem_alloc_block(struct mem_block *,
339 uint64_t size, int align2,
341 extern void nouveau_mem_takedown(struct mem_block **heap);
342 extern void nouveau_mem_free_block(struct mem_block *);
343 extern uint64_t nouveau_mem_fb_amount(struct drm_device *);
344 extern void nouveau_mem_release(struct drm_file *, struct mem_block *heap);
345 extern int nouveau_ioctl_mem_alloc(struct drm_device *, void *data,
347 extern int nouveau_ioctl_mem_free(struct drm_device *, void *data,
349 extern struct mem_block* nouveau_mem_alloc(struct drm_device *,
350 int alignment, uint64_t size,
351 int flags, struct drm_file *);
352 extern void nouveau_mem_free(struct drm_device *dev, struct mem_block*);
353 extern int nouveau_mem_init(struct drm_device *);
354 extern void nouveau_mem_close(struct drm_device *);
356 /* nouveau_notifier.c */
357 extern int nouveau_notifier_init_channel(struct nouveau_channel *);
358 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
359 extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
360 int cout, uint32_t *offset);
361 extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
363 extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
367 extern int nouveau_fifo_init(struct drm_device *);
368 extern int nouveau_fifo_number(struct drm_device *);
369 extern int nouveau_fifo_ctx_size(struct drm_device *);
370 extern void nouveau_fifo_cleanup(struct drm_device *, struct drm_file *);
371 extern int nouveau_fifo_owner(struct drm_device *, struct drm_file *,
373 extern int nouveau_fifo_alloc(struct drm_device *dev,
374 struct nouveau_channel **chan,
375 struct drm_file *file_priv,
376 struct mem_block *pushbuf,
377 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
378 extern void nouveau_fifo_free(struct nouveau_channel *);
380 /* nouveau_object.c */
381 extern int nouveau_gpuobj_early_init(struct drm_device *);
382 extern int nouveau_gpuobj_init(struct drm_device *);
383 extern void nouveau_gpuobj_takedown(struct drm_device *);
384 extern void nouveau_gpuobj_late_takedown(struct drm_device *);
385 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
386 uint32_t vram_h, uint32_t tt_h);
387 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
388 extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
389 int size, int align, uint32_t flags,
390 struct nouveau_gpuobj **);
391 extern int nouveau_gpuobj_del(struct drm_device *, struct nouveau_gpuobj **);
392 extern int nouveau_gpuobj_ref_add(struct drm_device *, struct nouveau_channel *,
393 uint32_t handle, struct nouveau_gpuobj *,
394 struct nouveau_gpuobj_ref **);
395 extern int nouveau_gpuobj_ref_del(struct drm_device *,
396 struct nouveau_gpuobj_ref **);
397 extern int nouveau_gpuobj_ref_find(struct nouveau_channel *, uint32_t handle,
398 struct nouveau_gpuobj_ref **ref_ret);
399 extern int nouveau_gpuobj_new_ref(struct drm_device *,
400 struct nouveau_channel *alloc_chan,
401 struct nouveau_channel *ref_chan,
402 uint32_t handle, int size, int align,
403 uint32_t flags, struct nouveau_gpuobj_ref **);
404 extern int nouveau_gpuobj_new_fake(struct drm_device *,
405 uint32_t p_offset, uint32_t b_offset,
406 uint32_t size, uint32_t flags,
407 struct nouveau_gpuobj **,
408 struct nouveau_gpuobj_ref**);
409 extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
410 uint64_t offset, uint64_t size, int access,
411 int target, struct nouveau_gpuobj **);
412 extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
413 uint64_t offset, uint64_t size,
414 int access, struct nouveau_gpuobj **,
416 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
417 struct nouveau_gpuobj **);
418 extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
420 extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
424 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
425 extern void nouveau_irq_preinstall(struct drm_device *);
426 extern void nouveau_irq_postinstall(struct drm_device *);
427 extern void nouveau_irq_uninstall(struct drm_device *);
429 /* nouveau_sgdma.c */
430 extern int nouveau_sgdma_init(struct drm_device *);
431 extern void nouveau_sgdma_takedown(struct drm_device *);
432 extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
434 extern struct drm_ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
435 extern int nouveau_sgdma_nottm_hack_init(struct drm_device *);
436 extern void nouveau_sgdma_nottm_hack_takedown(struct drm_device *);
439 extern int nouveau_dma_channel_init(struct drm_device *);
440 extern void nouveau_dma_channel_takedown(struct drm_device *);
441 extern int nouveau_dma_wait(struct drm_device *, int size);
444 extern int nv04_fb_init(struct drm_device *);
445 extern void nv04_fb_takedown(struct drm_device *);
448 extern int nv10_fb_init(struct drm_device *);
449 extern void nv10_fb_takedown(struct drm_device *);
452 extern int nv40_fb_init(struct drm_device *);
453 extern void nv40_fb_takedown(struct drm_device *);
456 extern int nv04_fifo_create_context(struct nouveau_channel *);
457 extern void nv04_fifo_destroy_context(struct nouveau_channel *);
458 extern int nv04_fifo_load_context(struct nouveau_channel *);
459 extern int nv04_fifo_save_context(struct nouveau_channel *);
462 extern int nv10_fifo_create_context(struct nouveau_channel *);
463 extern void nv10_fifo_destroy_context(struct nouveau_channel *);
464 extern int nv10_fifo_load_context(struct nouveau_channel *);
465 extern int nv10_fifo_save_context(struct nouveau_channel *);
468 extern int nv40_fifo_init(struct drm_device *);
469 extern int nv40_fifo_create_context(struct nouveau_channel *);
470 extern void nv40_fifo_destroy_context(struct nouveau_channel *);
471 extern int nv40_fifo_load_context(struct nouveau_channel *);
472 extern int nv40_fifo_save_context(struct nouveau_channel *);
475 extern int nv50_fifo_init(struct drm_device *);
476 extern void nv50_fifo_takedown(struct drm_device *);
477 extern int nv50_fifo_create_context(struct nouveau_channel *);
478 extern void nv50_fifo_destroy_context(struct nouveau_channel *);
479 extern int nv50_fifo_load_context(struct nouveau_channel *);
480 extern int nv50_fifo_save_context(struct nouveau_channel *);
483 extern void nouveau_nv04_context_switch(struct drm_device *);
484 extern int nv04_graph_init(struct drm_device *);
485 extern void nv04_graph_takedown(struct drm_device *);
486 extern int nv04_graph_create_context(struct nouveau_channel *);
487 extern void nv04_graph_destroy_context(struct nouveau_channel *);
488 extern int nv04_graph_load_context(struct nouveau_channel *);
489 extern int nv04_graph_save_context(struct nouveau_channel *);
492 extern void nouveau_nv10_context_switch(struct drm_device *);
493 extern int nv10_graph_init(struct drm_device *);
494 extern void nv10_graph_takedown(struct drm_device *);
495 extern int nv10_graph_create_context(struct nouveau_channel *);
496 extern void nv10_graph_destroy_context(struct nouveau_channel *);
497 extern int nv10_graph_load_context(struct nouveau_channel *);
498 extern int nv10_graph_save_context(struct nouveau_channel *);
501 extern int nv20_graph_create_context(struct nouveau_channel *);
502 extern void nv20_graph_destroy_context(struct nouveau_channel *);
503 extern int nv20_graph_load_context(struct nouveau_channel *);
504 extern int nv20_graph_save_context(struct nouveau_channel *);
505 extern int nv20_graph_init(struct drm_device *);
506 extern void nv20_graph_takedown(struct drm_device *);
507 extern int nv30_graph_init(struct drm_device *);
510 extern int nv40_graph_init(struct drm_device *);
511 extern void nv40_graph_takedown(struct drm_device *);
512 extern int nv40_graph_create_context(struct nouveau_channel *);
513 extern void nv40_graph_destroy_context(struct nouveau_channel *);
514 extern int nv40_graph_load_context(struct nouveau_channel *);
515 extern int nv40_graph_save_context(struct nouveau_channel *);
518 extern int nv50_graph_init(struct drm_device *);
519 extern void nv50_graph_takedown(struct drm_device *);
520 extern int nv50_graph_create_context(struct nouveau_channel *);
521 extern void nv50_graph_destroy_context(struct nouveau_channel *);
522 extern int nv50_graph_load_context(struct nouveau_channel *);
523 extern int nv50_graph_save_context(struct nouveau_channel *);
526 extern int nv04_instmem_init(struct drm_device *);
527 extern void nv04_instmem_takedown(struct drm_device *);
528 extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
530 extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
531 extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
532 extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
535 extern int nv50_instmem_init(struct drm_device *);
536 extern void nv50_instmem_takedown(struct drm_device *);
537 extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
539 extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
540 extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
541 extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
544 extern int nv04_mc_init(struct drm_device *);
545 extern void nv04_mc_takedown(struct drm_device *);
548 extern int nv40_mc_init(struct drm_device *);
549 extern void nv40_mc_takedown(struct drm_device *);
552 extern int nv50_mc_init(struct drm_device *);
553 extern void nv50_mc_takedown(struct drm_device *);
556 extern int nv04_timer_init(struct drm_device *);
557 extern uint64_t nv04_timer_read(struct drm_device *);
558 extern void nv04_timer_takedown(struct drm_device *);
560 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
563 #ifdef NOUVEAU_HAVE_BUFFER
564 /* nouveau_buffer.c */
565 extern struct drm_ttm_backend *nouveau_create_ttm_backend_entry(struct drm_device *dev);
566 extern int nouveau_fence_types(struct drm_buffer_object *bo, uint32_t *fclass, uint32_t *type);
567 extern int nouveau_invalidate_caches(struct drm_device *dev, uint64_t buffer_flags);
568 extern int nouveau_init_mem_type(struct drm_device *dev, uint32_t type, struct drm_mem_type_manager *man);
569 extern uint32_t nouveau_evict_mask(struct drm_buffer_object *bo);
570 extern int nouveau_move(struct drm_buffer_object *bo, int evict, int no_wait, struct drm_bo_mem_reg *new_mem);
571 void nouveau_flush_ttm(struct drm_ttm *ttm);
574 #if defined(__powerpc__)
575 #define NV_READ(reg) in_be32((void __iomem *)(dev_priv->mmio)->handle + (reg) )
576 #define NV_WRITE(reg,val) out_be32((void __iomem *)(dev_priv->mmio)->handle + (reg) , (val) )
578 #define NV_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
579 #define NV_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
583 #if defined(__powerpc__)
584 #define NV_RI32(o) in_be32((void __iomem *)(dev_priv->ramin)->handle+(o))
585 #define NV_WI32(o,v) out_be32((void __iomem*)(dev_priv->ramin)->handle+(o), (v))
587 #define NV_RI32(o) DRM_READ32(dev_priv->ramin, (o))
588 #define NV_WI32(o,v) DRM_WRITE32(dev_priv->ramin, (o), (v))
591 #define INSTANCE_RD(o,i) NV_RI32((o)->im_pramin->start + ((i)<<2))
592 #define INSTANCE_WR(o,i,v) NV_WI32((o)->im_pramin->start + ((i)<<2), (v))
594 #endif /* __NOUVEAU_DRV_H__ */