2 * Copyright 2005 Stephane Marchesin.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 #ifndef __NOUVEAU_DRV_H__
26 #define __NOUVEAU_DRV_H__
28 #define DRIVER_AUTHOR "Stephane Marchesin"
29 #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
31 #define DRIVER_NAME "nouveau"
32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33 #define DRIVER_DATE "20060213"
35 #define DRIVER_MAJOR 0
36 #define DRIVER_MINOR 0
37 #define DRIVER_PATCHLEVEL 10
39 #define NOUVEAU_FAMILY 0x0000FFFF
40 #define NOUVEAU_FLAGS 0xFFFF0000
42 #include "nouveau_drm.h"
43 #include "nouveau_reg.h"
46 struct mem_block *next;
47 struct mem_block *prev;
50 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
53 drm_handle_t map_handle;
57 NV_NFORCE =0x10000000,
58 NV_NFORCE2 =0x20000000
61 #define NVOBJ_ENGINE_SW 0
62 #define NVOBJ_ENGINE_GR 1
63 #define NVOBJ_ENGINE_INT 0xdeadbeef
65 #define NVOBJ_FLAG_ALLOW_NO_REFS (1 << 0)
66 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
67 #define NVOBJ_FLAG_ZERO_FREE (1 << 2)
68 #define NVOBJ_FLAG_FAKE (1 << 3)
69 struct nouveau_gpuobj {
70 struct list_head list;
73 struct mem_block *im_pramin;
74 struct mem_block *im_backing;
83 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
87 struct nouveau_gpuobj_ref {
88 struct list_head list;
90 struct nouveau_gpuobj *gpuobj;
97 struct nouveau_channel
99 struct drm_device *dev;
102 /* owner of this fifo */
103 struct drm_file *file_priv;
104 /* mapping of the fifo itself */
105 drm_local_map_t *map;
106 /* mapping of the regs controling the fifo */
107 drm_local_map_t *regs;
109 /* DMA push buffer */
110 struct nouveau_gpuobj_ref *pushbuf;
111 struct mem_block *pushbuf_mem;
112 uint32_t pushbuf_base;
114 /* Notifier memory */
115 struct mem_block *notifier_block;
116 struct mem_block *notifier_heap;
117 drm_local_map_t *notifier_map;
120 struct nouveau_gpuobj_ref *ramfc;
123 /* XXX may be merge 2 pointers as private data ??? */
124 struct nouveau_gpuobj_ref *ramin_grctx;
128 struct nouveau_gpuobj *vm_pd;
129 struct nouveau_gpuobj_ref *vm_gart_pt;
132 struct nouveau_gpuobj_ref *ramin; /* Private instmem */
133 struct mem_block *ramin_heap; /* Private PRAMIN heap */
134 struct nouveau_gpuobj_ref *ramht; /* Hash table */
135 struct list_head ramht_refs; /* Objects referenced by RAMHT */
138 struct nouveau_drm_channel {
139 struct nouveau_channel *chan;
142 int max, put, cur, free;
144 volatile uint32_t *pushbuf;
147 uint32_t notify0_offset;
150 uint32_t m2mf_dma_source;
151 uint32_t m2mf_dma_destin;
154 struct nouveau_config {
161 struct nouveau_instmem_engine {
164 int (*init)(struct drm_device *dev);
165 void (*takedown)(struct drm_device *dev);
167 int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
169 void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
170 int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
171 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
174 struct nouveau_mc_engine {
175 int (*init)(struct drm_device *dev);
176 void (*takedown)(struct drm_device *dev);
179 struct nouveau_timer_engine {
180 int (*init)(struct drm_device *dev);
181 void (*takedown)(struct drm_device *dev);
182 uint64_t (*read)(struct drm_device *dev);
185 struct nouveau_fb_engine {
186 int (*init)(struct drm_device *dev);
187 void (*takedown)(struct drm_device *dev);
190 struct nouveau_fifo_engine {
193 int (*init)(struct drm_device *);
194 void (*takedown)(struct drm_device *);
196 int (*create_context)(struct nouveau_channel *);
197 void (*destroy_context)(struct nouveau_channel *);
198 int (*load_context)(struct nouveau_channel *);
199 int (*save_context)(struct nouveau_channel *);
202 struct nouveau_pgraph_engine {
203 int (*init)(struct drm_device *);
204 void (*takedown)(struct drm_device *);
206 int (*create_context)(struct nouveau_channel *);
207 void (*destroy_context)(struct nouveau_channel *);
208 int (*load_context)(struct nouveau_channel *);
209 int (*save_context)(struct nouveau_channel *);
212 struct nouveau_engine {
213 struct nouveau_instmem_engine instmem;
214 struct nouveau_mc_engine mc;
215 struct nouveau_timer_engine timer;
216 struct nouveau_fb_engine fb;
217 struct nouveau_pgraph_engine graph;
218 struct nouveau_fifo_engine fifo;
221 struct drm_nouveau_private {
223 NOUVEAU_CARD_INIT_DOWN,
224 NOUVEAU_CARD_INIT_DONE,
225 NOUVEAU_CARD_INIT_FAILED
228 /* the card type, takes NV_* as values */
230 /* exact chipset, derived from NV_PMC_BOOT_0 */
234 drm_local_map_t *mmio;
236 drm_local_map_t *ramin; /* NV40 onwards */
238 int fifo_alloc_count;
239 struct nouveau_channel *fifos[NV_MAX_FIFO_NUMBER];
241 struct nouveau_engine Engine;
242 struct nouveau_drm_channel channel;
244 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
245 struct nouveau_gpuobj *ramht;
246 uint32_t ramin_rsvd_vram;
247 uint32_t ramht_offset;
250 uint32_t ramfc_offset;
252 uint32_t ramro_offset;
255 /* base physical adresses */
257 uint64_t fb_available_size;
261 NOUVEAU_GART_NONE = 0,
268 struct nouveau_gpuobj *sg_ctxdma;
269 struct page *sg_dummy_page;
270 dma_addr_t sg_dummy_bus;
273 struct drm_ttm_backend *sg_be;
274 unsigned long sg_handle;
277 /* the mtrr covering the FB */
280 struct mem_block *agp_heap;
281 struct mem_block *fb_heap;
282 struct mem_block *fb_nomap_heap;
283 struct mem_block *ramin_heap;
284 struct mem_block *pci_heap;
286 /* context table pointed to be NV_PGRAPH_CHANNEL_CTX_TABLE (0x400780) */
287 uint32_t ctx_table_size;
288 struct nouveau_gpuobj_ref *ctx_table;
290 struct nouveau_config config;
292 struct list_head gpuobj_list;
295 #define NOUVEAU_CHECK_INITIALISED_WITH_RETURN do { \
296 struct drm_nouveau_private *nv = dev->dev_private; \
297 if (nv->init_state != NOUVEAU_CARD_INIT_DONE) { \
298 DRM_ERROR("called without init\n"); \
303 #define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id,cl,ch) do { \
304 struct drm_nouveau_private *nv = dev->dev_private; \
305 if (!nouveau_fifo_owner(dev, (cl), (id))) { \
306 DRM_ERROR("pid %d doesn't own channel %d\n", \
307 DRM_CURRENTPID, (id)); \
310 (ch) = nv->fifos[(id)]; \
313 /* nouveau_state.c */
314 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
315 extern int nouveau_load(struct drm_device *, unsigned long flags);
316 extern int nouveau_firstopen(struct drm_device *);
317 extern void nouveau_lastclose(struct drm_device *);
318 extern int nouveau_unload(struct drm_device *);
319 extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
321 extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
323 extern void nouveau_wait_for_idle(struct drm_device *);
324 extern int nouveau_card_init(struct drm_device *);
325 extern int nouveau_ioctl_card_init(struct drm_device *, void *data,
329 extern int nouveau_mem_init_heap(struct mem_block **, uint64_t start,
331 extern struct mem_block *nouveau_mem_alloc_block(struct mem_block *,
332 uint64_t size, int align2,
334 extern void nouveau_mem_takedown(struct mem_block **heap);
335 extern void nouveau_mem_free_block(struct mem_block *);
336 extern uint64_t nouveau_mem_fb_amount(struct drm_device *);
337 extern void nouveau_mem_release(struct drm_file *, struct mem_block *heap);
338 extern int nouveau_ioctl_mem_alloc(struct drm_device *, void *data,
340 extern int nouveau_ioctl_mem_free(struct drm_device *, void *data,
342 extern struct mem_block* nouveau_mem_alloc(struct drm_device *,
343 int alignment, uint64_t size,
344 int flags, struct drm_file *);
345 extern void nouveau_mem_free(struct drm_device *dev, struct mem_block*);
346 extern int nouveau_mem_init(struct drm_device *);
347 extern void nouveau_mem_close(struct drm_device *);
349 /* nouveau_notifier.c */
350 extern int nouveau_notifier_init_channel(struct nouveau_channel *);
351 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
352 extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
353 int cout, uint32_t *offset);
354 extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
356 extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
360 extern int nouveau_fifo_init(struct drm_device *);
361 extern int nouveau_fifo_number(struct drm_device *);
362 extern int nouveau_fifo_ctx_size(struct drm_device *);
363 extern void nouveau_fifo_cleanup(struct drm_device *, struct drm_file *);
364 extern int nouveau_fifo_owner(struct drm_device *, struct drm_file *,
366 extern int nouveau_fifo_alloc(struct drm_device *dev,
367 struct nouveau_channel **chan,
368 struct drm_file *file_priv,
369 struct mem_block *pushbuf,
370 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
371 extern void nouveau_fifo_free(struct nouveau_channel *);
373 /* nouveau_object.c */
374 extern int nouveau_gpuobj_early_init(struct drm_device *);
375 extern int nouveau_gpuobj_init(struct drm_device *);
376 extern void nouveau_gpuobj_takedown(struct drm_device *);
377 extern void nouveau_gpuobj_late_takedown(struct drm_device *);
378 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
379 uint32_t vram_h, uint32_t tt_h);
380 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
381 extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
382 int size, int align, uint32_t flags,
383 struct nouveau_gpuobj **);
384 extern int nouveau_gpuobj_del(struct drm_device *, struct nouveau_gpuobj **);
385 extern int nouveau_gpuobj_ref_add(struct drm_device *, struct nouveau_channel *,
386 uint32_t handle, struct nouveau_gpuobj *,
387 struct nouveau_gpuobj_ref **);
388 extern int nouveau_gpuobj_ref_del(struct drm_device *,
389 struct nouveau_gpuobj_ref **);
390 extern int nouveau_gpuobj_ref_find(struct nouveau_channel *, uint32_t handle,
391 struct nouveau_gpuobj_ref **ref_ret);
392 extern int nouveau_gpuobj_new_ref(struct drm_device *,
393 struct nouveau_channel *alloc_chan,
394 struct nouveau_channel *ref_chan,
395 uint32_t handle, int size, int align,
396 uint32_t flags, struct nouveau_gpuobj_ref **);
397 extern int nouveau_gpuobj_new_fake(struct drm_device *,
398 uint32_t p_offset, uint32_t b_offset,
399 uint32_t size, uint32_t flags,
400 struct nouveau_gpuobj **,
401 struct nouveau_gpuobj_ref**);
402 extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
403 uint64_t offset, uint64_t size, int access,
404 int target, struct nouveau_gpuobj **);
405 extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
406 uint64_t offset, uint64_t size,
407 int access, struct nouveau_gpuobj **,
409 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
410 struct nouveau_gpuobj **);
411 extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
413 extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
417 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
418 extern void nouveau_irq_preinstall(struct drm_device *);
419 extern int nouveau_irq_postinstall(struct drm_device *);
420 extern void nouveau_irq_uninstall(struct drm_device *);
422 /* nouveau_sgdma.c */
423 extern int nouveau_sgdma_init(struct drm_device *);
424 extern void nouveau_sgdma_takedown(struct drm_device *);
425 extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
427 extern struct drm_ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
428 extern int nouveau_sgdma_nottm_hack_init(struct drm_device *);
429 extern void nouveau_sgdma_nottm_hack_takedown(struct drm_device *);
432 extern int nouveau_dma_channel_init(struct drm_device *);
433 extern void nouveau_dma_channel_takedown(struct drm_device *);
434 extern int nouveau_dma_wait(struct drm_device *, int size);
437 extern int nv04_fb_init(struct drm_device *);
438 extern void nv04_fb_takedown(struct drm_device *);
441 extern int nv10_fb_init(struct drm_device *);
442 extern void nv10_fb_takedown(struct drm_device *);
445 extern int nv40_fb_init(struct drm_device *);
446 extern void nv40_fb_takedown(struct drm_device *);
449 extern int nv04_fifo_create_context(struct nouveau_channel *);
450 extern void nv04_fifo_destroy_context(struct nouveau_channel *);
451 extern int nv04_fifo_load_context(struct nouveau_channel *);
452 extern int nv04_fifo_save_context(struct nouveau_channel *);
455 extern int nv10_fifo_create_context(struct nouveau_channel *);
456 extern void nv10_fifo_destroy_context(struct nouveau_channel *);
457 extern int nv10_fifo_load_context(struct nouveau_channel *);
458 extern int nv10_fifo_save_context(struct nouveau_channel *);
461 extern int nv40_fifo_init(struct drm_device *);
462 extern int nv40_fifo_create_context(struct nouveau_channel *);
463 extern void nv40_fifo_destroy_context(struct nouveau_channel *);
464 extern int nv40_fifo_load_context(struct nouveau_channel *);
465 extern int nv40_fifo_save_context(struct nouveau_channel *);
468 extern int nv50_fifo_init(struct drm_device *);
469 extern void nv50_fifo_takedown(struct drm_device *);
470 extern int nv50_fifo_create_context(struct nouveau_channel *);
471 extern void nv50_fifo_destroy_context(struct nouveau_channel *);
472 extern int nv50_fifo_load_context(struct nouveau_channel *);
473 extern int nv50_fifo_save_context(struct nouveau_channel *);
476 extern void nouveau_nv04_context_switch(struct drm_device *);
477 extern int nv04_graph_init(struct drm_device *);
478 extern void nv04_graph_takedown(struct drm_device *);
479 extern int nv04_graph_create_context(struct nouveau_channel *);
480 extern void nv04_graph_destroy_context(struct nouveau_channel *);
481 extern int nv04_graph_load_context(struct nouveau_channel *);
482 extern int nv04_graph_save_context(struct nouveau_channel *);
485 extern void nouveau_nv10_context_switch(struct drm_device *);
486 extern int nv10_graph_init(struct drm_device *);
487 extern void nv10_graph_takedown(struct drm_device *);
488 extern int nv10_graph_create_context(struct nouveau_channel *);
489 extern void nv10_graph_destroy_context(struct nouveau_channel *);
490 extern int nv10_graph_load_context(struct nouveau_channel *);
491 extern int nv10_graph_save_context(struct nouveau_channel *);
494 extern int nv20_graph_create_context(struct nouveau_channel *);
495 extern void nv20_graph_destroy_context(struct nouveau_channel *);
496 extern int nv20_graph_load_context(struct nouveau_channel *);
497 extern int nv20_graph_save_context(struct nouveau_channel *);
498 extern int nv20_graph_init(struct drm_device *);
499 extern void nv20_graph_takedown(struct drm_device *);
500 extern int nv30_graph_init(struct drm_device *);
503 extern int nv40_graph_init(struct drm_device *);
504 extern void nv40_graph_takedown(struct drm_device *);
505 extern int nv40_graph_create_context(struct nouveau_channel *);
506 extern void nv40_graph_destroy_context(struct nouveau_channel *);
507 extern int nv40_graph_load_context(struct nouveau_channel *);
508 extern int nv40_graph_save_context(struct nouveau_channel *);
511 extern int nv50_graph_init(struct drm_device *);
512 extern void nv50_graph_takedown(struct drm_device *);
513 extern int nv50_graph_create_context(struct nouveau_channel *);
514 extern void nv50_graph_destroy_context(struct nouveau_channel *);
515 extern int nv50_graph_load_context(struct nouveau_channel *);
516 extern int nv50_graph_save_context(struct nouveau_channel *);
519 extern int nv04_instmem_init(struct drm_device *);
520 extern void nv04_instmem_takedown(struct drm_device *);
521 extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
523 extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
524 extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
525 extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
528 extern int nv50_instmem_init(struct drm_device *);
529 extern void nv50_instmem_takedown(struct drm_device *);
530 extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
532 extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
533 extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
534 extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
537 extern int nv04_mc_init(struct drm_device *);
538 extern void nv04_mc_takedown(struct drm_device *);
541 extern int nv40_mc_init(struct drm_device *);
542 extern void nv40_mc_takedown(struct drm_device *);
545 extern int nv50_mc_init(struct drm_device *);
546 extern void nv50_mc_takedown(struct drm_device *);
549 extern int nv04_timer_init(struct drm_device *);
550 extern uint64_t nv04_timer_read(struct drm_device *);
551 extern void nv04_timer_takedown(struct drm_device *);
553 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
556 #if defined(__powerpc__)
557 #define NV_READ(reg) in_be32((void __iomem *)(dev_priv->mmio)->handle + (reg) )
558 #define NV_WRITE(reg,val) out_be32((void __iomem *)(dev_priv->mmio)->handle + (reg) , (val) )
560 #define NV_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
561 #define NV_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
565 #if defined(__powerpc__)
566 #define NV_RI32(o) in_be32((void __iomem *)(dev_priv->ramin)->handle+(o))
567 #define NV_WI32(o,v) out_be32((void __iomem*)(dev_priv->ramin)->handle+(o), (v))
569 #define NV_RI32(o) DRM_READ32(dev_priv->ramin, (o))
570 #define NV_WI32(o,v) DRM_WRITE32(dev_priv->ramin, (o), (v))
573 #define INSTANCE_RD(o,i) NV_RI32((o)->im_pramin->start + ((i)<<2))
574 #define INSTANCE_WR(o,i,v) NV_WI32((o)->im_pramin->start + ((i)<<2), (v))
576 #endif /* __NOUVEAU_DRV_H__ */