2 * Copyright 2005 Stephane Marchesin.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 #ifndef __NOUVEAU_DRV_H__
26 #define __NOUVEAU_DRV_H__
28 #define DRIVER_AUTHOR "Stephane Marchesin"
29 #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
31 #define DRIVER_NAME "nouveau"
32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33 #define DRIVER_DATE "20060213"
35 #define DRIVER_MAJOR 0
36 #define DRIVER_MINOR 0
37 #define DRIVER_PATCHLEVEL 10
39 #define NOUVEAU_FAMILY 0x0000FFFF
40 #define NOUVEAU_FLAGS 0xFFFF0000
42 #include "nouveau_drm.h"
43 #include "nouveau_reg.h"
44 #include "nouveau_bios.h"
46 #define MAX_NUM_DCB_ENTRIES 16
49 struct mem_block *next;
50 struct mem_block *prev;
53 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
56 drm_handle_t map_handle;
60 NV_NFORCE =0x10000000,
61 NV_NFORCE2 =0x20000000
64 #define NVOBJ_ENGINE_SW 0
65 #define NVOBJ_ENGINE_GR 1
66 #define NVOBJ_ENGINE_INT 0xdeadbeef
68 #define NVOBJ_FLAG_ALLOW_NO_REFS (1 << 0)
69 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
70 #define NVOBJ_FLAG_ZERO_FREE (1 << 2)
71 #define NVOBJ_FLAG_FAKE (1 << 3)
72 struct nouveau_gpuobj {
73 struct list_head list;
76 struct mem_block *im_pramin;
77 struct mem_block *im_backing;
86 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
90 struct nouveau_gpuobj_ref {
91 struct list_head list;
93 struct nouveau_gpuobj *gpuobj;
100 struct nouveau_channel
102 struct drm_device *dev;
105 /* owner of this fifo */
106 struct drm_file *file_priv;
107 /* mapping of the fifo itself */
108 drm_local_map_t *map;
109 /* mapping of the regs controling the fifo */
110 drm_local_map_t *regs;
113 uint32_t next_sequence;
115 /* DMA push buffer */
116 struct nouveau_gpuobj_ref *pushbuf;
117 struct mem_block *pushbuf_mem;
118 uint32_t pushbuf_base;
120 /* FIFO user control regs */
121 uint32_t user, user_size;
126 /* Notifier memory */
127 struct mem_block *notifier_block;
128 struct mem_block *notifier_heap;
129 drm_local_map_t *notifier_map;
132 struct nouveau_gpuobj_ref *ramfc;
135 /* XXX may be merge 2 pointers as private data ??? */
136 struct nouveau_gpuobj_ref *ramin_grctx;
140 struct nouveau_gpuobj *vm_pd;
141 struct nouveau_gpuobj_ref *vm_gart_pt;
142 struct nouveau_gpuobj_ref *vm_vram_pt;
145 struct nouveau_gpuobj_ref *ramin; /* Private instmem */
146 struct mem_block *ramin_heap; /* Private PRAMIN heap */
147 struct nouveau_gpuobj_ref *ramht; /* Hash table */
148 struct list_head ramht_refs; /* Objects referenced by RAMHT */
151 struct nouveau_drm_channel {
152 struct nouveau_channel *chan;
155 int max, put, cur, free;
157 volatile uint32_t *pushbuf;
160 uint32_t notify0_offset;
163 uint32_t m2mf_dma_source;
164 uint32_t m2mf_dma_destin;
167 struct nouveau_config {
174 struct nouveau_instmem_engine {
177 int (*init)(struct drm_device *dev);
178 void (*takedown)(struct drm_device *dev);
180 int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
182 void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
183 int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
184 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
187 struct nouveau_mc_engine {
188 int (*init)(struct drm_device *dev);
189 void (*takedown)(struct drm_device *dev);
192 struct nouveau_timer_engine {
193 int (*init)(struct drm_device *dev);
194 void (*takedown)(struct drm_device *dev);
195 uint64_t (*read)(struct drm_device *dev);
198 struct nouveau_fb_engine {
199 int (*init)(struct drm_device *dev);
200 void (*takedown)(struct drm_device *dev);
203 struct nouveau_fifo_engine {
208 int (*init)(struct drm_device *);
209 void (*takedown)(struct drm_device *);
211 int (*channel_id)(struct drm_device *);
213 int (*create_context)(struct nouveau_channel *);
214 void (*destroy_context)(struct nouveau_channel *);
215 int (*load_context)(struct nouveau_channel *);
216 int (*save_context)(struct nouveau_channel *);
219 struct nouveau_pgraph_engine {
220 int (*init)(struct drm_device *);
221 void (*takedown)(struct drm_device *);
223 int (*create_context)(struct nouveau_channel *);
224 void (*destroy_context)(struct nouveau_channel *);
225 int (*load_context)(struct nouveau_channel *);
226 int (*save_context)(struct nouveau_channel *);
229 struct nouveau_engine {
230 struct nouveau_instmem_engine instmem;
231 struct nouveau_mc_engine mc;
232 struct nouveau_timer_engine timer;
233 struct nouveau_fb_engine fb;
234 struct nouveau_pgraph_engine graph;
235 struct nouveau_fifo_engine fifo;
238 #define NOUVEAU_MAX_CHANNEL_NR 128
239 struct drm_nouveau_private {
241 NOUVEAU_CARD_INIT_DOWN,
242 NOUVEAU_CARD_INIT_DONE,
243 NOUVEAU_CARD_INIT_FAILED
248 /* the card type, takes NV_* as values */
250 /* exact chipset, derived from NV_PMC_BOOT_0 */
254 drm_local_map_t *mmio;
256 drm_local_map_t *ramin; /* NV40 onwards */
258 int fifo_alloc_count;
259 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR];
261 struct nouveau_engine Engine;
262 struct nouveau_drm_channel channel;
264 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
265 struct nouveau_gpuobj *ramht;
266 uint32_t ramin_rsvd_vram;
267 uint32_t ramht_offset;
270 uint32_t ramfc_offset;
272 uint32_t ramro_offset;
275 /* base physical adresses */
277 uint64_t fb_available_size;
281 NOUVEAU_GART_NONE = 0,
288 struct nouveau_gpuobj *sg_ctxdma;
289 struct page *sg_dummy_page;
290 dma_addr_t sg_dummy_bus;
293 struct drm_ttm_backend *sg_be;
294 unsigned long sg_handle;
297 /* G8x global VRAM page table */
298 struct nouveau_gpuobj *vm_vram_pt;
300 /* the mtrr covering the FB */
303 struct mem_block *agp_heap;
304 struct mem_block *fb_heap;
305 struct mem_block *fb_nomap_heap;
306 struct mem_block *ramin_heap;
307 struct mem_block *pci_heap;
309 /* context table pointed to be NV_PGRAPH_CHANNEL_CTX_TABLE (0x400780) */
310 uint32_t ctx_table_size;
311 struct nouveau_gpuobj_ref *ctx_table;
313 struct nouveau_config config;
315 struct list_head gpuobj_list;
317 void *display_priv; /* internal modesetting */
318 void *kms_priv; /* related to public interface */
320 /* Hook these up to the "public interface" to accomodate a certain allocation style. */
321 /* This is to avoid polluting the internal interface. */
322 void *(*alloc_crtc) (struct drm_device *dev);
323 void *(*alloc_output) (struct drm_device *dev);
324 void *(*alloc_connector) (struct drm_device *dev);
326 void (*free_crtc) (void *crtc);
327 void (*free_output) (void *output);
328 void (*free_connector) (void *connector);
334 struct dcb_entry entry[MAX_NUM_DCB_ENTRIES];
335 unsigned char i2c_read[MAX_NUM_DCB_ENTRIES];
336 unsigned char i2c_write[MAX_NUM_DCB_ENTRIES];
340 #define NOUVEAU_CHECK_INITIALISED_WITH_RETURN do { \
341 struct drm_nouveau_private *nv = dev->dev_private; \
342 if (nv->init_state != NOUVEAU_CARD_INIT_DONE) { \
343 DRM_ERROR("called without init\n"); \
348 #define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id,cl,ch) do { \
349 struct drm_nouveau_private *nv = dev->dev_private; \
350 if (!nouveau_fifo_owner(dev, (cl), (id))) { \
351 DRM_ERROR("pid %d doesn't own channel %d\n", \
352 DRM_CURRENTPID, (id)); \
355 (ch) = nv->fifos[(id)]; \
358 /* nouveau_state.c */
359 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
360 extern int nouveau_load(struct drm_device *, unsigned long flags);
361 extern int nouveau_firstopen(struct drm_device *);
362 extern void nouveau_lastclose(struct drm_device *);
363 extern int nouveau_unload(struct drm_device *);
364 extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
366 extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
368 extern void nouveau_wait_for_idle(struct drm_device *);
369 extern int nouveau_card_init(struct drm_device *);
370 extern int nouveau_ioctl_card_init(struct drm_device *, void *data,
374 extern int nouveau_mem_init_heap(struct mem_block **, uint64_t start,
376 extern struct mem_block *nouveau_mem_alloc_block(struct mem_block *,
377 uint64_t size, int align2,
379 extern void nouveau_mem_takedown(struct mem_block **heap);
380 extern void nouveau_mem_free_block(struct mem_block *);
381 extern struct mem_block* find_block_by_handle(struct mem_block *heap, drm_handle_t handle);
382 extern uint64_t nouveau_mem_fb_amount(struct drm_device *);
383 extern void nouveau_mem_release(struct drm_file *, struct mem_block *heap);
384 extern int nouveau_ioctl_mem_alloc(struct drm_device *, void *data,
386 extern int nouveau_ioctl_mem_free(struct drm_device *, void *data,
388 extern struct mem_block* nouveau_mem_alloc(struct drm_device *,
389 int alignment, uint64_t size,
390 int flags, struct drm_file *);
391 extern void nouveau_mem_free(struct drm_device *dev, struct mem_block*);
392 extern int nouveau_mem_init(struct drm_device *);
393 extern int nouveau_mem_init_ttm(struct drm_device *);
394 extern void nouveau_mem_close(struct drm_device *);
396 /* nouveau_notifier.c */
397 extern int nouveau_notifier_init_channel(struct nouveau_channel *);
398 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
399 extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
400 int cout, uint32_t *offset);
401 extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
403 extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
407 extern int nouveau_fifo_init(struct drm_device *);
408 extern int nouveau_fifo_ctx_size(struct drm_device *);
409 extern void nouveau_fifo_cleanup(struct drm_device *, struct drm_file *);
410 extern int nouveau_fifo_owner(struct drm_device *, struct drm_file *,
412 extern int nouveau_fifo_alloc(struct drm_device *dev,
413 struct nouveau_channel **chan,
414 struct drm_file *file_priv,
415 struct mem_block *pushbuf,
416 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
417 extern void nouveau_fifo_free(struct nouveau_channel *);
419 /* nouveau_object.c */
420 extern int nouveau_gpuobj_early_init(struct drm_device *);
421 extern int nouveau_gpuobj_init(struct drm_device *);
422 extern void nouveau_gpuobj_takedown(struct drm_device *);
423 extern void nouveau_gpuobj_late_takedown(struct drm_device *);
424 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
425 uint32_t vram_h, uint32_t tt_h);
426 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
427 extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
428 int size, int align, uint32_t flags,
429 struct nouveau_gpuobj **);
430 extern int nouveau_gpuobj_del(struct drm_device *, struct nouveau_gpuobj **);
431 extern int nouveau_gpuobj_ref_add(struct drm_device *, struct nouveau_channel *,
432 uint32_t handle, struct nouveau_gpuobj *,
433 struct nouveau_gpuobj_ref **);
434 extern int nouveau_gpuobj_ref_del(struct drm_device *,
435 struct nouveau_gpuobj_ref **);
436 extern int nouveau_gpuobj_ref_find(struct nouveau_channel *, uint32_t handle,
437 struct nouveau_gpuobj_ref **ref_ret);
438 extern int nouveau_gpuobj_new_ref(struct drm_device *,
439 struct nouveau_channel *alloc_chan,
440 struct nouveau_channel *ref_chan,
441 uint32_t handle, int size, int align,
442 uint32_t flags, struct nouveau_gpuobj_ref **);
443 extern int nouveau_gpuobj_new_fake(struct drm_device *,
444 uint32_t p_offset, uint32_t b_offset,
445 uint32_t size, uint32_t flags,
446 struct nouveau_gpuobj **,
447 struct nouveau_gpuobj_ref**);
448 extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
449 uint64_t offset, uint64_t size, int access,
450 int target, struct nouveau_gpuobj **);
451 extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
452 uint64_t offset, uint64_t size,
453 int access, struct nouveau_gpuobj **,
455 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
456 struct nouveau_gpuobj **);
457 extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
459 extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
463 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
464 extern void nouveau_irq_preinstall(struct drm_device *);
465 extern int nouveau_irq_postinstall(struct drm_device *);
466 extern void nouveau_irq_uninstall(struct drm_device *);
468 /* nouveau_sgdma.c */
469 extern int nouveau_sgdma_init(struct drm_device *);
470 extern void nouveau_sgdma_takedown(struct drm_device *);
471 extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
473 extern struct drm_ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
474 extern int nouveau_sgdma_nottm_hack_init(struct drm_device *);
475 extern void nouveau_sgdma_nottm_hack_takedown(struct drm_device *);
478 extern int nouveau_dma_channel_init(struct drm_device *);
479 extern void nouveau_dma_channel_takedown(struct drm_device *);
480 extern int nouveau_dma_wait(struct drm_device *, int size);
483 extern int nv04_fb_init(struct drm_device *);
484 extern void nv04_fb_takedown(struct drm_device *);
487 extern int nv10_fb_init(struct drm_device *);
488 extern void nv10_fb_takedown(struct drm_device *);
491 extern int nv40_fb_init(struct drm_device *);
492 extern void nv40_fb_takedown(struct drm_device *);
495 extern int nv04_fifo_channel_id(struct drm_device *);
496 extern int nv04_fifo_create_context(struct nouveau_channel *);
497 extern void nv04_fifo_destroy_context(struct nouveau_channel *);
498 extern int nv04_fifo_load_context(struct nouveau_channel *);
499 extern int nv04_fifo_save_context(struct nouveau_channel *);
502 extern int nv10_fifo_channel_id(struct drm_device *);
503 extern int nv10_fifo_create_context(struct nouveau_channel *);
504 extern void nv10_fifo_destroy_context(struct nouveau_channel *);
505 extern int nv10_fifo_load_context(struct nouveau_channel *);
506 extern int nv10_fifo_save_context(struct nouveau_channel *);
509 extern int nv40_fifo_init(struct drm_device *);
510 extern int nv40_fifo_create_context(struct nouveau_channel *);
511 extern void nv40_fifo_destroy_context(struct nouveau_channel *);
512 extern int nv40_fifo_load_context(struct nouveau_channel *);
513 extern int nv40_fifo_save_context(struct nouveau_channel *);
516 extern int nv50_fifo_init(struct drm_device *);
517 extern void nv50_fifo_takedown(struct drm_device *);
518 extern int nv50_fifo_channel_id(struct drm_device *);
519 extern int nv50_fifo_create_context(struct nouveau_channel *);
520 extern void nv50_fifo_destroy_context(struct nouveau_channel *);
521 extern int nv50_fifo_load_context(struct nouveau_channel *);
522 extern int nv50_fifo_save_context(struct nouveau_channel *);
525 extern void nouveau_nv04_context_switch(struct drm_device *);
526 extern int nv04_graph_init(struct drm_device *);
527 extern void nv04_graph_takedown(struct drm_device *);
528 extern int nv04_graph_create_context(struct nouveau_channel *);
529 extern void nv04_graph_destroy_context(struct nouveau_channel *);
530 extern int nv04_graph_load_context(struct nouveau_channel *);
531 extern int nv04_graph_save_context(struct nouveau_channel *);
534 extern void nouveau_nv10_context_switch(struct drm_device *);
535 extern int nv10_graph_init(struct drm_device *);
536 extern void nv10_graph_takedown(struct drm_device *);
537 extern int nv10_graph_create_context(struct nouveau_channel *);
538 extern void nv10_graph_destroy_context(struct nouveau_channel *);
539 extern int nv10_graph_load_context(struct nouveau_channel *);
540 extern int nv10_graph_save_context(struct nouveau_channel *);
543 extern int nv20_graph_create_context(struct nouveau_channel *);
544 extern void nv20_graph_destroy_context(struct nouveau_channel *);
545 extern int nv20_graph_load_context(struct nouveau_channel *);
546 extern int nv20_graph_save_context(struct nouveau_channel *);
547 extern int nv20_graph_init(struct drm_device *);
548 extern void nv20_graph_takedown(struct drm_device *);
549 extern int nv30_graph_init(struct drm_device *);
552 extern int nv40_graph_init(struct drm_device *);
553 extern void nv40_graph_takedown(struct drm_device *);
554 extern int nv40_graph_create_context(struct nouveau_channel *);
555 extern void nv40_graph_destroy_context(struct nouveau_channel *);
556 extern int nv40_graph_load_context(struct nouveau_channel *);
557 extern int nv40_graph_save_context(struct nouveau_channel *);
560 extern int nv50_graph_init(struct drm_device *);
561 extern void nv50_graph_takedown(struct drm_device *);
562 extern int nv50_graph_create_context(struct nouveau_channel *);
563 extern void nv50_graph_destroy_context(struct nouveau_channel *);
564 extern int nv50_graph_load_context(struct nouveau_channel *);
565 extern int nv50_graph_save_context(struct nouveau_channel *);
568 extern int nv04_instmem_init(struct drm_device *);
569 extern void nv04_instmem_takedown(struct drm_device *);
570 extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
572 extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
573 extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
574 extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
577 extern int nv50_instmem_init(struct drm_device *);
578 extern void nv50_instmem_takedown(struct drm_device *);
579 extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
581 extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
582 extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
583 extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
586 extern int nv04_mc_init(struct drm_device *);
587 extern void nv04_mc_takedown(struct drm_device *);
590 extern int nv40_mc_init(struct drm_device *);
591 extern void nv40_mc_takedown(struct drm_device *);
594 extern int nv50_mc_init(struct drm_device *);
595 extern void nv50_mc_takedown(struct drm_device *);
598 extern int nv04_timer_init(struct drm_device *);
599 extern uint64_t nv04_timer_read(struct drm_device *);
600 extern void nv04_timer_takedown(struct drm_device *);
602 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
605 /* nouveau_buffer.c */
606 extern struct drm_bo_driver nouveau_bo_driver;
608 /* nouveau_fence.c */
609 extern struct drm_fence_driver nouveau_fence_driver;
610 extern void nouveau_fence_handler(struct drm_device *dev, int channel);
612 #if defined(__powerpc__)
613 #define NV_READ(reg) in_be32((void __iomem *)(dev_priv->mmio)->handle + (reg) )
614 #define NV_WRITE(reg,val) out_be32((void __iomem *)(dev_priv->mmio)->handle + (reg) , (val) )
616 #define NV_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
617 #define NV_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
621 #if defined(__powerpc__)
622 #define NV_RI32(o) in_be32((void __iomem *)(dev_priv->ramin)->handle+(o))
623 #define NV_WI32(o,v) out_be32((void __iomem*)(dev_priv->ramin)->handle+(o), (v))
625 #define NV_RI32(o) DRM_READ32(dev_priv->ramin, (o))
626 #define NV_WI32(o,v) DRM_WRITE32(dev_priv->ramin, (o), (v))
629 #define INSTANCE_RD(o,i) NV_RI32((o)->im_pramin->start + ((i)<<2))
630 #define INSTANCE_WR(o,i,v) NV_WI32((o)->im_pramin->start + ((i)<<2), (v))
632 #endif /* __NOUVEAU_DRV_H__ */