2 * Copyright 2005 Stephane Marchesin.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 #ifndef __NOUVEAU_DRV_H__
26 #define __NOUVEAU_DRV_H__
28 #define DRIVER_AUTHOR "Stephane Marchesin"
29 #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
31 #define DRIVER_NAME "nouveau"
32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33 #define DRIVER_DATE "20060213"
35 #define DRIVER_MAJOR 0
36 #define DRIVER_MINOR 0
37 #define DRIVER_PATCHLEVEL 7
39 #define NOUVEAU_FAMILY 0x0000FFFF
40 #define NOUVEAU_FLAGS 0xFFFF0000
42 #include "nouveau_drm.h"
43 #include "nouveau_reg.h"
46 struct mem_block *next;
47 struct mem_block *prev;
50 DRMFILE filp; /* 0: free, -1: heap, other: real files */
56 NV_NFORCE =0x10000000,
57 NV_NFORCE2 =0x20000000
60 #define NVOBJ_ENGINE_SW 0
61 #define NVOBJ_ENGINE_GR 1
62 #define NVOBJ_ENGINE_INT 0xdeadbeef
64 #define NVOBJ_FLAG_ALLOW_NO_REFS (1 << 0)
65 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
66 #define NVOBJ_FLAG_ZERO_FREE (1 << 2)
67 #define NVOBJ_FLAG_FAKE (1 << 3)
68 typedef struct nouveau_gpuobj {
69 struct nouveau_gpuobj *next;
70 struct nouveau_gpuobj *prev;
73 struct mem_block *im_pramin;
74 struct mem_block *im_backing;
84 typedef struct nouveau_gpuobj_ref {
85 struct nouveau_gpuobj_ref *next;
87 nouveau_gpuobj_t *gpuobj;
92 } nouveau_gpuobj_ref_t;
96 /* owner of this fifo */
98 /* mapping of the fifo itself */
100 /* mapping of the regs controling the fifo */
101 drm_local_map_t *regs;
103 /* DMA push buffer */
104 nouveau_gpuobj_ref_t *pushbuf;
105 struct mem_block *pushbuf_mem;
106 uint32_t pushbuf_base;
108 /* Notifier memory */
109 struct mem_block *notifier_block;
110 struct mem_block *notifier_heap;
111 drm_local_map_t *notifier_map;
114 nouveau_gpuobj_ref_t *ramfc;
117 nouveau_gpuobj_ref_t *ramin_grctx;
118 uint32_t pgraph_ctx [340]; /* XXX dynamic alloc ? */
121 nouveau_gpuobj_ref_t *ramin; /* Private instmem */
122 struct mem_block *ramin_heap; /* Private PRAMIN heap */
123 nouveau_gpuobj_ref_t *ramht; /* Hash table */
124 nouveau_gpuobj_ref_t *ramht_refs; /* Objects referenced by RAMHT */
127 struct nouveau_config {
134 typedef struct nouveau_engine_func {
138 int (*init)(drm_device_t *dev);
139 void (*takedown)(drm_device_t *dev);
141 int (*populate)(drm_device_t *, nouveau_gpuobj_t *,
143 void (*clear)(drm_device_t *, nouveau_gpuobj_t *);
144 int (*bind)(drm_device_t *, nouveau_gpuobj_t *);
145 int (*unbind)(drm_device_t *, nouveau_gpuobj_t *);
149 int (*init)(drm_device_t *dev);
150 void (*takedown)(drm_device_t *dev);
154 int (*init)(drm_device_t *dev);
155 void (*takedown)(drm_device_t *dev);
159 int (*init)(drm_device_t *dev);
160 void (*takedown)(drm_device_t *dev);
164 int (*init)(drm_device_t *);
165 void (*takedown)(drm_device_t *);
167 int (*create_context)(drm_device_t *, int channel);
168 void (*destroy_context)(drm_device_t *, int channel);
169 int (*load_context)(drm_device_t *, int channel);
170 int (*save_context)(drm_device_t *, int channel);
176 int (*init)(drm_device_t *);
177 void (*takedown)(drm_device_t *);
179 int (*create_context)(drm_device_t *, int channel);
180 void (*destroy_context)(drm_device_t *, int channel);
181 int (*load_context)(drm_device_t *, int channel);
182 int (*save_context)(drm_device_t *, int channel);
184 } nouveau_engine_func_t;
186 typedef struct drm_nouveau_private {
188 NOUVEAU_CARD_INIT_DOWN,
189 NOUVEAU_CARD_INIT_DONE,
190 NOUVEAU_CARD_INIT_FAILED
193 /* the card type, takes NV_* as values */
195 /* exact chipset, derived from NV_PMC_BOOT_0 */
199 drm_local_map_t *mmio;
201 drm_local_map_t *ramin; /* NV40 onwards */
203 int fifo_alloc_count;
204 struct nouveau_fifo *fifos[NV_MAX_FIFO_NUMBER];
206 struct nouveau_engine_func Engine;
208 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
209 nouveau_gpuobj_t *ramht;
210 uint32_t ramin_rsvd_vram;
211 uint32_t ramht_offset;
214 uint32_t ramfc_offset;
216 uint32_t ramro_offset;
219 /* base physical adresses */
221 uint64_t fb_available_size;
223 uint64_t agp_available_size;
225 /* the mtrr covering the FB */
228 struct mem_block *agp_heap;
229 struct mem_block *fb_heap;
230 struct mem_block *fb_nomap_heap;
231 struct mem_block *ramin_heap;
233 /* context table pointed to be NV_PGRAPH_CHANNEL_CTX_TABLE (0x400780) */
234 uint32_t ctx_table_size;
235 nouveau_gpuobj_ref_t *ctx_table;
237 struct nouveau_config config;
239 nouveau_gpuobj_t *gpuobj_all;
241 drm_nouveau_private_t;
243 /* nouveau_state.c */
244 extern void nouveau_preclose(drm_device_t * dev, DRMFILE filp);
245 extern int nouveau_load(struct drm_device *dev, unsigned long flags);
246 extern int nouveau_firstopen(struct drm_device *dev);
247 extern void nouveau_lastclose(struct drm_device *dev);
248 extern int nouveau_unload(struct drm_device *dev);
249 extern int nouveau_ioctl_getparam(DRM_IOCTL_ARGS);
250 extern int nouveau_ioctl_setparam(DRM_IOCTL_ARGS);
251 extern void nouveau_wait_for_idle(struct drm_device *dev);
252 extern int nouveau_ioctl_card_init(DRM_IOCTL_ARGS);
255 extern int nouveau_mem_init_heap(struct mem_block **,
256 uint64_t start, uint64_t size);
257 extern struct mem_block *nouveau_mem_alloc_block(struct mem_block *,
258 uint64_t size, int align2,
260 extern void nouveau_mem_takedown(struct mem_block **heap);
261 extern void nouveau_mem_free_block(struct mem_block *);
262 extern uint64_t nouveau_mem_fb_amount(struct drm_device *dev);
263 extern void nouveau_mem_release(DRMFILE filp, struct mem_block *heap);
264 extern int nouveau_ioctl_mem_alloc(DRM_IOCTL_ARGS);
265 extern int nouveau_ioctl_mem_free(DRM_IOCTL_ARGS);
266 extern struct mem_block* nouveau_mem_alloc(struct drm_device *dev, int alignment, uint64_t size, int flags, DRMFILE filp);
267 extern void nouveau_mem_free(struct drm_device* dev, struct mem_block*);
268 extern int nouveau_mem_init(struct drm_device *dev);
269 extern void nouveau_mem_close(struct drm_device *dev);
271 /* nouveau_notifier.c */
272 extern int nouveau_notifier_init_channel(drm_device_t *, int channel, DRMFILE);
273 extern void nouveau_notifier_takedown_channel(drm_device_t *, int channel);
274 extern int nouveau_notifier_alloc(drm_device_t *, int channel,
275 uint32_t handle, int cout, uint32_t *offset);
276 extern int nouveau_ioctl_notifier_alloc(DRM_IOCTL_ARGS);
279 extern int nouveau_fifo_init(drm_device_t *dev);
280 extern int nouveau_fifo_number(drm_device_t *dev);
281 extern int nouveau_fifo_ctx_size(drm_device_t *dev);
282 extern void nouveau_fifo_cleanup(drm_device_t *dev, DRMFILE filp);
283 extern int nouveau_fifo_owner(drm_device_t *dev, DRMFILE filp, int channel);
284 extern void nouveau_fifo_free(drm_device_t *dev, int channel);
286 /* nouveau_object.c */
287 extern void nouveau_gpuobj_takedown(drm_device_t *dev);
288 extern int nouveau_gpuobj_channel_init(drm_device_t *, int channel,
289 uint32_t vram_h, uint32_t tt_h);
290 extern void nouveau_gpuobj_channel_takedown(drm_device_t *, int channel);
291 extern int nouveau_gpuobj_new(drm_device_t *, int channel, int size, int align,
292 uint32_t flags, nouveau_gpuobj_t **);
293 extern int nouveau_gpuobj_del(drm_device_t *, nouveau_gpuobj_t **);
294 extern int nouveau_gpuobj_ref_add(drm_device_t *, int channel, uint32_t handle,
295 nouveau_gpuobj_t *, nouveau_gpuobj_ref_t **);
296 extern int nouveau_gpuobj_ref_del(drm_device_t *, nouveau_gpuobj_ref_t **);
297 extern int nouveau_gpuobj_new_ref(drm_device_t *, int chan_obj, int chan_ref,
298 uint32_t handle, int size, int align,
299 uint32_t flags, nouveau_gpuobj_ref_t **);
300 extern int nouveau_gpuobj_new_fake(drm_device_t *, uint32_t offset,
301 uint32_t size, uint32_t flags,
302 nouveau_gpuobj_t**, nouveau_gpuobj_ref_t**);
303 extern int nouveau_gpuobj_dma_new(drm_device_t *, int channel, int class,
304 uint64_t offset, uint64_t size,
305 int access, int target, nouveau_gpuobj_t **);
306 extern int nouveau_gpuobj_gr_new(drm_device_t *, int channel, int class,
307 nouveau_gpuobj_t **);
308 extern int nouveau_ioctl_grobj_alloc(DRM_IOCTL_ARGS);
311 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
312 extern void nouveau_irq_preinstall(drm_device_t*);
313 extern void nouveau_irq_postinstall(drm_device_t*);
314 extern void nouveau_irq_uninstall(drm_device_t*);
317 extern int nv04_fb_init(drm_device_t *dev);
318 extern void nv04_fb_takedown(drm_device_t *dev);
321 extern int nv10_fb_init(drm_device_t *dev);
322 extern void nv10_fb_takedown(drm_device_t *dev);
325 extern int nv40_fb_init(drm_device_t *dev);
326 extern void nv40_fb_takedown(drm_device_t *dev);
329 extern int nv04_fifo_create_context(drm_device_t *dev, int channel);
330 extern void nv04_fifo_destroy_context(drm_device_t *dev, int channel);
331 extern int nv04_fifo_load_context(drm_device_t *dev, int channel);
332 extern int nv04_fifo_save_context(drm_device_t *dev, int channel);
335 extern int nv10_fifo_create_context(drm_device_t *dev, int channel);
336 extern void nv10_fifo_destroy_context(drm_device_t *dev, int channel);
337 extern int nv10_fifo_load_context(drm_device_t *dev, int channel);
338 extern int nv10_fifo_save_context(drm_device_t *dev, int channel);
341 extern int nv40_fifo_create_context(drm_device_t *, int channel);
342 extern void nv40_fifo_destroy_context(drm_device_t *, int channel);
343 extern int nv40_fifo_load_context(drm_device_t *, int channel);
344 extern int nv40_fifo_save_context(drm_device_t *, int channel);
347 extern int nv50_fifo_init(drm_device_t *);
348 extern void nv50_fifo_takedown(drm_device_t *);
349 extern int nv50_fifo_create_context(drm_device_t *, int channel);
350 extern void nv50_fifo_destroy_context(drm_device_t *, int channel);
351 extern int nv50_fifo_load_context(drm_device_t *, int channel);
352 extern int nv50_fifo_save_context(drm_device_t *, int channel);
355 extern void nouveau_nv04_context_switch(drm_device_t *dev);
356 extern int nv04_graph_init(drm_device_t *dev);
357 extern void nv04_graph_takedown(drm_device_t *dev);
358 extern int nv04_graph_create_context(drm_device_t *dev, int channel);
359 extern void nv04_graph_destroy_context(drm_device_t *dev, int channel);
360 extern int nv04_graph_load_context(drm_device_t *dev, int channel);
361 extern int nv04_graph_save_context(drm_device_t *dev, int channel);
364 extern void nouveau_nv10_context_switch(drm_device_t *dev);
365 extern int nv10_graph_init(drm_device_t *dev);
366 extern void nv10_graph_takedown(drm_device_t *dev);
367 extern int nv10_graph_create_context(drm_device_t *dev, int channel);
368 extern void nv10_graph_destroy_context(drm_device_t *dev, int channel);
369 extern int nv10_graph_load_context(drm_device_t *dev, int channel);
370 extern int nv10_graph_save_context(drm_device_t *dev, int channel);
373 extern void nouveau_nv20_context_switch(drm_device_t *dev);
374 extern int nv20_graph_init(drm_device_t *dev);
375 extern void nv20_graph_takedown(drm_device_t *dev);
376 extern int nv20_graph_create_context(drm_device_t *dev, int channel);
377 extern void nv20_graph_destroy_context(drm_device_t *dev, int channel);
378 extern int nv20_graph_load_context(drm_device_t *dev, int channel);
379 extern int nv20_graph_save_context(drm_device_t *dev, int channel);
382 extern int nv30_graph_init(drm_device_t *dev);
383 extern void nv30_graph_takedown(drm_device_t *dev);
384 extern int nv30_graph_create_context(drm_device_t *, int channel);
385 extern void nv30_graph_destroy_context(drm_device_t *, int channel);
386 extern int nv30_graph_load_context(drm_device_t *, int channel);
387 extern int nv30_graph_save_context(drm_device_t *, int channel);
390 extern int nv40_graph_init(drm_device_t *);
391 extern void nv40_graph_takedown(drm_device_t *);
392 extern int nv40_graph_create_context(drm_device_t *, int channel);
393 extern void nv40_graph_destroy_context(drm_device_t *, int channel);
394 extern int nv40_graph_load_context(drm_device_t *, int channel);
395 extern int nv40_graph_save_context(drm_device_t *, int channel);
398 extern int nv50_graph_init(drm_device_t *);
399 extern void nv50_graph_takedown(drm_device_t *);
400 extern int nv50_graph_create_context(drm_device_t *, int channel);
401 extern void nv50_graph_destroy_context(drm_device_t *, int channel);
402 extern int nv50_graph_load_context(drm_device_t *, int channel);
403 extern int nv50_graph_save_context(drm_device_t *, int channel);
406 extern int nv04_instmem_init(drm_device_t *dev);
407 extern void nv04_instmem_takedown(drm_device_t *dev);
408 extern int nv04_instmem_populate(drm_device_t*, nouveau_gpuobj_t*,
410 extern void nv04_instmem_clear(drm_device_t*, nouveau_gpuobj_t*);
411 extern int nv04_instmem_bind(drm_device_t*, nouveau_gpuobj_t*);
412 extern int nv04_instmem_unbind(drm_device_t*, nouveau_gpuobj_t*);
415 extern int nv50_instmem_init(drm_device_t *dev);
416 extern void nv50_instmem_takedown(drm_device_t *dev);
417 extern int nv50_instmem_populate(drm_device_t*, nouveau_gpuobj_t*,
419 extern void nv50_instmem_clear(drm_device_t*, nouveau_gpuobj_t*);
420 extern int nv50_instmem_bind(drm_device_t*, nouveau_gpuobj_t*);
421 extern int nv50_instmem_unbind(drm_device_t*, nouveau_gpuobj_t*);
424 extern int nv04_mc_init(drm_device_t *dev);
425 extern void nv04_mc_takedown(drm_device_t *dev);
428 extern int nv40_mc_init(drm_device_t *dev);
429 extern void nv40_mc_takedown(drm_device_t *dev);
432 extern int nv50_mc_init(drm_device_t *dev);
433 extern void nv50_mc_takedown(drm_device_t *dev);
436 extern int nv04_timer_init(drm_device_t *dev);
437 extern void nv04_timer_takedown(drm_device_t *dev);
439 extern long nouveau_compat_ioctl(struct file *filp, unsigned int cmd,
442 #if defined(__powerpc__)
443 #define NV_READ(reg) in_be32((void __iomem *)(dev_priv->mmio)->handle + (reg) )
444 #define NV_WRITE(reg,val) out_be32((void __iomem *)(dev_priv->mmio)->handle + (reg) , (val) )
446 #define NV_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
447 #define NV_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
451 #if defined(__powerpc__)
452 #define NV_RI32(o) in_be32((void __iomem *)(dev_priv->ramin)->handle+(o))
453 #define NV_WI32(o,v) out_be32((void __iomem*)(dev_priv->ramin)->handle+(o), (v))
455 #define NV_RI32(o) DRM_READ32(dev_priv->ramin, (o))
456 #define NV_WI32(o,v) DRM_WRITE32(dev_priv->ramin, (o), (v))
459 #define INSTANCE_RD(o,i) NV_RI32((o)->im_pramin->start + ((i)<<2))
460 #define INSTANCE_WR(o,i,v) NV_WI32((o)->im_pramin->start + ((i)<<2), (v))
462 #endif /* __NOUVEAU_DRV_H__ */