2 * Copyright 2005 Stephane Marchesin.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 #ifndef __NOUVEAU_DRV_H__
26 #define __NOUVEAU_DRV_H__
28 #define DRIVER_AUTHOR "Stephane Marchesin"
29 #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
31 #define DRIVER_NAME "nouveau"
32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33 #define DRIVER_DATE "20060213"
35 #define DRIVER_MAJOR 0
36 #define DRIVER_MINOR 0
37 #define DRIVER_PATCHLEVEL 10
39 #define NOUVEAU_FAMILY 0x0000FFFF
40 #define NOUVEAU_FLAGS 0xFFFF0000
42 #include "nouveau_drm.h"
43 #include "nouveau_reg.h"
46 struct mem_block *next;
47 struct mem_block *prev;
50 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
53 drm_handle_t map_handle;
57 NV_NFORCE =0x10000000,
58 NV_NFORCE2 =0x20000000
61 #define NVOBJ_ENGINE_SW 0
62 #define NVOBJ_ENGINE_GR 1
63 #define NVOBJ_ENGINE_INT 0xdeadbeef
65 #define NVOBJ_FLAG_ALLOW_NO_REFS (1 << 0)
66 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
67 #define NVOBJ_FLAG_ZERO_FREE (1 << 2)
68 #define NVOBJ_FLAG_FAKE (1 << 3)
69 struct nouveau_gpuobj {
70 struct list_head list;
73 struct mem_block *im_pramin;
74 struct mem_block *im_backing;
83 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
87 struct nouveau_gpuobj_ref {
88 struct list_head list;
90 struct nouveau_gpuobj *gpuobj;
97 struct nouveau_channel
99 struct drm_device *dev;
102 /* owner of this fifo */
103 struct drm_file *file_priv;
104 /* mapping of the fifo itself */
105 drm_local_map_t *map;
106 /* mapping of the regs controling the fifo */
107 drm_local_map_t *regs;
110 uint32_t next_sequence;
112 /* DMA push buffer */
113 struct nouveau_gpuobj_ref *pushbuf;
114 struct mem_block *pushbuf_mem;
115 uint32_t pushbuf_base;
117 /* FIFO user control regs */
118 uint32_t user, user_size;
123 /* Notifier memory */
124 struct mem_block *notifier_block;
125 struct mem_block *notifier_heap;
126 drm_local_map_t *notifier_map;
129 struct nouveau_gpuobj_ref *ramfc;
132 /* XXX may be merge 2 pointers as private data ??? */
133 struct nouveau_gpuobj_ref *ramin_grctx;
137 struct nouveau_gpuobj *vm_pd;
138 struct nouveau_gpuobj_ref *vm_gart_pt;
141 struct nouveau_gpuobj_ref *ramin; /* Private instmem */
142 struct mem_block *ramin_heap; /* Private PRAMIN heap */
143 struct nouveau_gpuobj_ref *ramht; /* Hash table */
144 struct list_head ramht_refs; /* Objects referenced by RAMHT */
147 struct nouveau_drm_channel {
148 struct nouveau_channel *chan;
151 int max, put, cur, free;
153 volatile uint32_t *pushbuf;
156 uint32_t notify0_offset;
159 uint32_t m2mf_dma_source;
160 uint32_t m2mf_dma_destin;
163 struct nouveau_config {
170 struct nouveau_instmem_engine {
173 int (*init)(struct drm_device *dev);
174 void (*takedown)(struct drm_device *dev);
176 int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
178 void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
179 int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
180 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
183 struct nouveau_mc_engine {
184 int (*init)(struct drm_device *dev);
185 void (*takedown)(struct drm_device *dev);
188 struct nouveau_timer_engine {
189 int (*init)(struct drm_device *dev);
190 void (*takedown)(struct drm_device *dev);
191 uint64_t (*read)(struct drm_device *dev);
194 struct nouveau_fb_engine {
195 int (*init)(struct drm_device *dev);
196 void (*takedown)(struct drm_device *dev);
199 struct nouveau_fifo_engine {
204 int (*init)(struct drm_device *);
205 void (*takedown)(struct drm_device *);
207 int (*channel_id)(struct drm_device *);
209 int (*create_context)(struct nouveau_channel *);
210 void (*destroy_context)(struct nouveau_channel *);
211 int (*load_context)(struct nouveau_channel *);
212 int (*save_context)(struct nouveau_channel *);
215 struct nouveau_pgraph_engine {
216 int (*init)(struct drm_device *);
217 void (*takedown)(struct drm_device *);
219 int (*create_context)(struct nouveau_channel *);
220 void (*destroy_context)(struct nouveau_channel *);
221 int (*load_context)(struct nouveau_channel *);
222 int (*save_context)(struct nouveau_channel *);
225 struct nouveau_engine {
226 struct nouveau_instmem_engine instmem;
227 struct nouveau_mc_engine mc;
228 struct nouveau_timer_engine timer;
229 struct nouveau_fb_engine fb;
230 struct nouveau_pgraph_engine graph;
231 struct nouveau_fifo_engine fifo;
234 #define NOUVEAU_MAX_CHANNEL_NR 128
235 struct drm_nouveau_private {
237 NOUVEAU_CARD_INIT_DOWN,
238 NOUVEAU_CARD_INIT_DONE,
239 NOUVEAU_CARD_INIT_FAILED
244 /* the card type, takes NV_* as values */
246 /* exact chipset, derived from NV_PMC_BOOT_0 */
250 drm_local_map_t *mmio;
252 drm_local_map_t *ramin; /* NV40 onwards */
254 int fifo_alloc_count;
255 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR];
257 struct nouveau_engine Engine;
258 struct nouveau_drm_channel channel;
260 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
261 struct nouveau_gpuobj *ramht;
262 uint32_t ramin_rsvd_vram;
263 uint32_t ramht_offset;
266 uint32_t ramfc_offset;
268 uint32_t ramro_offset;
271 /* base physical adresses */
273 uint64_t fb_available_size;
277 NOUVEAU_GART_NONE = 0,
284 struct nouveau_gpuobj *sg_ctxdma;
285 struct page *sg_dummy_page;
286 dma_addr_t sg_dummy_bus;
289 struct drm_ttm_backend *sg_be;
290 unsigned long sg_handle;
293 /* the mtrr covering the FB */
296 struct mem_block *agp_heap;
297 struct mem_block *fb_heap;
298 struct mem_block *fb_nomap_heap;
299 struct mem_block *ramin_heap;
300 struct mem_block *pci_heap;
302 /* context table pointed to be NV_PGRAPH_CHANNEL_CTX_TABLE (0x400780) */
303 uint32_t ctx_table_size;
304 struct nouveau_gpuobj_ref *ctx_table;
306 struct nouveau_config config;
308 struct list_head gpuobj_list;
311 #define NOUVEAU_CHECK_INITIALISED_WITH_RETURN do { \
312 struct drm_nouveau_private *nv = dev->dev_private; \
313 if (nv->init_state != NOUVEAU_CARD_INIT_DONE) { \
314 DRM_ERROR("called without init\n"); \
319 #define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id,cl,ch) do { \
320 struct drm_nouveau_private *nv = dev->dev_private; \
321 if (!nouveau_fifo_owner(dev, (cl), (id))) { \
322 DRM_ERROR("pid %d doesn't own channel %d\n", \
323 DRM_CURRENTPID, (id)); \
326 (ch) = nv->fifos[(id)]; \
329 /* nouveau_state.c */
330 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
331 extern int nouveau_load(struct drm_device *, unsigned long flags);
332 extern int nouveau_firstopen(struct drm_device *);
333 extern void nouveau_lastclose(struct drm_device *);
334 extern int nouveau_unload(struct drm_device *);
335 extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
337 extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
339 extern void nouveau_wait_for_idle(struct drm_device *);
340 extern int nouveau_card_init(struct drm_device *);
341 extern int nouveau_ioctl_card_init(struct drm_device *, void *data,
345 extern int nouveau_mem_init_heap(struct mem_block **, uint64_t start,
347 extern struct mem_block *nouveau_mem_alloc_block(struct mem_block *,
348 uint64_t size, int align2,
350 extern void nouveau_mem_takedown(struct mem_block **heap);
351 extern void nouveau_mem_free_block(struct mem_block *);
352 extern uint64_t nouveau_mem_fb_amount(struct drm_device *);
353 extern void nouveau_mem_release(struct drm_file *, struct mem_block *heap);
354 extern int nouveau_ioctl_mem_alloc(struct drm_device *, void *data,
356 extern int nouveau_ioctl_mem_free(struct drm_device *, void *data,
358 extern struct mem_block* nouveau_mem_alloc(struct drm_device *,
359 int alignment, uint64_t size,
360 int flags, struct drm_file *);
361 extern void nouveau_mem_free(struct drm_device *dev, struct mem_block*);
362 extern int nouveau_mem_init(struct drm_device *);
363 extern int nouveau_mem_init_ttm(struct drm_device *);
364 extern void nouveau_mem_close(struct drm_device *);
366 /* nouveau_notifier.c */
367 extern int nouveau_notifier_init_channel(struct nouveau_channel *);
368 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
369 extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
370 int cout, uint32_t *offset);
371 extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
373 extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
377 extern int nouveau_fifo_init(struct drm_device *);
378 extern int nouveau_fifo_ctx_size(struct drm_device *);
379 extern void nouveau_fifo_cleanup(struct drm_device *, struct drm_file *);
380 extern int nouveau_fifo_owner(struct drm_device *, struct drm_file *,
382 extern int nouveau_fifo_alloc(struct drm_device *dev,
383 struct nouveau_channel **chan,
384 struct drm_file *file_priv,
385 struct mem_block *pushbuf,
386 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
387 extern void nouveau_fifo_free(struct nouveau_channel *);
389 /* nouveau_object.c */
390 extern int nouveau_gpuobj_early_init(struct drm_device *);
391 extern int nouveau_gpuobj_init(struct drm_device *);
392 extern void nouveau_gpuobj_takedown(struct drm_device *);
393 extern void nouveau_gpuobj_late_takedown(struct drm_device *);
394 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
395 uint32_t vram_h, uint32_t tt_h);
396 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
397 extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
398 int size, int align, uint32_t flags,
399 struct nouveau_gpuobj **);
400 extern int nouveau_gpuobj_del(struct drm_device *, struct nouveau_gpuobj **);
401 extern int nouveau_gpuobj_ref_add(struct drm_device *, struct nouveau_channel *,
402 uint32_t handle, struct nouveau_gpuobj *,
403 struct nouveau_gpuobj_ref **);
404 extern int nouveau_gpuobj_ref_del(struct drm_device *,
405 struct nouveau_gpuobj_ref **);
406 extern int nouveau_gpuobj_ref_find(struct nouveau_channel *, uint32_t handle,
407 struct nouveau_gpuobj_ref **ref_ret);
408 extern int nouveau_gpuobj_new_ref(struct drm_device *,
409 struct nouveau_channel *alloc_chan,
410 struct nouveau_channel *ref_chan,
411 uint32_t handle, int size, int align,
412 uint32_t flags, struct nouveau_gpuobj_ref **);
413 extern int nouveau_gpuobj_new_fake(struct drm_device *,
414 uint32_t p_offset, uint32_t b_offset,
415 uint32_t size, uint32_t flags,
416 struct nouveau_gpuobj **,
417 struct nouveau_gpuobj_ref**);
418 extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
419 uint64_t offset, uint64_t size, int access,
420 int target, struct nouveau_gpuobj **);
421 extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
422 uint64_t offset, uint64_t size,
423 int access, struct nouveau_gpuobj **,
425 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
426 struct nouveau_gpuobj **);
427 extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
429 extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
433 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
434 extern void nouveau_irq_preinstall(struct drm_device *);
435 extern int nouveau_irq_postinstall(struct drm_device *);
436 extern void nouveau_irq_uninstall(struct drm_device *);
438 /* nouveau_sgdma.c */
439 extern int nouveau_sgdma_init(struct drm_device *);
440 extern void nouveau_sgdma_takedown(struct drm_device *);
441 extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
443 extern struct drm_ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
444 extern int nouveau_sgdma_nottm_hack_init(struct drm_device *);
445 extern void nouveau_sgdma_nottm_hack_takedown(struct drm_device *);
448 extern int nouveau_dma_channel_init(struct drm_device *);
449 extern void nouveau_dma_channel_takedown(struct drm_device *);
450 extern int nouveau_dma_wait(struct drm_device *, int size);
453 extern int nv04_fb_init(struct drm_device *);
454 extern void nv04_fb_takedown(struct drm_device *);
457 extern int nv10_fb_init(struct drm_device *);
458 extern void nv10_fb_takedown(struct drm_device *);
461 extern int nv40_fb_init(struct drm_device *);
462 extern void nv40_fb_takedown(struct drm_device *);
465 extern int nv04_fifo_channel_id(struct drm_device *);
466 extern int nv04_fifo_create_context(struct nouveau_channel *);
467 extern void nv04_fifo_destroy_context(struct nouveau_channel *);
468 extern int nv04_fifo_load_context(struct nouveau_channel *);
469 extern int nv04_fifo_save_context(struct nouveau_channel *);
472 extern int nv10_fifo_channel_id(struct drm_device *);
473 extern int nv10_fifo_create_context(struct nouveau_channel *);
474 extern void nv10_fifo_destroy_context(struct nouveau_channel *);
475 extern int nv10_fifo_load_context(struct nouveau_channel *);
476 extern int nv10_fifo_save_context(struct nouveau_channel *);
479 extern int nv40_fifo_init(struct drm_device *);
480 extern int nv40_fifo_create_context(struct nouveau_channel *);
481 extern void nv40_fifo_destroy_context(struct nouveau_channel *);
482 extern int nv40_fifo_load_context(struct nouveau_channel *);
483 extern int nv40_fifo_save_context(struct nouveau_channel *);
486 extern int nv50_fifo_init(struct drm_device *);
487 extern void nv50_fifo_takedown(struct drm_device *);
488 extern int nv50_fifo_channel_id(struct drm_device *);
489 extern int nv50_fifo_create_context(struct nouveau_channel *);
490 extern void nv50_fifo_destroy_context(struct nouveau_channel *);
491 extern int nv50_fifo_load_context(struct nouveau_channel *);
492 extern int nv50_fifo_save_context(struct nouveau_channel *);
495 extern void nouveau_nv04_context_switch(struct drm_device *);
496 extern int nv04_graph_init(struct drm_device *);
497 extern void nv04_graph_takedown(struct drm_device *);
498 extern int nv04_graph_create_context(struct nouveau_channel *);
499 extern void nv04_graph_destroy_context(struct nouveau_channel *);
500 extern int nv04_graph_load_context(struct nouveau_channel *);
501 extern int nv04_graph_save_context(struct nouveau_channel *);
504 extern void nouveau_nv10_context_switch(struct drm_device *);
505 extern int nv10_graph_init(struct drm_device *);
506 extern void nv10_graph_takedown(struct drm_device *);
507 extern int nv10_graph_create_context(struct nouveau_channel *);
508 extern void nv10_graph_destroy_context(struct nouveau_channel *);
509 extern int nv10_graph_load_context(struct nouveau_channel *);
510 extern int nv10_graph_save_context(struct nouveau_channel *);
513 extern int nv20_graph_create_context(struct nouveau_channel *);
514 extern void nv20_graph_destroy_context(struct nouveau_channel *);
515 extern int nv20_graph_load_context(struct nouveau_channel *);
516 extern int nv20_graph_save_context(struct nouveau_channel *);
517 extern int nv20_graph_init(struct drm_device *);
518 extern void nv20_graph_takedown(struct drm_device *);
519 extern int nv30_graph_init(struct drm_device *);
522 extern int nv40_graph_init(struct drm_device *);
523 extern void nv40_graph_takedown(struct drm_device *);
524 extern int nv40_graph_create_context(struct nouveau_channel *);
525 extern void nv40_graph_destroy_context(struct nouveau_channel *);
526 extern int nv40_graph_load_context(struct nouveau_channel *);
527 extern int nv40_graph_save_context(struct nouveau_channel *);
530 extern int nv50_graph_init(struct drm_device *);
531 extern void nv50_graph_takedown(struct drm_device *);
532 extern int nv50_graph_create_context(struct nouveau_channel *);
533 extern void nv50_graph_destroy_context(struct nouveau_channel *);
534 extern int nv50_graph_load_context(struct nouveau_channel *);
535 extern int nv50_graph_save_context(struct nouveau_channel *);
538 extern int nv04_instmem_init(struct drm_device *);
539 extern void nv04_instmem_takedown(struct drm_device *);
540 extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
542 extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
543 extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
544 extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
547 extern int nv50_instmem_init(struct drm_device *);
548 extern void nv50_instmem_takedown(struct drm_device *);
549 extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
551 extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
552 extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
553 extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
556 extern int nv04_mc_init(struct drm_device *);
557 extern void nv04_mc_takedown(struct drm_device *);
560 extern int nv40_mc_init(struct drm_device *);
561 extern void nv40_mc_takedown(struct drm_device *);
564 extern int nv50_mc_init(struct drm_device *);
565 extern void nv50_mc_takedown(struct drm_device *);
568 extern int nv04_timer_init(struct drm_device *);
569 extern uint64_t nv04_timer_read(struct drm_device *);
570 extern void nv04_timer_takedown(struct drm_device *);
572 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
575 /* nouveau_buffer.c */
576 extern struct drm_bo_driver nouveau_bo_driver;
578 /* nouveau_fence.c */
579 extern struct drm_fence_driver nouveau_fence_driver;
580 extern void nouveau_fence_handler(struct drm_device *dev, int channel);
582 #if defined(__powerpc__)
583 #define NV_READ(reg) in_be32((void __iomem *)(dev_priv->mmio)->handle + (reg) )
584 #define NV_WRITE(reg,val) out_be32((void __iomem *)(dev_priv->mmio)->handle + (reg) , (val) )
586 #define NV_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
587 #define NV_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
591 #if defined(__powerpc__)
592 #define NV_RI32(o) in_be32((void __iomem *)(dev_priv->ramin)->handle+(o))
593 #define NV_WI32(o,v) out_be32((void __iomem*)(dev_priv->ramin)->handle+(o), (v))
595 #define NV_RI32(o) DRM_READ32(dev_priv->ramin, (o))
596 #define NV_WI32(o,v) DRM_WRITE32(dev_priv->ramin, (o), (v))
599 #define INSTANCE_RD(o,i) NV_RI32((o)->im_pramin->start + ((i)<<2))
600 #define INSTANCE_WR(o,i,v) NV_WI32((o)->im_pramin->start + ((i)<<2), (v))
602 #endif /* __NOUVEAU_DRV_H__ */